2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
30 #include "opt_polling.h"
33 #include <sys/param.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
37 #include <sys/interrupt.h>
38 #include <sys/malloc.h>
41 #include <sys/serialize.h>
42 #include <sys/serialize2.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
47 #include <net/ethernet.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/ifq_var.h>
54 #include <net/toeplitz.h>
55 #include <net/toeplitz2.h>
56 #include <net/vlan/if_vlan_var.h>
57 #include <net/vlan/if_vlan_ether.h>
59 #include <netinet/ip.h>
60 #include <netinet/tcp.h>
62 #include <dev/netif/mii_layer/miivar.h>
63 #include <dev/netif/mii_layer/jmphyreg.h>
65 #include <bus/pci/pcireg.h>
66 #include <bus/pci/pcivar.h>
67 #include <bus/pci/pcidevs.h>
69 #include <dev/netif/jme/if_jmereg.h>
70 #include <dev/netif/jme/if_jmevar.h>
72 #include "miibus_if.h"
74 #define JME_TX_SERIALIZE 1
75 #define JME_RX_SERIALIZE 2
77 #define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
80 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
82 if ((sc)->jme_rss_debug >= (lvl)) \
83 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
85 #else /* !JME_RSS_DEBUG */
86 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
87 #endif /* JME_RSS_DEBUG */
89 static int jme_probe(device_t);
90 static int jme_attach(device_t);
91 static int jme_detach(device_t);
92 static int jme_shutdown(device_t);
93 static int jme_suspend(device_t);
94 static int jme_resume(device_t);
96 static int jme_miibus_readreg(device_t, int, int);
97 static int jme_miibus_writereg(device_t, int, int, int);
98 static void jme_miibus_statchg(device_t);
100 static void jme_init(void *);
101 static int jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
102 static void jme_start(struct ifnet *);
103 static void jme_watchdog(struct ifnet *);
104 static void jme_mediastatus(struct ifnet *, struct ifmediareq *);
105 static int jme_mediachange(struct ifnet *);
106 #ifdef DEVICE_POLLING
107 static void jme_poll(struct ifnet *, enum poll_cmd, int);
109 static void jme_serialize(struct ifnet *, enum ifnet_serialize);
110 static void jme_deserialize(struct ifnet *, enum ifnet_serialize);
111 static int jme_tryserialize(struct ifnet *, enum ifnet_serialize);
113 static void jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
117 static void jme_intr(void *);
118 static void jme_msix_tx(void *);
119 static void jme_msix_rx(void *);
120 static void jme_txeof(struct jme_softc *);
121 static void jme_rxeof(struct jme_rxdata *, int);
122 static void jme_rx_intr(struct jme_softc *, uint32_t);
124 static int jme_msix_setup(device_t);
125 static void jme_msix_teardown(device_t, int);
126 static int jme_intr_setup(device_t);
127 static void jme_intr_teardown(device_t);
128 static void jme_msix_try_alloc(device_t);
129 static void jme_msix_free(device_t);
130 static int jme_intr_alloc(device_t);
131 static void jme_intr_free(device_t);
132 static int jme_dma_alloc(struct jme_softc *);
133 static void jme_dma_free(struct jme_softc *);
134 static int jme_init_rx_ring(struct jme_rxdata *);
135 static void jme_init_tx_ring(struct jme_softc *);
136 static void jme_init_ssb(struct jme_softc *);
137 static int jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
138 static int jme_encap(struct jme_softc *, struct mbuf **);
139 static void jme_rxpkt(struct jme_rxdata *);
140 static int jme_rxring_dma_alloc(struct jme_rxdata *);
141 static int jme_rxbuf_dma_alloc(struct jme_rxdata *);
142 static int jme_rxbuf_dma_filter(void *, bus_addr_t);
144 static void jme_tick(void *);
145 static void jme_stop(struct jme_softc *);
146 static void jme_reset(struct jme_softc *);
147 static void jme_set_msinum(struct jme_softc *);
148 static void jme_set_vlan(struct jme_softc *);
149 static void jme_set_filter(struct jme_softc *);
150 static void jme_stop_tx(struct jme_softc *);
151 static void jme_stop_rx(struct jme_softc *);
152 static void jme_mac_config(struct jme_softc *);
153 static void jme_reg_macaddr(struct jme_softc *, uint8_t[]);
154 static int jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
155 static int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
157 static void jme_setwol(struct jme_softc *);
158 static void jme_setlinkspeed(struct jme_softc *);
160 static void jme_set_tx_coal(struct jme_softc *);
161 static void jme_set_rx_coal(struct jme_softc *);
162 static void jme_enable_rss(struct jme_softc *);
163 static void jme_disable_rss(struct jme_softc *);
164 static void jme_serialize_skipmain(struct jme_softc *);
165 static void jme_deserialize_skipmain(struct jme_softc *);
167 static void jme_sysctl_node(struct jme_softc *);
168 static int jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
169 static int jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
170 static int jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
171 static int jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
174 * Devices supported by this driver.
176 static const struct jme_dev {
177 uint16_t jme_vendorid;
178 uint16_t jme_deviceid;
180 const char *jme_name;
182 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
184 "JMicron Inc, JMC250 Gigabit Ethernet" },
185 { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
187 "JMicron Inc, JMC260 Fast Ethernet" },
191 static device_method_t jme_methods[] = {
192 /* Device interface. */
193 DEVMETHOD(device_probe, jme_probe),
194 DEVMETHOD(device_attach, jme_attach),
195 DEVMETHOD(device_detach, jme_detach),
196 DEVMETHOD(device_shutdown, jme_shutdown),
197 DEVMETHOD(device_suspend, jme_suspend),
198 DEVMETHOD(device_resume, jme_resume),
201 DEVMETHOD(bus_print_child, bus_generic_print_child),
202 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
205 DEVMETHOD(miibus_readreg, jme_miibus_readreg),
206 DEVMETHOD(miibus_writereg, jme_miibus_writereg),
207 DEVMETHOD(miibus_statchg, jme_miibus_statchg),
212 static driver_t jme_driver = {
215 sizeof(struct jme_softc)
218 static devclass_t jme_devclass;
220 DECLARE_DUMMY_MODULE(if_jme);
221 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
222 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
223 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
225 static const struct {
229 } jme_rx_status[JME_NRXRING_MAX] = {
230 { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
231 INTR_RXQ0_DESC_EMPTY },
232 { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
233 INTR_RXQ1_DESC_EMPTY },
234 { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
235 INTR_RXQ2_DESC_EMPTY },
236 { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
237 INTR_RXQ3_DESC_EMPTY }
240 static int jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
241 static int jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
242 static int jme_rx_ring_count = 0;
243 static int jme_msi_enable = 1;
244 static int jme_msix_enable = 1;
246 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
247 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
248 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
249 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
250 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
253 jme_setup_rxdesc(struct jme_rxdesc *rxd)
255 struct jme_desc *desc;
258 desc->buflen = htole32(MCLBYTES);
259 desc->addr_lo = htole32(JME_ADDR_LO(rxd->rx_paddr));
260 desc->addr_hi = htole32(JME_ADDR_HI(rxd->rx_paddr));
261 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
265 * Read a PHY register on the MII of the JMC250.
268 jme_miibus_readreg(device_t dev, int phy, int reg)
270 struct jme_softc *sc = device_get_softc(dev);
274 /* For FPGA version, PHY address 0 should be ignored. */
275 if (sc->jme_caps & JME_CAP_FPGA) {
279 if (sc->jme_phyaddr != phy)
283 CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
284 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
286 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
288 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
292 device_printf(sc->jme_dev, "phy read timeout: "
293 "phy %d, reg %d\n", phy, reg);
297 return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
301 * Write a PHY register on the MII of the JMC250.
304 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
306 struct jme_softc *sc = device_get_softc(dev);
309 /* For FPGA version, PHY address 0 should be ignored. */
310 if (sc->jme_caps & JME_CAP_FPGA) {
314 if (sc->jme_phyaddr != phy)
318 CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
319 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
320 SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
322 for (i = JME_PHY_TIMEOUT; i > 0; i--) {
324 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
328 device_printf(sc->jme_dev, "phy write timeout: "
329 "phy %d, reg %d\n", phy, reg);
336 * Callback from MII layer when media changes.
339 jme_miibus_statchg(device_t dev)
341 struct jme_softc *sc = device_get_softc(dev);
342 struct ifnet *ifp = &sc->arpcom.ac_if;
343 struct mii_data *mii;
344 struct jme_txdesc *txd;
349 jme_serialize_skipmain(sc);
350 ASSERT_IFNET_SERIALIZED_ALL(ifp);
352 if ((ifp->if_flags & IFF_RUNNING) == 0)
355 mii = device_get_softc(sc->jme_miibus);
357 sc->jme_has_link = FALSE;
358 if ((mii->mii_media_status & IFM_AVALID) != 0) {
359 switch (IFM_SUBTYPE(mii->mii_media_active)) {
362 sc->jme_has_link = TRUE;
365 if (sc->jme_caps & JME_CAP_FASTETH)
367 sc->jme_has_link = TRUE;
375 * Disabling Rx/Tx MACs have a side-effect of resetting
376 * JME_TXNDA/JME_RXNDA register to the first address of
377 * Tx/Rx descriptor address. So driver should reset its
378 * internal procucer/consumer pointer and reclaim any
379 * allocated resources. Note, just saving the value of
380 * JME_TXNDA and JME_RXNDA registers before stopping MAC
381 * and restoring JME_TXNDA/JME_RXNDA register is not
382 * sufficient to make sure correct MAC state because
383 * stopping MAC operation can take a while and hardware
384 * might have updated JME_TXNDA/JME_RXNDA registers
385 * during the stop operation.
388 /* Disable interrupts */
389 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
392 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
394 callout_stop(&sc->jme_tick_ch);
396 /* Stop receiver/transmitter. */
400 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
401 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
403 jme_rxeof(rdata, -1);
404 if (rdata->jme_rxhead != NULL)
405 m_freem(rdata->jme_rxhead);
406 JME_RXCHAIN_RESET(rdata);
409 * Reuse configured Rx descriptors and reset
410 * procuder/consumer index.
412 rdata->jme_rx_cons = 0;
414 if (JME_ENABLE_HWRSS(sc))
420 if (sc->jme_cdata.jme_tx_cnt != 0) {
421 /* Remove queued packets for transmit. */
422 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
423 txd = &sc->jme_cdata.jme_txdesc[i];
424 if (txd->tx_m != NULL) {
426 sc->jme_cdata.jme_tx_tag,
435 jme_init_tx_ring(sc);
437 /* Initialize shadow status block. */
440 /* Program MAC with resolved speed/duplex/flow-control. */
441 if (sc->jme_has_link) {
444 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
446 /* Set Tx ring address to the hardware. */
447 paddr = sc->jme_cdata.jme_tx_ring_paddr;
448 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
449 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
451 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
452 CSR_WRITE_4(sc, JME_RXCSR,
453 sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
455 /* Set Rx ring address to the hardware. */
456 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
457 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
458 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
461 /* Restart receiver/transmitter. */
462 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
464 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
467 ifp->if_flags |= IFF_RUNNING;
468 ifp->if_flags &= ~IFF_OACTIVE;
469 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
471 #ifdef DEVICE_POLLING
472 if (!(ifp->if_flags & IFF_POLLING))
474 /* Reenable interrupts. */
475 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
479 jme_deserialize_skipmain(sc);
483 * Get the current interface media status.
486 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
488 struct jme_softc *sc = ifp->if_softc;
489 struct mii_data *mii = device_get_softc(sc->jme_miibus);
491 ASSERT_IFNET_SERIALIZED_ALL(ifp);
494 ifmr->ifm_status = mii->mii_media_status;
495 ifmr->ifm_active = mii->mii_media_active;
499 * Set hardware to newly-selected media.
502 jme_mediachange(struct ifnet *ifp)
504 struct jme_softc *sc = ifp->if_softc;
505 struct mii_data *mii = device_get_softc(sc->jme_miibus);
508 ASSERT_IFNET_SERIALIZED_ALL(ifp);
510 if (mii->mii_instance != 0) {
511 struct mii_softc *miisc;
513 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
514 mii_phy_reset(miisc);
516 error = mii_mediachg(mii);
522 jme_probe(device_t dev)
524 const struct jme_dev *sp;
527 vid = pci_get_vendor(dev);
528 did = pci_get_device(dev);
529 for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
530 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
531 struct jme_softc *sc = device_get_softc(dev);
533 sc->jme_caps = sp->jme_caps;
534 device_set_desc(dev, sp->jme_name);
542 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
548 for (i = JME_TIMEOUT; i > 0; i--) {
549 reg = CSR_READ_4(sc, JME_SMBCSR);
550 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
556 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
560 reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
561 CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
562 for (i = JME_TIMEOUT; i > 0; i--) {
564 reg = CSR_READ_4(sc, JME_SMBINTF);
565 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
570 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
574 reg = CSR_READ_4(sc, JME_SMBINTF);
575 *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
581 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
583 uint8_t fup, reg, val;
588 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
589 fup != JME_EEPROM_SIG0)
591 if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
592 fup != JME_EEPROM_SIG1)
596 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
598 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
599 (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
600 if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0)
602 if (reg >= JME_PAR0 &&
603 reg < JME_PAR0 + ETHER_ADDR_LEN) {
604 if (jme_eeprom_read_byte(sc, offset + 2,
607 eaddr[reg - JME_PAR0] = val;
611 /* Check for the end of EEPROM descriptor. */
612 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
614 /* Try next eeprom descriptor. */
615 offset += JME_EEPROM_DESC_BYTES;
616 } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
618 if (match == ETHER_ADDR_LEN)
625 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
629 /* Read station address. */
630 par0 = CSR_READ_4(sc, JME_PAR0);
631 par1 = CSR_READ_4(sc, JME_PAR1);
633 if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
634 device_printf(sc->jme_dev,
635 "generating fake ethernet address.\n");
636 par0 = karc4random();
637 /* Set OUI to JMicron. */
641 eaddr[3] = (par0 >> 16) & 0xff;
642 eaddr[4] = (par0 >> 8) & 0xff;
643 eaddr[5] = par0 & 0xff;
645 eaddr[0] = (par0 >> 0) & 0xFF;
646 eaddr[1] = (par0 >> 8) & 0xFF;
647 eaddr[2] = (par0 >> 16) & 0xFF;
648 eaddr[3] = (par0 >> 24) & 0xFF;
649 eaddr[4] = (par1 >> 0) & 0xFF;
650 eaddr[5] = (par1 >> 8) & 0xFF;
655 jme_attach(device_t dev)
657 struct jme_softc *sc = device_get_softc(dev);
658 struct ifnet *ifp = &sc->arpcom.ac_if;
661 uint8_t pcie_ptr, rev;
662 int error = 0, i, j, rx_desc_cnt;
663 uint8_t eaddr[ETHER_ADDR_LEN];
665 lwkt_serialize_init(&sc->jme_serialize);
666 lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
667 for (i = 0; i < JME_NRXRING_MAX; ++i) {
669 &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
672 rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
674 rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
675 if (rx_desc_cnt > JME_NDESC_MAX)
676 rx_desc_cnt = JME_NDESC_MAX;
678 sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
680 sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt,
682 if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX)
683 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX;
688 sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
690 sc->jme_cdata.jme_rx_ring_cnt =
691 if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
694 sc->jme_serialize_arr[i++] = &sc->jme_serialize;
696 KKASSERT(i == JME_TX_SERIALIZE);
697 sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
699 KKASSERT(i == JME_RX_SERIALIZE);
700 for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
701 sc->jme_serialize_arr[i++] =
702 &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
704 KKASSERT(i <= JME_NSERIALIZE);
705 sc->jme_serialize_cnt = i;
707 sc->jme_cdata.jme_sc = sc;
708 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
709 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
712 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
713 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
714 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
715 rdata->jme_rx_idx = i;
716 rdata->jme_rx_desc_cnt = rx_desc_cnt;
720 sc->jme_lowaddr = BUS_SPACE_MAXADDR;
722 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
724 callout_init(&sc->jme_tick_ch);
727 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
730 irq = pci_read_config(dev, PCIR_INTLINE, 4);
731 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
733 device_printf(dev, "chip is in D%d power mode "
734 "-- setting to D0\n", pci_get_powerstate(dev));
736 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
738 pci_write_config(dev, PCIR_INTLINE, irq, 4);
739 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
741 #endif /* !BURN_BRIDGE */
743 /* Enable bus mastering */
744 pci_enable_busmaster(dev);
749 * JMC250 supports both memory mapped and I/O register space
750 * access. Because I/O register access should use different
751 * BARs to access registers it's waste of time to use I/O
752 * register spce access. JMC250 uses 16K to map entire memory
755 sc->jme_mem_rid = JME_PCIR_BAR;
756 sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
757 &sc->jme_mem_rid, RF_ACTIVE);
758 if (sc->jme_mem_res == NULL) {
759 device_printf(dev, "can't allocate IO memory\n");
762 sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
763 sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
768 error = jme_intr_alloc(dev);
775 reg = CSR_READ_4(sc, JME_CHIPMODE);
776 if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
778 sc->jme_caps |= JME_CAP_FPGA;
780 device_printf(dev, "FPGA revision: 0x%04x\n",
781 (reg & CHIPMODE_FPGA_REV_MASK) >>
782 CHIPMODE_FPGA_REV_SHIFT);
786 /* NOTE: FM revision is put in the upper 4 bits */
787 rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
788 rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
790 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
792 did = pci_get_device(dev);
794 case PCI_PRODUCT_JMICRON_JMC250:
795 if (rev == JME_REV1_A2)
796 sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
799 case PCI_PRODUCT_JMICRON_JMC260:
801 sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
805 panic("unknown device id 0x%04x", did);
807 if (rev >= JME_REV2) {
808 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
809 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
810 GHC_TXMAC_CLKSRC_1000;
813 /* Reset the ethernet controller. */
816 /* Map MSI/MSI-X vectors */
819 /* Get station address. */
820 reg = CSR_READ_4(sc, JME_SMBCSR);
821 if (reg & SMBCSR_EEPROM_PRESENT)
822 error = jme_eeprom_macaddr(sc, eaddr);
823 if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
824 if (error != 0 && (bootverbose)) {
825 device_printf(dev, "ethernet hardware address "
826 "not found in EEPROM.\n");
828 jme_reg_macaddr(sc, eaddr);
833 * Integrated JR0211 has fixed PHY address whereas FPGA version
834 * requires PHY probing to get correct PHY address.
836 if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
837 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
838 GPREG0_PHY_ADDR_MASK;
840 device_printf(dev, "PHY is at address %d.\n",
847 /* Set max allowable DMA size. */
848 pcie_ptr = pci_get_pciecap_ptr(dev);
852 sc->jme_caps |= JME_CAP_PCIE;
853 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
855 device_printf(dev, "Read request size : %d bytes.\n",
856 128 << ((ctrl >> 12) & 0x07));
857 device_printf(dev, "TLP payload size : %d bytes.\n",
858 128 << ((ctrl >> 5) & 0x07));
860 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
861 case PCIEM_DEVCTL_MAX_READRQ_128:
862 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
864 case PCIEM_DEVCTL_MAX_READRQ_256:
865 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
868 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
871 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
873 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
874 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
878 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
879 sc->jme_caps |= JME_CAP_PMCAP;
887 /* Allocate DMA stuffs */
888 error = jme_dma_alloc(sc);
893 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
894 ifp->if_init = jme_init;
895 ifp->if_ioctl = jme_ioctl;
896 ifp->if_start = jme_start;
897 #ifdef DEVICE_POLLING
898 ifp->if_poll = jme_poll;
900 ifp->if_watchdog = jme_watchdog;
901 ifp->if_serialize = jme_serialize;
902 ifp->if_deserialize = jme_deserialize;
903 ifp->if_tryserialize = jme_tryserialize;
905 ifp->if_serialize_assert = jme_serialize_assert;
907 ifq_set_maxlen(&ifp->if_snd,
908 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
909 ifq_set_ready(&ifp->if_snd);
911 /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
912 ifp->if_capabilities = IFCAP_HWCSUM |
915 IFCAP_VLAN_HWTAGGING;
916 if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
917 ifp->if_capabilities |= IFCAP_RSS;
918 ifp->if_capenable = ifp->if_capabilities;
921 * Disable TXCSUM by default to improve bulk data
922 * transmit performance (+20Mbps improvement).
924 ifp->if_capenable &= ~IFCAP_TXCSUM;
926 if (ifp->if_capenable & IFCAP_TXCSUM)
927 ifp->if_hwassist |= JME_CSUM_FEATURES;
928 ifp->if_hwassist |= CSUM_TSO;
930 /* Set up MII bus. */
931 error = mii_phy_probe(dev, &sc->jme_miibus,
932 jme_mediachange, jme_mediastatus);
934 device_printf(dev, "no PHY found!\n");
939 * Save PHYADDR for FPGA mode PHY.
941 if (sc->jme_caps & JME_CAP_FPGA) {
942 struct mii_data *mii = device_get_softc(sc->jme_miibus);
944 if (mii->mii_instance != 0) {
945 struct mii_softc *miisc;
947 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
948 if (miisc->mii_phy != 0) {
949 sc->jme_phyaddr = miisc->mii_phy;
953 if (sc->jme_phyaddr != 0) {
954 device_printf(sc->jme_dev,
955 "FPGA PHY is at %d\n", sc->jme_phyaddr);
957 jme_miibus_writereg(dev, sc->jme_phyaddr,
958 JMPHY_CONF, JMPHY_CONF_DEFFIFO);
960 /* XXX should we clear JME_WA_EXTFIFO */
965 ether_ifattach(ifp, eaddr, NULL);
967 /* Tell the upper layer(s) we support long frames. */
968 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
970 error = jme_intr_setup(dev);
983 jme_detach(device_t dev)
985 struct jme_softc *sc = device_get_softc(dev);
987 if (device_is_attached(dev)) {
988 struct ifnet *ifp = &sc->arpcom.ac_if;
990 ifnet_serialize_all(ifp);
992 jme_intr_teardown(dev);
993 ifnet_deserialize_all(ifp);
998 if (sc->jme_sysctl_tree != NULL)
999 sysctl_ctx_free(&sc->jme_sysctl_ctx);
1001 if (sc->jme_miibus != NULL)
1002 device_delete_child(dev, sc->jme_miibus);
1003 bus_generic_detach(dev);
1007 if (sc->jme_mem_res != NULL) {
1008 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
1018 jme_sysctl_node(struct jme_softc *sc)
1021 #ifdef JME_RSS_DEBUG
1025 sysctl_ctx_init(&sc->jme_sysctl_ctx);
1026 sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
1027 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1028 device_get_nameunit(sc->jme_dev),
1030 if (sc->jme_sysctl_tree == NULL) {
1031 device_printf(sc->jme_dev, "can't add sysctl node\n");
1035 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1036 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1037 "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1038 sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1040 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1041 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1042 "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1043 sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1045 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1046 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1047 "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1048 sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1050 SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1051 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1052 "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1053 sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1055 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1056 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1057 "rx_desc_count", CTLFLAG_RD,
1058 &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
1059 0, "RX desc count");
1060 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1061 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1062 "tx_desc_count", CTLFLAG_RD,
1063 &sc->jme_cdata.jme_tx_desc_cnt,
1064 0, "TX desc count");
1065 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1066 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1067 "rx_ring_count", CTLFLAG_RD,
1068 &sc->jme_cdata.jme_rx_ring_cnt,
1069 0, "RX ring count");
1070 #ifdef JME_RSS_DEBUG
1071 SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1072 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1073 "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1074 0, "RSS debug level");
1075 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1076 char rx_ring_desc[32];
1078 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc),
1079 "rx_ring%d_pkt", r);
1080 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1081 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1082 rx_ring_desc, CTLFLAG_RW,
1083 &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
1085 ksnprintf(rx_ring_desc, sizeof(rx_ring_desc),
1086 "rx_ring%d_emp", r);
1087 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1088 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1089 rx_ring_desc, CTLFLAG_RW,
1090 &sc->jme_cdata.jme_rx_data[r].jme_rx_emp,
1091 "# of time RX ring empty");
1096 * Set default coalesce valves
1098 sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1099 sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1100 sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1101 sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1104 * Adjust coalesce valves, in case that the number of TX/RX
1105 * descs are set to small values by users.
1107 * NOTE: coal_max will not be zero, since number of descs
1108 * must aligned by JME_NDESC_ALIGN (16 currently)
1110 coal_max = sc->jme_cdata.jme_tx_desc_cnt / 2;
1111 if (coal_max < sc->jme_tx_coal_pkt)
1112 sc->jme_tx_coal_pkt = coal_max;
1114 coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 2;
1115 if (coal_max < sc->jme_rx_coal_pkt)
1116 sc->jme_rx_coal_pkt = coal_max;
1120 jme_dma_alloc(struct jme_softc *sc)
1122 struct jme_txdesc *txd;
1124 int error, i, asize;
1126 sc->jme_cdata.jme_txdesc =
1127 kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1128 M_DEVBUF, M_WAITOK | M_ZERO);
1129 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1130 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1133 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1134 M_DEVBUF, M_WAITOK | M_ZERO);
1137 /* Create parent ring tag. */
1138 error = bus_dma_tag_create(NULL,/* parent */
1139 1, JME_RING_BOUNDARY, /* algnmnt, boundary */
1140 sc->jme_lowaddr, /* lowaddr */
1141 BUS_SPACE_MAXADDR, /* highaddr */
1142 NULL, NULL, /* filter, filterarg */
1143 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1145 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1147 &sc->jme_cdata.jme_ring_tag);
1149 device_printf(sc->jme_dev,
1150 "could not create parent ring DMA tag.\n");
1155 * Create DMA stuffs for TX ring
1157 asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN);
1158 error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1159 JME_TX_RING_ALIGN, 0,
1160 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1161 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1163 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1166 sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1167 sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1168 sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1169 sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1172 * Create DMA stuffs for RX rings
1174 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1175 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1180 /* Create parent buffer tag. */
1181 error = bus_dma_tag_create(NULL,/* parent */
1182 1, 0, /* algnmnt, boundary */
1183 sc->jme_lowaddr, /* lowaddr */
1184 BUS_SPACE_MAXADDR, /* highaddr */
1185 NULL, NULL, /* filter, filterarg */
1186 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1188 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1190 &sc->jme_cdata.jme_buffer_tag);
1192 device_printf(sc->jme_dev,
1193 "could not create parent buffer DMA tag.\n");
1198 * Create DMA stuffs for shadow status block
1200 asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1201 error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1202 JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1203 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1205 device_printf(sc->jme_dev,
1206 "could not create shadow status block.\n");
1209 sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1210 sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1211 sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1212 sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1215 * Create DMA stuffs for TX buffers
1218 /* Create tag for Tx buffers. */
1219 error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1220 1, 0, /* algnmnt, boundary */
1221 BUS_SPACE_MAXADDR, /* lowaddr */
1222 BUS_SPACE_MAXADDR, /* highaddr */
1223 NULL, NULL, /* filter, filterarg */
1224 JME_TSO_MAXSIZE, /* maxsize */
1225 JME_MAXTXSEGS, /* nsegments */
1226 JME_MAXSEGSIZE, /* maxsegsize */
1227 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1228 &sc->jme_cdata.jme_tx_tag);
1230 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1234 /* Create DMA maps for Tx buffers. */
1235 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1236 txd = &sc->jme_cdata.jme_txdesc[i];
1237 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1238 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1243 device_printf(sc->jme_dev,
1244 "could not create %dth Tx dmamap.\n", i);
1246 for (j = 0; j < i; ++j) {
1247 txd = &sc->jme_cdata.jme_txdesc[j];
1248 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1251 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1252 sc->jme_cdata.jme_tx_tag = NULL;
1258 * Create DMA stuffs for RX buffers
1260 for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1261 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1269 jme_dma_free(struct jme_softc *sc)
1271 struct jme_txdesc *txd;
1272 struct jme_rxdesc *rxd;
1273 struct jme_rxdata *rdata;
1277 if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1278 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1279 sc->jme_cdata.jme_tx_ring_map);
1280 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1281 sc->jme_cdata.jme_tx_ring,
1282 sc->jme_cdata.jme_tx_ring_map);
1283 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1284 sc->jme_cdata.jme_tx_ring_tag = NULL;
1288 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1289 rdata = &sc->jme_cdata.jme_rx_data[r];
1290 if (rdata->jme_rx_ring_tag != NULL) {
1291 bus_dmamap_unload(rdata->jme_rx_ring_tag,
1292 rdata->jme_rx_ring_map);
1293 bus_dmamem_free(rdata->jme_rx_ring_tag,
1295 rdata->jme_rx_ring_map);
1296 bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1297 rdata->jme_rx_ring_tag = NULL;
1302 if (sc->jme_cdata.jme_tx_tag != NULL) {
1303 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1304 txd = &sc->jme_cdata.jme_txdesc[i];
1305 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1308 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1309 sc->jme_cdata.jme_tx_tag = NULL;
1313 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1314 rdata = &sc->jme_cdata.jme_rx_data[r];
1315 if (rdata->jme_rx_tag != NULL) {
1316 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
1317 rxd = &rdata->jme_rxdesc[i];
1318 bus_dmamap_destroy(rdata->jme_rx_tag,
1321 bus_dmamap_destroy(rdata->jme_rx_tag,
1322 rdata->jme_rx_sparemap);
1323 bus_dma_tag_destroy(rdata->jme_rx_tag);
1324 rdata->jme_rx_tag = NULL;
1328 /* Shadow status block. */
1329 if (sc->jme_cdata.jme_ssb_tag != NULL) {
1330 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1331 sc->jme_cdata.jme_ssb_map);
1332 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1333 sc->jme_cdata.jme_ssb_block,
1334 sc->jme_cdata.jme_ssb_map);
1335 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1336 sc->jme_cdata.jme_ssb_tag = NULL;
1339 if (sc->jme_cdata.jme_buffer_tag != NULL) {
1340 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1341 sc->jme_cdata.jme_buffer_tag = NULL;
1343 if (sc->jme_cdata.jme_ring_tag != NULL) {
1344 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1345 sc->jme_cdata.jme_ring_tag = NULL;
1348 if (sc->jme_cdata.jme_txdesc != NULL) {
1349 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1350 sc->jme_cdata.jme_txdesc = NULL;
1352 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1353 rdata = &sc->jme_cdata.jme_rx_data[r];
1354 if (rdata->jme_rxdesc != NULL) {
1355 kfree(rdata->jme_rxdesc, M_DEVBUF);
1356 rdata->jme_rxdesc = NULL;
1362 * Make sure the interface is stopped at reboot time.
1365 jme_shutdown(device_t dev)
1367 return jme_suspend(dev);
1372 * Unlike other ethernet controllers, JMC250 requires
1373 * explicit resetting link speed to 10/100Mbps as gigabit
1374 * link will cunsume more power than 375mA.
1375 * Note, we reset the link speed to 10/100Mbps with
1376 * auto-negotiation but we don't know whether that operation
1377 * would succeed or not as we have no control after powering
1378 * off. If the renegotiation fail WOL may not work. Running
1379 * at 1Gbps draws more power than 375mA at 3.3V which is
1380 * specified in PCI specification and that would result in
1381 * complete shutdowning power to ethernet controller.
1384 * Save current negotiated media speed/duplex/flow-control
1385 * to softc and restore the same link again after resuming.
1386 * PHY handling such as power down/resetting to 100Mbps
1387 * may be better handled in suspend method in phy driver.
1390 jme_setlinkspeed(struct jme_softc *sc)
1392 struct mii_data *mii;
1395 JME_LOCK_ASSERT(sc);
1397 mii = device_get_softc(sc->jme_miibus);
1400 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1401 switch IFM_SUBTYPE(mii->mii_media_active) {
1411 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1412 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1413 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1414 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1415 BMCR_AUTOEN | BMCR_STARTNEG);
1418 /* Poll link state until jme(4) get a 10/100 link. */
1419 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1421 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1422 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1432 pause("jmelnk", hz);
1435 if (i == MII_ANEGTICKS_GIGE)
1436 device_printf(sc->jme_dev, "establishing link failed, "
1437 "WOL may not work!");
1440 * No link, force MAC to have 100Mbps, full-duplex link.
1441 * This is the last resort and may/may not work.
1443 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1444 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1449 jme_setwol(struct jme_softc *sc)
1451 struct ifnet *ifp = &sc->arpcom.ac_if;
1456 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1457 /* No PME capability, PHY power down. */
1458 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1459 MII_BMCR, BMCR_PDOWN);
1463 gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1464 pmcs = CSR_READ_4(sc, JME_PMCS);
1465 pmcs &= ~PMCS_WOL_ENB_MASK;
1466 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1467 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1468 /* Enable PME message. */
1469 gpr |= GPREG0_PME_ENB;
1470 /* For gigabit controllers, reset link speed to 10/100. */
1471 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1472 jme_setlinkspeed(sc);
1475 CSR_WRITE_4(sc, JME_PMCS, pmcs);
1476 CSR_WRITE_4(sc, JME_GPREG0, gpr);
1479 pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1480 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1481 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1482 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1483 pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1484 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1485 /* No WOL, PHY power down. */
1486 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1487 MII_BMCR, BMCR_PDOWN);
1493 jme_suspend(device_t dev)
1495 struct jme_softc *sc = device_get_softc(dev);
1496 struct ifnet *ifp = &sc->arpcom.ac_if;
1498 ifnet_serialize_all(ifp);
1503 ifnet_deserialize_all(ifp);
1509 jme_resume(device_t dev)
1511 struct jme_softc *sc = device_get_softc(dev);
1512 struct ifnet *ifp = &sc->arpcom.ac_if;
1517 ifnet_serialize_all(ifp);
1520 if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1523 pmstat = pci_read_config(sc->jme_dev,
1524 pmc + PCIR_POWER_STATUS, 2);
1525 /* Disable PME clear PME status. */
1526 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1527 pci_write_config(sc->jme_dev,
1528 pmc + PCIR_POWER_STATUS, pmstat, 2);
1532 if (ifp->if_flags & IFF_UP)
1535 ifnet_deserialize_all(ifp);
1541 jme_tso_pullup(struct mbuf **mp)
1543 int hoff, iphlen, thoff;
1547 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
1549 iphlen = m->m_pkthdr.csum_iphlen;
1550 thoff = m->m_pkthdr.csum_thlen;
1551 hoff = m->m_pkthdr.csum_lhlen;
1553 KASSERT(iphlen > 0, ("invalid ip hlen"));
1554 KASSERT(thoff > 0, ("invalid tcp hlen"));
1555 KASSERT(hoff > 0, ("invalid ether hlen"));
1557 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
1558 m = m_pullup(m, hoff + iphlen + thoff);
1569 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1571 struct jme_txdesc *txd;
1572 struct jme_desc *desc;
1574 bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1576 int error, i, prod, symbol_desc;
1577 uint32_t cflags, flag64, mss;
1579 M_ASSERTPKTHDR((*m_head));
1581 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) {
1582 /* XXX Is this necessary? */
1583 error = jme_tso_pullup(m_head);
1588 prod = sc->jme_cdata.jme_tx_prod;
1589 txd = &sc->jme_cdata.jme_txdesc[prod];
1591 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1596 maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1597 (JME_TXD_RSVD + symbol_desc);
1598 if (maxsegs > JME_MAXTXSEGS)
1599 maxsegs = JME_MAXTXSEGS;
1600 KASSERT(maxsegs >= (JME_TXD_SPARE - symbol_desc),
1601 ("not enough segments %d", maxsegs));
1603 error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1604 txd->tx_dmamap, m_head,
1605 txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1609 bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1610 BUS_DMASYNC_PREWRITE);
1616 /* Configure checksum offload. */
1617 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1618 mss = (uint32_t)m->m_pkthdr.tso_segsz << JME_TD_MSS_SHIFT;
1619 cflags |= JME_TD_TSO;
1620 } else if (m->m_pkthdr.csum_flags & JME_CSUM_FEATURES) {
1621 if (m->m_pkthdr.csum_flags & CSUM_IP)
1622 cflags |= JME_TD_IPCSUM;
1623 if (m->m_pkthdr.csum_flags & CSUM_TCP)
1624 cflags |= JME_TD_TCPCSUM;
1625 if (m->m_pkthdr.csum_flags & CSUM_UDP)
1626 cflags |= JME_TD_UDPCSUM;
1629 /* Configure VLAN. */
1630 if (m->m_flags & M_VLANTAG) {
1631 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1632 cflags |= JME_TD_VLAN_TAG;
1635 desc = &sc->jme_cdata.jme_tx_ring[prod];
1636 desc->flags = htole32(cflags);
1637 desc->addr_hi = htole32(m->m_pkthdr.len);
1638 if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1640 * Use 64bits TX desc chain format.
1642 * The first TX desc of the chain, which is setup here,
1643 * is just a symbol TX desc carrying no payload.
1645 flag64 = JME_TD_64BIT;
1646 desc->buflen = htole32(mss);
1649 /* No effective TX desc is consumed */
1653 * Use 32bits TX desc chain format.
1655 * The first TX desc of the chain, which is setup here,
1656 * is an effective TX desc carrying the first segment of
1660 desc->buflen = htole32(mss | txsegs[0].ds_len);
1661 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1663 /* One effective TX desc is consumed */
1666 sc->jme_cdata.jme_tx_cnt++;
1667 KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1668 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1669 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1671 txd->tx_ndesc = 1 - i;
1672 for (; i < nsegs; i++) {
1673 desc = &sc->jme_cdata.jme_tx_ring[prod];
1674 desc->buflen = htole32(txsegs[i].ds_len);
1675 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1676 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1677 desc->flags = htole32(JME_TD_OWN | flag64);
1679 sc->jme_cdata.jme_tx_cnt++;
1680 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1681 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1682 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1685 /* Update producer index. */
1686 sc->jme_cdata.jme_tx_prod = prod;
1688 * Finally request interrupt and give the first descriptor
1689 * owenership to hardware.
1691 desc = txd->tx_desc;
1692 desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1695 txd->tx_ndesc += nsegs;
1705 jme_start(struct ifnet *ifp)
1707 struct jme_softc *sc = ifp->if_softc;
1708 struct mbuf *m_head;
1711 ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1713 if (!sc->jme_has_link) {
1714 ifq_purge(&ifp->if_snd);
1718 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1721 if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1724 while (!ifq_is_empty(&ifp->if_snd)) {
1726 * Check number of available TX descs, always
1727 * leave JME_TXD_RSVD free TX descs.
1729 if (sc->jme_cdata.jme_tx_cnt + JME_TXD_SPARE >
1730 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) {
1731 ifp->if_flags |= IFF_OACTIVE;
1735 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1740 * Pack the data into the transmit ring. If we
1741 * don't have room, set the OACTIVE flag and wait
1742 * for the NIC to drain the ring.
1744 if (jme_encap(sc, &m_head)) {
1745 KKASSERT(m_head == NULL);
1747 ifp->if_flags |= IFF_OACTIVE;
1753 * If there's a BPF listener, bounce a copy of this frame
1756 ETHER_BPF_MTAP(ifp, m_head);
1761 * Reading TXCSR takes very long time under heavy load
1762 * so cache TXCSR value and writes the ORed value with
1763 * the kick command to the TXCSR. This saves one register
1766 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1767 TXCSR_TXQ_N_START(TXCSR_TXQ0));
1768 /* Set a timeout in case the chip goes out to lunch. */
1769 ifp->if_timer = JME_TX_TIMEOUT;
1774 jme_watchdog(struct ifnet *ifp)
1776 struct jme_softc *sc = ifp->if_softc;
1778 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1780 if (!sc->jme_has_link) {
1781 if_printf(ifp, "watchdog timeout (missed link)\n");
1788 if (sc->jme_cdata.jme_tx_cnt == 0) {
1789 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1791 if (!ifq_is_empty(&ifp->if_snd))
1796 if_printf(ifp, "watchdog timeout\n");
1799 if (!ifq_is_empty(&ifp->if_snd))
1804 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1806 struct jme_softc *sc = ifp->if_softc;
1807 struct mii_data *mii = device_get_softc(sc->jme_miibus);
1808 struct ifreq *ifr = (struct ifreq *)data;
1809 int error = 0, mask;
1811 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1815 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1816 (!(sc->jme_caps & JME_CAP_JUMBO) &&
1817 ifr->ifr_mtu > JME_MAX_MTU)) {
1822 if (ifp->if_mtu != ifr->ifr_mtu) {
1824 * No special configuration is required when interface
1825 * MTU is changed but availability of Tx checksum
1826 * offload should be chcked against new MTU size as
1827 * FIFO size is just 2K.
1829 if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1830 ifp->if_capenable &=
1831 ~(IFCAP_TXCSUM | IFCAP_TSO);
1833 ~(JME_CSUM_FEATURES | CSUM_TSO);
1835 ifp->if_mtu = ifr->ifr_mtu;
1836 if (ifp->if_flags & IFF_RUNNING)
1842 if (ifp->if_flags & IFF_UP) {
1843 if (ifp->if_flags & IFF_RUNNING) {
1844 if ((ifp->if_flags ^ sc->jme_if_flags) &
1845 (IFF_PROMISC | IFF_ALLMULTI))
1851 if (ifp->if_flags & IFF_RUNNING)
1854 sc->jme_if_flags = ifp->if_flags;
1859 if (ifp->if_flags & IFF_RUNNING)
1865 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1869 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1871 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1872 ifp->if_capenable ^= IFCAP_TXCSUM;
1873 if (ifp->if_capenable & IFCAP_TXCSUM)
1874 ifp->if_hwassist |= JME_CSUM_FEATURES;
1876 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1878 if (mask & IFCAP_RXCSUM) {
1881 ifp->if_capenable ^= IFCAP_RXCSUM;
1882 reg = CSR_READ_4(sc, JME_RXMAC);
1883 reg &= ~RXMAC_CSUM_ENB;
1884 if (ifp->if_capenable & IFCAP_RXCSUM)
1885 reg |= RXMAC_CSUM_ENB;
1886 CSR_WRITE_4(sc, JME_RXMAC, reg);
1889 if (mask & IFCAP_VLAN_HWTAGGING) {
1890 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1894 if ((mask & IFCAP_TSO) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1895 ifp->if_capenable ^= IFCAP_TSO;
1896 if (ifp->if_capenable & IFCAP_TSO)
1897 ifp->if_hwassist |= CSUM_TSO;
1899 ifp->if_hwassist &= ~CSUM_TSO;
1902 if (mask & IFCAP_RSS)
1903 ifp->if_capenable ^= IFCAP_RSS;
1907 error = ether_ioctl(ifp, cmd, data);
1914 jme_mac_config(struct jme_softc *sc)
1916 struct mii_data *mii;
1917 uint32_t ghc, rxmac, txmac, txpause, gp1;
1918 int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1920 mii = device_get_softc(sc->jme_miibus);
1922 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1924 CSR_WRITE_4(sc, JME_GHC, 0);
1926 rxmac = CSR_READ_4(sc, JME_RXMAC);
1927 rxmac &= ~RXMAC_FC_ENB;
1928 txmac = CSR_READ_4(sc, JME_TXMAC);
1929 txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1930 txpause = CSR_READ_4(sc, JME_TXPFC);
1931 txpause &= ~TXPFC_PAUSE_ENB;
1932 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1933 ghc |= GHC_FULL_DUPLEX;
1934 rxmac &= ~RXMAC_COLL_DET_ENB;
1935 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1936 TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1939 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1940 txpause |= TXPFC_PAUSE_ENB;
1941 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1942 rxmac |= RXMAC_FC_ENB;
1944 /* Disable retry transmit timer/retry limit. */
1945 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1946 ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1948 rxmac |= RXMAC_COLL_DET_ENB;
1949 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1950 /* Enable retry transmit timer/retry limit. */
1951 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1952 TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1956 * Reprogram Tx/Rx MACs with resolved speed/duplex.
1958 gp1 = CSR_READ_4(sc, JME_GPREG1);
1959 gp1 &= ~GPREG1_WA_HDX;
1961 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1964 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1966 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1968 gp1 |= GPREG1_WA_HDX;
1972 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1974 gp1 |= GPREG1_WA_HDX;
1977 * Use extended FIFO depth to workaround CRC errors
1978 * emitted by chips before JMC250B
1980 phyconf = JMPHY_CONF_EXTFIFO;
1984 if (sc->jme_caps & JME_CAP_FASTETH)
1987 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1989 txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1995 CSR_WRITE_4(sc, JME_GHC, ghc);
1996 CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1997 CSR_WRITE_4(sc, JME_TXMAC, txmac);
1998 CSR_WRITE_4(sc, JME_TXPFC, txpause);
2000 if (sc->jme_workaround & JME_WA_EXTFIFO) {
2001 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
2002 JMPHY_CONF, phyconf);
2004 if (sc->jme_workaround & JME_WA_HDX)
2005 CSR_WRITE_4(sc, JME_GPREG1, gp1);
2011 struct jme_softc *sc = xsc;
2012 struct ifnet *ifp = &sc->arpcom.ac_if;
2016 ASSERT_SERIALIZED(&sc->jme_serialize);
2018 status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
2019 if (status == 0 || status == 0xFFFFFFFF)
2022 /* Disable interrupts. */
2023 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2025 status = CSR_READ_4(sc, JME_INTR_STATUS);
2026 if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
2029 /* Reset PCC counter/timer and Ack interrupts. */
2030 status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
2032 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
2033 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
2035 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2036 if (status & jme_rx_status[r].jme_coal) {
2037 status |= jme_rx_status[r].jme_coal |
2038 jme_rx_status[r].jme_comp;
2042 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
2044 if (ifp->if_flags & IFF_RUNNING) {
2045 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
2046 jme_rx_intr(sc, status);
2048 if (status & INTR_RXQ_DESC_EMPTY) {
2050 * Notify hardware availability of new Rx buffers.
2051 * Reading RXCSR takes very long time under heavy
2052 * load so cache RXCSR value and writes the ORed
2053 * value with the kick command to the RXCSR. This
2054 * saves one register access cycle.
2056 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
2057 RXCSR_RX_ENB | RXCSR_RXQ_START);
2060 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
2061 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
2063 if (!ifq_is_empty(&ifp->if_snd))
2065 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
2069 /* Reenable interrupts. */
2070 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2074 jme_txeof(struct jme_softc *sc)
2076 struct ifnet *ifp = &sc->arpcom.ac_if;
2079 cons = sc->jme_cdata.jme_tx_cons;
2080 if (cons == sc->jme_cdata.jme_tx_prod)
2084 * Go through our Tx list and free mbufs for those
2085 * frames which have been transmitted.
2087 while (cons != sc->jme_cdata.jme_tx_prod) {
2088 struct jme_txdesc *txd, *next_txd;
2089 uint32_t status, next_status;
2090 int next_cons, nsegs;
2092 txd = &sc->jme_cdata.jme_txdesc[cons];
2093 KASSERT(txd->tx_m != NULL,
2094 ("%s: freeing NULL mbuf!", __func__));
2096 status = le32toh(txd->tx_desc->flags);
2097 if ((status & JME_TD_OWN) == JME_TD_OWN)
2102 * This chip will always update the TX descriptor's
2103 * buflen field and this updating always happens
2104 * after clearing the OWN bit, so even if the OWN
2105 * bit is cleared by the chip, we still don't sure
2106 * about whether the buflen field has been updated
2107 * by the chip or not. To avoid this race, we wait
2108 * for the next TX descriptor's OWN bit to be cleared
2109 * by the chip before reusing this TX descriptor.
2112 JME_DESC_ADD(next_cons, txd->tx_ndesc,
2113 sc->jme_cdata.jme_tx_desc_cnt);
2114 next_txd = &sc->jme_cdata.jme_txdesc[next_cons];
2115 if (next_txd->tx_m == NULL)
2117 next_status = le32toh(next_txd->tx_desc->flags);
2118 if ((next_status & JME_TD_OWN) == JME_TD_OWN)
2121 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2125 if (status & JME_TD_COLLISION) {
2126 ifp->if_collisions +=
2127 le32toh(txd->tx_desc->buflen) &
2128 JME_TD_BUF_LEN_MASK;
2133 * Only the first descriptor of multi-descriptor
2134 * transmission is updated so driver have to skip entire
2135 * chained buffers for the transmiited frame. In other
2136 * words, JME_TD_OWN bit is valid only at the first
2137 * descriptor of a multi-descriptor transmission.
2139 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2140 sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2141 JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt);
2144 /* Reclaim transferred mbufs. */
2145 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2148 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2149 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2150 ("%s: Active Tx desc counter was garbled", __func__));
2153 sc->jme_cdata.jme_tx_cons = cons;
2155 /* 1 for symbol TX descriptor */
2156 if (sc->jme_cdata.jme_tx_cnt <= JME_MAXTXSEGS + 1)
2159 if (sc->jme_cdata.jme_tx_cnt + JME_TXD_SPARE <=
2160 sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD)
2161 ifp->if_flags &= ~IFF_OACTIVE;
2164 static __inline void
2165 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2169 for (i = 0; i < count; ++i) {
2170 jme_setup_rxdesc(&rdata->jme_rxdesc[cons]);
2171 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2175 static __inline struct pktinfo *
2176 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2178 if (flags & JME_RD_IPV4)
2179 pi->pi_netisr = NETISR_IP;
2180 else if (flags & JME_RD_IPV6)
2181 pi->pi_netisr = NETISR_IPV6;
2186 pi->pi_l3proto = IPPROTO_UNKNOWN;
2188 if (flags & JME_RD_MORE_FRAG)
2189 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2190 else if (flags & JME_RD_TCP)
2191 pi->pi_l3proto = IPPROTO_TCP;
2192 else if (flags & JME_RD_UDP)
2193 pi->pi_l3proto = IPPROTO_UDP;
2199 /* Receive a frame. */
2201 jme_rxpkt(struct jme_rxdata *rdata)
2203 struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2204 struct jme_desc *desc;
2205 struct jme_rxdesc *rxd;
2206 struct mbuf *mp, *m;
2207 uint32_t flags, status, hash, hashinfo;
2208 int cons, count, nsegs;
2210 cons = rdata->jme_rx_cons;
2211 desc = &rdata->jme_rx_ring[cons];
2213 flags = le32toh(desc->flags);
2214 status = le32toh(desc->buflen);
2215 hash = le32toh(desc->addr_hi);
2216 hashinfo = le32toh(desc->addr_lo);
2217 nsegs = JME_RX_NSEGS(status);
2220 /* Skip the first descriptor. */
2221 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2224 * Clear the OWN bit of the following RX descriptors;
2225 * hardware will not clear the OWN bit except the first
2228 * Since the first RX descriptor is setup, i.e. OWN bit
2229 * on, before its followins RX descriptors, leaving the
2230 * OWN bit on the following RX descriptors will trick
2231 * the hardware into thinking that the following RX
2232 * descriptors are ready to be used too.
2234 for (count = 1; count < nsegs; count++,
2235 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt))
2236 rdata->jme_rx_ring[cons].flags = 0;
2238 cons = rdata->jme_rx_cons;
2241 JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
2242 "hash 0x%08x, hash info 0x%08x\n",
2243 rdata->jme_rx_idx, flags, hash, hashinfo);
2245 if (status & JME_RX_ERR_STAT) {
2247 jme_discard_rxbufs(rdata, cons, nsegs);
2248 #ifdef JME_SHOW_ERRORS
2249 if_printf(ifp, "%s : receive error = 0x%b\n",
2250 __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2252 rdata->jme_rx_cons += nsegs;
2253 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2257 rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2258 for (count = 0; count < nsegs; count++,
2259 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
2260 rxd = &rdata->jme_rxdesc[cons];
2263 /* Add a new receive buffer to the ring. */
2264 if (jme_newbuf(rdata, rxd, 0) != 0) {
2267 jme_discard_rxbufs(rdata, cons, nsegs - count);
2268 if (rdata->jme_rxhead != NULL) {
2269 m_freem(rdata->jme_rxhead);
2270 JME_RXCHAIN_RESET(rdata);
2276 * Assume we've received a full sized frame.
2277 * Actual size is fixed when we encounter the end of
2278 * multi-segmented frame.
2280 mp->m_len = MCLBYTES;
2282 /* Chain received mbufs. */
2283 if (rdata->jme_rxhead == NULL) {
2284 rdata->jme_rxhead = mp;
2285 rdata->jme_rxtail = mp;
2288 * Receive processor can receive a maximum frame
2289 * size of 65535 bytes.
2291 rdata->jme_rxtail->m_next = mp;
2292 rdata->jme_rxtail = mp;
2295 if (count == nsegs - 1) {
2296 struct pktinfo pi0, *pi;
2298 /* Last desc. for this frame. */
2299 m = rdata->jme_rxhead;
2300 m->m_pkthdr.len = rdata->jme_rxlen;
2302 /* Set first mbuf size. */
2303 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2304 /* Set last mbuf size. */
2305 mp->m_len = rdata->jme_rxlen -
2306 ((MCLBYTES - JME_RX_PAD_BYTES) +
2307 (MCLBYTES * (nsegs - 2)));
2309 m->m_len = rdata->jme_rxlen;
2311 m->m_pkthdr.rcvif = ifp;
2314 * Account for 10bytes auto padding which is used
2315 * to align IP header on 32bit boundary. Also note,
2316 * CRC bytes is automatically removed by the
2319 m->m_data += JME_RX_PAD_BYTES;
2321 /* Set checksum information. */
2322 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2323 (flags & JME_RD_IPV4)) {
2324 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2325 if (flags & JME_RD_IPCSUM)
2326 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2327 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2328 ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2329 (JME_RD_TCP | JME_RD_TCPCSUM) ||
2330 (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2331 (JME_RD_UDP | JME_RD_UDPCSUM))) {
2332 m->m_pkthdr.csum_flags |=
2333 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2334 m->m_pkthdr.csum_data = 0xffff;
2338 /* Check for VLAN tagged packets. */
2339 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2340 (flags & JME_RD_VLAN_TAG)) {
2341 m->m_pkthdr.ether_vlantag =
2342 flags & JME_RD_VLAN_MASK;
2343 m->m_flags |= M_VLANTAG;
2348 if (ifp->if_capenable & IFCAP_RSS)
2349 pi = jme_pktinfo(&pi0, flags);
2354 (hashinfo & JME_RD_HASH_FN_MASK) ==
2355 JME_RD_HASH_FN_TOEPLITZ) {
2356 m->m_flags |= (M_HASH | M_CKHASH);
2357 m->m_pkthdr.hash = toeplitz_hash(hash);
2360 #ifdef JME_RSS_DEBUG
2362 JME_RSS_DPRINTF(rdata->jme_sc, 10,
2363 "isr %d flags %08x, l3 %d %s\n",
2364 pi->pi_netisr, pi->pi_flags,
2366 (m->m_flags & M_HASH) ? "hash" : "");
2371 ether_input_pkt(ifp, m, pi);
2373 /* Reset mbuf chains. */
2374 JME_RXCHAIN_RESET(rdata);
2375 #ifdef JME_RSS_DEBUG
2376 rdata->jme_rx_pkt++;
2381 rdata->jme_rx_cons += nsegs;
2382 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2386 jme_rxeof(struct jme_rxdata *rdata, int count)
2388 struct jme_desc *desc;
2392 #ifdef DEVICE_POLLING
2393 if (count >= 0 && count-- == 0)
2396 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2397 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2399 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2403 * Check number of segments against received bytes.
2404 * Non-matching value would indicate that hardware
2405 * is still trying to update Rx descriptors. I'm not
2406 * sure whether this check is needed.
2408 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2409 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2410 if (nsegs != howmany(pktlen, MCLBYTES)) {
2411 if_printf(&rdata->jme_sc->arpcom.ac_if,
2412 "RX fragment count(%d) and "
2413 "packet size(%d) mismach\n", nsegs, pktlen);
2419 * RSS hash and hash information may _not_ be set by the
2420 * hardware even if the OWN bit is cleared and VALID bit
2423 * If the RSS information is not delivered by the hardware
2424 * yet, we MUST NOT accept this packet, let alone reusing
2425 * its RX descriptor. If this packet was accepted and its
2426 * RX descriptor was reused before hardware delivering the
2427 * RSS information, the RX buffer's address would be trashed
2428 * by the RSS information delivered by the hardware.
2430 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
2431 struct jme_rxdesc *rxd;
2434 hashinfo = le32toh(desc->addr_lo);
2435 rxd = &rdata->jme_rxdesc[rdata->jme_rx_cons];
2438 * This test should be enough to detect the pending
2439 * RSS information delivery, given:
2440 * - If RSS hash is not calculated, the hashinfo
2441 * will be 0. Howvever, the lower 32bits of RX
2442 * buffers' physical address will never be 0.
2443 * (see jme_rxbuf_dma_filter)
2444 * - If RSS hash is calculated, the lowest 4 bits
2445 * of hashinfo will be set, while the RX buffers
2446 * are at least 2K aligned.
2448 if (hashinfo == JME_ADDR_LO(rxd->rx_paddr)) {
2449 #ifdef JME_SHOW_RSSWB
2450 if_printf(&rdata->jme_sc->arpcom.ac_if,
2451 "RSS is not written back yet\n");
2457 /* Received a frame. */
2465 struct jme_softc *sc = xsc;
2466 struct mii_data *mii = device_get_softc(sc->jme_miibus);
2468 lwkt_serialize_enter(&sc->jme_serialize);
2470 sc->jme_in_tick = TRUE;
2472 sc->jme_in_tick = FALSE;
2474 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2476 lwkt_serialize_exit(&sc->jme_serialize);
2480 jme_reset(struct jme_softc *sc)
2484 /* Make sure that TX and RX are stopped */
2489 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2493 * Hold reset bit before stop reset
2496 /* Disable TXMAC and TXOFL clock sources */
2497 CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2498 /* Disable RXMAC clock source */
2499 val = CSR_READ_4(sc, JME_GPREG1);
2500 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2502 CSR_READ_4(sc, JME_GHC);
2505 CSR_WRITE_4(sc, JME_GHC, 0);
2507 CSR_READ_4(sc, JME_GHC);
2510 * Clear reset bit after stop reset
2513 /* Enable TXMAC and TXOFL clock sources */
2514 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2515 /* Enable RXMAC clock source */
2516 val = CSR_READ_4(sc, JME_GPREG1);
2517 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2519 CSR_READ_4(sc, JME_GHC);
2521 /* Disable TXMAC and TXOFL clock sources */
2522 CSR_WRITE_4(sc, JME_GHC, 0);
2523 /* Disable RXMAC clock source */
2524 val = CSR_READ_4(sc, JME_GPREG1);
2525 CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2527 CSR_READ_4(sc, JME_GHC);
2529 /* Enable TX and RX */
2530 val = CSR_READ_4(sc, JME_TXCSR);
2531 CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2532 val = CSR_READ_4(sc, JME_RXCSR);
2533 CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2535 CSR_READ_4(sc, JME_TXCSR);
2536 CSR_READ_4(sc, JME_RXCSR);
2538 /* Enable TXMAC and TXOFL clock sources */
2539 CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2540 /* Eisable RXMAC clock source */
2541 val = CSR_READ_4(sc, JME_GPREG1);
2542 CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2544 CSR_READ_4(sc, JME_GHC);
2546 /* Stop TX and RX */
2554 struct jme_softc *sc = xsc;
2555 struct ifnet *ifp = &sc->arpcom.ac_if;
2556 struct mii_data *mii;
2557 uint8_t eaddr[ETHER_ADDR_LEN];
2562 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2565 * Cancel any pending I/O.
2570 * Reset the chip to a known state.
2575 * Setup MSI/MSI-X vectors to interrupts mapping
2579 if (JME_ENABLE_HWRSS(sc))
2582 jme_disable_rss(sc);
2584 /* Init RX descriptors */
2585 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2586 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2588 if_printf(ifp, "initialization failed: "
2589 "no memory for %dth RX ring.\n", r);
2595 /* Init TX descriptors */
2596 jme_init_tx_ring(sc);
2598 /* Initialize shadow status block. */
2601 /* Reprogram the station address. */
2602 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2603 CSR_WRITE_4(sc, JME_PAR0,
2604 eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2605 CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2608 * Configure Tx queue.
2609 * Tx priority queue weight value : 0
2610 * Tx FIFO threshold for processing next packet : 16QW
2611 * Maximum Tx DMA length : 512
2612 * Allow Tx DMA burst.
2614 sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2615 sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2616 sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2617 sc->jme_txcsr |= sc->jme_tx_dma_size;
2618 sc->jme_txcsr |= TXCSR_DMA_BURST;
2619 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2621 /* Set Tx descriptor counter. */
2622 CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt);
2624 /* Set Tx ring address to the hardware. */
2625 paddr = sc->jme_cdata.jme_tx_ring_paddr;
2626 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2627 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2629 /* Configure TxMAC parameters. */
2630 reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2631 reg |= TXMAC_THRESH_1_PKT;
2632 reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2633 CSR_WRITE_4(sc, JME_TXMAC, reg);
2636 * Configure Rx queue.
2637 * FIFO full threshold for transmitting Tx pause packet : 128T
2638 * FIFO threshold for processing next packet : 128QW
2640 * Max Rx DMA length : 128
2641 * Rx descriptor retry : 32
2642 * Rx descriptor retry time gap : 256ns
2643 * Don't receive runt/bad frame.
2645 sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2648 * Since Rx FIFO size is 4K bytes, receiving frames larger
2649 * than 4K bytes will suffer from Rx FIFO overruns. So
2650 * decrease FIFO threshold to reduce the FIFO overruns for
2651 * frames larger than 4000 bytes.
2652 * For best performance of standard MTU sized frames use
2653 * maximum allowable FIFO threshold, 128QW.
2655 if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2657 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2659 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2661 /* Improve PCI Express compatibility */
2662 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2664 sc->jme_rxcsr |= sc->jme_rx_dma_size;
2665 sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2666 sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2667 /* XXX TODO DROP_BAD */
2669 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2670 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2672 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2674 /* Set Rx descriptor counter. */
2675 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
2677 /* Set Rx ring address to the hardware. */
2678 paddr = rdata->jme_rx_ring_paddr;
2679 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2680 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2683 /* Clear receive filter. */
2684 CSR_WRITE_4(sc, JME_RXMAC, 0);
2686 /* Set up the receive filter. */
2691 * Disable all WOL bits as WOL can interfere normal Rx
2692 * operation. Also clear WOL detection status bits.
2694 reg = CSR_READ_4(sc, JME_PMCS);
2695 reg &= ~PMCS_WOL_ENB_MASK;
2696 CSR_WRITE_4(sc, JME_PMCS, reg);
2699 * Pad 10bytes right before received frame. This will greatly
2700 * help Rx performance on strict-alignment architectures as
2701 * it does not need to copy the frame to align the payload.
2703 reg = CSR_READ_4(sc, JME_RXMAC);
2704 reg |= RXMAC_PAD_10BYTES;
2706 if (ifp->if_capenable & IFCAP_RXCSUM)
2707 reg |= RXMAC_CSUM_ENB;
2708 CSR_WRITE_4(sc, JME_RXMAC, reg);
2710 /* Configure general purpose reg0 */
2711 reg = CSR_READ_4(sc, JME_GPREG0);
2712 reg &= ~GPREG0_PCC_UNIT_MASK;
2713 /* Set PCC timer resolution to micro-seconds unit. */
2714 reg |= GPREG0_PCC_UNIT_US;
2716 * Disable all shadow register posting as we have to read
2717 * JME_INTR_STATUS register in jme_intr. Also it seems
2718 * that it's hard to synchronize interrupt status between
2719 * hardware and software with shadow posting due to
2720 * requirements of bus_dmamap_sync(9).
2722 reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2723 GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2724 GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2725 GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2726 /* Disable posting of DW0. */
2727 reg &= ~GPREG0_POST_DW0_ENB;
2728 /* Clear PME message. */
2729 reg &= ~GPREG0_PME_ENB;
2730 /* Set PHY address. */
2731 reg &= ~GPREG0_PHY_ADDR_MASK;
2732 reg |= sc->jme_phyaddr;
2733 CSR_WRITE_4(sc, JME_GPREG0, reg);
2735 /* Configure Tx queue 0 packet completion coalescing. */
2736 jme_set_tx_coal(sc);
2738 /* Configure Rx queues packet completion coalescing. */
2739 jme_set_rx_coal(sc);
2741 /* Configure shadow status block but don't enable posting. */
2742 paddr = sc->jme_cdata.jme_ssb_block_paddr;
2743 CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2744 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2746 /* Disable Timer 1 and Timer 2. */
2747 CSR_WRITE_4(sc, JME_TIMER1, 0);
2748 CSR_WRITE_4(sc, JME_TIMER2, 0);
2750 /* Configure retry transmit period, retry limit value. */
2751 CSR_WRITE_4(sc, JME_TXTRHD,
2752 ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2753 TXTRHD_RT_PERIOD_MASK) |
2754 ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2755 TXTRHD_RT_LIMIT_SHIFT));
2757 #ifdef DEVICE_POLLING
2758 if (!(ifp->if_flags & IFF_POLLING))
2760 /* Initialize the interrupt mask. */
2761 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2762 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2765 * Enabling Tx/Rx DMA engines and Rx queue processing is
2766 * done after detection of valid link in jme_miibus_statchg.
2768 sc->jme_has_link = FALSE;
2770 /* Set the current media. */
2771 mii = device_get_softc(sc->jme_miibus);
2774 callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2776 ifp->if_flags |= IFF_RUNNING;
2777 ifp->if_flags &= ~IFF_OACTIVE;
2781 jme_stop(struct jme_softc *sc)
2783 struct ifnet *ifp = &sc->arpcom.ac_if;
2784 struct jme_txdesc *txd;
2785 struct jme_rxdesc *rxd;
2786 struct jme_rxdata *rdata;
2789 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2792 * Mark the interface down and cancel the watchdog timer.
2794 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2797 callout_stop(&sc->jme_tick_ch);
2798 sc->jme_has_link = FALSE;
2801 * Disable interrupts.
2803 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2804 CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2806 /* Disable updating shadow status block. */
2807 CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2808 CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2810 /* Stop receiver, transmitter. */
2815 * Free partial finished RX segments
2817 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2818 rdata = &sc->jme_cdata.jme_rx_data[r];
2819 if (rdata->jme_rxhead != NULL)
2820 m_freem(rdata->jme_rxhead);
2821 JME_RXCHAIN_RESET(rdata);
2825 * Free RX and TX mbufs still in the queues.
2827 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2828 rdata = &sc->jme_cdata.jme_rx_data[r];
2829 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2830 rxd = &rdata->jme_rxdesc[i];
2831 if (rxd->rx_m != NULL) {
2832 bus_dmamap_unload(rdata->jme_rx_tag,
2839 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2840 txd = &sc->jme_cdata.jme_txdesc[i];
2841 if (txd->tx_m != NULL) {
2842 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2852 jme_stop_tx(struct jme_softc *sc)
2857 reg = CSR_READ_4(sc, JME_TXCSR);
2858 if ((reg & TXCSR_TX_ENB) == 0)
2860 reg &= ~TXCSR_TX_ENB;
2861 CSR_WRITE_4(sc, JME_TXCSR, reg);
2862 for (i = JME_TIMEOUT; i > 0; i--) {
2864 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2868 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2872 jme_stop_rx(struct jme_softc *sc)
2877 reg = CSR_READ_4(sc, JME_RXCSR);
2878 if ((reg & RXCSR_RX_ENB) == 0)
2880 reg &= ~RXCSR_RX_ENB;
2881 CSR_WRITE_4(sc, JME_RXCSR, reg);
2882 for (i = JME_TIMEOUT; i > 0; i--) {
2884 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2888 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2892 jme_init_tx_ring(struct jme_softc *sc)
2894 struct jme_chain_data *cd;
2895 struct jme_txdesc *txd;
2898 sc->jme_cdata.jme_tx_prod = 0;
2899 sc->jme_cdata.jme_tx_cons = 0;
2900 sc->jme_cdata.jme_tx_cnt = 0;
2902 cd = &sc->jme_cdata;
2903 bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2904 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2905 txd = &sc->jme_cdata.jme_txdesc[i];
2907 txd->tx_desc = &cd->jme_tx_ring[i];
2913 jme_init_ssb(struct jme_softc *sc)
2915 struct jme_chain_data *cd;
2917 cd = &sc->jme_cdata;
2918 bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2922 jme_init_rx_ring(struct jme_rxdata *rdata)
2924 struct jme_rxdesc *rxd;
2927 KKASSERT(rdata->jme_rxhead == NULL &&
2928 rdata->jme_rxtail == NULL &&
2929 rdata->jme_rxlen == 0);
2930 rdata->jme_rx_cons = 0;
2932 bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2933 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2936 rxd = &rdata->jme_rxdesc[i];
2938 rxd->rx_desc = &rdata->jme_rx_ring[i];
2939 error = jme_newbuf(rdata, rxd, 1);
2947 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
2950 bus_dma_segment_t segs;
2954 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2958 * JMC250 has 64bit boundary alignment limitation so jme(4)
2959 * takes advantage of 10 bytes padding feature of hardware
2960 * in order not to copy entire frame to align IP header on
2963 m->m_len = m->m_pkthdr.len = MCLBYTES;
2965 error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2966 rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2971 if_printf(&rdata->jme_sc->arpcom.ac_if,
2972 "can't load RX mbuf\n");
2977 if (rxd->rx_m != NULL) {
2978 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2979 BUS_DMASYNC_POSTREAD);
2980 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2982 map = rxd->rx_dmamap;
2983 rxd->rx_dmamap = rdata->jme_rx_sparemap;
2984 rdata->jme_rx_sparemap = map;
2986 rxd->rx_paddr = segs.ds_addr;
2988 jme_setup_rxdesc(rxd);
2993 jme_set_vlan(struct jme_softc *sc)
2995 struct ifnet *ifp = &sc->arpcom.ac_if;
2998 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3000 reg = CSR_READ_4(sc, JME_RXMAC);
3001 reg &= ~RXMAC_VLAN_ENB;
3002 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
3003 reg |= RXMAC_VLAN_ENB;
3004 CSR_WRITE_4(sc, JME_RXMAC, reg);
3008 jme_set_filter(struct jme_softc *sc)
3010 struct ifnet *ifp = &sc->arpcom.ac_if;
3011 struct ifmultiaddr *ifma;
3016 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3018 rxcfg = CSR_READ_4(sc, JME_RXMAC);
3019 rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
3023 * Always accept frames destined to our station address.
3024 * Always accept broadcast frames.
3026 rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
3028 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
3029 if (ifp->if_flags & IFF_PROMISC)
3030 rxcfg |= RXMAC_PROMISC;
3031 if (ifp->if_flags & IFF_ALLMULTI)
3032 rxcfg |= RXMAC_ALLMULTI;
3033 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
3034 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
3035 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3040 * Set up the multicast address filter by passing all multicast
3041 * addresses through a CRC generator, and then using the low-order
3042 * 6 bits as an index into the 64 bit multicast hash table. The
3043 * high order bits select the register, while the rest of the bits
3044 * select the bit within the register.
3046 rxcfg |= RXMAC_MULTICAST;
3047 bzero(mchash, sizeof(mchash));
3049 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3050 if (ifma->ifma_addr->sa_family != AF_LINK)
3052 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3053 ifma->ifma_addr), ETHER_ADDR_LEN);
3055 /* Just want the 6 least significant bits. */
3058 /* Set the corresponding bit in the hash table. */
3059 mchash[crc >> 5] |= 1 << (crc & 0x1f);
3062 CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
3063 CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
3064 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
3068 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
3070 struct jme_softc *sc = arg1;
3071 struct ifnet *ifp = &sc->arpcom.ac_if;
3074 ifnet_serialize_all(ifp);
3076 v = sc->jme_tx_coal_to;
3077 error = sysctl_handle_int(oidp, &v, 0, req);
3078 if (error || req->newptr == NULL)
3081 if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
3086 if (v != sc->jme_tx_coal_to) {
3087 sc->jme_tx_coal_to = v;
3088 if (ifp->if_flags & IFF_RUNNING)
3089 jme_set_tx_coal(sc);
3092 ifnet_deserialize_all(ifp);
3097 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
3099 struct jme_softc *sc = arg1;
3100 struct ifnet *ifp = &sc->arpcom.ac_if;
3103 ifnet_serialize_all(ifp);
3105 v = sc->jme_tx_coal_pkt;
3106 error = sysctl_handle_int(oidp, &v, 0, req);
3107 if (error || req->newptr == NULL)
3110 if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
3115 if (v != sc->jme_tx_coal_pkt) {
3116 sc->jme_tx_coal_pkt = v;
3117 if (ifp->if_flags & IFF_RUNNING)
3118 jme_set_tx_coal(sc);
3121 ifnet_deserialize_all(ifp);
3126 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
3128 struct jme_softc *sc = arg1;
3129 struct ifnet *ifp = &sc->arpcom.ac_if;
3132 ifnet_serialize_all(ifp);
3134 v = sc->jme_rx_coal_to;
3135 error = sysctl_handle_int(oidp, &v, 0, req);
3136 if (error || req->newptr == NULL)
3139 if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
3144 if (v != sc->jme_rx_coal_to) {
3145 sc->jme_rx_coal_to = v;
3146 if (ifp->if_flags & IFF_RUNNING)
3147 jme_set_rx_coal(sc);
3150 ifnet_deserialize_all(ifp);
3155 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
3157 struct jme_softc *sc = arg1;
3158 struct ifnet *ifp = &sc->arpcom.ac_if;
3161 ifnet_serialize_all(ifp);
3163 v = sc->jme_rx_coal_pkt;
3164 error = sysctl_handle_int(oidp, &v, 0, req);
3165 if (error || req->newptr == NULL)
3168 if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3173 if (v != sc->jme_rx_coal_pkt) {
3174 sc->jme_rx_coal_pkt = v;
3175 if (ifp->if_flags & IFF_RUNNING)
3176 jme_set_rx_coal(sc);
3179 ifnet_deserialize_all(ifp);
3184 jme_set_tx_coal(struct jme_softc *sc)
3188 reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3190 reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3191 PCCTX_COAL_PKT_MASK;
3192 reg |= PCCTX_COAL_TXQ0;
3193 CSR_WRITE_4(sc, JME_PCCTX, reg);
3197 jme_set_rx_coal(struct jme_softc *sc)
3202 reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3204 reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3205 PCCRX_COAL_PKT_MASK;
3206 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
3207 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3210 #ifdef DEVICE_POLLING
3213 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3215 struct jme_softc *sc = ifp->if_softc;
3219 ASSERT_SERIALIZED(&sc->jme_serialize);
3223 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3226 case POLL_DEREGISTER:
3227 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3230 case POLL_AND_CHECK_STATUS:
3232 status = CSR_READ_4(sc, JME_INTR_STATUS);
3234 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3235 struct jme_rxdata *rdata =
3236 &sc->jme_cdata.jme_rx_data[r];
3238 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3239 jme_rxeof(rdata, count);
3240 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3243 if (status & INTR_RXQ_DESC_EMPTY) {
3244 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3245 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3246 RXCSR_RX_ENB | RXCSR_RXQ_START);
3249 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3251 if (!ifq_is_empty(&ifp->if_snd))
3253 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3258 #endif /* DEVICE_POLLING */
3261 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3266 asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
3267 error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3268 JME_RX_RING_ALIGN, 0,
3269 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3270 asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3272 device_printf(rdata->jme_sc->jme_dev,
3273 "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3276 rdata->jme_rx_ring_tag = dmem.dmem_tag;
3277 rdata->jme_rx_ring_map = dmem.dmem_map;
3278 rdata->jme_rx_ring = dmem.dmem_addr;
3279 rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3285 jme_rxbuf_dma_filter(void *arg __unused, bus_addr_t paddr)
3287 if ((paddr & 0xffffffff) == 0) {
3289 * Don't allow lower 32bits of the RX buffer's
3290 * physical address to be 0, else it will break
3291 * hardware pending RSS information delivery
3292 * detection on RX path.
3300 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3305 lowaddr = BUS_SPACE_MAXADDR;
3306 if (JME_ENABLE_HWRSS(rdata->jme_sc)) {
3307 /* jme_rxbuf_dma_filter will be called */
3308 lowaddr = BUS_SPACE_MAXADDR_32BIT;
3311 /* Create tag for Rx buffers. */
3312 error = bus_dma_tag_create(
3313 rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3314 JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */
3315 lowaddr, /* lowaddr */
3316 BUS_SPACE_MAXADDR, /* highaddr */
3317 jme_rxbuf_dma_filter, NULL, /* filter, filterarg */
3318 MCLBYTES, /* maxsize */
3320 MCLBYTES, /* maxsegsize */
3321 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3322 &rdata->jme_rx_tag);
3324 device_printf(rdata->jme_sc->jme_dev,
3325 "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3329 /* Create DMA maps for Rx buffers. */
3330 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3331 &rdata->jme_rx_sparemap);
3333 device_printf(rdata->jme_sc->jme_dev,
3334 "could not create %dth spare Rx dmamap.\n",
3336 bus_dma_tag_destroy(rdata->jme_rx_tag);
3337 rdata->jme_rx_tag = NULL;
3340 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3341 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3343 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3348 device_printf(rdata->jme_sc->jme_dev,
3349 "could not create %dth Rx dmamap "
3350 "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3352 for (j = 0; j < i; ++j) {
3353 rxd = &rdata->jme_rxdesc[j];
3354 bus_dmamap_destroy(rdata->jme_rx_tag,
3357 bus_dmamap_destroy(rdata->jme_rx_tag,
3358 rdata->jme_rx_sparemap);
3359 bus_dma_tag_destroy(rdata->jme_rx_tag);
3360 rdata->jme_rx_tag = NULL;
3368 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3372 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3373 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3375 if (status & rdata->jme_rx_coal) {
3376 lwkt_serialize_enter(&rdata->jme_rx_serialize);
3377 jme_rxeof(rdata, -1);
3378 lwkt_serialize_exit(&rdata->jme_rx_serialize);
3384 jme_enable_rss(struct jme_softc *sc)
3387 uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3390 KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3391 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
3392 ("%s: invalid # of RX rings (%d)",
3393 sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
3395 rssc = RSSC_HASH_64_ENTRY;
3396 rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3397 rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
3398 JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3399 CSR_WRITE_4(sc, JME_RSSC, rssc);
3401 toeplitz_get_key(key, sizeof(key));
3402 for (i = 0; i < RSSKEY_NREGS; ++i) {
3405 keyreg = RSSKEY_REGVAL(key, i);
3406 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3408 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3412 * Create redirect table in following fashion:
3413 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3416 for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3419 q = i % sc->jme_cdata.jme_rx_ring_cnt;
3420 ind |= q << (i * 8);
3422 JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3424 for (i = 0; i < RSSTBL_NREGS; ++i)
3425 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3429 jme_disable_rss(struct jme_softc *sc)
3431 CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3435 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3437 struct jme_softc *sc = ifp->if_softc;
3439 ifnet_serialize_array_enter(sc->jme_serialize_arr,
3440 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3444 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3446 struct jme_softc *sc = ifp->if_softc;
3448 ifnet_serialize_array_exit(sc->jme_serialize_arr,
3449 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3453 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3455 struct jme_softc *sc = ifp->if_softc;
3457 return ifnet_serialize_array_try(sc->jme_serialize_arr,
3458 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE, slz);
3464 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3465 boolean_t serialized)
3467 struct jme_softc *sc = ifp->if_softc;
3469 ifnet_serialize_array_assert(sc->jme_serialize_arr,
3470 sc->jme_serialize_cnt, JME_TX_SERIALIZE, JME_RX_SERIALIZE,
3474 #endif /* INVARIANTS */
3477 jme_msix_try_alloc(device_t dev)
3479 struct jme_softc *sc = device_get_softc(dev);
3480 struct jme_msix_data *msix;
3481 int error, i, r, msix_enable, msix_count;
3482 int offset, offset_def;
3484 msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
3485 KKASSERT(msix_count <= JME_NMSIX);
3487 msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3490 * We leave the 1st MSI-X vector unused, so we
3491 * actually need msix_count + 1 MSI-X vectors.
3493 if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3496 for (i = 0; i < msix_count; ++i)
3497 sc->jme_msix[i].jme_msix_rid = -1;
3505 offset_def = device_get_unit(dev) % ncpus2;
3506 offset = device_getenv_int(dev, "msix.txoff", offset_def);
3507 if (offset >= ncpus2) {
3508 device_printf(dev, "invalid msix.txoff %d, use %d\n",
3509 offset, offset_def);
3510 offset = offset_def;
3513 msix = &sc->jme_msix[i++];
3514 msix->jme_msix_cpuid = offset;
3515 sc->jme_tx_cpuid = msix->jme_msix_cpuid;
3516 msix->jme_msix_arg = &sc->jme_cdata;
3517 msix->jme_msix_func = jme_msix_tx;
3518 msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3519 msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3520 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3521 device_get_nameunit(dev));
3527 if (sc->jme_cdata.jme_rx_ring_cnt == ncpus2) {
3530 offset_def = (sc->jme_cdata.jme_rx_ring_cnt *
3531 device_get_unit(dev)) % ncpus2;
3533 offset = device_getenv_int(dev, "msix.rxoff", offset_def);
3534 if (offset >= ncpus2 ||
3535 offset % sc->jme_cdata.jme_rx_ring_cnt != 0) {
3536 device_printf(dev, "invalid msix.rxoff %d, use %d\n",
3537 offset, offset_def);
3538 offset = offset_def;
3542 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3543 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3545 msix = &sc->jme_msix[i++];
3546 msix->jme_msix_cpuid = r + offset;
3547 KKASSERT(msix->jme_msix_cpuid < ncpus2);
3548 msix->jme_msix_arg = rdata;
3549 msix->jme_msix_func = jme_msix_rx;
3550 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3551 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3552 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3553 "%s rx%d", device_get_nameunit(dev), r);
3556 KKASSERT(i == msix_count);
3558 error = pci_setup_msix(dev);
3562 /* Setup jme_msix_cnt early, so we could cleanup */
3563 sc->jme_msix_cnt = msix_count;
3565 for (i = 0; i < msix_count; ++i) {
3566 msix = &sc->jme_msix[i];
3568 msix->jme_msix_vector = i + 1;
3569 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3570 &msix->jme_msix_rid, msix->jme_msix_cpuid);
3574 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3575 &msix->jme_msix_rid, RF_ACTIVE);
3576 if (msix->jme_msix_res == NULL) {
3582 for (i = 0; i < JME_INTR_CNT; ++i) {
3583 uint32_t intr_mask = (1 << i);
3586 if ((JME_INTRS & intr_mask) == 0)
3589 for (x = 0; x < msix_count; ++x) {
3590 msix = &sc->jme_msix[x];
3591 if (msix->jme_msix_intrs & intr_mask) {
3594 reg = i / JME_MSINUM_FACTOR;
3595 KKASSERT(reg < JME_MSINUM_CNT);
3597 shift = (i % JME_MSINUM_FACTOR) * 4;
3599 sc->jme_msinum[reg] |=
3600 (msix->jme_msix_vector << shift);
3608 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3609 device_printf(dev, "MSINUM%d: %#x\n", i,
3614 pci_enable_msix(dev);
3615 sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3623 jme_intr_alloc(device_t dev)
3625 struct jme_softc *sc = device_get_softc(dev);
3628 jme_msix_try_alloc(dev);
3630 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3631 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3632 &sc->jme_irq_rid, &irq_flags);
3634 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3635 &sc->jme_irq_rid, irq_flags);
3636 if (sc->jme_irq_res == NULL) {
3637 device_printf(dev, "can't allocate irq\n");
3645 jme_msix_free(device_t dev)
3647 struct jme_softc *sc = device_get_softc(dev);
3650 KKASSERT(sc->jme_msix_cnt > 1);
3652 for (i = 0; i < sc->jme_msix_cnt; ++i) {
3653 struct jme_msix_data *msix = &sc->jme_msix[i];
3655 if (msix->jme_msix_res != NULL) {
3656 bus_release_resource(dev, SYS_RES_IRQ,
3657 msix->jme_msix_rid, msix->jme_msix_res);
3658 msix->jme_msix_res = NULL;
3660 if (msix->jme_msix_rid >= 0) {
3661 pci_release_msix_vector(dev, msix->jme_msix_rid);
3662 msix->jme_msix_rid = -1;
3665 pci_teardown_msix(dev);
3669 jme_intr_free(device_t dev)
3671 struct jme_softc *sc = device_get_softc(dev);
3673 if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3674 if (sc->jme_irq_res != NULL) {
3675 bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3678 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3679 pci_release_msi(dev);
3686 jme_msix_tx(void *xcd)
3688 struct jme_chain_data *cd = xcd;
3689 struct jme_softc *sc = cd->jme_sc;
3690 struct ifnet *ifp = &sc->arpcom.ac_if;
3692 ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3694 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3696 CSR_WRITE_4(sc, JME_INTR_STATUS,
3697 INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3699 if (ifp->if_flags & IFF_RUNNING) {
3701 if (!ifq_is_empty(&ifp->if_snd))
3705 CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3709 jme_msix_rx(void *xrdata)
3711 struct jme_rxdata *rdata = xrdata;
3712 struct jme_softc *sc = rdata->jme_sc;
3713 struct ifnet *ifp = &sc->arpcom.ac_if;
3716 ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3718 CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3719 (rdata->jme_rx_coal | rdata->jme_rx_empty));
3721 status = CSR_READ_4(sc, JME_INTR_STATUS);
3722 status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3724 if (status & rdata->jme_rx_coal)
3725 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3726 CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3728 if (ifp->if_flags & IFF_RUNNING) {
3729 if (status & rdata->jme_rx_coal)
3730 jme_rxeof(rdata, -1);
3732 if (status & rdata->jme_rx_empty) {
3733 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3734 RXCSR_RX_ENB | RXCSR_RXQ_START);
3735 rdata->jme_rx_emp++;
3739 CSR_WRITE_4(sc, JME_INTR_MASK_SET,
3740 (rdata->jme_rx_coal | rdata->jme_rx_empty));
3744 jme_set_msinum(struct jme_softc *sc)
3748 for (i = 0; i < JME_MSINUM_CNT; ++i)
3749 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3753 jme_intr_setup(device_t dev)
3755 struct jme_softc *sc = device_get_softc(dev);
3756 struct ifnet *ifp = &sc->arpcom.ac_if;
3759 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3760 return jme_msix_setup(dev);
3762 error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3763 jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3765 device_printf(dev, "could not set up interrupt handler.\n");
3769 ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3770 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3775 jme_intr_teardown(device_t dev)
3777 struct jme_softc *sc = device_get_softc(dev);
3779 if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3780 jme_msix_teardown(dev, sc->jme_msix_cnt);
3782 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3786 jme_msix_setup(device_t dev)
3788 struct jme_softc *sc = device_get_softc(dev);
3789 struct ifnet *ifp = &sc->arpcom.ac_if;
3792 for (x = 0; x < sc->jme_msix_cnt; ++x) {
3793 struct jme_msix_data *msix = &sc->jme_msix[x];
3796 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3797 INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3798 &msix->jme_msix_handle, msix->jme_msix_serialize,
3799 msix->jme_msix_desc);
3801 device_printf(dev, "could not set up %s "
3802 "interrupt handler.\n", msix->jme_msix_desc);
3803 jme_msix_teardown(dev, x);
3807 ifp->if_cpuid = sc->jme_tx_cpuid;
3812 jme_msix_teardown(device_t dev, int msix_count)
3814 struct jme_softc *sc = device_get_softc(dev);
3817 for (x = 0; x < msix_count; ++x) {
3818 struct jme_msix_data *msix = &sc->jme_msix[x];
3820 bus_teardown_intr(dev, msix->jme_msix_res,
3821 msix->jme_msix_handle);
3826 jme_serialize_skipmain(struct jme_softc *sc)
3828 lwkt_serialize_array_enter(sc->jme_serialize_arr,
3829 sc->jme_serialize_cnt, 1);
3833 jme_deserialize_skipmain(struct jme_softc *sc)
3835 lwkt_serialize_array_exit(sc->jme_serialize_arr,
3836 sc->jme_serialize_cnt, 1);