2 * Copyright (c) 1997, 2001 Hellmuth Michaelis. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 *---------------------------------------------------------------------------
27 * i4b_isac.c - i4b siemens isdn chipset driver ISAC handler
28 * ---------------------------------------------------------
30 * $FreeBSD: src/sys/i4b/layer1/isic/i4b_isac.c,v 1.5.2.1 2001/08/10 14:08:38 obrien Exp $
31 * $DragonFly: src/sys/net/i4b/layer1/isic/i4b_isac.c,v 1.4 2003/08/07 21:17:26 dillon Exp $
33 * last edit-date: [Wed Jan 24 09:10:36 2001]
35 *---------------------------------------------------------------------------*/
43 #include <sys/param.h>
44 #include <sys/systm.h>
46 #include <sys/socket.h>
50 #include <net/i4b/include/machine/i4b_debug.h>
51 #include <net/i4b/include/machine/i4b_ioctl.h>
52 #include <net/i4b/include/machine/i4b_trace.h>
54 #include "../i4b_l1.h"
60 #include "../../include/i4b_global.h"
61 #include "../../include/i4b_mbuf.h"
63 static u_char isic_isac_exir_hdlr(struct l1_softc *sc, u_char exir);
64 static void isic_isac_ind_hdlr(struct l1_softc *sc, int ind);
66 /*---------------------------------------------------------------------------*
67 * ISAC interrupt service routine
68 *---------------------------------------------------------------------------*/
70 isic_isac_irq(struct l1_softc *sc, int ista)
73 NDBGL1(L1_F_MSG, "unit %d: ista = 0x%02x", sc->sc_unit, ista);
75 if(ista & ISAC_ISTA_EXI) /* extended interrupt */
77 c |= isic_isac_exir_hdlr(sc, ISAC_READ(I_EXIR));
80 if(ista & ISAC_ISTA_RME) /* receive message end */
85 /* get rx status register */
87 rsta = ISAC_READ(I_RSTA);
89 if((rsta & ISAC_RSTA_MASK) != 0x20)
93 if(!(rsta & ISAC_RSTA_CRC)) /* CRC error */
96 NDBGL1(L1_I_ERR, "unit %d: CRC error", sc->sc_unit);
99 if(rsta & ISAC_RSTA_RDO) /* ReceiveDataOverflow */
102 NDBGL1(L1_I_ERR, "unit %d: Data Overrun error", sc->sc_unit);
105 if(rsta & ISAC_RSTA_RAB) /* ReceiveABorted */
108 NDBGL1(L1_I_ERR, "unit %d: Receive Aborted error", sc->sc_unit);
112 NDBGL1(L1_I_ERR, "unit %d: RME unknown error, RSTA = 0x%02x!", sc->sc_unit, rsta);
114 i4b_Dfreembuf(sc->sc_ibuf);
116 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
122 ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES);
128 rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1));
131 rest = ISAC_FIFO_LEN;
133 if(sc->sc_ibuf == NULL)
135 if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
136 sc->sc_ib = sc->sc_ibuf->m_data;
138 panic("isic_isac_irq: RME, i4b_Dgetmbuf returns NULL!\n");
142 if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
144 ISAC_RDFIFO(sc->sc_ib, rest);
147 sc->sc_ibuf->m_pkthdr.len =
148 sc->sc_ibuf->m_len = sc->sc_ilen;
150 if(sc->sc_trace & TRACE_D_RX)
153 hdr.unit = L0ISICUNIT(sc->sc_unit);
156 hdr.count = ++sc->sc_trace_dcount;
158 i4b_l1_trace_ind(&hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
164 (ctrl_desc[sc->sc_unit].protocol != PROTOCOL_D64S))
166 i4b_l1_ph_data_ind(L0ISICUNIT(sc->sc_unit), sc->sc_ibuf);
170 i4b_Dfreembuf(sc->sc_ibuf);
175 NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
176 i4b_Dfreembuf(sc->sc_ibuf);
177 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
185 if(ista & ISAC_ISTA_RPF) /* receive fifo full */
187 if(sc->sc_ibuf == NULL)
189 if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
190 sc->sc_ib= sc->sc_ibuf->m_data;
192 panic("isic_isac_irq: RPF, i4b_Dgetmbuf returns NULL!\n");
196 if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN))
198 ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN);
199 sc->sc_ilen += ISAC_FIFO_LEN;
200 sc->sc_ib += ISAC_FIFO_LEN;
205 NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
206 i4b_Dfreembuf(sc->sc_ibuf);
210 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
214 if(ista & ISAC_ISTA_XPR) /* transmit fifo empty (XPR bit set) */
216 if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
218 sc->sc_freeflag = sc->sc_freeflag2;
219 sc->sc_obuf = sc->sc_obuf2;
220 sc->sc_op = sc->sc_obuf->m_data;
221 sc->sc_ol = sc->sc_obuf->m_len;
224 printf("ob2=%x, op=%x, ol=%d, f=%d #",
234 printf("ob=%x, op=%x, ol=%d, f=%d #",
244 ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN));
246 if(sc->sc_ol > ISAC_FIFO_LEN) /* length > 32 ? */
248 sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */
249 sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */
250 c |= ISAC_CMDR_XTF; /* set XTF bit */
256 i4b_Dfreembuf(sc->sc_obuf);
263 c |= ISAC_CMDR_XTF | ISAC_CMDR_XME;
268 sc->sc_state &= ~ISAC_TX_ACTIVE;
272 if(ista & ISAC_ISTA_CISQ) /* channel status change CISQ */
276 /* get command/indication rx register*/
278 ci = ISAC_READ(I_CIRR);
280 /* if S/Q IRQ, read SQC reg to clr SQC IRQ */
282 if(ci & ISAC_CIRR_SQC)
283 (void) ISAC_READ(I_SQRR);
285 /* C/I code change IRQ (flag already cleared by CIRR read) */
287 if(ci & ISAC_CIRR_CIC0)
288 isic_isac_ind_hdlr(sc, (ci >> 2) & 0xf);
293 ISAC_WRITE(I_CMDR, c);
298 /*---------------------------------------------------------------------------*
299 * ISAC L1 Extended IRQ handler
300 *---------------------------------------------------------------------------*/
302 isic_isac_exir_hdlr(struct l1_softc *sc, u_char exir)
306 if(exir & ISAC_EXIR_XMR)
308 NDBGL1(L1_I_ERR, "EXIRQ Tx Message Repeat");
313 if(exir & ISAC_EXIR_XDU)
315 NDBGL1(L1_I_ERR, "EXIRQ Tx Data Underrun");
320 if(exir & ISAC_EXIR_PCE)
322 NDBGL1(L1_I_ERR, "EXIRQ Protocol Error");
325 if(exir & ISAC_EXIR_RFO)
327 NDBGL1(L1_I_ERR, "EXIRQ Rx Frame Overflow");
329 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
332 if(exir & ISAC_EXIR_SOV)
334 NDBGL1(L1_I_ERR, "EXIRQ Sync Xfer Overflow");
337 if(exir & ISAC_EXIR_MOS)
339 NDBGL1(L1_I_ERR, "EXIRQ Monitor Status");
342 if(exir & ISAC_EXIR_SAW)
344 /* cannot happen, STCR:TSF is set to 0 */
346 NDBGL1(L1_I_ERR, "EXIRQ Subscriber Awake");
349 if(exir & ISAC_EXIR_WOV)
351 /* cannot happen, STCR:TSF is set to 0 */
353 NDBGL1(L1_I_ERR, "EXIRQ Watchdog Timer Overflow");
359 /*---------------------------------------------------------------------------*
360 * ISAC L1 Indication handler
361 *---------------------------------------------------------------------------*/
363 isic_isac_ind_hdlr(struct l1_softc *sc, int ind)
370 NDBGL1(L1_I_CICO, "rx AI8 in state %s", isic_printstate(sc));
371 if(sc->sc_bustyp == BUS_TYPE_IOM2)
372 isic_isac_l1_cmd(sc, CMD_AR8);
374 i4b_l1_mph_status_ind(L0ISICUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
377 case ISAC_CIRR_IAI10:
378 NDBGL1(L1_I_CICO, "rx AI10 in state %s", isic_printstate(sc));
379 if(sc->sc_bustyp == BUS_TYPE_IOM2)
380 isic_isac_l1_cmd(sc, CMD_AR10);
382 i4b_l1_mph_status_ind(L0ISICUNIT(sc->sc_unit), STI_L1STAT, LAYER_ACTIVE, NULL);
386 NDBGL1(L1_I_CICO, "rx RSY in state %s", isic_printstate(sc));
391 NDBGL1(L1_I_CICO, "rx PU in state %s", isic_printstate(sc));
396 NDBGL1(L1_I_CICO, "rx DR in state %s", isic_printstate(sc));
397 isic_isac_l1_cmd(sc, CMD_DIU);
402 NDBGL1(L1_I_CICO, "rx DID in state %s", isic_printstate(sc));
404 i4b_l1_mph_status_ind(L0ISICUNIT(sc->sc_unit), STI_L1STAT, LAYER_IDLE, NULL);
408 NDBGL1(L1_I_CICO, "rx DIS in state %s", isic_printstate(sc));
413 NDBGL1(L1_I_CICO, "rx EI in state %s", isic_printstate(sc));
414 isic_isac_l1_cmd(sc, CMD_DIU);
419 NDBGL1(L1_I_CICO, "rx ARD in state %s", isic_printstate(sc));
424 NDBGL1(L1_I_CICO, "rx TI in state %s", isic_printstate(sc));
429 NDBGL1(L1_I_CICO, "rx ATI in state %s", isic_printstate(sc));
434 NDBGL1(L1_I_CICO, "rx SD in state %s", isic_printstate(sc));
439 NDBGL1(L1_I_ERR, "UNKNOWN Indication 0x%x in state %s", ind, isic_printstate(sc));
443 isic_next_state(sc, event);
446 /*---------------------------------------------------------------------------*
447 * execute a layer 1 command
448 *---------------------------------------------------------------------------*/
450 isic_isac_l1_cmd(struct l1_softc *sc, int command)
454 #ifdef I4B_SMP_WORKAROUND
456 /* XXXXXXXXXXXXXXXXXXX */
459 * patch from Wolfgang Helbig:
461 * Here is a patch that makes i4b work on an SMP:
462 * The card (TELES 16.3) didn't interrupt on an SMP machine.
463 * This is a gross workaround, but anyway it works *and* provides
464 * some information as how to finally fix this problem.
467 HSCX_WRITE(0, H_MASK, 0xff);
468 HSCX_WRITE(1, H_MASK, 0xff);
469 ISAC_WRITE(I_MASK, 0xff);
471 HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
472 HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
473 ISAC_WRITE(I_MASK, ISAC_IMASK);
475 /* XXXXXXXXXXXXXXXXXXX */
477 #endif /* I4B_SMP_WORKAROUND */
479 if(command < 0 || command > CMD_ILL)
481 NDBGL1(L1_I_ERR, "illegal cmd 0x%x in state %s", command, isic_printstate(sc));
485 if(sc->sc_bustyp == BUS_TYPE_IOM2)
493 NDBGL1(L1_I_CICO, "tx TIM in state %s", isic_printstate(sc));
494 cmd |= (ISAC_CIXR_CTIM << 2);
498 NDBGL1(L1_I_CICO, "tx RS in state %s", isic_printstate(sc));
499 cmd |= (ISAC_CIXR_CRS << 2);
503 NDBGL1(L1_I_CICO, "tx AR8 in state %s", isic_printstate(sc));
504 cmd |= (ISAC_CIXR_CAR8 << 2);
508 NDBGL1(L1_I_CICO, "tx AR10 in state %s", isic_printstate(sc));
509 cmd |= (ISAC_CIXR_CAR10 << 2);
513 NDBGL1(L1_I_CICO, "tx DIU in state %s", isic_printstate(sc));
514 cmd |= (ISAC_CIXR_CDIU << 2);
517 ISAC_WRITE(I_CIXR, cmd);
520 /*---------------------------------------------------------------------------*
521 * L1 ISAC initialization
522 *---------------------------------------------------------------------------*/
524 isic_isac_init(struct l1_softc *sc)
526 ISAC_IMASK = 0xff; /* disable all irqs */
528 ISAC_WRITE(I_MASK, ISAC_IMASK);
530 if(sc->sc_bustyp != BUS_TYPE_IOM2)
532 NDBGL1(L1_I_SETUP, "configuring for IOM-1 mode");
534 /* ADF2: Select mode IOM-1 */
535 ISAC_WRITE(I_ADF2, 0x00);
537 /* SPCR: serial port control register:
538 * SPU - software power up = 0
539 * SAC - SIP port high Z
540 * SPM - timing mode 0
541 * TLP - test loop = 0
542 * C1C, C2C - B1 and B2 switched to/from SPa
544 ISAC_WRITE(I_SPCR, ISAC_SPCR_C1C1|ISAC_SPCR_C2C1);
546 /* SQXR: S/Q channel xmit register:
547 * SQIE - S/Q IRQ enable = 0
548 * SQX1-4 - Fa bits = 1
550 ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
552 /* ADF1: additional feature reg 1:
554 * TEM - test mode = 0
555 * PFS - pre-filter = 0
556 * CFS - IOM clock/frame always active
557 * FSC1/2 - polarity of 8kHz strobe
558 * ITF - interframe fill = idle
560 ISAC_WRITE(I_ADF1, ISAC_ADF1_FC2); /* ADF1 */
562 /* STCR: sync transfer control reg:
563 * TSF - terminal secific functions = 0
564 * TBA - TIC bus address = 7
567 ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
569 /* MODE: Mode Register:
570 * MDSx - transparent mode 2
571 * TMD - timer mode = external
572 * RAC - Receiver enabled
573 * DIMx - digital i/f mode
575 ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
579 NDBGL1(L1_I_SETUP, "configuring for IOM-2 mode");
581 /* ADF2: Select mode IOM-2 */
582 ISAC_WRITE(I_ADF2, ISAC_ADF2_IMS);
584 /* SPCR: serial port control register:
585 * SPU - software power up = 0
586 * SPM - timing mode 0
587 * TLP - test loop = 0
588 * C1C, C2C - B1 + C1 and B2 + IC2 monitoring
590 ISAC_WRITE(I_SPCR, 0x00);
592 /* SQXR: S/Q channel xmit register:
593 * IDC - IOM direction = 0 (master)
594 * CFS - Config Select = 0 (clock always active)
595 * CI1E - C/I channel 1 IRQ enable = 0
596 * SQIE - S/Q IRQ enable = 0
597 * SQX1-4 - Fa bits = 1
599 ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
601 /* ADF1: additional feature reg 1:
603 * TEM - test mode = 0
604 * PFS - pre-filter = 0
605 * IOF - IOM i/f off = 0
606 * ITF - interframe fill = idle
608 ISAC_WRITE(I_ADF1, 0x00);
610 /* STCR: sync transfer control reg:
611 * TSF - terminal secific functions = 0
612 * TBA - TIC bus address = 7
615 ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
617 /* MODE: Mode Register:
618 * MDSx - transparent mode 2
619 * TMD - timer mode = external
620 * RAC - Receiver enabled
621 * DIMx - digital i/f mode
623 ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
628 * XXX a transmitter reset causes an ISAC tx IRQ which will not
629 * be serviced at attach time under some circumstances leaving
630 * the associated IRQ line on the ISA bus active. This prevents
631 * any further interrupts to be serviced because no low -> high
632 * transition can take place anymore. (-hm)
636 * RRES - HDLC receiver reset
637 * XRES - transmitter reset
639 ISAC_WRITE(I_CMDR, ISAC_CMDR_RRES|ISAC_CMDR_XRES);
643 /* enabled interrupts:
644 * ===================
645 * RME - receive message end
646 * RPF - receive pool full
647 * XPR - transmit pool ready
648 * CISQ - CI or S/Q channel change
649 * EXI - extended interrupt
652 ISAC_IMASK = ISAC_MASK_RSC | /* auto mode only */
653 ISAC_MASK_TIN | /* timer irq */
654 ISAC_MASK_SIN; /* sync xfer irq */
656 ISAC_WRITE(I_MASK, ISAC_IMASK);
661 #endif /* NISIC > 0 */