1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */
4 /******************************************************************************
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
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18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
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24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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28 * in the file called COPYING.
30 * Contact Information:
31 * Intel Linux Wireless <ilw@linux.intel.com>
32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *****************************************************************************/
66 #ifndef __IF_IWM_REG_H__
67 #define __IF_IWM_REG_H__
69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
73 * CSR (control and status registers)
75 * CSR registers are mapped directly into PCI bus space, and are accessible
76 * whenever platform supplies power to device, even when device is in
77 * low power states due to driver-invoked device resets
78 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
80 * Use iwl_write32() and iwl_read32() family to access these registers;
81 * these provide simple PCI bus access, without waking up the MAC.
82 * Do not use iwl_write_direct32() family for these registers;
83 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
84 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
87 * NOTE: Device does need to be awake in order to read this memory
88 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
90 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
91 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
92 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
93 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
94 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
95 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
96 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
97 #define IWM_CSR_GP_CNTRL (0x024)
99 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
100 #define IWM_CSR_INT_PERIODIC_REG (0x005)
103 * Hardware revision info
106 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
107 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
108 * 1-0: "Dash" (-) value, as in A-1, etc.
110 #define IWM_CSR_HW_REV (0x028)
113 * EEPROM and OTP (one-time-programmable) memory reads
115 * NOTE: Device must be awake, initialized via apm_ops.init(),
118 #define IWM_CSR_EEPROM_REG (0x02c)
119 #define IWM_CSR_EEPROM_GP (0x030)
120 #define IWM_CSR_OTP_GP_REG (0x034)
122 #define IWM_CSR_GIO_REG (0x03C)
123 #define IWM_CSR_GP_UCODE_REG (0x048)
124 #define IWM_CSR_GP_DRIVER_REG (0x050)
127 * UCODE-DRIVER GP (general purpose) mailbox registers.
128 * SET/CLR registers set/clear bit(s) if "1" is written.
130 #define IWM_CSR_UCODE_DRV_GP1 (0x054)
131 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
132 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
133 #define IWM_CSR_UCODE_DRV_GP2 (0x060)
135 #define IWM_CSR_MBOX_SET_REG (0x088)
136 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20
138 #define IWM_CSR_LED_REG (0x094)
139 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
140 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
143 /* GIO Chicken Bits (PCI Express bus link power management) */
144 #define IWM_CSR_GIO_CHICKEN_BITS (0x100)
146 /* Analog phase-lock-loop configuration */
147 #define IWM_CSR_ANA_PLL_CFG (0x20c)
150 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
151 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
152 * See also IWM_CSR_HW_REV register.
154 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
155 * 1-0: "Dash" (-) value, as in C-1, etc.
157 #define IWM_CSR_HW_REV_WA_REG (0x22C)
159 #define IWM_CSR_DBG_HPET_MEM_REG (0x240)
160 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
162 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */
163 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
164 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
165 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
166 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
167 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
170 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
172 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
173 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
174 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
175 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
179 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
180 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
181 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
182 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
183 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
184 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
185 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
187 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
188 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
190 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
191 * acknowledged (reset) by host writing "1" to flagged bits. */
192 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
193 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
194 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
195 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
196 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
197 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
198 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
199 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
200 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
201 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
202 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
204 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
205 IWM_CSR_INT_BIT_HW_ERR | \
206 IWM_CSR_INT_BIT_FH_TX | \
207 IWM_CSR_INT_BIT_SW_ERR | \
208 IWM_CSR_INT_BIT_RF_KILL | \
209 IWM_CSR_INT_BIT_SW_RX | \
210 IWM_CSR_INT_BIT_WAKEUP | \
211 IWM_CSR_INT_BIT_ALIVE | \
212 IWM_CSR_INT_BIT_RX_PERIODIC)
214 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
215 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
216 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
217 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
218 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
219 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
220 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
222 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
223 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
224 IWM_CSR_FH_INT_BIT_RX_CHNL0)
226 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
227 IWM_CSR_FH_INT_BIT_TX_CHNL0)
230 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
231 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
232 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
235 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
236 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
237 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
238 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
239 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
240 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
243 * GP (general purpose) CONTROL REGISTER
246 * Indicates state of (platform's) hardware RF-Kill switch
247 * 26-24: POWER_SAVE_TYPE
248 * Indicates current power-saving mode:
249 * 000 -- No power saving
250 * 001 -- MAC power-down
251 * 010 -- PHY (radio) power-down
254 * Indicates current system configuration, reflecting pins on chip
255 * as forced high/low by device circuit board.
257 * Indicates MAC is entering a power-saving sleep power-down.
258 * Not a good time to access device-internal resources.
260 * Host sets this to request and maintain MAC wakeup, to allow host
261 * access to device-internal resources. Host must wait for
262 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
265 * Host sets this to put device into fully operational D0 power mode.
266 * Host resets this after SW_RESET to put device into low power mode.
268 * Indicates MAC (ucode processor, etc.) is powered up and can run.
269 * Internal resources are accessible.
270 * NOTE: This does not indicate that the processor is actually running.
271 * NOTE: This does not indicate that device has completed
272 * init or post-power-down restore of internal SRAM memory.
273 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
274 * SRAM is restored and uCode is in normal operation mode.
275 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
276 * do not need to save/restore it.
277 * NOTE: After device reset, this bit remains "0" until host sets
280 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
281 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
282 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
283 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
285 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
287 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
288 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
289 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
293 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
294 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
300 IWM_SILICON_A_STEP = 0,
306 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
307 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
308 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
309 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
310 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
311 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
312 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
313 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
314 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
315 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
316 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
317 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
318 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
319 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
320 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
321 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
322 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210)
323 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
326 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
327 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
328 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
329 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
332 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
333 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
334 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
335 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
336 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
337 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
339 /* One-time-programmable memory general purpose reg */
340 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
341 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
342 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
343 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
346 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
347 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
348 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
349 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
350 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
354 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
357 * UCODE-DRIVER GP (general purpose) mailbox register 1
358 * Host driver and uCode write and/or read this register to communicate with
362 * Host sets this to request permanent halt of uCode, same as
363 * sending CARD_STATE command with "halt" bit set.
365 * Host sets this to request exit from CT_KILL state, i.e. host thinks
366 * device temperature is low enough to continue normal operation.
368 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
369 * to release uCode to clear all Tx and command queues, enter
370 * unassociated mode, and power down.
371 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
373 * Host sets this when issuing CARD_STATE command to request
376 * uCode sets this when preparing a power-saving power-down.
377 * uCode resets this when power-up is complete and SRAM is sane.
378 * NOTE: device saves internal SRAM data to host when powering down,
379 * and must restore this data after powering back up.
380 * MAC_SLEEP is the best indication that restore is complete.
381 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
382 * do not need to save/restore it.
384 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
385 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
386 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
387 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
388 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
391 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
392 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
393 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
394 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
395 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
396 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
398 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
400 /* GIO Chicken Bits (PCI Express bus link power management) */
401 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
402 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
405 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
406 #define IWM_CSR_LED_REG_TURN_ON (0x60)
407 #define IWM_CSR_LED_REG_TURN_OFF (0x20)
410 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
413 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
416 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
417 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
418 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
420 /* SECURE boot registers */
421 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
422 enum iwm_secure_boot_config_reg {
423 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
424 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
427 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
428 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
429 enum iwm_secure_boot_status_reg {
430 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
431 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
432 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
433 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
434 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
437 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0
438 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70
439 enum iwm_secure_load_status_reg {
440 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001,
441 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003,
442 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007,
443 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8,
444 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00,
446 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
448 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38
449 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c
450 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
451 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
453 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000
454 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000
455 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000
456 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400
458 #define IWM_CSR_SECURE_TIME_OUT (100)
460 /* extended range in FW SRAM */
461 #define IWM_FW_MEM_EXTENDED_START 0x40000
462 #define IWM_FW_MEM_EXTENDED_END 0x57FFF
464 /* FW chicken bits */
465 #define IWM_LMPM_CHICK 0xa01ff8
466 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
468 #define IWM_FH_TCSR_0_REG0 (0x1D00)
471 * HBUS (Host-side Bus)
473 * HBUS registers are mapped directly into PCI bus space, but are used
474 * to indirectly access device's internal memory or registers that
475 * may be powered-down.
477 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
478 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
479 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
480 * internal resources.
482 * Do not use iwl_write32()/iwl_read32() family to access these registers;
483 * these provide only simple PCI bus access, without waking up the MAC.
485 #define IWM_HBUS_BASE (0x400)
488 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
489 * structures, error log, event log, verifying uCode load).
490 * First write to address register, then read from or write to data register
491 * to complete the job. Once the address register is set up, accesses to
492 * data registers auto-increment the address by one dword.
493 * Bit usage for address registers (read or write):
494 * 0-31: memory address within device
496 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
497 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
498 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
499 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
501 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
502 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
503 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
506 * Registers for accessing device's internal peripheral registers
507 * (e.g. SCD, BSM, etc.). First write to address register,
508 * then read from or write to data register to complete the job.
509 * Bit usage for address registers (read or write):
510 * 0-15: register address (offset) within device
511 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
513 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
514 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
515 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
516 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
518 /* enable the ID buf for read */
519 #define IWM_WFPM_PS_CTL_CLR 0xa0300c
520 #define IWM_WFMP_MAC_ADDR_0 0xa03080
521 #define IWM_WFMP_MAC_ADDR_1 0xa03084
522 #define IWM_LMPM_PMG_EN 0xa01cec
523 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078
524 #define IWM_RFIC_REG_RD 0xad0470
525 #define IWM_WFPM_CTRL_REG 0xa03030
526 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000
527 #define IWM_ENABLE_WFPM 0x80000000
529 #define IWM_AUX_MISC_REG 0xa200b0
530 #define IWM_HW_STEP_LOCATION_BITS 24
532 #define IWM_AUX_MISC_MASTER1_EN 0xa20818
533 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
534 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
535 #define IWM_RSA_ENABLE 0xa24b08
536 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
537 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
538 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
539 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
540 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088
541 #define IWM_SB_CPU_1_STATUS 0xa01e30
542 #define IWM_SB_CPU_2_STATUS 0Xa01e34
544 /* Used to enable DBGM */
545 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
548 * Per-Tx-queue write pointer (index, really!)
549 * Indicates index to next TFD that driver will fill (1 past latest filled).
551 * 0-7: queue write index
552 * 11-8: queue selector
554 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
556 /**********************************************************
558 **********************************************************/
560 * host interrupt timeout value
561 * used with setting interrupt coalescing timer
562 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
564 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
566 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
567 #define IWM_HOST_INT_TIMEOUT_DEF (0x40)
568 #define IWM_HOST_INT_TIMEOUT_MIN (0x0)
569 #define IWM_HOST_INT_OPER_MODE (1 << 31)
571 /*****************************************************************************
572 * 7000/3000 series SHR DTS addresses *
573 *****************************************************************************/
575 /* Diode Results Register Structure: */
576 enum iwm_dtd_diode_reg {
577 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
578 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
579 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
580 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
581 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
582 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
583 /* Those are the masks INSIDE the flags bit-field: */
584 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
585 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
586 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
587 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
591 * enum iwm_ucode_tlv_flag - ucode API flags
592 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
593 * was a separate TLV but moved here to save space.
594 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
595 * treats good CRC threshold as a boolean
596 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
597 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
598 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
599 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
600 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
601 * offload profile config command.
602 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
603 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
604 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
605 * (rather than two) IPv6 addresses
606 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
607 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
608 * from the probe request template.
609 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
610 * connection when going back to D0
611 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
612 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
613 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
614 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
615 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
616 * containing CAM (Continuous Active Mode) indication.
617 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
618 * single bound interface).
619 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
620 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
621 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
622 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
623 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients
626 enum iwm_ucode_tlv_flag {
627 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
628 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
629 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
630 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3),
631 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4),
632 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5),
633 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6),
634 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
635 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8),
636 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9),
637 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
638 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11),
639 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
640 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14),
641 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
642 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
643 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17),
644 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19),
645 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20),
646 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21),
647 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22),
648 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23),
649 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
650 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25),
651 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
652 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29),
653 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30),
654 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31),
657 #define IWM_UCODE_TLV_FLAG_BITS \
658 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \
659 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \
660 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \
661 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
664 * enum iwm_ucode_tlv_api - ucode api
665 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
666 * longer than the passive one, which is essential for fragmented scan.
667 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
668 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header
669 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
670 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority
672 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size
673 * (command version 3) that supports per-chain limits
675 * @IWM_NUM_UCODE_TLV_API: number of bits used
677 enum iwm_ucode_tlv_api {
678 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8),
679 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9),
680 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14),
681 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18),
682 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24),
683 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27),
685 IWM_NUM_UCODE_TLV_API = 32
688 #define IWM_UCODE_TLV_API_BITS \
689 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN"
692 * enum iwm_ucode_tlv_capa - ucode capabilities
693 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
694 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
695 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
696 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
697 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
698 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
699 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
700 * tx power value into TPC Report action frame and Link Measurement Report
702 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
703 * channel in DS parameter set element in probe requests.
704 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
706 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
707 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
708 * which also implies support for the scheduler configuration command
709 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
710 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
711 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
712 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
713 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command
714 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
715 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
716 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD
717 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
718 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
719 * sources for the MCC. This TLV bit is a future replacement to
720 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
722 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
723 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan
724 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN
725 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported,
727 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
728 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
729 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
730 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
731 * antenna the beacon should be transmitted
732 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
733 * from AP and will send it upon d0i3 exit.
734 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2
735 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
736 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
737 * thresholds reporting
738 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
739 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
741 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
742 * memory addresses from the firmware.
743 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
744 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported,
747 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used
749 enum iwm_ucode_tlv_capa {
750 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0,
751 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1,
752 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2,
753 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3,
754 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5,
755 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6,
756 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8,
757 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9,
758 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10,
759 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11,
760 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12,
761 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13,
762 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17,
763 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18,
764 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19,
765 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20,
766 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21,
767 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22,
768 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26,
769 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28,
770 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29,
771 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30,
772 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31,
773 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34,
774 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35,
775 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64,
776 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65,
777 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67,
778 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68,
779 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71,
780 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72,
781 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73,
782 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74,
783 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75,
784 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76,
785 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77,
786 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79,
787 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80,
788 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81,
790 IWM_NUM_UCODE_TLV_CAPA = 128
793 /* The default calibrate table size if not specified by firmware file */
794 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
795 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
796 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
798 /* The default max probe length if not specified by the firmware file */
799 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200
802 * enumeration of ucode section.
803 * This enumeration is used directly for older firmware (before 16.0).
804 * For new firmware, there can be up to 4 sections (see below) but the
805 * first one packaged into the firmware file is the DATA section and
806 * some debugging code accesses that.
809 IWM_UCODE_SECTION_DATA,
810 IWM_UCODE_SECTION_INST,
813 * For 16.0 uCode and above, there is no differentiation between sections,
814 * just an offset to the HW address.
816 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
817 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB
819 /* uCode version contains 4 values: Major/Minor/API/Serial */
820 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
821 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
822 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
823 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
826 * Calibration control struct.
827 * Sent as part of the phy configuration command.
828 * @flow_trigger: bitmap for which calibrations to perform according to
830 * @event_trigger: bitmap for which calibrations to perform according to
833 struct iwm_tlv_calib_ctrl {
834 uint32_t flow_trigger;
835 uint32_t event_trigger;
838 enum iwm_fw_phy_cfg {
839 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
840 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
841 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
842 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
843 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
844 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
845 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
846 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
847 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
848 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
851 #define IWM_UCODE_MAX_CS 1
854 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
855 * @cipher: a cipher suite selector
856 * @flags: cipher scheme flags (currently reserved for a future use)
857 * @hdr_len: a size of MPDU security header
858 * @pn_len: a size of PN
859 * @pn_off: an offset of pn from the beginning of the security header
860 * @key_idx_off: an offset of key index byte in the security header
861 * @key_idx_mask: a bit mask of key_idx bits
862 * @key_idx_shift: bit shift needed to get key_idx
863 * @mic_len: mic length in bytes
864 * @hw_cipher: a HW cipher index used in host commands
866 struct iwm_fw_cipher_scheme {
873 uint8_t key_idx_mask;
874 uint8_t key_idx_shift;
880 * struct iwm_fw_cscheme_list - a cipher scheme list
881 * @size: a number of entries
882 * @cs: cipher scheme entries
884 struct iwm_fw_cscheme_list {
886 struct iwm_fw_cipher_scheme cs[];
889 /* v1/v2 uCode file layout */
890 struct iwm_ucode_header {
891 uint32_t ver; /* major/minor/API/serial */
894 uint32_t inst_size; /* bytes of runtime code */
895 uint32_t data_size; /* bytes of runtime data */
896 uint32_t init_size; /* bytes of init code */
897 uint32_t init_data_size; /* bytes of init data */
898 uint32_t boot_size; /* bytes of bootstrap code */
899 uint8_t data[0]; /* in same order as sizes */
902 uint32_t build; /* build number */
903 uint32_t inst_size; /* bytes of runtime code */
904 uint32_t data_size; /* bytes of runtime data */
905 uint32_t init_size; /* bytes of init code */
906 uint32_t init_data_size; /* bytes of init data */
907 uint32_t boot_size; /* bytes of bootstrap code */
908 uint8_t data[0]; /* in same order as sizes */
914 * new TLV uCode file layout
916 * The new TLV file format contains TLVs, that each specify
917 * some piece of data.
920 enum iwm_ucode_tlv_type {
921 IWM_UCODE_TLV_INVALID = 0, /* unused */
922 IWM_UCODE_TLV_INST = 1,
923 IWM_UCODE_TLV_DATA = 2,
924 IWM_UCODE_TLV_INIT = 3,
925 IWM_UCODE_TLV_INIT_DATA = 4,
926 IWM_UCODE_TLV_BOOT = 5,
927 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */
928 IWM_UCODE_TLV_PAN = 7,
929 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
930 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
931 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
932 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11,
933 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
934 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13,
935 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14,
936 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
937 IWM_UCODE_TLV_WOWLAN_INST = 16,
938 IWM_UCODE_TLV_WOWLAN_DATA = 17,
939 IWM_UCODE_TLV_FLAGS = 18,
940 IWM_UCODE_TLV_SEC_RT = 19,
941 IWM_UCODE_TLV_SEC_INIT = 20,
942 IWM_UCODE_TLV_SEC_WOWLAN = 21,
943 IWM_UCODE_TLV_DEF_CALIB = 22,
944 IWM_UCODE_TLV_PHY_SKU = 23,
945 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
946 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
947 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
948 IWM_UCODE_TLV_NUM_OF_CPU = 27,
949 IWM_UCODE_TLV_CSCHEME = 28,
952 * Following two are not in our base tag, but allow
953 * handling ucode version 9.
955 IWM_UCODE_TLV_API_CHANGES_SET = 29,
956 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30,
958 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31,
959 IWM_UCODE_TLV_PAGING = 32,
960 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34,
961 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35,
962 IWM_UCODE_TLV_FW_VERSION = 36,
963 IWM_UCODE_TLV_FW_DBG_DEST = 38,
964 IWM_UCODE_TLV_FW_DBG_CONF = 39,
965 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40,
966 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50,
969 struct iwm_ucode_tlv {
970 uint32_t type; /* see above */
971 uint32_t length; /* not including type/length fields */
975 struct iwm_ucode_api {
980 struct iwm_ucode_capa {
985 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749
987 struct iwm_tlv_ucode_header {
989 * The TLV style ucode header is distinguished from
990 * the v1/v2 style header by first four bytes being
991 * zero, as such is an invalid combination of
992 * major/minor/API/serial versions.
996 uint8_t human_readable[64];
997 uint32_t ver; /* major/minor/API/serial */
1001 * The data contained herein has a TLV layout,
1002 * see above for the TLV header and types.
1003 * Note that each TLV is padded to a length
1004 * that is a multiple of 4 for alignment.
1010 * Registers in this file are internal, not PCI bus memory mapped.
1011 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
1013 #define IWM_PRPH_BASE (0x00000)
1014 #define IWM_PRPH_END (0xFFFFF)
1016 /* APMG (power management) constants */
1017 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
1018 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
1019 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
1020 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
1021 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
1022 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
1023 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
1024 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
1025 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
1026 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
1027 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
1029 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
1030 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
1031 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
1033 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
1034 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
1035 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
1036 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
1037 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
1038 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
1039 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
1041 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
1043 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
1045 /* Device system time */
1046 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
1048 /* Device NMI register */
1049 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30
1050 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01
1051 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80
1052 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24
1053 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000
1056 * Device reset for family 8000
1057 * write to bit 24 in order to reset the CPU
1059 #define IWM_RELEASE_CPU_RESET 0x300c
1060 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000
1063 /*****************************************************************************
1064 * 7000/3000 series SHR DTS addresses *
1065 *****************************************************************************/
1067 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
1068 #define IWM_DTSC_CFG_MODE (0x00a10604)
1069 #define IWM_DTSC_VREF_AVG (0x00a10648)
1070 #define IWM_DTSC_VREF5_AVG (0x00a1064c)
1071 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
1072 #define IWM_DTSC_PTAT_AVG (0x00a10650)
1078 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
1079 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
1080 * host DRAM. It steers each frame's Tx command (which contains the frame
1081 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1082 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
1083 * but one DMA channel may take input from several queues.
1085 * Tx DMA FIFOs have dedicated purposes.
1087 * For 5000 series and up, they are used differently
1088 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
1090 * 0 -- EDCA BK (background) frames, lowest priority
1091 * 1 -- EDCA BE (best effort) frames, normal priority
1092 * 2 -- EDCA VI (video) frames, higher priority
1093 * 3 -- EDCA VO (voice) and management frames, highest priority
1099 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1100 * In addition, driver can map the remaining queues to Tx DMA/FIFO
1101 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
1103 * The driver sets up each queue to work in one of two modes:
1105 * 1) Scheduler-Ack, in which the scheduler automatically supports a
1106 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1107 * contains TFDs for a unique combination of Recipient Address (RA)
1108 * and Traffic Identifier (TID), that is, traffic of a given
1109 * Quality-Of-Service (QOS) priority, destined for a single station.
1111 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1112 * each frame within the BA window, including whether it's been transmitted,
1113 * and whether it's been acknowledged by the receiving station. The device
1114 * automatically processes block-acks received from the receiving STA,
1115 * and reschedules un-acked frames to be retransmitted (successful
1116 * Tx completion may end up being out-of-order).
1118 * The driver must maintain the queue's Byte Count table in host DRAM
1120 * This mode does not support fragmentation.
1122 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1123 * The device may automatically retry Tx, but will retry only one frame
1124 * at a time, until receiving ACK from receiving station, or reaching
1125 * retry limit and giving up.
1127 * The command queue (#4/#9) must use this mode!
1128 * This mode does not require use of the Byte Count table in host DRAM.
1130 * Driver controls scheduler operation via 3 means:
1131 * 1) Scheduler registers
1132 * 2) Shared scheduler data base in internal SRAM
1133 * 3) Shared data in host DRAM
1137 * When loading, driver should allocate memory for:
1138 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
1139 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
1140 * (1024 bytes for each queue).
1142 * After receiving "Alive" response from uCode, driver must initialize
1143 * the scheduler (especially for queue #4/#9, the command queue, otherwise
1144 * the driver can't issue commands!):
1146 #define IWM_SCD_MEM_LOWER_BOUND (0x0000)
1149 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1150 * can keep track of at one time when creating block-ack chains of frames.
1151 * Note that "64" matches the number of ack bits in a block-ack packet.
1153 #define IWM_SCD_WIN_SIZE 64
1154 #define IWM_SCD_FRAME_LIMIT 64
1156 #define IWM_SCD_TXFIFO_POS_TID (0)
1157 #define IWM_SCD_TXFIFO_POS_RA (4)
1158 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1161 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
1162 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
1163 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
1164 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
1165 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
1167 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
1168 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
1169 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
1170 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
1171 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
1172 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
1173 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1174 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1175 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0)
1176 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18)
1179 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
1180 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1183 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1184 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1186 /* Translation Data */
1187 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1188 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
1190 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
1191 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
1193 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
1194 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
1196 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
1197 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
1199 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
1201 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
1202 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
1203 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
1204 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
1205 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
1206 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
1207 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
1208 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
1209 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
1210 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)
1211 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)
1213 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
1216 return IWM_SCD_BASE + 0x18 + chnl * 4;
1217 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1220 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
1223 return IWM_SCD_BASE + 0x68 + chnl * 4;
1224 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
1227 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
1230 return IWM_SCD_BASE + 0x10c + chnl * 4;
1231 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
1234 /*********************** END TX SCHEDULER *************************************/
1236 /* Oscillator clock */
1237 #define IWM_OSC_CLK (0xa04068)
1238 #define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1240 /****************************/
1241 /* Flow Handler Definitions */
1242 /****************************/
1245 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1246 * Addresses are offsets from device's PCI hardware base address.
1248 #define IWM_FH_MEM_LOWER_BOUND (0x1000)
1249 #define IWM_FH_MEM_UPPER_BOUND (0x2000)
1252 * Keep-Warm (KW) buffer base address.
1254 * Driver must allocate a 4KByte buffer that is for keeping the
1255 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1256 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1257 * from going into a power-savings mode that would cause higher DRAM latency,
1258 * and possible data over/under-runs, before all Tx/Rx is complete.
1260 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1261 * of the buffer, which must be 4K aligned. Once this is set up, the device
1262 * automatically invokes keep-warm accesses when normal accesses might not
1263 * be sufficient to maintain fast DRAM response.
1266 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1268 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1272 * TFD Circular Buffers Base (CBBC) addresses
1274 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1275 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1276 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1277 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1278 * aligned (address bits 0-7 must be 0).
1279 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1280 * for them are in different places.
1282 * Bit fields in each pointer register:
1283 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1285 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1286 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1287 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1288 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1289 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1290 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1292 /* Find TFD CB base pointer for given queue */
1293 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1296 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1298 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1299 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1304 * Rx SRAM Control and Status Registers (RSCSR)
1306 * These registers provide handshake between driver and device for the Rx queue
1307 * (this queue handles *all* command responses, notifications, Rx data, etc.
1308 * sent from uCode to host driver). Unlike Tx, there is only one Rx
1309 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1310 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1311 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1312 * mapping between RBDs and RBs.
1314 * Driver must allocate host DRAM memory for the following, and set the
1315 * physical address of each into device registers:
1317 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1318 * entries (although any power of 2, up to 4096, is selectable by driver).
1319 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1320 * (typically 4K, although 8K or 16K are also selectable by driver).
1321 * Driver sets up RB size and number of RBDs in the CB via Rx config
1322 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1324 * Bit fields within one RBD:
1325 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1327 * Driver sets physical address [35:8] of base of RBD circular buffer
1328 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1330 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1331 * (RBs) have been filled, via a "write pointer", actually the index of
1332 * the RB's corresponding RBD within the circular buffer. Driver sets
1333 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1335 * Bit fields in lower dword of Rx status buffer (upper dword not used
1337 * 31-12: Not used by driver
1338 * 11- 0: Index of last filled Rx buffer descriptor
1339 * (device writes, driver reads this value)
1341 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1342 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1343 * and update the device's "write" index register,
1344 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1346 * This "write" index corresponds to the *next* RBD that the driver will make
1347 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1348 * the circular buffer. This value should initially be 0 (before preparing any
1349 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1350 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1351 * "read" index has advanced past 1! See below).
1352 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1354 * As the device fills RBs (referenced from contiguous RBDs within the circular
1355 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1356 * to tell the driver the index of the latest filled RBD. The driver must
1357 * read this "read" index from DRAM after receiving an Rx interrupt from device
1359 * The driver must also internally keep track of a third index, which is the
1360 * next RBD to process. When receiving an Rx interrupt, driver should process
1361 * all filled but unprocessed RBs up to, but not including, the RB
1362 * corresponding to the "read" index. For example, if "read" index becomes "1",
1363 * driver may process the RB pointed to by RBD 0. Depending on volume of
1364 * traffic, there may be many RBs to process.
1366 * If read index == write index, device thinks there is no room to put new data.
1367 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1368 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1369 * and "read" indexes; that is, make sure that there are no more than 254
1370 * buffers waiting to be filled.
1372 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1373 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1374 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1377 * Physical base address of 8-byte Rx Status buffer.
1379 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1381 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1384 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1386 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1388 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1391 * Rx write pointer (index, really!).
1393 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1394 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1396 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1397 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1399 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1400 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1403 * Rx Config/Status Registers (RCSR)
1404 * Rx Config Reg for channel 0 (only channel used)
1406 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1407 * normal operation (see bit fields).
1409 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1410 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1411 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1414 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1415 * '10' operate normally
1417 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1418 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1420 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1421 * '10' 12K, '11' 16K.
1423 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1424 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1425 * typical value 0x10 (about 1/2 msec)
1428 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1429 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1430 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1432 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1433 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1434 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1436 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1437 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1438 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1439 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1440 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1441 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1443 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1444 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1445 #define IWM_RX_RB_TIMEOUT (0x11)
1447 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1448 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1449 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1451 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1452 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1453 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1454 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1456 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1457 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1458 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1461 * Rx Shared Status Registers (RSSR)
1463 * After stopping Rx DMA channel (writing 0 to
1464 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1465 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1468 * 24: 1 = Channel 0 is idle
1470 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1471 * contain default values that should not be altered by the driver.
1473 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1474 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1476 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1477 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1478 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1479 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1481 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1483 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1485 /* TFDB Area - TFDs buffer table */
1486 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1487 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1488 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1489 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1490 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1493 * Transmit DMA Channel Control/Status Registers (TCSR)
1495 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1496 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1497 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1499 * To use a Tx DMA channel, driver must initialize its
1500 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1502 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1503 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1505 * All other bits should be 0.
1508 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1509 * '10' operate normally
1510 * 29- 4: Reserved, set to "0"
1511 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1512 * 2- 0: Reserved, set to "0"
1514 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1515 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1517 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1518 #define IWM_FH_TCSR_CHNL_NUM (8)
1520 /* TCSR: tx_config register values */
1521 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1522 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1523 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1524 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1525 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1526 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1528 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1529 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1531 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1532 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1534 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1535 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1536 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1538 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1539 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1540 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1542 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1543 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1544 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1546 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1547 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1548 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1550 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1551 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1554 * Tx Shared Status Registers (TSSR)
1556 * After stopping Tx DMA channel (writing 0 to
1557 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1558 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1559 * (channel's buffers empty | no pending requests).
1562 * 31-24: 1 = Channel buffers empty (channel 7:0)
1563 * 23-16: 1 = No pending requests (channel 7:0)
1565 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1566 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1568 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1571 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1572 * 31: Indicates an address error when accessed to internal memory
1573 * uCode/driver must write "1" in order to clear this flag
1574 * 30: Indicates that Host did not send the expected number of dwords to FH
1575 * uCode/driver must write "1" in order to clear this flag
1576 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1577 * command was received from the scheduler while the TRB was already full
1578 * with previous command
1579 * uCode/driver must write "1" in order to clear this flag
1580 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1581 * bit is set, it indicates that the FH has received a full indication
1582 * from the RTC TxFIFO and the current value of the TxCredit counter was
1583 * not equal to zero. This mean that the credit mechanism was not
1584 * synchronized to the TxFIFO status
1585 * uCode/driver must write "1" in order to clear this flag
1587 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1588 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1590 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1592 /* Tx service channels */
1593 #define IWM_FH_SRVC_CHNL (9)
1594 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1595 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1596 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1597 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1599 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1600 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1603 /* Instruct FH to increment the retry count of a packet when
1604 * it is brought from the memory to TX-FIFO
1606 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1608 #define IWM_RX_QUEUE_SIZE 256
1609 #define IWM_RX_QUEUE_MASK 255
1610 #define IWM_RX_QUEUE_SIZE_LOG 8
1613 * RX related structures and functions
1615 #define IWM_RX_FREE_BUFFERS 64
1616 #define IWM_RX_LOW_WATERMARK 8
1619 * struct iwm_rb_status - reseve buffer status
1620 * host memory mapped FH registers
1621 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1622 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1623 * @finished_rb_num [0:11] - Indicates the index of the current RB
1624 * in which the last frame was written to
1625 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1626 * which was transferred
1628 struct iwm_rb_status {
1629 uint16_t closed_rb_num;
1630 uint16_t closed_fr_num;
1631 uint16_t finished_rb_num;
1632 uint16_t finished_fr_nam;
1637 #define IWM_TFD_QUEUE_SIZE_MAX (256)
1638 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1639 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1640 IWM_TFD_QUEUE_SIZE_BC_DUP)
1641 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1642 #define IWM_NUM_OF_TBS 20
1644 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1646 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1649 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1651 * This structure contains dma address and length of transmission address
1653 * @lo: low [31:0] portion of the dma address of TX buffer
1654 * every even is unaligned on 16 bit boundary
1655 * @hi_n_len 0-3 [35:32] portion of dma
1656 * 4-15 length of the tx buffer
1666 * Transmit Frame Descriptor (TFD)
1668 * @ __reserved1[3] reserved
1669 * @ num_tbs 0-4 number of active tbs
1671 * 6-7 padding (not used)
1672 * @ tbs[20] transmit frame buffer descriptors
1675 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1676 * Both driver and device share these circular buffers, each of which must be
1677 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1679 * Driver must indicate the physical address of the base of each
1680 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1682 * Each TFD contains pointer/size information for up to 20 data buffers
1683 * in host DRAM. These buffers collectively contain the (one) frame described
1684 * by the TFD. Each buffer must be a single contiguous block of memory within
1685 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1686 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1687 * Tx frame, up to 8 KBytes in size.
1689 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1692 uint8_t __reserved1[3];
1694 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1698 /* Keep Warm Size */
1699 #define IWM_KW_SIZE 0x1000 /* 4k */
1701 /* Fixed (non-configurable) rx data from phy */
1704 * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1705 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1706 * @tfd_offset 0-12 - tx command byte count
1707 * 12-16 - station index
1709 struct iwm_agn_scd_bc_tbl {
1710 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1713 /* Maximum number of Tx queues. */
1714 #define IWM_MVM_MAX_QUEUES 31
1716 /* Tx queue numbers */
1718 IWM_MVM_OFFCHANNEL_QUEUE = 8,
1719 IWM_MVM_CMD_QUEUE = 9,
1720 IWM_MVM_AUX_QUEUE = 15,
1723 enum iwm_mvm_tx_fifo {
1724 IWM_MVM_TX_FIFO_BK = 0,
1728 IWM_MVM_TX_FIFO_MCAST = 5,
1729 IWM_MVM_TX_FIFO_CMD = 7,
1732 #define IWM_MVM_STATION_COUNT 16
1736 IWM_MVM_ALIVE = 0x1,
1737 IWM_REPLY_ERROR = 0x2,
1739 IWM_INIT_COMPLETE_NOTIF = 0x4,
1741 /* PHY context commands */
1742 IWM_PHY_CONTEXT_CMD = 0x8,
1745 /* UMAC scan commands */
1746 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5,
1747 IWM_SCAN_CFG_CMD = 0xc,
1748 IWM_SCAN_REQ_UMAC = 0xd,
1749 IWM_SCAN_ABORT_UMAC = 0xe,
1750 IWM_SCAN_COMPLETE_UMAC = 0xf,
1753 IWM_ADD_STA_KEY = 0x17,
1755 IWM_REMOVE_STA = 0x19,
1759 IWM_TXPATH_FLUSH = 0x1e,
1760 IWM_MGMT_MCAST_KEY = 0x1f,
1762 /* scheduler config */
1763 IWM_SCD_QUEUE_CFG = 0x1d,
1768 /* MAC and Binding commands */
1769 IWM_MAC_CONTEXT_CMD = 0x28,
1770 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1771 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1772 IWM_BINDING_CONTEXT_CMD = 0x2b,
1773 IWM_TIME_QUOTA_CMD = 0x2c,
1774 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
1779 IWM_TEMPERATURE_NOTIFICATION = 0x62,
1780 IWM_CALIBRATION_CFG_CMD = 0x65,
1781 IWM_CALIBRATION_RES_NOTIFICATION = 0x66,
1782 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
1783 IWM_RADIO_VERSION_NOTIFICATION = 0x68,
1786 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1787 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1788 IWM_HOT_SPOT_CMD = 0x53,
1789 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d,
1790 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e,
1791 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1792 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1793 IWM_SCAN_ITERATION_COMPLETE = 0xe7,
1796 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1797 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1798 /* IWM_PHY_DB_CMD = 0x6c, */
1800 /* Power - legacy power table command */
1801 IWM_POWER_TABLE_CMD = 0x77,
1802 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1804 /* Thermal Throttling*/
1805 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1808 IWM_SCAN_ABORT_CMD = 0x81,
1809 IWM_SCAN_START_NOTIFICATION = 0x82,
1810 IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
1813 IWM_NVM_ACCESS_CMD = 0x88,
1815 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
1817 IWM_BEACON_NOTIFICATION = 0x90,
1818 IWM_BEACON_TEMPLATE_CMD = 0x91,
1819 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1820 IWM_BT_CONFIG = 0x9b,
1821 IWM_STATISTICS_NOTIFICATION = 0x9d,
1822 IWM_REDUCE_TX_POWER_CMD = 0x9f,
1824 /* RF-KILL commands and notifications */
1825 IWM_CARD_STATE_CMD = 0xa0,
1826 IWM_CARD_STATE_NOTIFICATION = 0xa1,
1828 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
1830 IWM_MFUART_LOAD_NOTIFICATION = 0xb1,
1832 /* Power - new power table command */
1833 IWM_MAC_PM_POWER_TABLE = 0xa9,
1835 IWM_REPLY_RX_PHY_CMD = 0xc0,
1836 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1837 IWM_BA_NOTIF = 0xc5,
1839 /* Location Aware Regulatory */
1840 IWM_MCC_UPDATE_CMD = 0xc8,
1841 IWM_MCC_CHUB_UPDATE_CMD = 0xc9,
1844 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1845 IWM_BT_COEX_PROT_ENV = 0xcd,
1846 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1847 IWM_BT_COEX_CI = 0x5d,
1849 IWM_REPLY_SF_CFG_CMD = 0xd1,
1850 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
1852 /* DTS measurements */
1853 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc,
1854 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd,
1856 IWM_REPLY_DEBUG_CMD = 0xf0,
1857 IWM_DEBUG_LOG_MSG = 0xf7,
1859 IWM_MCAST_FILTER_CMD = 0xd0,
1861 /* D3 commands/notifications */
1862 IWM_D3_CONFIG_CMD = 0xd3,
1863 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1864 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1865 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
1867 /* for WoWLAN in particular */
1868 IWM_WOWLAN_PATTERNS = 0xe0,
1869 IWM_WOWLAN_CONFIGURATION = 0xe1,
1870 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1871 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1872 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1873 IWM_WOWLAN_GET_STATUSES = 0xe5,
1874 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1876 /* and for NetDetect */
1877 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1878 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1879 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1880 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1881 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1883 IWM_REPLY_MAX = 0xff,
1887 * struct iwm_cmd_response - generic response struct for most commands
1888 * @status: status of the command asked, changes for each one
1890 struct iwm_cmd_response {
1895 * struct iwm_tx_ant_cfg_cmd
1896 * @valid: valid antenna configuration
1898 struct iwm_tx_ant_cfg_cmd {
1903 * struct iwm_reduce_tx_power_cmd - TX power reduction command
1904 * IWM_REDUCE_TX_POWER_CMD = 0x9f
1905 * @flags: (reserved for future implementation)
1906 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
1907 * @pwr_restriction: TX power restriction in dBms.
1909 struct iwm_reduce_tx_power_cmd {
1911 uint8_t mac_context_id;
1912 uint16_t pwr_restriction;
1913 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
1916 * Calibration control struct.
1917 * Sent as part of the phy configuration command.
1918 * @flow_trigger: bitmap for which calibrations to perform according to
1920 * @event_trigger: bitmap for which calibrations to perform according to
1923 struct iwm_calib_ctrl {
1924 uint32_t flow_trigger;
1925 uint32_t event_trigger;
1928 /* This enum defines the bitmap of various calibrations to enable in both
1929 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
1931 enum iwm_calib_cfg {
1932 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
1933 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
1934 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
1935 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
1936 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
1937 IWM_CALIB_CFG_DC_IDX = (1 << 5),
1938 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
1939 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
1940 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
1941 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
1942 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
1943 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
1944 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
1945 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
1946 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
1947 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
1948 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
1949 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
1950 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
1954 * Phy configuration command.
1956 struct iwm_phy_cfg_cmd {
1958 struct iwm_calib_ctrl calib_control;
1961 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
1962 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
1963 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
1964 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
1965 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
1966 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
1967 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
1968 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
1969 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
1970 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
1973 /* Target of the IWM_NVM_ACCESS_CMD */
1975 IWM_NVM_ACCESS_TARGET_CACHE = 0,
1976 IWM_NVM_ACCESS_TARGET_OTP = 1,
1977 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
1980 /* Section types for IWM_NVM_ACCESS_CMD */
1982 IWM_NVM_SECTION_TYPE_HW = 0,
1983 IWM_NVM_SECTION_TYPE_SW,
1984 IWM_NVM_SECTION_TYPE_PAPD,
1985 IWM_NVM_SECTION_TYPE_REGULATORY,
1986 IWM_NVM_SECTION_TYPE_CALIBRATION,
1987 IWM_NVM_SECTION_TYPE_PRODUCTION,
1988 IWM_NVM_SECTION_TYPE_POST_FCS_CALIB,
1989 /* 7, 8, 9 unknown */
1990 IWM_NVM_SECTION_TYPE_HW_8000 = 10,
1991 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE,
1992 IWM_NVM_SECTION_TYPE_PHY_SKU,
1993 IWM_NVM_NUM_OF_SECTIONS,
1997 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
1998 * @op_code: 0 - read, 1 - write
1999 * @target: IWM_NVM_ACCESS_TARGET_*
2000 * @type: IWM_NVM_SECTION_TYPE_*
2001 * @offset: offset in bytes into the section
2002 * @length: in bytes, to read/write
2003 * @data: if write operation, the data to write. On read its empty
2005 struct iwm_nvm_access_cmd {
2012 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
2015 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
2016 * @offset: offset in bytes into the section
2017 * @length: in bytes, either how much was written or read
2018 * @type: IWM_NVM_SECTION_TYPE_*
2019 * @status: 0 for success, fail otherwise
2020 * @data: if read operation, the data returned. Empty on write.
2022 struct iwm_nvm_access_resp {
2028 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
2030 /* IWM_MVM_ALIVE 0x1 */
2032 /* alive response is_valid values */
2033 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
2034 #define IWM_ALIVE_RESP_RFKILL (1 << 1)
2036 /* alive response ver_type values */
2039 IWM_FW_TYPE_PROT = 1,
2041 IWM_FW_TYPE_WOWLAN = 3,
2042 IWM_FW_TYPE_TIMING = 4,
2043 IWM_FW_TYPE_WIPAN = 5
2046 /* alive response ver_subtype values */
2048 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
2049 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
2050 IWM_FW_SUBTYPE_REDUCED = 2,
2051 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
2052 IWM_FW_SUBTYPE_WOWLAN = 4,
2053 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
2054 IWM_FW_SUBTYPE_WIPAN = 6,
2055 IWM_FW_SUBTYPE_INITIALIZE = 9
2058 #define IWM_ALIVE_STATUS_ERR 0xDEAD
2059 #define IWM_ALIVE_STATUS_OK 0xCAFE
2061 #define IWM_ALIVE_FLG_RFKILL (1 << 0)
2063 struct iwm_mvm_alive_resp_v1 {
2066 uint8_t ucode_minor;
2067 uint8_t ucode_major;
2071 uint8_t ver_subtype;
2077 uint32_t error_event_table_ptr; /* SRAM address for error log */
2078 uint32_t log_event_table_ptr; /* SRAM address for event log */
2079 uint32_t cpu_register_ptr;
2080 uint32_t dbgm_config_ptr;
2081 uint32_t alive_counter_ptr;
2082 uint32_t scd_base_ptr; /* SRAM address for SCD */
2083 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */
2085 struct iwm_mvm_alive_resp_v2 {
2088 uint8_t ucode_minor;
2089 uint8_t ucode_major;
2093 uint8_t ver_subtype;
2099 uint32_t error_event_table_ptr; /* SRAM address for error log */
2100 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2101 uint32_t cpu_register_ptr;
2102 uint32_t dbgm_config_ptr;
2103 uint32_t alive_counter_ptr;
2104 uint32_t scd_base_ptr; /* SRAM address for SCD */
2105 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2106 uint32_t st_fwrd_size;
2107 uint8_t umac_minor; /* UMAC version: minor */
2108 uint8_t umac_major; /* UMAC version: major */
2109 uint16_t umac_id; /* UMAC version: id */
2110 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2111 uint32_t dbg_print_buff_addr;
2112 } __packed; /* ALIVE_RES_API_S_VER_2 */
2114 struct iwm_mvm_alive_resp_v3 {
2117 uint32_t ucode_minor;
2118 uint32_t ucode_major;
2119 uint8_t ver_subtype;
2124 uint32_t error_event_table_ptr; /* SRAM address for error log */
2125 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2126 uint32_t cpu_register_ptr;
2127 uint32_t dbgm_config_ptr;
2128 uint32_t alive_counter_ptr;
2129 uint32_t scd_base_ptr; /* SRAM address for SCD */
2130 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2131 uint32_t st_fwrd_size;
2132 uint32_t umac_minor; /* UMAC version: minor */
2133 uint32_t umac_major; /* UMAC version: major */
2134 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2135 uint32_t dbg_print_buff_addr;
2136 } __packed; /* ALIVE_RES_API_S_VER_3 */
2138 /* Error response/notification */
2140 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
2141 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
2142 IWM_FW_ERR_SERVICE = 0x2,
2143 IWM_FW_ERR_ARC_MEMORY = 0x3,
2144 IWM_FW_ERR_ARC_CODE = 0x4,
2145 IWM_FW_ERR_WATCH_DOG = 0x5,
2146 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
2147 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
2148 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
2149 IWM_FW_ERR_UNEXPECTED = 0xFE,
2150 IWM_FW_ERR_FATAL = 0xFF
2154 * struct iwm_error_resp - FW error indication
2155 * ( IWM_REPLY_ERROR = 0x2 )
2156 * @error_type: one of IWM_FW_ERR_*
2157 * @cmd_id: the command ID for which the error occurred
2158 * @bad_cmd_seq_num: sequence number of the erroneous command
2159 * @error_service: which service created the error, applicable only if
2160 * error_type = 2, otherwise 0
2161 * @timestamp: TSF in usecs.
2163 struct iwm_error_resp {
2164 uint32_t error_type;
2167 uint16_t bad_cmd_seq_num;
2168 uint32_t error_service;
2173 /* Common PHY, MAC and Bindings definitions */
2175 #define IWM_MAX_MACS_IN_BINDING (3)
2176 #define IWM_MAX_BINDINGS (4)
2177 #define IWM_AUX_BINDING_INDEX (3)
2178 #define IWM_MAX_PHYS (4)
2180 /* Used to extract ID and color from the context dword */
2181 #define IWM_FW_CTXT_ID_POS (0)
2182 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
2183 #define IWM_FW_CTXT_COLOR_POS (8)
2184 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
2185 #define IWM_FW_CTXT_INVALID (0xffffffff)
2187 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
2188 (_color << IWM_FW_CTXT_COLOR_POS))
2190 /* Possible actions on PHYs, MACs and Bindings */
2192 IWM_FW_CTXT_ACTION_STUB = 0,
2193 IWM_FW_CTXT_ACTION_ADD,
2194 IWM_FW_CTXT_ACTION_MODIFY,
2195 IWM_FW_CTXT_ACTION_REMOVE,
2196 IWM_FW_CTXT_ACTION_NUM
2197 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2201 /* Time Event types, according to MAC type */
2202 enum iwm_time_event_type {
2203 /* BSS Station Events */
2204 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
2205 IWM_TE_BSS_STA_ASSOC,
2206 IWM_TE_BSS_EAP_DHCP_PROT,
2207 IWM_TE_BSS_QUIET_PERIOD,
2209 /* P2P Device Events */
2210 IWM_TE_P2P_DEVICE_DISCOVERABLE,
2211 IWM_TE_P2P_DEVICE_LISTEN,
2212 IWM_TE_P2P_DEVICE_ACTION_SCAN,
2213 IWM_TE_P2P_DEVICE_FULL_SCAN,
2215 /* P2P Client Events */
2216 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
2217 IWM_TE_P2P_CLIENT_ASSOC,
2218 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
2221 IWM_TE_P2P_GO_ASSOC_PROT,
2222 IWM_TE_P2P_GO_REPETITIVE_NOA,
2223 IWM_TE_P2P_GO_CT_WINDOW,
2225 /* WiDi Sync Events */
2226 IWM_TE_WIDI_TX_SYNC,
2229 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
2233 /* Time event - defines for command API v1 */
2236 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
2237 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2238 * the first fragment is scheduled.
2239 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
2240 * the first 2 fragments are scheduled.
2241 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2242 * number of fragments are valid.
2244 * Other than the constant defined above, specifying a fragmentation value 'x'
2245 * means that the event can be fragmented but only the first 'x' will be
2249 IWM_TE_V1_FRAG_NONE = 0,
2250 IWM_TE_V1_FRAG_SINGLE = 1,
2251 IWM_TE_V1_FRAG_DUAL = 2,
2252 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
2255 /* If a Time Event can be fragmented, this is the max number of fragments */
2256 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2257 /* Repeat the time event endlessly (until removed) */
2258 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2259 /* If a Time Event has bounded repetitions, this is the maximal value */
2260 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2262 /* Time Event dependencies: none, on another TE, or in a specific time */
2264 IWM_TE_V1_INDEPENDENT = 0,
2265 IWM_TE_V1_DEP_OTHER = (1 << 0),
2266 IWM_TE_V1_DEP_TSF = (1 << 1),
2267 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
2268 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
2271 * @IWM_TE_V1_NOTIF_NONE: no notifications
2272 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
2273 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
2274 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
2275 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
2276 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2277 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2278 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
2279 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
2281 * Supported Time event notifications configuration.
2282 * A notification (both event and fragment) includes a status indicating weather
2283 * the FW was able to schedule the event or not. For fragment start/end
2284 * notification the status is always success. There is no start/end fragment
2285 * notification for monolithic events.
2288 IWM_TE_V1_NOTIF_NONE = 0,
2289 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
2290 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
2291 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2292 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2293 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
2294 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
2295 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2296 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2297 IWM_T2_V2_START_IMMEDIATELY = (1 << 11),
2298 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2302 * struct iwm_time_event_cmd_api_v1 - configuring Time Events
2303 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also
2304 * with version 2. determined by IWM_UCODE_TLV_FLAGS)
2305 * ( IWM_TIME_EVENT_CMD = 0x29 )
2306 * @id_and_color: ID and color of the relevant MAC
2307 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2308 * @id: this field has two meanings, depending on the action:
2309 * If the action is ADD, then it means the type of event to add.
2310 * For all other actions it is the unique event ID assigned when the
2311 * event was added by the FW.
2312 * @apply_time: When to start the Time Event (in GP2)
2313 * @max_delay: maximum delay to event's start (apply time), in TU
2314 * @depends_on: the unique ID of the event we depend on (if any)
2315 * @interval: interval between repetitions, in TU
2316 * @interval_reciprocal: 2^32 / interval
2317 * @duration: duration of event in TU
2318 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2319 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF
2320 * and IWM_TE_V1_EVENT_SOCIOPATHIC
2321 * @is_present: 0 or 1, are we present or absent during the Time Event
2322 * @max_frags: maximal number of fragments the Time Event can be divided to
2323 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when)
2325 struct iwm_time_event_cmd_v1 {
2326 /* COMMON_INDEX_HDR_API_S_VER_1 */
2327 uint32_t id_and_color;
2330 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */
2331 uint32_t apply_time;
2333 uint32_t dep_policy;
2334 uint32_t depends_on;
2335 uint32_t is_present;
2338 uint32_t interval_reciprocal;
2342 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */
2345 /* Time event - defines for command API v2 */
2348 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2349 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2350 * the first fragment is scheduled.
2351 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2352 * the first 2 fragments are scheduled.
2353 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2354 * number of fragments are valid.
2356 * Other than the constant defined above, specifying a fragmentation value 'x'
2357 * means that the event can be fragmented but only the first 'x' will be
2361 IWM_TE_V2_FRAG_NONE = 0,
2362 IWM_TE_V2_FRAG_SINGLE = 1,
2363 IWM_TE_V2_FRAG_DUAL = 2,
2364 IWM_TE_V2_FRAG_MAX = 0xfe,
2365 IWM_TE_V2_FRAG_ENDLESS = 0xff
2368 /* Repeat the time event endlessly (until removed) */
2369 #define IWM_TE_V2_REPEAT_ENDLESS 0xff
2370 /* If a Time Event has bounded repetitions, this is the maximal value */
2371 #define IWM_TE_V2_REPEAT_MAX 0xfe
2373 #define IWM_TE_V2_PLACEMENT_POS 12
2374 #define IWM_TE_V2_ABSENCE_POS 15
2376 /* Time event policy values (for time event cmd api v2)
2377 * A notification (both event and fragment) includes a status indicating weather
2378 * the FW was able to schedule the event or not. For fragment start/end
2379 * notification the status is always success. There is no start/end fragment
2380 * notification for monolithic events.
2382 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2383 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2384 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2385 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2386 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2387 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2388 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2389 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2390 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2391 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2392 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2393 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2394 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2397 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2399 /* notifications (event start/stop, fragment start/stop) */
2400 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2401 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2402 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2403 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2405 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2406 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2407 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2408 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2410 IWM_TE_V2_NOTIF_MSK = 0xff,
2412 /* placement characteristics */
2413 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2414 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2415 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2417 /* are we present or absent during the Time Event. */
2418 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2422 * struct iwm_time_event_cmd_api_v2 - configuring Time Events
2423 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2424 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2425 * ( IWM_TIME_EVENT_CMD = 0x29 )
2426 * @id_and_color: ID and color of the relevant MAC
2427 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2428 * @id: this field has two meanings, depending on the action:
2429 * If the action is ADD, then it means the type of event to add.
2430 * For all other actions it is the unique event ID assigned when the
2431 * event was added by the FW.
2432 * @apply_time: When to start the Time Event (in GP2)
2433 * @max_delay: maximum delay to event's start (apply time), in TU
2434 * @depends_on: the unique ID of the event we depend on (if any)
2435 * @interval: interval between repetitions, in TU
2436 * @duration: duration of event in TU
2437 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2438 * @max_frags: maximal number of fragments the Time Event can be divided to
2439 * @policy: defines whether uCode shall notify the host or other uCode modules
2440 * on event and/or fragment start and/or end
2441 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2442 * IWM_TE_EVENT_SOCIOPATHIC
2443 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2445 struct iwm_time_event_cmd_v2 {
2446 /* COMMON_INDEX_HDR_API_S_VER_1 */
2447 uint32_t id_and_color;
2450 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2451 uint32_t apply_time;
2453 uint32_t depends_on;
2459 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2462 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2463 * @status: bit 0 indicates success, all others specify errors
2464 * @id: the Time Event type
2465 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2466 * @id_and_color: ID and color of the relevant MAC
2468 struct iwm_time_event_resp {
2472 uint32_t id_and_color;
2473 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2476 * struct iwm_time_event_notif - notifications of time event start/stop
2477 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2478 * @timestamp: action timestamp in GP2
2479 * @session_id: session's unique id
2480 * @unique_id: unique id of the Time Event itself
2481 * @id_and_color: ID and color of the relevant MAC
2482 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2483 * @status: true if scheduled, false otherwise (not executed)
2485 struct iwm_time_event_notif {
2487 uint32_t session_id;
2489 uint32_t id_and_color;
2492 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2495 /* Bindings and Time Quota */
2498 * struct iwm_binding_cmd - configuring bindings
2499 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2500 * @id_and_color: ID and color of the relevant Binding
2501 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2502 * @macs: array of MAC id and colors which belong to the binding
2503 * @phy: PHY id and color which belongs to the binding
2505 struct iwm_binding_cmd {
2506 /* COMMON_INDEX_HDR_API_S_VER_1 */
2507 uint32_t id_and_color;
2509 /* IWM_BINDING_DATA_API_S_VER_1 */
2510 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2512 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2514 /* The maximal number of fragments in the FW's schedule session */
2515 #define IWM_MVM_MAX_QUOTA 128
2518 * struct iwm_time_quota_data - configuration of time quota per binding
2519 * @id_and_color: ID and color of the relevant Binding
2520 * @quota: absolute time quota in TU. The scheduler will try to divide the
2521 * remainig quota (after Time Events) according to this quota.
2522 * @max_duration: max uninterrupted context duration in TU
2524 struct iwm_time_quota_data {
2525 uint32_t id_and_color;
2527 uint32_t max_duration;
2528 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2531 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2532 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2533 * @quotas: allocations per binding
2535 struct iwm_time_quota_cmd {
2536 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2537 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2542 /* Supported bands */
2543 #define IWM_PHY_BAND_5 (0)
2544 #define IWM_PHY_BAND_24 (1)
2546 /* Supported channel width, vary if there is VHT support */
2547 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2548 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2549 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2550 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2553 * Control channel position:
2554 * For legacy set bit means upper channel, otherwise lower.
2555 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2556 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2559 * 40Mhz |_______|_______|
2560 * 80Mhz |_______|_______|_______|_______|
2561 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2562 * code 011 010 001 000 | 100 101 110 111
2564 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2565 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2566 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2567 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2568 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2569 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2570 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2571 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2574 * @band: IWM_PHY_BAND_*
2575 * @channel: channel number
2576 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2577 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2579 struct iwm_fw_channel_info {
2586 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2587 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2588 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2589 #define IWM_PHY_RX_CHAIN_VALID_POS (1)
2590 #define IWM_PHY_RX_CHAIN_VALID_MSK \
2591 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2592 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2593 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2594 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2595 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2596 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2597 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2598 #define IWM_PHY_RX_CHAIN_CNT_POS (10)
2599 #define IWM_PHY_RX_CHAIN_CNT_MSK \
2600 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2601 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2602 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2603 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2604 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2605 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2606 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2608 /* TODO: fix the value, make it depend on firmware at runtime? */
2609 #define IWM_NUM_PHY_CTX 3
2611 /* TODO: complete missing documentation */
2613 * struct iwm_phy_context_cmd - config of the PHY context
2614 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2615 * @id_and_color: ID and color of the relevant Binding
2616 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2617 * @apply_time: 0 means immediate apply and context switch.
2618 * other value means apply new params after X usecs
2619 * @tx_param_color: ???
2621 * @txchain_info: ???
2622 * @rxchain_info: ???
2623 * @acquisition_data: ???
2624 * @dsp_cfg_flags: set to 0
2626 struct iwm_phy_context_cmd {
2627 /* COMMON_INDEX_HDR_API_S_VER_1 */
2628 uint32_t id_and_color;
2630 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2631 uint32_t apply_time;
2632 uint32_t tx_param_color;
2633 struct iwm_fw_channel_info ci;
2634 uint32_t txchain_info;
2635 uint32_t rxchain_info;
2636 uint32_t acquisition_data;
2637 uint32_t dsp_cfg_flags;
2638 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2640 #define IWM_RX_INFO_PHY_CNT 8
2641 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2642 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2643 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2644 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2645 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2646 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2647 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2649 #define IWM_RX_INFO_AGC_IDX 1
2650 #define IWM_RX_INFO_RSSI_AB_IDX 2
2651 #define IWM_OFDM_AGC_A_MSK 0x0000007f
2652 #define IWM_OFDM_AGC_A_POS 0
2653 #define IWM_OFDM_AGC_B_MSK 0x00003f80
2654 #define IWM_OFDM_AGC_B_POS 7
2655 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2656 #define IWM_OFDM_AGC_CODE_POS 20
2657 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2658 #define IWM_OFDM_RSSI_A_POS 0
2659 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2660 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2661 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2662 #define IWM_OFDM_RSSI_B_POS 16
2663 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2664 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2667 * struct iwm_rx_phy_info - phy info
2668 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2669 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2670 * @cfg_phy_cnt: configurable DSP phy data byte count
2671 * @stat_id: configurable DSP phy data set ID
2673 * @system_timestamp: GP2 at on air rise
2674 * @timestamp: TSF at on air rise
2675 * @beacon_time_stamp: beacon at on-air rise
2676 * @phy_flags: general phy flags: band, modulation, ...
2677 * @channel: channel number
2678 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2679 * @rate_n_flags: IWM_RATE_MCS_*
2680 * @byte_count: frame's byte-count
2681 * @frame_time: frame's time on the air, based on byte count and frame rate
2683 * @mac_active_msk: what MACs were active when the frame was received
2685 * Before each Rx, the device sends this data. It contains PHY information
2686 * about the reception of the packet.
2688 struct iwm_rx_phy_info {
2689 uint8_t non_cfg_phy_cnt;
2690 uint8_t cfg_phy_cnt;
2693 uint32_t system_timestamp;
2695 uint32_t beacon_time_stamp;
2697 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2699 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2703 uint32_t byte_count;
2704 uint16_t mac_active_msk;
2705 uint16_t frame_time;
2708 struct iwm_rx_mpdu_res_start {
2709 uint16_t byte_count;
2714 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
2715 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2716 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2717 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2718 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2719 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2720 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2721 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2722 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2723 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2725 enum iwm_rx_phy_flags {
2726 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2727 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2728 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2729 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2730 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2731 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2732 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2733 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2734 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2735 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2739 * enum iwm_mvm_rx_status - written by fw for each Rx packet
2740 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2741 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2742 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2743 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2744 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2745 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2746 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2748 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2749 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2750 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2751 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2752 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2753 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2754 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2755 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2756 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2757 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2758 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2759 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2760 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2761 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2762 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2763 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2764 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2765 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2766 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2767 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2768 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2770 enum iwm_mvm_rx_status {
2771 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2772 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2773 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2774 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2775 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2776 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2777 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2778 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2779 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2780 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2781 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2782 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2783 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2784 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2785 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2786 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2787 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2788 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2789 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2790 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2791 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2792 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2793 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2794 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2795 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2796 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2797 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2801 * struct iwm_radio_version_notif - information on the radio version
2802 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2807 struct iwm_radio_version_notif {
2808 uint32_t radio_flavor;
2809 uint32_t radio_step;
2810 uint32_t radio_dash;
2811 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2813 enum iwm_card_state_flags {
2814 IWM_CARD_ENABLED = 0x00,
2815 IWM_HW_CARD_DISABLED = 0x01,
2816 IWM_SW_CARD_DISABLED = 0x02,
2817 IWM_CT_KILL_CARD_DISABLED = 0x04,
2818 IWM_HALT_CARD_DISABLED = 0x08,
2819 IWM_CARD_DISABLED_MSK = 0x0f,
2820 IWM_CARD_IS_RX_ON = 0x10,
2824 * struct iwm_radio_version_notif - information on the radio version
2825 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2826 * @flags: %iwm_card_state_flags
2828 struct iwm_card_state_notif {
2830 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
2833 * struct iwm_missed_beacons_notif - information on missed beacons
2834 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
2835 * @mac_id: interface ID
2836 * @consec_missed_beacons_since_last_rx: number of consecutive missed
2837 * beacons since last RX.
2838 * @consec_missed_beacons: number of consecutive missed beacons
2839 * @num_expected_beacons:
2840 * @num_recvd_beacons:
2842 struct iwm_missed_beacons_notif {
2844 uint32_t consec_missed_beacons_since_last_rx;
2845 uint32_t consec_missed_beacons;
2846 uint32_t num_expected_beacons;
2847 uint32_t num_recvd_beacons;
2848 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
2851 * struct iwm_mfuart_load_notif - mfuart image version & status
2852 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 )
2853 * @installed_ver: installed image version
2854 * @external_ver: external image version
2855 * @status: MFUART loading status
2856 * @duration: MFUART loading time
2858 struct iwm_mfuart_load_notif {
2859 uint32_t installed_ver;
2860 uint32_t external_ver;
2863 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
2866 * struct iwm_set_calib_default_cmd - set default value for calibration.
2867 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
2868 * @calib_index: the calibration to set value for
2870 * @data: the value to set for the calibration result
2872 struct iwm_set_calib_default_cmd {
2873 uint16_t calib_index;
2876 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
2878 #define IWM_MAX_PORT_ID_NUM 2
2879 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
2882 * struct iwm_mcast_filter_cmd - configure multicast filter.
2883 * @filter_own: Set 1 to filter out multicast packets sent by station itself
2884 * @port_id: Multicast MAC addresses array specifier. This is a strange way
2885 * to identify network interface adopted in host-device IF.
2886 * It is used by FW as index in array of addresses. This array has
2887 * IWM_MAX_PORT_ID_NUM members.
2888 * @count: Number of MAC addresses in the array
2889 * @pass_all: Set 1 to pass all multicast packets.
2890 * @bssid: current association BSSID.
2891 * @addr_list: Place holder for array of MAC addresses.
2892 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
2894 struct iwm_mcast_filter_cmd {
2900 uint8_t reserved[2];
2901 uint8_t addr_list[0];
2902 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
2904 struct iwm_mvm_statistics_dbg {
2905 uint32_t burst_check;
2906 uint32_t burst_count;
2907 uint32_t wait_for_silence_timeout_cnt;
2908 uint32_t reserved[3];
2909 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
2911 struct iwm_mvm_statistics_div {
2915 uint32_t probe_time;
2918 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
2920 struct iwm_mvm_statistics_general_common {
2921 uint32_t temperature; /* radio temperature */
2922 uint32_t temperature_m; /* radio voltage */
2923 struct iwm_mvm_statistics_dbg dbg;
2924 uint32_t sleep_time;
2926 uint32_t slots_idle;
2927 uint32_t ttl_timestamp;
2928 struct iwm_mvm_statistics_div div;
2929 uint32_t rx_enable_counter;
2931 * num_of_sos_states:
2932 * count the number of times we have to re-tune
2933 * in order to get out of bad PHY status
2935 uint32_t num_of_sos_states;
2936 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2938 struct iwm_mvm_statistics_rx_non_phy {
2939 uint32_t bogus_cts; /* CTS received when not expecting CTS */
2940 uint32_t bogus_ack; /* ACK received when not expecting ACK */
2941 uint32_t non_bssid_frames; /* number of frames with BSSID that
2942 * doesn't belong to the STA BSSID */
2943 uint32_t filtered_frames; /* count frames that were dumped in the
2944 * filtering process */
2945 uint32_t non_channel_beacons; /* beacons with our bss id but not on
2946 * our serving channel */
2947 uint32_t channel_beacons; /* beacons with our bss id and in our
2948 * serving channel */
2949 uint32_t num_missed_bcon; /* number of missed beacons */
2950 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
2951 * ADC was in saturation */
2952 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
2954 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
2955 uint32_t interference_data_flag; /* flag for interference data
2956 * availability. 1 when data is
2958 uint32_t channel_load; /* counts RX Enable time in uSec */
2959 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
2960 * and CCK) counter */
2961 uint32_t beacon_rssi_a;
2962 uint32_t beacon_rssi_b;
2963 uint32_t beacon_rssi_c;
2964 uint32_t beacon_energy_a;
2965 uint32_t beacon_energy_b;
2966 uint32_t beacon_energy_c;
2967 uint32_t num_bt_kills;
2969 uint32_t directed_data_mpdu;
2970 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
2972 struct iwm_mvm_statistics_rx_phy {
2977 uint32_t overrun_err;
2978 uint32_t early_overrun_err;
2979 uint32_t crc32_good;
2980 uint32_t false_alarm_cnt;
2981 uint32_t fina_sync_err_cnt;
2982 uint32_t sfd_timeout;
2983 uint32_t fina_timeout;
2984 uint32_t unresponded_rts;
2985 uint32_t rxe_frame_limit_overrun;
2986 uint32_t sent_ack_cnt;
2987 uint32_t sent_cts_cnt;
2988 uint32_t sent_ba_rsp_cnt;
2989 uint32_t dsp_self_kill;
2990 uint32_t mh_format_err;
2991 uint32_t re_acq_main_rssi_sum;
2993 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
2995 struct iwm_mvm_statistics_rx_ht_phy {
2997 uint32_t overrun_err;
2998 uint32_t early_overrun_err;
2999 uint32_t crc32_good;
3001 uint32_t mh_format_err;
3002 uint32_t agg_crc32_good;
3003 uint32_t agg_mpdu_cnt;
3005 uint32_t unsupport_mcs;
3006 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
3008 #define IWM_MAX_CHAINS 3
3010 struct iwm_mvm_statistics_tx_non_phy_agg {
3011 uint32_t ba_timeout;
3012 uint32_t ba_reschedule_frames;
3013 uint32_t scd_query_agg_frame_cnt;
3014 uint32_t scd_query_no_agg;
3015 uint32_t scd_query_agg;
3016 uint32_t scd_query_mismatch;
3017 uint32_t frame_not_ready;
3019 uint32_t bt_prio_kill;
3020 uint32_t rx_ba_rsp_cnt;
3021 int8_t txpower[IWM_MAX_CHAINS];
3024 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
3026 struct iwm_mvm_statistics_tx_channel_width {
3027 uint32_t ext_cca_narrow_ch20[1];
3028 uint32_t ext_cca_narrow_ch40[2];
3029 uint32_t ext_cca_narrow_ch80[3];
3030 uint32_t ext_cca_narrow_ch160[4];
3031 uint32_t last_tx_ch_width_indx;
3032 uint32_t rx_detected_per_ch_width[4];
3033 uint32_t success_per_ch_width[4];
3034 uint32_t fail_per_ch_width[4];
3035 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
3037 struct iwm_mvm_statistics_tx {
3038 uint32_t preamble_cnt;
3039 uint32_t rx_detected_cnt;
3040 uint32_t bt_prio_defer_cnt;
3041 uint32_t bt_prio_kill_cnt;
3042 uint32_t few_bytes_cnt;
3043 uint32_t cts_timeout;
3044 uint32_t ack_timeout;
3045 uint32_t expected_ack_cnt;
3046 uint32_t actual_ack_cnt;
3047 uint32_t dump_msdu_cnt;
3048 uint32_t burst_abort_next_frame_mismatch_cnt;
3049 uint32_t burst_abort_missing_next_frame_cnt;
3050 uint32_t cts_timeout_collision;
3051 uint32_t ack_or_ba_timeout_collision;
3052 struct iwm_mvm_statistics_tx_non_phy_agg agg;
3053 struct iwm_mvm_statistics_tx_channel_width channel_width;
3054 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
3057 struct iwm_mvm_statistics_bt_activity {
3058 uint32_t hi_priority_tx_req_cnt;
3059 uint32_t hi_priority_tx_denied_cnt;
3060 uint32_t lo_priority_tx_req_cnt;
3061 uint32_t lo_priority_tx_denied_cnt;
3062 uint32_t hi_priority_rx_req_cnt;
3063 uint32_t hi_priority_rx_denied_cnt;
3064 uint32_t lo_priority_rx_req_cnt;
3065 uint32_t lo_priority_rx_denied_cnt;
3066 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3068 struct iwm_mvm_statistics_general {
3069 struct iwm_mvm_statistics_general_common common;
3070 uint32_t beacon_filtered;
3071 uint32_t missed_beacons;
3072 int8_t beacon_filter_average_energy;
3073 int8_t beacon_filter_reason;
3074 int8_t beacon_filter_current_energy;
3075 int8_t beacon_filter_reserved;
3076 uint32_t beacon_filter_delta_time;
3077 struct iwm_mvm_statistics_bt_activity bt_activity;
3078 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
3080 struct iwm_mvm_statistics_rx {
3081 struct iwm_mvm_statistics_rx_phy ofdm;
3082 struct iwm_mvm_statistics_rx_phy cck;
3083 struct iwm_mvm_statistics_rx_non_phy general;
3084 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht;
3085 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
3088 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
3090 * By default, uCode issues this notification after receiving a beacon
3091 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
3092 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
3094 * Statistics counters continue to increment beacon after beacon, but are
3095 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
3096 * 0x9c with CLEAR_STATS bit set (see above).
3098 * uCode also issues this notification during scans. uCode clears statistics
3099 * appropriately so that each notification contains statistics for only the
3100 * one channel that has just been scanned.
3103 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
3105 struct iwm_mvm_statistics_rx rx;
3106 struct iwm_mvm_statistics_tx tx;
3107 struct iwm_mvm_statistics_general general;
3110 /***********************************
3112 ***********************************/
3113 /* Smart Fifo state */
3115 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
3119 IWM_SF_HW_NUM_STATES
3122 /* Smart Fifo possible scenario */
3123 enum iwm_sf_scenario {
3124 IWM_SF_SCENARIO_SINGLE_UNICAST,
3125 IWM_SF_SCENARIO_AGG_UNICAST,
3126 IWM_SF_SCENARIO_MULTICAST,
3127 IWM_SF_SCENARIO_BA_RESP,
3128 IWM_SF_SCENARIO_TX_RESP,
3132 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
3133 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
3135 /* smart FIFO default values */
3136 #define IWM_SF_W_MARK_SISO 4096
3137 #define IWM_SF_W_MARK_MIMO2 8192
3138 #define IWM_SF_W_MARK_MIMO3 6144
3139 #define IWM_SF_W_MARK_LEGACY 4096
3140 #define IWM_SF_W_MARK_SCAN 4096
3142 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */
3143 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3144 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3145 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3146 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3147 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3148 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3149 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
3150 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
3151 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
3152 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
3154 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
3155 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3156 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3157 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3158 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3159 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
3160 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
3161 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
3162 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
3163 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
3164 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
3166 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
3168 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
3171 * Smart Fifo configuration command.
3172 * @state: smart fifo state, types listed in enum %iwm_sf_state.
3173 * @watermark: Minimum allowed available free space in RXF for transient state.
3174 * @long_delay_timeouts: aging and idle timer values for each scenario
3175 * in long delay state.
3176 * @full_on_timeouts: timer values for each scenario in full on state.
3178 struct iwm_sf_cfg_cmd {
3180 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
3181 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3182 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3183 } __packed; /* IWM_SF_CFG_API_S_VER_2 */
3186 * The first MAC indices (starting from 0)
3187 * are available to the driver, AUX follows
3189 #define IWM_MAC_INDEX_AUX 4
3190 #define IWM_MAC_INDEX_MIN_DRIVER 0
3191 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
3202 * enum iwm_mac_protection_flags - MAC context flags
3203 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
3204 * this will require CCK RTS/CTS2self.
3205 * RTS/CTS will protect full burst time.
3206 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
3207 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
3208 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
3210 enum iwm_mac_protection_flags {
3211 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
3212 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
3213 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
3214 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
3217 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
3218 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
3221 * enum iwm_mac_types - Supported MAC types
3222 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
3223 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
3224 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
3225 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
3226 * @IWM_FW_MAC_TYPE_IBSS: IBSS
3227 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
3228 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
3229 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
3230 * @IWM_FW_MAC_TYPE_GO: P2P GO
3231 * @IWM_FW_MAC_TYPE_TEST: ?
3232 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
3234 enum iwm_mac_types {
3235 IWM_FW_MAC_TYPE_FIRST = 1,
3236 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
3237 IWM_FW_MAC_TYPE_LISTENER,
3238 IWM_FW_MAC_TYPE_PIBSS,
3239 IWM_FW_MAC_TYPE_IBSS,
3240 IWM_FW_MAC_TYPE_BSS_STA,
3241 IWM_FW_MAC_TYPE_P2P_DEVICE,
3242 IWM_FW_MAC_TYPE_P2P_STA,
3244 IWM_FW_MAC_TYPE_TEST,
3245 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
3246 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
3249 * enum iwm_tsf_id - TSF hw timer ID
3250 * @IWM_TSF_ID_A: use TSF A
3251 * @IWM_TSF_ID_B: use TSF B
3252 * @IWM_TSF_ID_C: use TSF C
3253 * @IWM_TSF_ID_D: use TSF D
3254 * @IWM_NUM_TSF_IDS: number of TSF timers available
3261 IWM_NUM_TSF_IDS = 4,
3262 }; /* IWM_TSF_ID_API_E_VER_1 */
3265 * struct iwm_mac_data_ap - configuration data for AP MAC context
3266 * @beacon_time: beacon transmit time in system time
3267 * @beacon_tsf: beacon transmit time in TSF
3268 * @bi: beacon interval in TU
3269 * @bi_reciprocal: 2^32 / bi
3270 * @dtim_interval: dtim transmit time in TU
3271 * @dtim_reciprocal: 2^32 / dtim_interval
3272 * @mcast_qid: queue ID for multicast traffic
3273 * @beacon_template: beacon template ID
3275 struct iwm_mac_data_ap {
3276 uint32_t beacon_time;
3277 uint64_t beacon_tsf;
3279 uint32_t bi_reciprocal;
3280 uint32_t dtim_interval;
3281 uint32_t dtim_reciprocal;
3283 uint32_t beacon_template;
3284 } __packed; /* AP_MAC_DATA_API_S_VER_1 */
3287 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3288 * @beacon_time: beacon transmit time in system time
3289 * @beacon_tsf: beacon transmit time in TSF
3290 * @bi: beacon interval in TU
3291 * @bi_reciprocal: 2^32 / bi
3292 * @beacon_template: beacon template ID
3294 struct iwm_mac_data_ibss {
3295 uint32_t beacon_time;
3296 uint64_t beacon_tsf;
3298 uint32_t bi_reciprocal;
3299 uint32_t beacon_template;
3300 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
3303 * struct iwm_mac_data_sta - configuration data for station MAC context
3304 * @is_assoc: 1 for associated state, 0 otherwise
3305 * @dtim_time: DTIM arrival time in system time
3306 * @dtim_tsf: DTIM arrival time in TSF
3307 * @bi: beacon interval in TU, applicable only when associated
3308 * @bi_reciprocal: 2^32 / bi , applicable only when associated
3309 * @dtim_interval: DTIM interval in TU, applicable only when associated
3310 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
3311 * @listen_interval: in beacon intervals, applicable only when associated
3312 * @assoc_id: unique ID assigned by the AP during association
3314 struct iwm_mac_data_sta {
3319 uint32_t bi_reciprocal;
3320 uint32_t dtim_interval;
3321 uint32_t dtim_reciprocal;
3322 uint32_t listen_interval;
3324 uint32_t assoc_beacon_arrive_time;
3325 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
3328 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3329 * @ap: iwm_mac_data_ap struct with most config data
3330 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3331 * 0 indicates that there is no CT window.
3332 * @opp_ps_enabled: indicate that opportunistic PS allowed
3334 struct iwm_mac_data_go {
3335 struct iwm_mac_data_ap ap;
3337 uint32_t opp_ps_enabled;
3338 } __packed; /* GO_MAC_DATA_API_S_VER_1 */
3341 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3342 * @sta: iwm_mac_data_sta struct with most config data
3343 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3344 * 0 indicates that there is no CT window.
3346 struct iwm_mac_data_p2p_sta {
3347 struct iwm_mac_data_sta sta;
3349 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
3352 * struct iwm_mac_data_pibss - Pseudo IBSS config data
3353 * @stats_interval: interval in TU between statistics notifications to host.
3355 struct iwm_mac_data_pibss {
3356 uint32_t stats_interval;
3357 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3360 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3362 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3363 * other channels as well. This should be to true only in case that the
3364 * device is discoverable and there is an active GO. Note that setting this
3365 * field when not needed, will increase the number of interrupts and have
3366 * effect on the platform power, as this setting opens the Rx filters on
3369 struct iwm_mac_data_p2p_dev {
3370 uint32_t is_disc_extended;
3371 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3374 * enum iwm_mac_filter_flags - MAC context filter flags
3375 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3376 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3377 * control frames to the host
3378 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3379 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3380 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3381 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3382 * (in station mode when associated)
3383 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3384 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3385 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3387 enum iwm_mac_filter_flags {
3388 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3389 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3390 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3391 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3392 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3393 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3394 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3395 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3396 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3400 * enum iwm_mac_qos_flags - QoS flags
3401 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3402 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3403 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3406 enum iwm_mac_qos_flags {
3407 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3408 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3409 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3413 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3414 * @cw_min: Contention window, start value in numbers of slots.
3415 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3416 * @cw_max: Contention window, max value in numbers of slots.
3417 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3418 * @aifsn: Number of slots in Arbitration Interframe Space (before
3419 * performing random backoff timing prior to Tx). Device default 1.
3420 * @fifos_mask: FIFOs used by this MAC for this AC
3421 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3423 * One instance of this config struct for each of 4 EDCA access categories
3424 * in struct iwm_qosparam_cmd.
3426 * Device will automatically increase contention window by (2*CW) + 1 for each
3427 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3428 * value, to cap the CW value.
3436 } __packed; /* IWM_AC_QOS_API_S_VER_2 */
3439 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3440 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3441 * @id_and_color: ID and color of the MAC
3442 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3443 * @mac_type: one of IWM_FW_MAC_TYPE_*
3444 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
3445 * @node_addr: MAC address
3446 * @bssid_addr: BSSID
3447 * @cck_rates: basic rates available for CCK
3448 * @ofdm_rates: basic rates available for OFDM
3449 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3450 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3451 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3452 * @filter_flags: combination of IWM_MAC_FILTER_*
3453 * @qos_flags: from IWM_MAC_QOS_FLG_*
3454 * @ac: one iwm_mac_qos configuration for each AC
3455 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3457 struct iwm_mac_ctx_cmd {
3458 /* COMMON_INDEX_HDR_API_S_VER_1 */
3459 uint32_t id_and_color;
3461 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3464 uint8_t node_addr[6];
3465 uint16_t reserved_for_node_addr;
3466 uint8_t bssid_addr[6];
3467 uint16_t reserved_for_bssid_addr;
3469 uint32_t ofdm_rates;
3470 uint32_t protection_flags;
3471 uint32_t cck_short_preamble;
3472 uint32_t short_slot;
3473 uint32_t filter_flags;
3474 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3476 struct iwm_ac_qos ac[IWM_AC_NUM+1];
3477 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3479 struct iwm_mac_data_ap ap;
3480 struct iwm_mac_data_go go;
3481 struct iwm_mac_data_sta sta;
3482 struct iwm_mac_data_p2p_sta p2p_sta;
3483 struct iwm_mac_data_p2p_dev p2p_dev;
3484 struct iwm_mac_data_pibss pibss;
3485 struct iwm_mac_data_ibss ibss;
3487 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3489 static inline uint32_t iwm_mvm_reciprocal(uint32_t v)
3493 return 0xFFFFFFFF / v;
3496 #define IWM_NONQOS_SEQ_GET 0x1
3497 #define IWM_NONQOS_SEQ_SET 0x2
3498 struct iwm_nonqos_seq_query_cmd {
3499 uint32_t get_set_flag;
3500 uint32_t mac_id_n_color;
3503 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3505 /* Power Management Commands, Responses, Notifications */
3507 /* Radio LP RX Energy Threshold measured in dBm */
3508 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3509 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3510 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3513 * enum iwm_scan_flags - masks for power table command flags
3514 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3515 * receiver and transmitter. '0' - does not allow.
3516 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3517 * '1' Driver enables PM (use rest of parameters)
3518 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3519 * '1' PM could sleep over DTIM till listen Interval.
3520 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3521 * access categories are both delivery and trigger enabled.
3522 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3523 * PBW Snoozing enabled
3524 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3525 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3526 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3527 * detection enablement
3529 enum iwm_power_flags {
3530 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3531 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3532 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3533 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3534 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3535 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3536 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3537 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3540 #define IWM_POWER_VEC_SIZE 5
3543 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3544 * is used also with a new power API for device wide power settings.
3545 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3547 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3548 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3549 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3550 * set regardless of power scheme or current power state.
3551 * FW use this value also when PM is disabled.
3552 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3553 * PSM transition - legacy PM
3554 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3555 * PSM transition - legacy PM
3556 * @sleep_interval: not in use
3557 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3558 * is set. For example, if it is required to skip over
3559 * one DTIM, this value need to be set to 2 (DTIM periods).
3560 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3563 struct iwm_powertable_cmd {
3564 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3566 uint8_t keep_alive_seconds;
3567 uint8_t debug_flags;
3568 uint32_t rx_data_timeout;
3569 uint32_t tx_data_timeout;
3570 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3571 uint32_t skip_dtim_periods;
3572 uint32_t lprx_rssi_threshold;
3576 * enum iwm_device_power_flags - masks for device power command flags
3577 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3578 * receiver and transmitter. '0' - does not allow. This flag should be
3579 * always set to '1' unless one need to disable actual power down for debug
3581 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning
3582 * that power management is disabled. '0' Power management is enabled, one
3583 * of power schemes is applied.
3585 enum iwm_device_power_flags {
3586 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3587 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13),
3591 * struct iwm_device_power_cmd - device wide power command.
3592 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
3594 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3596 struct iwm_device_power_cmd {
3597 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3603 * struct iwm_mac_power_cmd - New power command containing uAPSD support
3604 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3605 * @id_and_color: MAC contex identifier
3606 * @flags: Power table command flags from POWER_FLAGS_*
3607 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3608 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3609 * set regardless of power scheme or current power state.
3610 * FW use this value also when PM is disabled.
3611 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3612 * PSM transition - legacy PM
3613 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3614 * PSM transition - legacy PM
3615 * @sleep_interval: not in use
3616 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3617 * is set. For example, if it is required to skip over
3618 * one DTIM, this value need to be set to 2 (DTIM periods).
3619 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3620 * PSM transition - uAPSD
3621 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3622 * PSM transition - uAPSD
3623 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3625 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3626 * @snooze_interval: Maximum time between attempts to retrieve buffered data
3627 * from the AP [msec]
3628 * @snooze_window: A window of time in which PBW snoozing insures that all
3629 * packets received. It is also the minimum time from last
3630 * received unicast RX packet, before client stops snoozing
3633 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3634 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3635 * each corresponding AC.
3636 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3637 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3639 * @heavy_tx_thld_packets: TX threshold measured in number of packets
3640 * @heavy_rx_thld_packets: RX threshold measured in number of packets
3641 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3642 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3643 * @limited_ps_threshold:
3645 struct iwm_mac_power_cmd {
3646 /* CONTEXT_DESC_API_T_VER_1 */
3647 uint32_t id_and_color;
3649 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3651 uint16_t keep_alive_seconds;
3652 uint32_t rx_data_timeout;
3653 uint32_t tx_data_timeout;
3654 uint32_t rx_data_timeout_uapsd;
3655 uint32_t tx_data_timeout_uapsd;
3656 uint8_t lprx_rssi_threshold;
3657 uint8_t skip_dtim_periods;
3658 uint16_t snooze_interval;
3659 uint16_t snooze_window;
3660 uint8_t snooze_step;
3662 uint8_t uapsd_ac_flags;
3663 uint8_t uapsd_max_sp;
3664 uint8_t heavy_tx_thld_packets;
3665 uint8_t heavy_rx_thld_packets;
3666 uint8_t heavy_tx_thld_percentage;
3667 uint8_t heavy_rx_thld_percentage;
3668 uint8_t limited_ps_threshold;
3673 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3674 * associated AP is identified as improperly implementing uAPSD protocol.
3675 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3676 * @sta_id: index of station in uCode's station table - associated AP ID in
3679 struct iwm_uapsd_misbehaving_ap_notif {
3682 uint8_t reserved[3];
3686 * struct iwm_beacon_filter_cmd
3687 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3688 * @id_and_color: MAC contex identifier
3689 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3690 * to driver if delta in Energy values calculated for this and last
3691 * passed beacon is greater than this threshold. Zero value means that
3692 * the Energy change is ignored for beacon filtering, and beacon will
3693 * not be forced to be sent to driver regardless of this delta. Typical
3695 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3696 * Send beacon to driver if delta in Energy values calculated for this
3697 * and last passed beacon is greater than this threshold. Zero value
3698 * means that the Energy change is ignored for beacon filtering while in
3699 * Roaming state, typical energy delta 1dB.
3700 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3701 * calculated for current beacon is less than the threshold, use
3702 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3703 * Threshold. Typical energy threshold is -72dBm.
3704 * @bf_temp_threshold: This threshold determines the type of temperature
3705 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3706 * If the current temperature is above this threshold - Fast filter
3707 * will be used, If the current temperature is below this threshold -
3708 * Slow filter will be used.
3709 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3710 * calculated for this and the last passed beacon is greater than this
3711 * threshold. Zero value means that the temperature change is ignored for
3712 * beacon filtering; beacons will not be forced to be sent to driver
3713 * regardless of whether its temperature has been changed.
3714 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3715 * calculated for this and the last passed beacon is greater than this
3716 * threshold. Zero value means that the temperature change is ignored for
3717 * beacon filtering; beacons will not be forced to be sent to driver
3718 * regardless of whether its temperature has been changed.
3719 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3720 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed
3721 * for a specific period of time. Units: Beacons.
3722 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3723 * for a longer period of time then this escape-timeout. Units: Beacons.
3724 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3726 struct iwm_beacon_filter_cmd {
3727 uint32_t bf_energy_delta;
3728 uint32_t bf_roaming_energy_delta;
3729 uint32_t bf_roaming_state;
3730 uint32_t bf_temp_threshold;
3731 uint32_t bf_temp_fast_filter;
3732 uint32_t bf_temp_slow_filter;
3733 uint32_t bf_enable_beacon_filter;
3734 uint32_t bf_debug_flag;
3735 uint32_t bf_escape_timer;
3736 uint32_t ba_escape_timer;
3737 uint32_t ba_enable_beacon_abort;
3740 /* Beacon filtering and beacon abort */
3741 #define IWM_BF_ENERGY_DELTA_DEFAULT 5
3742 #define IWM_BF_ENERGY_DELTA_MAX 255
3743 #define IWM_BF_ENERGY_DELTA_MIN 0
3745 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3746 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3747 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3749 #define IWM_BF_ROAMING_STATE_DEFAULT 72
3750 #define IWM_BF_ROAMING_STATE_MAX 255
3751 #define IWM_BF_ROAMING_STATE_MIN 0
3753 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3754 #define IWM_BF_TEMP_THRESHOLD_MAX 255
3755 #define IWM_BF_TEMP_THRESHOLD_MIN 0
3757 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
3758 #define IWM_BF_TEMP_FAST_FILTER_MAX 255
3759 #define IWM_BF_TEMP_FAST_FILTER_MIN 0
3761 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
3762 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255
3763 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0
3765 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
3767 #define IWM_BF_DEBUG_FLAG_DEFAULT 0
3769 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50
3770 #define IWM_BF_ESCAPE_TIMER_MAX 1024
3771 #define IWM_BF_ESCAPE_TIMER_MIN 0
3773 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6
3774 #define IWM_BA_ESCAPE_TIMER_D3 9
3775 #define IWM_BA_ESCAPE_TIMER_MAX 1024
3776 #define IWM_BA_ESCAPE_TIMER_MIN 0
3778 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
3780 #define IWM_BF_CMD_CONFIG_DEFAULTS \
3781 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
3782 .bf_roaming_energy_delta = \
3783 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
3784 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
3785 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
3786 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
3787 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
3788 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
3789 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
3790 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
3793 * These serve as indexes into
3794 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
3795 * TODO: avoid overlap between legacy and HT rates
3798 IWM_RATE_1M_INDEX = 0,
3799 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
3803 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
3805 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
3806 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
3807 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
3808 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
3811 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
3813 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
3815 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
3817 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
3819 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
3821 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
3822 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
3824 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX,
3825 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
3826 IWM_RATE_MCS_8_INDEX,
3827 IWM_RATE_MCS_9_INDEX,
3828 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
3829 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
3830 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
3833 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
3835 /* fw API values for legacy bit rates, both OFDM and CCK */
3837 IWM_RATE_6M_PLCP = 13,
3838 IWM_RATE_9M_PLCP = 15,
3839 IWM_RATE_12M_PLCP = 5,
3840 IWM_RATE_18M_PLCP = 7,
3841 IWM_RATE_24M_PLCP = 9,
3842 IWM_RATE_36M_PLCP = 11,
3843 IWM_RATE_48M_PLCP = 1,
3844 IWM_RATE_54M_PLCP = 3,
3845 IWM_RATE_1M_PLCP = 10,
3846 IWM_RATE_2M_PLCP = 20,
3847 IWM_RATE_5M_PLCP = 55,
3848 IWM_RATE_11M_PLCP = 110,
3849 IWM_RATE_INVM_PLCP = -1,
3853 * rate_n_flags bit fields
3855 * The 32-bit value has different layouts in the low 8 bites depending on the
3856 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
3857 * for CCK and OFDM).
3859 * High-throughput (HT) rate format
3860 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
3861 * Very High-throughput (VHT) rate format
3862 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
3863 * Legacy OFDM rate format for bits 7:0
3864 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
3865 * Legacy CCK rate format for bits 7:0:
3866 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
3869 /* Bit 8: (1) HT format, (0) legacy or VHT format */
3870 #define IWM_RATE_MCS_HT_POS 8
3871 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
3873 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
3874 #define IWM_RATE_MCS_CCK_POS 9
3875 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
3877 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
3878 #define IWM_RATE_MCS_VHT_POS 26
3879 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
3883 * High-throughput (HT) rate format for bits 7:0
3885 * 2-0: MCS rate base
3894 * 4-3: 0) Single stream (SISO)
3895 * 1) Dual stream (MIMO)
3896 * 2) Triple stream (MIMO)
3897 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
3898 * (bits 7-6 are zero)
3900 * Together the low 5 bits work out to the MCS index because we don't
3901 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
3902 * streams and 16-23 have three streams. We could also support MCS 32
3903 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
3905 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
3906 #define IWM_RATE_HT_MCS_NSS_POS 3
3907 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
3909 /* Bit 10: (1) Use Green Field preamble */
3910 #define IWM_RATE_HT_MCS_GF_POS 10
3911 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
3913 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
3916 * Very High-throughput (VHT) rate format for bits 7:0
3918 * 3-0: VHT MCS (0-9)
3919 * 5-4: number of streams - 1:
3920 * 0) Single stream (SISO)
3921 * 1) Dual stream (MIMO)
3922 * 2) Triple stream (MIMO)
3925 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
3926 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
3927 #define IWM_RATE_VHT_MCS_NSS_POS 4
3928 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
3931 * Legacy OFDM rate format for bits 7:0
3943 * Legacy CCK rate format for bits 7:0:
3944 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
3952 #define IWM_RATE_LEGACY_RATE_MSK 0xff
3956 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
3957 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
3959 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11
3960 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3961 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3962 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3963 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3964 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3966 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
3967 #define IWM_RATE_MCS_SGI_POS 13
3968 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
3970 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
3971 #define IWM_RATE_MCS_ANT_POS 14
3972 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
3973 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
3974 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
3975 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
3976 IWM_RATE_MCS_ANT_B_MSK)
3977 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
3978 IWM_RATE_MCS_ANT_C_MSK)
3979 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
3980 #define IWM_RATE_MCS_ANT_NUM 3
3982 /* Bit 17-18: (0) SS, (1) SS*2 */
3983 #define IWM_RATE_MCS_STBC_POS 17
3984 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
3986 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
3987 #define IWM_RATE_MCS_BF_POS 19
3988 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
3990 /* Bit 20: (0) ZLF is off, (1) ZLF is on */
3991 #define IWM_RATE_MCS_ZLF_POS 20
3992 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
3994 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
3995 #define IWM_RATE_MCS_DUP_POS 24
3996 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)
3998 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
3999 #define IWM_RATE_MCS_LDPC_POS 27
4000 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)
4003 /* Link Quality definitions */
4005 /* # entries in rate scale table to support Tx retries */
4006 #define IWM_LQ_MAX_RETRY_NUM 16
4008 /* Link quality command flags bit fields */
4010 /* Bit 0: (0) Don't use RTS (1) Use RTS */
4011 #define IWM_LQ_FLAG_USE_RTS_POS 0
4012 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
4014 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
4015 #define IWM_LQ_FLAG_COLOR_POS 1
4016 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
4018 /* Bit 4-5: Tx RTS BW Signalling
4019 * (0) No RTS BW signalling
4020 * (1) Static BW signalling
4021 * (2) Dynamic BW signalling
4023 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
4024 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4025 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4026 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4028 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
4029 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
4031 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
4032 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
4035 * struct iwm_lq_cmd - link quality command
4036 * @sta_id: station to update
4037 * @control: not used
4038 * @flags: combination of IWM_LQ_FLAG_*
4039 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
4041 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
4042 * Should be ANT_[ABC]
4043 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
4044 * @initial_rate_index: first index from rs_table per AC category
4045 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
4046 * value of 100 is one usec. Range is 100 to 8000
4047 * @agg_disable_start_th: try-count threshold for starting aggregation.
4048 * If a frame has higher try-count, it should not be selected for
4049 * starting an aggregation sequence.
4050 * @agg_frame_cnt_limit: max frame count in an aggregation.
4052 * 1: no aggregation (one frame per aggregation)
4053 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
4054 * @rs_table: array of rates for each TX try, each is rate_n_flags,
4055 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
4056 * @bf_params: beam forming params, currently not used
4062 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
4065 uint8_t single_stream_ant_msk;
4066 uint8_t dual_stream_ant_msk;
4067 uint8_t initial_rate_index[IWM_AC_NUM];
4068 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
4069 uint16_t agg_time_limit;
4070 uint8_t agg_disable_start_th;
4071 uint8_t agg_frame_cnt_limit;
4073 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
4075 }; /* LINK_QUALITY_CMD_API_S_VER_1 */
4078 * enum iwm_tx_flags - bitmasks for tx_flags in TX command
4079 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
4080 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
4081 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
4082 * Otherwise, use rate_n_flags from the TX command
4083 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
4084 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
4085 * Must set IWM_TX_CMD_FLG_ACK with this flag.
4086 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection
4087 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
4088 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
4089 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
4090 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame
4091 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
4092 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
4093 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
4094 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame
4095 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
4096 * Should be set for beacons and probe responses
4097 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
4098 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
4099 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
4100 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
4101 * Should be set for 26/30 length MAC headers
4102 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
4103 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration
4104 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
4105 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
4106 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
4107 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
4108 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
4109 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
4112 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0),
4113 IWM_TX_CMD_FLG_ACK = (1 << 3),
4114 IWM_TX_CMD_FLG_STA_RATE = (1 << 4),
4115 IWM_TX_CMD_FLG_BA = (1 << 5),
4116 IWM_TX_CMD_FLG_BAR = (1 << 6),
4117 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7),
4118 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8),
4119 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9),
4120 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10),
4121 IWM_TX_CMD_FLG_BT_DIS = (1 << 12),
4122 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13),
4123 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14),
4124 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15),
4125 IWM_TX_CMD_FLG_TSF = (1 << 16),
4126 IWM_TX_CMD_FLG_CALIB = (1 << 17),
4127 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18),
4128 IWM_TX_CMD_FLG_AGG_START = (1 << 19),
4129 IWM_TX_CMD_FLG_MH_PAD = (1 << 20),
4130 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21),
4131 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22),
4132 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23),
4133 IWM_TX_CMD_FLG_DUR = (1 << 25),
4134 IWM_TX_CMD_FLG_FW_DROP = (1 << 26),
4135 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27),
4136 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28),
4137 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31)
4138 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
4141 * enum iwm_tx_pm_timeouts - pm timeout values in TX command
4142 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode
4143 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU
4144 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec
4146 enum iwm_tx_pm_timeouts {
4147 IWM_PM_FRAME_NONE = 0,
4148 IWM_PM_FRAME_MGMT = 2,
4149 IWM_PM_FRAME_ASSOC = 3,
4153 * TX command security control
4155 #define IWM_TX_CMD_SEC_WEP 0x01
4156 #define IWM_TX_CMD_SEC_CCM 0x02
4157 #define IWM_TX_CMD_SEC_TKIP 0x03
4158 #define IWM_TX_CMD_SEC_EXT 0x04
4159 #define IWM_TX_CMD_SEC_MSK 0x07
4160 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
4161 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
4162 #define IWM_TX_CMD_SEC_KEY128 0x08
4164 /* TODO: how does these values are OK with only 16 bit variable??? */
4166 * TX command next frame info
4168 * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
4169 * bit 3 - immediate ACK required
4170 * bit 4 - rate is taken from STA table
4171 * bit 5 - frame belongs to BA stream
4172 * bit 6 - immediate BA response expected
4174 * bits 8:15 - Station ID
4177 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
4178 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
4179 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
4180 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
4181 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
4182 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
4183 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
4184 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
4185 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)
4188 * TX command Frame life time in us - to be written in pm_frame_timeout
4190 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
4191 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
4192 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
4193 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
4196 * TID for non QoS frames - to be written in tid_tspec
4198 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
4201 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
4203 #define IWM_DEFAULT_TX_RETRY 15
4204 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3
4205 #define IWM_RTS_DFAULT_RETRY_LIMIT 60
4206 #define IWM_BAR_DFAULT_RETRY_LIMIT 60
4207 #define IWM_LOW_RETRY_LIMIT 7
4209 /* TODO: complete documentation for try_cnt and btkill_cnt */
4211 * struct iwm_tx_cmd - TX command struct to FW
4212 * ( IWM_TX_CMD = 0x1c )
4213 * @len: in bytes of the payload, see below for details
4214 * @next_frame_len: same as len, but for next frame (0 if not applicable)
4215 * Used for fragmentation and bursting, but not in 11n aggregation.
4216 * @tx_flags: combination of IWM_TX_CMD_FLG_*
4217 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
4218 * cleared. Combination of IWM_RATE_MCS_*
4219 * @sta_id: index of destination station in FW station table
4220 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
4221 * @initial_rate_index: index into the rate table for initial TX attempt.
4222 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
4223 * @key: security key
4224 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_*
4225 * @life_time: frame life time (usecs??)
4226 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt +
4227 * btkill_cnd + reserved), first 32 bits. "0" disables usage.
4228 * @dram_msb_ptr: upper bits of the scratch physical address
4229 * @rts_retry_limit: max attempts for RTS
4230 * @data_retry_limit: max attempts to send the data packet
4231 * @tid_spec: TID/tspec
4232 * @pm_frame_timeout: PM TX frame timeout
4233 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not
4234 * specified by HCCA protocol
4236 * The byte count (both len and next_frame_len) includes MAC header
4237 * (24/26/30/32 bytes)
4238 * + 2 bytes pad if 26/30 header size
4239 * + 8 byte IV for CCM or TKIP (not used for WEP)
4241 * + 8-byte MIC (not used for CCM/WEP)
4242 * It does not include post-MAC padding, i.e.,
4243 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.
4244 * Range of len: 14-2342 bytes.
4246 * After the struct fields the MAC header is placed, plus any padding,
4247 * and then the actial payload.
4251 uint16_t next_frame_len;
4257 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */
4258 uint32_t rate_n_flags;
4261 uint8_t initial_rate_index;
4264 uint16_t next_frame_flags;
4267 uint32_t dram_lsb_ptr;
4268 uint8_t dram_msb_ptr;
4269 uint8_t rts_retry_limit;
4270 uint8_t data_retry_limit;
4272 uint16_t pm_frame_timeout;
4273 uint16_t driver_txop;
4275 struct ieee80211_frame hdr[0];
4276 } __packed; /* IWM_TX_CMD_API_S_VER_3 */
4279 * TX response related data
4283 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx
4284 * @IWM_TX_STATUS_SUCCESS:
4285 * @IWM_TX_STATUS_DIRECT_DONE:
4286 * @IWM_TX_STATUS_POSTPONE_DELAY:
4287 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES:
4288 * @IWM_TX_STATUS_POSTPONE_BT_PRIO:
4289 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD:
4290 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK:
4291 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
4292 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT:
4293 * @IWM_TX_STATUS_FAIL_LONG_LIMIT:
4294 * @IWM_TX_STATUS_FAIL_UNDERRUN:
4295 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW:
4296 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH:
4297 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE:
4298 * @IWM_TX_STATUS_FAIL_DEST_PS:
4299 * @IWM_TX_STATUS_FAIL_HOST_ABORTED:
4300 * @IWM_TX_STATUS_FAIL_BT_RETRY:
4301 * @IWM_TX_STATUS_FAIL_STA_INVALID:
4302 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED:
4303 * @IWM_TX_STATUS_FAIL_TID_DISABLE:
4304 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED:
4305 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL:
4306 * @IWM_TX_STATUS_FAIL_FW_DROP:
4307 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
4309 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT:
4311 * @IWM_TX_MODE_NO_BURST:
4312 * @IWM_TX_MODE_IN_BURST_SEQ:
4313 * @IWM_TX_MODE_FIRST_IN_BURST:
4314 * @IWM_TX_QUEUE_NUM_MSK:
4316 * Valid only if frame_count =1
4317 * TODO: complete documentation
4319 enum iwm_tx_status {
4320 IWM_TX_STATUS_MSK = 0x000000ff,
4321 IWM_TX_STATUS_SUCCESS = 0x01,
4322 IWM_TX_STATUS_DIRECT_DONE = 0x02,
4324 IWM_TX_STATUS_POSTPONE_DELAY = 0x40,
4325 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
4326 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42,
4327 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
4328 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
4330 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
4331 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
4332 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83,
4333 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84,
4334 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
4335 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
4336 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
4337 IWM_TX_STATUS_FAIL_DEST_PS = 0x88,
4338 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89,
4339 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a,
4340 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b,
4341 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
4342 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d,
4343 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
4344 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f,
4345 IWM_TX_STATUS_FAIL_FW_DROP = 0x90,
4346 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91,
4347 IWM_TX_STATUS_INTERNAL_ABORT = 0x92,
4348 IWM_TX_MODE_MSK = 0x00000f00,
4349 IWM_TX_MODE_NO_BURST = 0x00000000,
4350 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100,
4351 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200,
4352 IWM_TX_QUEUE_NUM_MSK = 0x0001f000,
4353 IWM_TX_NARROW_BW_MSK = 0x00060000,
4354 IWM_TX_NARROW_BW_1DIV2 = 0x00020000,
4355 IWM_TX_NARROW_BW_1DIV4 = 0x00040000,
4356 IWM_TX_NARROW_BW_1DIV8 = 0x00060000,
4360 * enum iwm_tx_agg_status - TX aggregation status
4361 * @IWM_AGG_TX_STATE_STATUS_MSK:
4362 * @IWM_AGG_TX_STATE_TRANSMITTED:
4363 * @IWM_AGG_TX_STATE_UNDERRUN:
4364 * @IWM_AGG_TX_STATE_BT_PRIO:
4365 * @IWM_AGG_TX_STATE_FEW_BYTES:
4366 * @IWM_AGG_TX_STATE_ABORT:
4367 * @IWM_AGG_TX_STATE_LAST_SENT_TTL:
4368 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT:
4369 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL:
4370 * @IWM_AGG_TX_STATE_SCD_QUERY:
4371 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32:
4372 * @IWM_AGG_TX_STATE_RESPONSE:
4373 * @IWM_AGG_TX_STATE_DUMP_TX:
4374 * @IWM_AGG_TX_STATE_DELAY_TX:
4375 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
4376 * occur if tx failed for this frame when it was a member of a previous
4377 * aggregation block). If rate scaling is used, retry count indicates the
4378 * rate table entry used for all frames in the new agg.
4379 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
4382 * TODO: complete documentation
4384 enum iwm_tx_agg_status {
4385 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff,
4386 IWM_AGG_TX_STATE_TRANSMITTED = 0x000,
4387 IWM_AGG_TX_STATE_UNDERRUN = 0x001,
4388 IWM_AGG_TX_STATE_BT_PRIO = 0x002,
4389 IWM_AGG_TX_STATE_FEW_BYTES = 0x004,
4390 IWM_AGG_TX_STATE_ABORT = 0x008,
4391 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010,
4392 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020,
4393 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040,
4394 IWM_AGG_TX_STATE_SCD_QUERY = 0x080,
4395 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100,
4396 IWM_AGG_TX_STATE_RESPONSE = 0x1ff,
4397 IWM_AGG_TX_STATE_DUMP_TX = 0x200,
4398 IWM_AGG_TX_STATE_DELAY_TX = 0x400,
4399 IWM_AGG_TX_STATE_TRY_CNT_POS = 12,
4400 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS,
4403 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
4404 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
4405 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)
4408 * The mask below describes a status where we are absolutely sure that the MPDU
4409 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've
4410 * written the bytes to the TXE, but we know nothing about what the DSP did.
4412 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \
4413 IWM_AGG_TX_STATE_ABORT | \
4414 IWM_AGG_TX_STATE_SCD_QUERY)
4417 * IWM_REPLY_TX = 0x1c (response)
4419 * This response may be in one of two slightly different formats, indicated
4420 * by the frame_count field:
4422 * 1) No aggregation (frame_count == 1). This reports Tx results for a single
4423 * frame. Multiple attempts, at various bit rates, may have been made for
4426 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more
4427 * frames that used block-acknowledge. All frames were transmitted at
4428 * same rate. Rate scaling may have been used if first frame in this new
4429 * agg block failed in previous agg block(s).
4431 * Note that, for aggregation, ACK (block-ack) status is not delivered
4432 * here; block-ack has not been received by the time the device records
4434 * This status relates to reasons the tx might have been blocked or aborted
4435 * within the device, rather than whether it was received successfully by
4436 * the destination station.
4440 * struct iwm_agg_tx_status - per packet TX aggregation status
4441 * @status: enum iwm_tx_agg_status
4442 * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
4444 struct iwm_agg_tx_status {
4450 * definitions for initial rate index field
4451 * bits [3:0] initial rate index
4452 * bits [6:4] rate table color, used for the initial rate
4453 * bit-7 invalid rate indication
4455 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f
4456 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70
4457 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80
4459 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
4460 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)
4463 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet
4464 * ( IWM_REPLY_TX = 0x1c )
4465 * @frame_count: 1 no aggregation, >1 aggregation
4466 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
4467 * @failure_rts: num of failures due to unsuccessful RTS
4468 * @failure_frame: num failures due to no ACK (unused for agg)
4469 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
4470 * Tx of all the batch. IWM_RATE_MCS_*
4471 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
4472 * for agg: RTS + CTS + aggregation tx time + block-ack time.
4474 * @pa_status: tx power info
4475 * @pa_integ_res_a: tx power info
4476 * @pa_integ_res_b: tx power info
4477 * @pa_integ_res_c: tx power info
4478 * @measurement_req_id: tx power info
4479 * @tfd_info: TFD information set by the FH
4480 * @seq_ctl: sequence control from the Tx cmd
4481 * @byte_cnt: byte count from the Tx cmd
4482 * @tlc_info: TLC rate info
4483 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
4484 * @frame_ctrl: frame control
4485 * @status: for non-agg: frame status IWM_TX_STATUS_*
4486 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields
4487 * follow this one, up to frame_count.
4489 * After the array of statuses comes the SSN of the SCD. Look at
4490 * %iwm_mvm_get_scd_ssn for more details.
4492 struct iwm_mvm_tx_resp {
4493 uint8_t frame_count;
4494 uint8_t bt_kill_count;
4495 uint8_t failure_rts;
4496 uint8_t failure_frame;
4497 uint32_t initial_rate;
4498 uint16_t wireless_media_time;
4501 uint8_t pa_integ_res_a[3];
4502 uint8_t pa_integ_res_b[3];
4503 uint8_t pa_integ_res_c[3];
4504 uint16_t measurement_req_id;
4512 uint16_t frame_ctrl;
4514 struct iwm_agg_tx_status status;
4515 } __packed; /* IWM_TX_RSP_API_S_VER_3 */
4518 * struct iwm_mvm_ba_notif - notifies about reception of BA
4519 * ( IWM_BA_NOTIF = 0xc5 )
4520 * @sta_addr_lo32: lower 32 bits of the MAC address
4521 * @sta_addr_hi16: upper 16 bits of the MAC address
4522 * @sta_id: Index of recipient (BA-sending) station in fw's station table
4523 * @tid: tid of the session
4525 * @bitmap: the bitmap of the BA notification as seen in the air
4526 * @scd_flow: the tx queue this BA relates to
4527 * @scd_ssn: the index of the last contiguously sent packet
4528 * @txed: number of Txed frames in this batch
4529 * @txed_2_done: number of Acked frames in this batch
4531 struct iwm_mvm_ba_notif {
4532 uint32_t sta_addr_lo32;
4533 uint16_t sta_addr_hi16;
4543 uint8_t txed_2_done;
4548 * struct iwm_mac_beacon_cmd - beacon template command
4549 * @tx: the tx commands associated with the beacon frame
4550 * @template_id: currently equal to the mac context id of the coresponding
4552 * @tim_idx: the offset of the tim IE in the beacon
4553 * @tim_size: the length of the tim IE
4554 * @frame: the template of the beacon frame
4556 struct iwm_mac_beacon_cmd {
4557 struct iwm_tx_cmd tx;
4558 uint32_t template_id;
4561 struct ieee80211_frame frame[0];
4564 struct iwm_beacon_notif {
4565 struct iwm_mvm_tx_resp beacon_notify_hdr;
4567 uint32_t ibss_mgr_status;
4571 * enum iwm_dump_control - dump (flush) control flags
4572 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
4573 * and the TFD queues are empty.
4575 enum iwm_dump_control {
4576 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1),
4580 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4581 * @queues_ctl: bitmap of queues to flush
4582 * @flush_ctl: control flags
4583 * @reserved: reserved
4585 struct iwm_tx_path_flush_cmd {
4586 uint32_t queues_ctl;
4589 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4592 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD
4593 * @tx_resp: the Tx response from the fw (agg or non-agg)
4595 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4596 * it can't know that everything will go well until the end of the AMPDU, it
4597 * can't know in advance the number of MPDUs that will be sent in the current
4598 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4599 * Hence, it can't know in advance what the SSN of the SCD will be at the end
4600 * of the batch. This is why the SSN of the SCD is written at the end of the
4601 * whole struct at a variable offset. This function knows how to cope with the
4602 * variable offset and returns the SSN of the SCD.
4604 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp)
4606 return le32_to_cpup((uint32_t *)&tx_resp->status +
4607 tx_resp->frame_count) & 0xfff;
4611 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command
4613 * @sta_id: station id
4615 * @scd_queue: scheduler queue to confiug
4616 * @enable: 1 queue enable, 0 queue disable
4617 * @aggregate: 1 aggregated queue, 0 otherwise
4618 * @tx_fifo: %enum iwm_mvm_tx_fifo
4619 * @window: BA window size
4620 * @ssn: SSN for the BA agreement
4622 struct iwm_scd_txq_cfg_cmd {
4633 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */
4636 * struct iwm_scd_txq_cfg_rsp
4637 * @token: taken from the command
4638 * @sta_id: station id from the command
4639 * @tid: tid from the command
4640 * @scd_queue: scd_queue from the command
4642 struct iwm_scd_txq_cfg_rsp {
4647 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */
4650 /* Scan Commands, Responses, Notifications */
4652 /* Max number of IEs for direct SSID scans in a command */
4653 #define IWM_PROBE_OPTION_MAX 20
4656 * struct iwm_ssid_ie - directed scan network information element
4658 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
4659 * selected by "type" bit field in struct iwm_scan_channel;
4660 * each channel may select different ssids from among the 20 entries.
4661 * SSID IEs get transmitted in reverse order of entry.
4663 struct iwm_ssid_ie {
4666 uint8_t ssid[IEEE80211_NWID_LEN];
4667 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4670 #define IWM_SCAN_MAX_BLACKLIST_LEN 64
4671 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16
4672 #define IWM_SCAN_MAX_PROFILES 11
4673 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
4675 /* Default watchdog (in MS) for scheduled scan iteration */
4676 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
4678 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
4679 #define IWM_CAN_ABORT_STATUS 1
4681 #define IWM_FULL_SCAN_MULTIPLIER 5
4682 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3
4683 #define IWM_MAX_SCHED_SCAN_PLANS 2
4686 * iwm_scan_schedule_lmac - schedule of scan offload
4687 * @delay: delay between iterations, in seconds.
4688 * @iterations: num of scan iterations
4689 * @full_scan_mul: number of partial scans before each full scan
4691 struct iwm_scan_schedule_lmac {
4694 uint8_t full_scan_mul;
4695 } __packed; /* SCAN_SCHEDULE_API_S */
4698 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S
4699 * @tx_flags: combination of TX_CMD_FLG_*
4700 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
4701 * cleared. Combination of RATE_MCS_*
4702 * @sta_id: index of destination station in FW station table
4703 * @reserved: for alignment and future use
4705 struct iwm_scan_req_tx_cmd {
4707 uint32_t rate_n_flags;
4709 uint8_t reserved[3];
4712 enum iwm_scan_channel_flags_lmac {
4713 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27),
4714 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28),
4718 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
4719 * @flags: bits 1-20: directed scan to i'th ssid
4720 * other bits &enum iwm_scan_channel_flags_lmac
4721 * @channel_number: channel number 1-13 etc
4722 * @iter_count: scan iteration on this channel
4723 * @iter_interval: interval in seconds between iterations on one channel
4725 struct iwm_scan_channel_cfg_lmac {
4727 uint16_t channel_num;
4728 uint16_t iter_count;
4729 uint32_t iter_interval;
4733 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1
4734 * @offset: offset in the data block
4735 * @len: length of the segment
4737 struct iwm_scan_probe_segment {
4742 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
4743 * @mac_header: first (and common) part of the probe
4744 * @band_data: band specific data
4745 * @common_data: last (and common) part of the probe
4746 * @buf: raw data block
4748 struct iwm_scan_probe_req {
4749 struct iwm_scan_probe_segment mac_header;
4750 struct iwm_scan_probe_segment band_data[2];
4751 struct iwm_scan_probe_segment common_data;
4752 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE];
4755 enum iwm_scan_channel_flags {
4756 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0),
4757 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1),
4758 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2),
4761 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
4762 * @flags: enum iwm_scan_channel_flags
4763 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
4765 * 1 - EBS is disabled.
4766 * 2 - every second scan will be full scan(and so on).
4768 struct iwm_scan_channel_opt {
4770 uint16_t non_ebs_ratio;
4774 * iwm_mvm_lmac_scan_flags
4775 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses
4776 * without filtering.
4777 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels
4778 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan
4779 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification
4780 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching
4781 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented
4782 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report
4783 * and DS parameter set IEs into probe requests.
4784 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels
4786 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches
4788 enum iwm_mvm_lmac_scan_flags {
4789 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0),
4790 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1),
4791 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2),
4792 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3),
4793 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4),
4794 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5),
4795 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6),
4796 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7),
4797 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9),
4800 enum iwm_scan_priority {
4801 IWM_SCAN_PRIORITY_LOW,
4802 IWM_SCAN_PRIORITY_MEDIUM,
4803 IWM_SCAN_PRIORITY_HIGH,
4807 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1
4808 * @reserved1: for alignment and future use
4809 * @channel_num: num of channels to scan
4810 * @active-dwell: dwell time for active channels
4811 * @passive-dwell: dwell time for passive channels
4812 * @fragmented-dwell: dwell time for fragmented passive scan
4813 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases)
4814 * @reserved2: for alignment and future use
4815 * @rx_chain_selct: PHY_RX_CHAIN_* flags
4816 * @scan_flags: &enum iwm_mvm_lmac_scan_flags
4817 * @max_out_time: max time (in TU) to be out of associated channel
4818 * @suspend_time: pause scan this long (TUs) when returning to service channel
4819 * @flags: RXON flags
4820 * @filter_flags: RXON filter
4821 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz
4822 * @direct_scan: list of SSIDs for directed active scan
4823 * @scan_prio: enum iwm_scan_priority
4824 * @iter_num: number of scan iterations
4825 * @delay: delay in seconds before first iteration
4826 * @schedule: two scheduling plans. The first one is finite, the second one can
4828 * @channel_opt: channel optimization options, for full and partial scan
4829 * @data: channel configuration and probe request packet.
4831 struct iwm_scan_req_lmac {
4832 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */
4835 uint8_t active_dwell;
4836 uint8_t passive_dwell;
4837 uint8_t fragmented_dwell;
4838 uint8_t extended_dwell;
4840 uint16_t rx_chain_select;
4841 uint32_t scan_flags;
4842 uint32_t max_out_time;
4843 uint32_t suspend_time;
4844 /* RX_ON_FLAGS_API_S_VER_1 */
4846 uint32_t filter_flags;
4847 struct iwm_scan_req_tx_cmd tx_cmd[2];
4848 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4850 /* SCAN_REQ_PERIODIC_PARAMS_API_S */
4853 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS];
4854 struct iwm_scan_channel_opt channel_opt[2];
4859 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2
4860 * @last_schedule_line: last schedule line executed (fast or regular)
4861 * @last_schedule_iteration: last scan iteration executed before scan abort
4862 * @status: enum iwm_scan_offload_complete_status
4863 * @ebs_status: EBS success status &enum iwm_scan_ebs_status
4864 * @time_after_last_iter; time in seconds elapsed after last iteration
4866 struct iwm_periodic_scan_complete {
4867 uint8_t last_schedule_line;
4868 uint8_t last_schedule_iteration;
4871 uint32_t time_after_last_iter;
4875 /* How many statistics are gathered for each channel */
4876 #define IWM_SCAN_RESULTS_STATISTICS 1
4879 * enum iwm_scan_complete_status - status codes for scan complete notifications
4880 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully
4881 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user
4882 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed
4883 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready
4884 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed
4885 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed
4886 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command
4887 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort
4888 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax
4889 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful
4891 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver
4893 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events
4895 enum iwm_scan_complete_status {
4896 IWM_SCAN_COMP_STATUS_OK = 0x1,
4897 IWM_SCAN_COMP_STATUS_ABORT = 0x2,
4898 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3,
4899 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4,
4900 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5,
4901 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6,
4902 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7,
4903 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8,
4904 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9,
4905 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA,
4906 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B,
4907 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C,
4911 * struct iwm_scan_results_notif - scan results for one channel
4912 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 )
4913 * @channel: which channel the results are from
4914 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4915 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request
4916 * @num_probe_not_sent: # of request that weren't sent due to not enough time
4917 * @duration: duration spent in channel, in usecs
4918 * @statistics: statistics gathered for this channel
4920 struct iwm_scan_results_notif {
4923 uint8_t probe_status;
4924 uint8_t num_probe_not_sent;
4926 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS];
4927 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */
4929 enum iwm_scan_framework_client {
4930 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0),
4931 IWM_SCAN_CLIENT_NETDETECT = (1 << 1),
4932 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2),
4936 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
4937 * @ssid: MAC address to filter out
4938 * @reported_rssi: AP rssi reported to the host
4939 * @client_bitmap: clients ignore this entry - enum scan_framework_client
4941 struct iwm_scan_offload_blacklist {
4942 uint8_t ssid[IEEE80211_ADDR_LEN];
4943 uint8_t reported_rssi;
4944 uint8_t client_bitmap;
4947 enum iwm_scan_offload_network_type {
4948 IWM_NETWORK_TYPE_BSS = 1,
4949 IWM_NETWORK_TYPE_IBSS = 2,
4950 IWM_NETWORK_TYPE_ANY = 3,
4953 enum iwm_scan_offload_band_selection {
4954 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4,
4955 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8,
4956 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc,
4960 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
4961 * @ssid_index: index to ssid list in fixed part
4962 * @unicast_cipher: encryption olgorithm to match - bitmap
4963 * @aut_alg: authentication olgorithm to match - bitmap
4964 * @network_type: enum iwm_scan_offload_network_type
4965 * @band_selection: enum iwm_scan_offload_band_selection
4966 * @client_bitmap: clients waiting for match - enum scan_framework_client
4968 struct iwm_scan_offload_profile {
4970 uint8_t unicast_cipher;
4972 uint8_t network_type;
4973 uint8_t band_selection;
4974 uint8_t client_bitmap;
4975 uint8_t reserved[2];
4979 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
4980 * @blaclist: AP list to filter off from scan results
4981 * @profiles: profiles to search for match
4982 * @blacklist_len: length of blacklist
4983 * @num_profiles: num of profiles in the list
4984 * @match_notify: clients waiting for match found notification
4985 * @pass_match: clients waiting for the results
4986 * @active_clients: active clients bitmap - enum scan_framework_client
4987 * @any_beacon_notify: clients waiting for match notification without match
4989 struct iwm_scan_offload_profile_cfg {
4990 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES];
4991 uint8_t blacklist_len;
4992 uint8_t num_profiles;
4993 uint8_t match_notify;
4995 uint8_t active_clients;
4996 uint8_t any_beacon_notify;
4997 uint8_t reserved[2];
5000 enum iwm_scan_offload_complete_status {
5001 IWM_SCAN_OFFLOAD_COMPLETED = 1,
5002 IWM_SCAN_OFFLOAD_ABORTED = 2,
5006 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels)
5007 * SCAN_COMPLETE_NTF_API_S_VER_3
5008 * @scanned_channels: number of channels scanned (and number of valid results)
5009 * @status: one of SCAN_COMP_STATUS_*
5010 * @bt_status: BT on/off status
5011 * @last_channel: last channel that was scanned
5012 * @tsf_low: TSF timer (lower half) in usecs
5013 * @tsf_high: TSF timer (higher half) in usecs
5014 * @results: an array of scan results, only "scanned_channels" of them are valid
5016 struct iwm_lmac_scan_complete_notif {
5017 uint8_t scanned_channels;
5020 uint8_t last_channel;
5023 struct iwm_scan_results_notif results[];
5029 /* The maximum of either of these cannot exceed 8, because we use an
5030 * 8-bit mask (see IWM_MVM_SCAN_MASK).
5032 #define IWM_MVM_MAX_UMAC_SCANS 8
5033 #define IWM_MVM_MAX_LMAC_SCANS 1
5035 enum iwm_scan_config_flags {
5036 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0),
5037 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1),
5038 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2),
5039 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3),
5040 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8),
5041 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9),
5042 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10),
5043 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11),
5044 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12),
5045 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13),
5046 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14),
5047 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15),
5048 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16),
5049 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17),
5050 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18),
5051 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19),
5052 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20),
5053 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21),
5055 /* Bits 26-31 are for num of channels in channel_array */
5056 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)
5059 enum iwm_scan_config_rates {
5060 /* OFDM basic rates */
5061 IWM_SCAN_CONFIG_RATE_6M = (1 << 0),
5062 IWM_SCAN_CONFIG_RATE_9M = (1 << 1),
5063 IWM_SCAN_CONFIG_RATE_12M = (1 << 2),
5064 IWM_SCAN_CONFIG_RATE_18M = (1 << 3),
5065 IWM_SCAN_CONFIG_RATE_24M = (1 << 4),
5066 IWM_SCAN_CONFIG_RATE_36M = (1 << 5),
5067 IWM_SCAN_CONFIG_RATE_48M = (1 << 6),
5068 IWM_SCAN_CONFIG_RATE_54M = (1 << 7),
5069 /* CCK basic rates */
5070 IWM_SCAN_CONFIG_RATE_1M = (1 << 8),
5071 IWM_SCAN_CONFIG_RATE_2M = (1 << 9),
5072 IWM_SCAN_CONFIG_RATE_5M = (1 << 10),
5073 IWM_SCAN_CONFIG_RATE_11M = (1 << 11),
5075 /* Bits 16-27 are for supported rates */
5076 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)
5079 enum iwm_channel_flags {
5080 IWM_CHANNEL_FLAG_EBS = (1 << 0),
5081 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1),
5082 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2),
5083 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3),
5087 * struct iwm_scan_config
5088 * @flags: enum scan_config_flags
5089 * @tx_chains: valid_tx antenna - ANT_* definitions
5090 * @rx_chains: valid_rx antenna - ANT_* definitions
5091 * @legacy_rates: default legacy rates - enum scan_config_rates
5092 * @out_of_channel_time: default max out of serving channel time
5093 * @suspend_time: default max suspend time
5094 * @dwell_active: default dwell time for active scan
5095 * @dwell_passive: default dwell time for passive scan
5096 * @dwell_fragmented: default dwell time for fragmented scan
5097 * @dwell_extended: default dwell time for channels 1, 6 and 11
5098 * @mac_addr: default mac address to be used in probes
5099 * @bcast_sta_id: the index of the station in the fw
5100 * @channel_flags: default channel flags - enum iwm_channel_flags
5101 * scan_config_channel_flag
5102 * @channel_array: default supported channels
5104 struct iwm_scan_config {
5108 uint32_t legacy_rates;
5109 uint32_t out_of_channel_time;
5110 uint32_t suspend_time;
5111 uint8_t dwell_active;
5112 uint8_t dwell_passive;
5113 uint8_t dwell_fragmented;
5114 uint8_t dwell_extended;
5115 uint8_t mac_addr[IEEE80211_ADDR_LEN];
5116 uint8_t bcast_sta_id;
5117 uint8_t channel_flags;
5118 uint8_t channel_array[];
5119 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */
5122 * iwm_umac_scan_flags
5123 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
5124 * can be preempted by other scan requests with higher priority.
5125 * The low priority scan will be resumed when the higher proirity scan is
5127 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
5130 enum iwm_umac_scan_flags {
5131 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0),
5132 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1),
5135 enum iwm_umac_scan_uid_offsets {
5136 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0,
5137 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8,
5140 enum iwm_umac_scan_general_flags {
5141 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0),
5142 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1),
5143 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2),
5144 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3),
5145 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4),
5146 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5),
5147 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6),
5148 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7),
5149 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8),
5150 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9),
5151 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10),
5155 * struct iwm_scan_channel_cfg_umac
5156 * @flags: bitmap - 0-19: directed scan to i'th ssid.
5157 * @channel_num: channel number 1-13 etc.
5158 * @iter_count: repetition count for the channel.
5159 * @iter_interval: interval between two scan iterations on one channel.
5161 struct iwm_scan_channel_cfg_umac {
5163 uint8_t channel_num;
5165 uint16_t iter_interval;
5166 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */
5169 * struct iwm_scan_umac_schedule
5170 * @interval: interval in seconds between scan iterations
5171 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
5172 * @reserved: for alignment and future use
5174 struct iwm_scan_umac_schedule {
5178 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */
5181 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5182 * parameters following channels configuration array.
5183 * @schedule: two scheduling plans.
5184 * @delay: delay in TUs before starting the first scan iteration
5185 * @reserved: for future use and alignment
5186 * @preq: probe request with IEs blocks
5187 * @direct_scan: list of SSIDs for directed active scan
5189 struct iwm_scan_req_umac_tail {
5190 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
5191 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS];
5194 /* SCAN_PROBE_PARAMS_API_S_VER_1 */
5195 struct iwm_scan_probe_req preq;
5196 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5200 * struct iwm_scan_req_umac
5201 * @flags: &enum iwm_umac_scan_flags
5202 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5203 * @ooc_priority: out of channel priority - &enum iwm_scan_priority
5204 * @general_flags: &enum iwm_umac_scan_general_flags
5205 * @extended_dwell: dwell time for channels 1, 6 and 11
5206 * @active_dwell: dwell time for active scan
5207 * @passive_dwell: dwell time for passive scan
5208 * @fragmented_dwell: dwell time for fragmented passive scan
5209 * @max_out_time: max out of serving channel time
5210 * @suspend_time: max suspend time
5211 * @scan_priority: scan internal prioritization &enum iwm_scan_priority
5212 * @channel_flags: &enum iwm_scan_channel_flags
5213 * @n_channels: num of channels in scan request
5214 * @reserved: for future use and alignment
5215 * @data: &struct iwm_scan_channel_cfg_umac and
5216 * &struct iwm_scan_req_umac_tail
5218 struct iwm_scan_req_umac {
5221 uint32_t ooc_priority;
5222 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */
5223 uint32_t general_flags;
5224 uint8_t extended_dwell;
5225 uint8_t active_dwell;
5226 uint8_t passive_dwell;
5227 uint8_t fragmented_dwell;
5228 uint32_t max_out_time;
5229 uint32_t suspend_time;
5230 uint32_t scan_priority;
5231 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */
5232 uint8_t channel_flags;
5236 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */
5239 * struct iwm_umac_scan_abort
5240 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5243 struct iwm_umac_scan_abort {
5246 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */
5249 * struct iwm_umac_scan_complete
5250 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5251 * @last_schedule: last scheduling line
5252 * @last_iter: last scan iteration number
5253 * @scan status: &enum iwm_scan_offload_complete_status
5254 * @ebs_status: &enum iwm_scan_ebs_status
5255 * @time_from_last_iter: time elapsed from last iteration
5256 * @reserved: for future use
5258 struct iwm_umac_scan_complete {
5260 uint8_t last_schedule;
5264 uint32_t time_from_last_iter;
5266 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */
5268 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5
5270 * struct iwm_scan_offload_profile_match - match information
5271 * @bssid: matched bssid
5272 * @channel: channel where the match occurred
5274 * @matching_feature:
5275 * @matching_channels: bitmap of channels that matched, referencing
5276 * the channels passed in tue scan offload request
5278 struct iwm_scan_offload_profile_match {
5279 uint8_t bssid[IEEE80211_ADDR_LEN];
5283 uint8_t matching_feature;
5284 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN];
5285 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */
5288 * struct iwm_scan_offload_profiles_query - match results query response
5289 * @matched_profiles: bitmap of matched profiles, referencing the
5290 * matches passed in the scan offload request
5291 * @last_scan_age: age of the last offloaded scan
5292 * @n_scans_done: number of offloaded scans done
5293 * @gp2_d0u: GP2 when D0U occurred
5294 * @gp2_invoked: GP2 when scan offload was invoked
5295 * @resume_while_scanning: not used
5296 * @self_recovery: obsolete
5297 * @reserved: reserved
5298 * @matches: array of match information, one for each match
5300 struct iwm_scan_offload_profiles_query {
5301 uint32_t matched_profiles;
5302 uint32_t last_scan_age;
5303 uint32_t n_scans_done;
5305 uint32_t gp2_invoked;
5306 uint8_t resume_while_scanning;
5307 uint8_t self_recovery;
5309 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES];
5310 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */
5313 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration
5314 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5315 * @scanned_channels: number of channels scanned and number of valid elements in
5317 * @status: one of SCAN_COMP_STATUS_*
5318 * @bt_status: BT on/off status
5319 * @last_channel: last channel that was scanned
5320 * @tsf_low: TSF timer (lower half) in usecs
5321 * @tsf_high: TSF timer (higher half) in usecs
5322 * @results: array of scan results, only "scanned_channels" of them are valid
5324 struct iwm_umac_scan_iter_complete_notif {
5326 uint8_t scanned_channels;
5329 uint8_t last_channel;
5332 struct iwm_scan_results_notif results[];
5333 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */
5335 /* Please keep this enum *SORTED* by hex value.
5336 * Needed for binary search, otherwise a warning will be triggered.
5338 enum iwm_scan_subcmd_ids {
5339 IWM_GSCAN_START_CMD = 0x0,
5340 IWM_GSCAN_STOP_CMD = 0x1,
5341 IWM_GSCAN_SET_HOTLIST_CMD = 0x2,
5342 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3,
5343 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4,
5344 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5,
5345 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD,
5346 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE,
5347 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF,
5353 * enum iwm_sta_flags - flags for the ADD_STA host command
5354 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
5355 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
5356 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled
5357 * @IWM_STA_FLG_PS: set if STA is in Power Save
5358 * @IWM_STA_FLG_INVALID: set if STA is invalid
5359 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
5360 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
5361 * @IWM_STA_FLG_DRAIN_FLOW: drain flow
5362 * @IWM_STA_FLG_PAN: STA is for PAN interface
5363 * @IWM_STA_FLG_CLASS_AUTH:
5364 * @IWM_STA_FLG_CLASS_ASSOC:
5365 * @IWM_STA_FLG_CLASS_MIMO_PROT:
5366 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
5367 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
5368 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
5369 * initialised by driver and can be updated by fw upon reception of
5370 * action frames that can change the channel width. When cleared the fw
5371 * will send all the frames in 20MHz even when FAT channel is requested.
5372 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
5373 * driver and can be updated by fw upon reception of action frames.
5374 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
5376 enum iwm_sta_flags {
5377 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3),
5378 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6),
5380 IWM_STA_FLG_DISABLE_TX = (1 << 4),
5382 IWM_STA_FLG_PS = (1 << 8),
5383 IWM_STA_FLG_DRAIN_FLOW = (1 << 12),
5384 IWM_STA_FLG_PAN = (1 << 13),
5385 IWM_STA_FLG_CLASS_AUTH = (1 << 14),
5386 IWM_STA_FLG_CLASS_ASSOC = (1 << 15),
5387 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17),
5389 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19,
5390 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5391 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5392 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5393 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5394 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5395 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5396 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5397 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5398 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5400 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23,
5401 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5402 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5403 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5404 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5405 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5407 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26),
5408 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26),
5409 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26),
5410 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26),
5411 IWM_STA_FLG_FAT_EN_MSK = (3 << 26),
5413 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28),
5414 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28),
5415 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28),
5416 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28),
5420 * enum iwm_sta_key_flag - key flags for the ADD_STA host command
5421 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
5422 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
5423 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
5424 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
5425 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
5426 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
5427 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
5428 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
5429 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
5430 * station info array (1 - n 1X mode)
5431 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
5432 * @IWM_STA_KEY_NOT_VALID: key is invalid
5433 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
5434 * @IWM_STA_KEY_MULTICAST: set for multical key
5435 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
5437 enum iwm_sta_key_flag {
5438 IWM_STA_KEY_FLG_NO_ENC = (0 << 0),
5439 IWM_STA_KEY_FLG_WEP = (1 << 0),
5440 IWM_STA_KEY_FLG_CCM = (2 << 0),
5441 IWM_STA_KEY_FLG_TKIP = (3 << 0),
5442 IWM_STA_KEY_FLG_EXT = (4 << 0),
5443 IWM_STA_KEY_FLG_CMAC = (6 << 0),
5444 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0),
5445 IWM_STA_KEY_FLG_EN_MSK = (7 << 0),
5447 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3),
5448 IWM_STA_KEY_FLG_KEYID_POS = 8,
5449 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS),
5450 IWM_STA_KEY_NOT_VALID = (1 << 11),
5451 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12),
5452 IWM_STA_KEY_MULTICAST = (1 << 14),
5453 IWM_STA_KEY_MFP = (1 << 15),
5457 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed
5458 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue
5459 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
5460 * @IWM_STA_MODIFY_TX_RATE: unused
5461 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
5462 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
5463 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
5464 * @IWM_STA_MODIFY_PROT_TH:
5465 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
5467 enum iwm_sta_modify_flag {
5468 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0),
5469 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1),
5470 IWM_STA_MODIFY_TX_RATE = (1 << 2),
5471 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3),
5472 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4),
5473 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5),
5474 IWM_STA_MODIFY_PROT_TH = (1 << 6),
5475 IWM_STA_MODIFY_QUEUES = (1 << 7),
5478 #define IWM_STA_MODE_MODIFY 1
5481 * enum iwm_sta_sleep_flag - type of sleep of the station
5482 * @IWM_STA_SLEEP_STATE_AWAKE:
5483 * @IWM_STA_SLEEP_STATE_PS_POLL:
5484 * @IWM_STA_SLEEP_STATE_UAPSD:
5485 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on
5486 * (last) released frame
5488 enum iwm_sta_sleep_flag {
5489 IWM_STA_SLEEP_STATE_AWAKE = 0,
5490 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0),
5491 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1),
5492 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2),
5495 /* STA ID and color bits definitions */
5496 #define IWM_STA_ID_SEED (0x0f)
5497 #define IWM_STA_ID_POS (0)
5498 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
5500 #define IWM_STA_COLOR_SEED (0x7)
5501 #define IWM_STA_COLOR_POS (4)
5502 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)
5504 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
5505 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)
5506 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \
5507 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)
5509 #define IWM_STA_KEY_MAX_NUM (16)
5510 #define IWM_STA_KEY_IDX_INVALID (0xff)
5511 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)
5512 #define IWM_MAX_GLOBAL_KEYS (4)
5513 #define IWM_STA_KEY_LEN_WEP40 (5)
5514 #define IWM_STA_KEY_LEN_WEP104 (13)
5517 * struct iwm_mvm_keyinfo - key information
5518 * @key_flags: type %iwm_sta_key_flag
5519 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5520 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5521 * @key_offset: key offset in the fw's key table
5522 * @key: 16-byte unicast decryption key
5523 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
5524 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
5525 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
5527 struct iwm_mvm_keyinfo {
5529 uint8_t tkip_rx_tsc_byte2;
5531 uint16_t tkip_rx_ttak[5];
5535 uint64_t tx_secur_seq_cnt;
5536 uint64_t hw_tkip_mic_rx_key;
5537 uint64_t hw_tkip_mic_tx_key;
5540 #define IWM_ADD_STA_STATUS_MASK 0xFF
5541 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000
5542 #define IWM_ADD_STA_BAID_MASK 0x7F00
5543 #define IWM_ADD_STA_BAID_SHIFT 8
5546 * struct iwm_mvm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table.
5547 * ( REPLY_ADD_STA = 0x18 )
5548 * @add_modify: 1: modify existing, 0: add new station
5550 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5551 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field.
5552 * @mac_id_n_color: the Mac context this station belongs to
5553 * @addr[IEEE80211_ADDR_LEN]: station's MAC address
5554 * @sta_id: index of station in uCode's station table
5555 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave
5556 * alone. 1 - modify, 0 - don't change.
5557 * @station_flags: look at %iwm_sta_flags
5558 * @station_flags_msk: what of %station_flags have changed
5559 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5560 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set
5561 * add_immediate_ba_ssn.
5562 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5563 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field
5564 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5565 * add_immediate_ba_tid.
5566 * @sleep_tx_count: number of packets to transmit to station even though it is
5567 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5568 * keeps track of STA sleep state.
5569 * @sleep_state_flags: Look at %iwm_sta_sleep_flag.
5570 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5572 * @beamform_flags: beam forming controls
5573 * @tfd_queue_msk: tfd queues used by this station
5575 * The device contains an internal table of per-station information, with info
5576 * on security keys, aggregation parameters, and Tx rates for initial Tx
5577 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD).
5579 * ADD_STA sets up the table entry for one station, either creating a new
5580 * entry, or modifying a pre-existing one.
5582 struct iwm_mvm_add_sta_cmd_v7 {
5585 uint16_t tid_disable_tx;
5586 uint32_t mac_id_n_color;
5587 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5590 uint8_t modify_mask;
5592 uint32_t station_flags;
5593 uint32_t station_flags_msk;
5594 uint8_t add_immediate_ba_tid;
5595 uint8_t remove_immediate_ba_tid;
5596 uint16_t add_immediate_ba_ssn;
5597 uint16_t sleep_tx_count;
5598 uint16_t sleep_state_flags;
5600 uint16_t beamform_flags;
5601 uint32_t tfd_queue_msk;
5602 } __packed; /* ADD_STA_CMD_API_S_VER_7 */
5605 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key
5606 * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
5607 * @sta_id: index of station in uCode's station table
5608 * @key_offset: key offset in key storage
5609 * @key_flags: type %iwm_sta_key_flag
5610 * @key: key material data
5611 * @key2: key material data
5612 * @rx_secur_seq_cnt: RX security sequence counter for the key
5613 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5614 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5616 struct iwm_mvm_add_sta_key_cmd {
5622 uint8_t rx_secur_seq_cnt[16];
5623 uint8_t tkip_rx_tsc_byte2;
5625 uint16_t tkip_rx_ttak[5];
5626 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
5629 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command
5630 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
5631 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
5632 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
5633 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
5634 * that doesn't exist.
5636 enum iwm_mvm_add_sta_rsp_status {
5637 IWM_ADD_STA_SUCCESS = 0x1,
5638 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2,
5639 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4,
5640 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8,
5644 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table
5645 * ( IWM_REMOVE_STA = 0x19 )
5646 * @sta_id: the station id of the station to be removed
5648 struct iwm_mvm_rm_sta_cmd {
5650 uint8_t reserved[3];
5651 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */
5654 * struct iwm_mvm_mgmt_mcast_key_cmd
5655 * ( IWM_MGMT_MCAST_KEY = 0x1f )
5656 * @ctrl_flags: %iwm_sta_key_flag
5658 * @K1: IGTK master key
5660 * @sta_id: station ID that support IGTK
5662 * @receive_seq_cnt: initial RSC/PN needed for replay check
5664 struct iwm_mvm_mgmt_mcast_key_cmd {
5665 uint32_t ctrl_flags;
5671 uint64_t receive_seq_cnt;
5672 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
5674 struct iwm_mvm_wep_key {
5679 uint8_t reserved2[3];
5683 struct iwm_mvm_wep_key_cmd {
5684 uint32_t mac_id_n_color;
5686 uint8_t decryption_type;
5689 struct iwm_mvm_wep_key wep_key[0];
5690 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
5696 enum iwm_bt_coex_mode {
5697 IWM_BT_COEX_DISABLE = 0x0,
5698 IWM_BT_COEX_NW = 0x1,
5699 IWM_BT_COEX_BT = 0x2,
5700 IWM_BT_COEX_WIFI = 0x3,
5701 }; /* BT_COEX_MODES_E */
5703 enum iwm_bt_coex_enabled_modules {
5704 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0),
5705 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1),
5706 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2),
5707 IWM_BT_COEX_CORUN_ENABLED = (1 << 3),
5708 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4),
5709 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */
5712 * struct iwm_bt_coex_cmd - bt coex configuration command
5713 * @mode: enum %iwm_bt_coex_mode
5714 * @enabled_modules: enum %iwm_bt_coex_enabled_modules
5716 * The structure is used for the BT_COEX command.
5718 struct iwm_bt_coex_cmd {
5720 uint32_t enabled_modules;
5721 } __packed; /* BT_COEX_CMD_API_S_VER_6 */
5725 * Location Aware Regulatory (LAR) API - MCC updates
5729 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic
5730 * regulatory profile according to the given MCC (Mobile Country Code).
5731 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5732 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5733 * MCC in the cmd response will be the relevant MCC in the NVM.
5734 * @mcc: given mobile country code
5735 * @source_id: the source from where we got the MCC, see iwm_mcc_source
5736 * @reserved: reserved for alignment
5738 struct iwm_mcc_update_cmd_v1 {
5742 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */
5745 * struct iwm_mcc_update_cmd - Request the device to update geographic
5746 * regulatory profile according to the given MCC (Mobile Country Code).
5747 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5748 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5749 * MCC in the cmd response will be the relevant MCC in the NVM.
5750 * @mcc: given mobile country code
5751 * @source_id: the source from where we got the MCC, see iwm_mcc_source
5752 * @reserved: reserved for alignment
5753 * @key: integrity key for MCC API OEM testing
5754 * @reserved2: reserved
5756 struct iwm_mcc_update_cmd {
5761 uint32_t reserved2[5];
5762 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */
5765 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD.
5766 * Contains the new channel control profile map, if changed, and the new MCC
5767 * (mobile country code).
5768 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5769 * @status: see &enum iwm_mcc_update_status
5770 * @mcc: the new applied MCC
5771 * @cap: capabilities for all channels which matches the MCC
5772 * @source_id: the MCC source, see iwm_mcc_source
5773 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5774 * channels, depending on platform)
5775 * @channels: channel control data map, DWORD for each channel. Only the first
5778 struct iwm_mcc_update_resp_v1 {
5783 uint32_t n_channels;
5784 uint32_t channels[0];
5785 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */
5788 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD.
5789 * Contains the new channel control profile map, if changed, and the new MCC
5790 * (mobile country code).
5791 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5792 * @status: see &enum iwm_mcc_update_status
5793 * @mcc: the new applied MCC
5794 * @cap: capabilities for all channels which matches the MCC
5795 * @source_id: the MCC source, see iwm_mcc_source
5796 * @time: time elapsed from the MCC test start (in 30 seconds TU)
5797 * @reserved: reserved.
5798 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5799 * channels, depending on platform)
5800 * @channels: channel control data map, DWORD for each channel. Only the first
5803 struct iwm_mcc_update_resp {
5810 uint32_t n_channels;
5811 uint32_t channels[0];
5812 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */
5815 * struct iwm_mcc_chub_notif - chub notifies of mcc change
5816 * (MCC_CHUB_UPDATE_CMD = 0xc9)
5817 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
5818 * the cellular and connectivity cores that gets updates of the mcc, and
5819 * notifies the ucode directly of any mcc change.
5820 * The ucode requests the driver to request the device to update geographic
5821 * regulatory profile according to the given MCC (Mobile Country Code).
5822 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5823 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5824 * MCC in the cmd response will be the relevant MCC in the NVM.
5825 * @mcc: given mobile country code
5826 * @source_id: identity of the change originator, see iwm_mcc_source
5827 * @reserved1: reserved for alignment
5829 struct iwm_mcc_chub_notif {
5833 } __packed; /* LAR_MCC_NOTIFY_S */
5835 enum iwm_mcc_update_status {
5836 IWM_MCC_RESP_NEW_CHAN_PROFILE,
5837 IWM_MCC_RESP_SAME_CHAN_PROFILE,
5838 IWM_MCC_RESP_INVALID,
5839 IWM_MCC_RESP_NVM_DISABLED,
5840 IWM_MCC_RESP_ILLEGAL,
5841 IWM_MCC_RESP_LOW_PRIORITY,
5842 IWM_MCC_RESP_TEST_MODE_ACTIVE,
5843 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE,
5844 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE,
5847 enum iwm_mcc_source {
5848 IWM_MCC_SOURCE_OLD_FW = 0,
5849 IWM_MCC_SOURCE_ME = 1,
5850 IWM_MCC_SOURCE_BIOS = 2,
5851 IWM_MCC_SOURCE_3G_LTE_HOST = 3,
5852 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4,
5853 IWM_MCC_SOURCE_WIFI = 5,
5854 IWM_MCC_SOURCE_RESERVED = 6,
5855 IWM_MCC_SOURCE_DEFAULT = 7,
5856 IWM_MCC_SOURCE_UNINITIALIZED = 8,
5857 IWM_MCC_SOURCE_MCC_API = 9,
5858 IWM_MCC_SOURCE_GET_CURRENT = 0x10,
5859 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11,
5863 * Some cherry-picked definitions
5866 #define IWM_FRAME_LIMIT 64
5869 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811:
5870 * As the firmware is slowly running out of command IDs and grouping of
5871 * commands is desirable anyway, the firmware is extending the command
5872 * header from 4 bytes to 8 bytes to introduce a group (in place of the
5873 * former flags field, since that's always 0 on commands and thus can
5874 * be easily used to distinguish between the two).
5876 * These functions retrieve specific information from the id field in
5877 * the iwm_host_cmd struct which contains the command id, the group id,
5878 * and the version of the command.
5880 static inline uint8_t
5881 iwm_cmd_opcode(uint32_t cmdid)
5883 return cmdid & 0xff;
5886 static inline uint8_t
5887 iwm_cmd_groupid(uint32_t cmdid)
5889 return ((cmdid & 0Xff00) >> 8);
5892 static inline uint8_t
5893 iwm_cmd_version(uint32_t cmdid)
5895 return ((cmdid & 0xff0000) >> 16);
5898 static inline uint32_t
5899 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version)
5901 return opcode + (groupid << 8) + (version << 16);
5904 /* make uint16_t wide id out of uint8_t group and opcode */
5905 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode)
5907 /* due to the conversion, this group is special */
5908 #define IWM_ALWAYS_LONG_GROUP 1
5910 struct iwm_cmd_header {
5917 struct iwm_cmd_header_wide {
5927 enum iwm_power_scheme {
5928 IWM_POWER_SCHEME_CAM = 1,
5929 IWM_POWER_SCHEME_BPS,
5933 #define IWM_DEF_CMD_PAYLOAD_SIZE 320
5934 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
5935 #define IWM_CMD_FAILED_MSK 0x40
5938 * struct iwm_device_cmd
5940 * For allocation of the command and tx queues, this establishes the overall
5941 * size of the largest command we send to uCode, except for commands that
5942 * aren't fully copied and use other TFD space.
5944 struct iwm_device_cmd {
5947 struct iwm_cmd_header hdr;
5948 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE];
5951 struct iwm_cmd_header_wide hdr_wide;
5952 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE -
5953 sizeof(struct iwm_cmd_header_wide) +
5954 sizeof(struct iwm_cmd_header)];
5959 struct iwm_rx_packet {
5961 * The first 4 bytes of the RX frame header contain both the RX frame
5962 * size and some flags.
5964 * 31: flag flush RB request
5965 * 30: flag ignore TC (terminal counter) request
5966 * 29: flag fast IRQ request
5968 * 13-00: RX frame size
5970 uint32_t len_n_flags;
5971 struct iwm_cmd_header hdr;
5975 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
5977 static inline uint32_t
5978 iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
5981 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
5984 static inline uint32_t
5985 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
5988 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
5992 #define IWM_MIN_DBM -100
5993 #define IWM_MAX_DBM -33 /* realistic guess */
5995 #define IWM_READ(sc, reg) \
5996 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
5998 #define IWM_WRITE(sc, reg, val) \
5999 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6001 #define IWM_WRITE_1(sc, reg, val) \
6002 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6004 #define IWM_SETBITS(sc, reg, mask) \
6005 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
6007 #define IWM_CLRBITS(sc, reg, mask) \
6008 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
6010 #define IWM_BARRIER_WRITE(sc) \
6011 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6012 BUS_SPACE_BARRIER_WRITE)
6014 #define IWM_BARRIER_READ_WRITE(sc) \
6015 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6016 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
6018 #endif /* __IF_IWM_REG_H__ */