sys/dev/netif/bwi/bwiphy.c

   1 /*
   2  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
   3  *
   4  * This code is derived from software contributed to The DragonFly Project
   5  * by Sepherosa Ziehau <sepherosa@gmail.com>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in
  15  *    the documentation and/or other materials provided with the
  16  *    distribution.
  17  * 3. Neither the name of The DragonFly Project nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific, prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  */
  34
  35 #include <sys/param.h>
  36 #include <sys/bitops.h>
  37 #include <sys/endian.h>
  38 #include <sys/kernel.h>
  39 #include <sys/bus.h>
  40 #include <sys/malloc.h>
  41 #include <sys/proc.h>
  42 #include <sys/rman.h>
  43 #include <sys/serialize.h>
  44 #include <sys/socket.h>
  45 #include <sys/sockio.h>
  46 #include <sys/sysctl.h>
  47
  48 #include <net/ethernet.h>
  49 #include <net/if.h>
  50 #include <net/bpf.h>
  51 #include <net/if_arp.h>
  52 #include <net/if_dl.h>
  53 #include <net/if_media.h>
  54 #include <net/ifq_var.h>
  55
  56 #include <netproto/802_11/ieee80211_radiotap.h>
  57 #include <netproto/802_11/ieee80211_var.h>
  58 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
  59
  60 #include <bus/pci/pcireg.h>
  61 #include <bus/pci/pcivar.h>
  62 #include <bus/pci/pcidevs.h>
  63
  64 #include <dev/netif/bwi/if_bwireg.h>
  65 #include <dev/netif/bwi/if_bwivar.h>
  66 #include <dev/netif/bwi/bwirf.h>
  67 #include <dev/netif/bwi/bwiphy.h>
  68 #include <dev/netif/bwi/bwimac.h>
  69
  70 static void     bwi_phy_init_11a(struct bwi_mac *);
  71 static void     bwi_phy_init_11g(struct bwi_mac *);
  72 static void     bwi_phy_init_11b_rev2(struct bwi_mac *);
  73 static void     bwi_phy_init_11b_rev4(struct bwi_mac *);
  74 static void     bwi_phy_init_11b_rev5(struct bwi_mac *);
  75 static void     bwi_phy_init_11b_rev6(struct bwi_mac *);
  76
  77 static void     bwi_phy_config_11g(struct bwi_mac *);
  78 static void     bwi_phy_config_agc(struct bwi_mac *);
  79
  80 static void     bwi_tbl_write_2(struct bwi_mac *mac, uint16_t, uint16_t);
  81 static void     bwi_tbl_write_4(struct bwi_mac *mac, uint16_t, uint32_t);
  82
  83 #define SUP_BPHY(num)   { .rev = num, .init = bwi_phy_init_11b_rev##num }
  84
  85 static const struct {
  86         uint8_t rev;
  87         void    (*init)(struct bwi_mac *);
  88 } bwi_sup_bphy[] = {
  89         SUP_BPHY(2),
  90         SUP_BPHY(4),
  91         SUP_BPHY(5),
  92         SUP_BPHY(6)
  93 };
  94
  95 #undef SUP_BPHY
  96
  97 #define BWI_PHYTBL_WRSSI        0x1000
  98 #define BWI_PHYTBL_NOISE_SCALE  0x1400
  99 #define BWI_PHYTBL_NOISE        0x1800
 100 #define BWI_PHYTBL_ROTOR        0x2000
 101 #define BWI_PHYTBL_DELAY        0x2400
 102 #define BWI_PHYTBL_RSSI         0x4000
 103 #define BWI_PHYTBL_SIGMA_SQ     0x5000
 104 #define BWI_PHYTBL_WRSSI_REV1   0x5400
 105 #define BWI_PHYTBL_FREQ         0x5800
 106
 107 static const uint16_t   bwi_phy_freq_11g_rev1[] =
 108         { BWI_PHY_FREQ_11G_REV1 };
 109 static const uint16_t   bwi_phy_noise_11g_rev1[] =
 110         { BWI_PHY_NOISE_11G_REV1 };
 111 static const uint16_t   bwi_phy_noise_11g[] =
 112         { BWI_PHY_NOISE_11G };
 113 static const uint32_t   bwi_phy_rotor_11g_rev1[] =
 114         { BWI_PHY_ROTOR_11G_REV1 };
 115 static const uint16_t   bwi_phy_noise_scale_11g_rev2[] =
 116         { BWI_PHY_NOISE_SCALE_11G_REV2 };
 117 static const uint16_t   bwi_phy_noise_scale_11g_rev7[] =
 118         { BWI_PHY_NOISE_SCALE_11G_REV7 };
 119 static const uint16_t   bwi_phy_noise_scale_11g[] =
 120         { BWI_PHY_NOISE_SCALE_11G };
 121 static const uint16_t   bwi_phy_sigma_sq_11g_rev2[] =
 122         { BWI_PHY_SIGMA_SQ_11G_REV2 };
 123 static const uint16_t   bwi_phy_sigma_sq_11g_rev7[] =
 124         { BWI_PHY_SIGMA_SQ_11G_REV7 };
 125 static const uint32_t   bwi_phy_delay_11g_rev1[] =
 126         { BWI_PHY_DELAY_11G_REV1 };
 127
 128 void
 129 bwi_phy_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)
 130 {
 131         struct bwi_softc *sc = mac->mac_sc;
 132
 133         /* TODO: 11A */
 134         CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
 135         CSR_WRITE_2(sc, BWI_PHY_DATA, data);
 136 }
 137
 138 uint16_t
 139 bwi_phy_read(struct bwi_mac *mac, uint16_t ctrl)
 140 {
 141         struct bwi_softc *sc = mac->mac_sc;
 142
 143         /* TODO: 11A */
 144         CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
 145         return CSR_READ_2(sc, BWI_PHY_DATA);
 146 }
 147
 148 int
 149 bwi_phy_attach(struct bwi_mac *mac)
 150 {
 151         struct bwi_softc *sc = mac->mac_sc;
 152         struct bwi_phy *phy = &mac->mac_phy;
 153         uint8_t phyrev, phytype, phyver;
 154         uint16_t val;
 155         int i;
 156
 157         /* Get PHY type/revision/version */
 158         val = CSR_READ_2(sc, BWI_PHYINFO);
 159         phyrev = __SHIFTOUT(val, BWI_PHYINFO_REV_MASK);
 160         phytype = __SHIFTOUT(val, BWI_PHYINFO_TYPE_MASK);
 161         phyver = __SHIFTOUT(val, BWI_PHYINFO_VER_MASK);
 162         device_printf(sc->sc_dev, "PHY: type %d, rev %d, ver %d\n",
 163                       phytype, phyrev, phyver);
 164
 165         /*
 166          * Verify whether the revision of the PHY type is supported
 167          * Convert PHY type to ieee80211_phymode
 168          */
 169         switch (phytype) {
 170         case BWI_PHYINFO_TYPE_11A:
 171                 if (phyrev >= 4) {
 172                         device_printf(sc->sc_dev, "unsupported 11A PHY, "
 173                                       "rev %u\n", phyrev);
 174                         return ENXIO;
 175                 }
 176                 phy->phy_init = bwi_phy_init_11a;
 177                 phy->phy_mode = IEEE80211_MODE_11A;
 178                 phy->phy_tbl_ctrl = BWI_PHYR_TBL_CTRL_11A;
 179                 phy->phy_tbl_data_lo = BWI_PHYR_TBL_DATA_LO_11A;
 180                 phy->phy_tbl_data_hi = BWI_PHYR_TBL_DATA_HI_11A;
 181                 break;
 182         case BWI_PHYINFO_TYPE_11B:
 183                 for (i = 0; i < NELEM(bwi_sup_bphy); ++i) {
 184                         if (phyrev == bwi_sup_bphy[i].rev) {
 185                                 phy->phy_init = bwi_sup_bphy[i].init;
 186                                 break;
 187                         }
 188                 }
 189                 if (i == NELEM(bwi_sup_bphy)) {
 190                         device_printf(sc->sc_dev, "unsupported 11B PHY, "
 191                                       "rev %u\n", phyrev);
 192                         return ENXIO;
 193                 }
 194                 phy->phy_mode = IEEE80211_MODE_11B;
 195                 break;
 196         case BWI_PHYINFO_TYPE_11G:
 197                 if (phyrev > 8) {
 198                         device_printf(sc->sc_dev, "unsupported 11G PHY, "
 199                                       "rev %u\n", phyrev);
 200                         return ENXIO;
 201                 }
 202                 phy->phy_init = bwi_phy_init_11g;
 203                 phy->phy_mode = IEEE80211_MODE_11G;
 204                 phy->phy_tbl_ctrl = BWI_PHYR_TBL_CTRL_11G;
 205                 phy->phy_tbl_data_lo = BWI_PHYR_TBL_DATA_LO_11G;
 206                 phy->phy_tbl_data_hi = BWI_PHYR_TBL_DATA_HI_11G;
 207                 break;
 208         default:
 209                 device_printf(sc->sc_dev, "unsupported PHY type %d\n",
 210                               phytype);
 211                 return ENXIO;
 212         }
 213         phy->phy_rev = phyrev;
 214         phy->phy_version = phyver;
 215         return 0;
 216 }
 217
 218 void
 219 bwi_phy_set_bbp_atten(struct bwi_mac *mac, uint16_t bbp_atten)
 220 {
 221         struct bwi_phy *phy = &mac->mac_phy;
 222         uint16_t mask = __BITS(3, 0);
 223
 224         if (phy->phy_version == 0) {
 225                 CSR_FILT_SETBITS_2(mac->mac_sc, BWI_BBP_ATTEN, ~mask,
 226                                    __SHIFTIN(bbp_atten, mask));
 227         } else {
 228                 if (phy->phy_version > 1)
 229                         mask <<= 2;
 230                 else
 231                         mask <<= 3;
 232                 PHY_FILT_SETBITS(mac, BWI_PHYR_BBP_ATTEN, ~mask,
 233                                  __SHIFTIN(bbp_atten, mask));
 234         }
 235 }
 236
 237 int
 238 bwi_phy_calibrate(struct bwi_mac *mac)
 239 {
 240         struct bwi_phy *phy = &mac->mac_phy;
 241
 242         /* Dummy read */
 243         CSR_READ_4(mac->mac_sc, BWI_MAC_STATUS);
 244
 245         /* Don't re-init */
 246         if (phy->phy_flags & BWI_PHY_F_CALIBRATED)
 247                 return 0;
 248
 249         if (phy->phy_mode == IEEE80211_MODE_11G && phy->phy_rev == 1) {
 250                 bwi_mac_reset(mac, 0);
 251                 bwi_phy_init_11g(mac);
 252                 bwi_mac_reset(mac, 1);
 253         }
 254
 255         phy->phy_flags |= BWI_PHY_F_CALIBRATED;
 256         return 0;
 257 }
 258
 259 static void
 260 bwi_tbl_write_2(struct bwi_mac *mac, uint16_t ofs, uint16_t data)
 261 {
 262         struct bwi_phy *phy = &mac->mac_phy;
 263
 264         KKASSERT(phy->phy_tbl_ctrl != 0 && phy->phy_tbl_data_lo != 0);
 265         PHY_WRITE(mac, phy->phy_tbl_ctrl, ofs);
 266         PHY_WRITE(mac, phy->phy_tbl_data_lo, data);
 267 }
 268
 269 static void
 270 bwi_tbl_write_4(struct bwi_mac *mac, uint16_t ofs, uint32_t data)
 271 {
 272         struct bwi_phy *phy = &mac->mac_phy;
 273
 274         KKASSERT(phy->phy_tbl_data_lo != 0 && phy->phy_tbl_data_hi != 0 &&
 275                  phy->phy_tbl_ctrl != 0);
 276
 277         PHY_WRITE(mac, phy->phy_tbl_ctrl, ofs);
 278         PHY_WRITE(mac, phy->phy_tbl_data_hi, data >> 16);
 279         PHY_WRITE(mac, phy->phy_tbl_data_lo, data & 0xffff);
 280 }
 281
 282 void
 283 bwi_nrssi_write(struct bwi_mac *mac, uint16_t ofs, int16_t data)
 284 {
 285         PHY_WRITE(mac, BWI_PHYR_NRSSI_CTRL, ofs);
 286         PHY_WRITE(mac, BWI_PHYR_NRSSI_DATA, (uint16_t)data);
 287 }
 288
 289 int16_t
 290 bwi_nrssi_read(struct bwi_mac *mac, uint16_t ofs)
 291 {
 292         PHY_WRITE(mac, BWI_PHYR_NRSSI_CTRL, ofs);
 293         return (int16_t)PHY_READ(mac, BWI_PHYR_NRSSI_DATA);
 294 }
 295
 296 static void
 297 bwi_phy_init_11a(struct bwi_mac *mac)
 298 {
 299         /* TODO:11A */
 300 }
 301
 302 static void
 303 bwi_phy_init_11g(struct bwi_mac *mac)
 304 {
 305         struct bwi_softc *sc = mac->mac_sc;
 306         struct bwi_phy *phy = &mac->mac_phy;
 307         struct bwi_rf *rf = &mac->mac_rf;
 308         const struct bwi_tpctl *tpctl = &mac->mac_tpctl;
 309
 310         if (phy->phy_rev == 1)
 311                 bwi_phy_init_11b_rev5(mac);
 312         else
 313                 bwi_phy_init_11b_rev6(mac);
 314
 315         if (phy->phy_rev >= 2 || (phy->phy_flags & BWI_PHY_F_LINKED))
 316                 bwi_phy_config_11g(mac);
 317
 318         if (phy->phy_rev >= 2) {
 319                 PHY_WRITE(mac, 0x814, 0);
 320                 PHY_WRITE(mac, 0x815, 0);
 321
 322                 if (phy->phy_rev == 2) {
 323                         PHY_WRITE(mac, 0x811, 0);
 324                         PHY_WRITE(mac, 0x15, 0xc0);
 325                 } else if (phy->phy_rev > 5) {
 326                         PHY_WRITE(mac, 0x811, 0x400);
 327                         PHY_WRITE(mac, 0x15, 0xc0);
 328                 }
 329         }
 330
 331         if (phy->phy_rev >= 2 || (phy->phy_flags & BWI_PHY_F_LINKED)) {
 332                 uint16_t val;
 333
 334                 val = PHY_READ(mac, 0x400) & 0xff;
 335                 if (val == 3 || val == 5) {
 336                         PHY_WRITE(mac, 0x4c2, 0x1816);
 337                         PHY_WRITE(mac, 0x4c3, 0x8006);
 338                         if (val == 5) {
 339                                 PHY_FILT_SETBITS(mac, 0x4cc,
 340                                                  0xff, 0x1f00);
 341                         }
 342                 }
 343         }
 344
 345         if ((phy->phy_rev <= 2 && (phy->phy_flags & BWI_PHY_F_LINKED)) ||
 346             phy->phy_rev >= 2)
 347                 PHY_WRITE(mac, 0x47e, 0x78);
 348
 349         if (rf->rf_rev == 8) {
 350                 PHY_SETBITS(mac, 0x801, 0x80);
 351                 PHY_SETBITS(mac, 0x43e, 0x4);
 352         }
 353
 354         if (phy->phy_rev >= 2 && (phy->phy_flags & BWI_PHY_F_LINKED))
 355                 bwi_rf_get_gains(mac);
 356
 357         if (rf->rf_rev != 8)
 358                 bwi_rf_init(mac);
 359
 360         if (tpctl->tp_ctrl2 == 0xffff) {
 361                 bwi_rf_lo_update(mac);
 362         } else {
 363                 if (rf->rf_type == BWI_RF_T_BCM2050 && rf->rf_rev == 8) {
 364                         RF_WRITE(mac, 0x52,
 365                                  (tpctl->tp_ctrl1 << 4) | tpctl->tp_ctrl2);
 366                 } else {
 367                         RF_FILT_SETBITS(mac, 0x52, 0xfff0, tpctl->tp_ctrl1);
 368                 }
 369
 370                 if (phy->phy_rev >= 6) {
 371                         PHY_FILT_SETBITS(mac, 0x36, 0xfff,
 372                                          tpctl->tp_ctrl2 << 12);
 373                 }
 374
 375                 if (sc->sc_card_flags & BWI_CARD_F_PA_GPIO9)
 376                         PHY_WRITE(mac, 0x2e, 0x8075);
 377                 else
 378                         PHY_WRITE(mac, 0x2e, 0x807f);
 379
 380                 if (phy->phy_rev < 2)
 381                         PHY_WRITE(mac, 0x2f, 0x101);
 382                 else
 383                         PHY_WRITE(mac, 0x2f, 0x202);
 384         }
 385
 386         if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 387                 bwi_rf_lo_adjust(mac, tpctl);
 388                 PHY_WRITE(mac, 0x80f, 0x8078);
 389         }
 390
 391         if ((sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0) {
 392                 bwi_rf_init_hw_nrssi_table(mac, 0xffff /* XXX */);
 393                 bwi_rf_set_nrssi_thr(mac);
 394         } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 395                 if (rf->rf_nrssi[0] == BWI_INVALID_NRSSI) {
 396                         KKASSERT(rf->rf_nrssi[1] == BWI_INVALID_NRSSI);
 397                         bwi_rf_calc_nrssi_slope(mac);
 398                 } else {
 399                         KKASSERT(rf->rf_nrssi[1] != BWI_INVALID_NRSSI);
 400                         bwi_rf_set_nrssi_thr(mac);
 401                 }
 402         }
 403
 404         if (rf->rf_rev == 8)
 405                 PHY_WRITE(mac, 0x805, 0x3230);
 406
 407         bwi_mac_init_tpctl_11bg(mac);
 408
 409         if (sc->sc_bbp_id == BWI_BBPID_BCM4306 && sc->sc_bbp_pkg == 2) {
 410                 PHY_CLRBITS(mac, 0x429, 0x4000);
 411                 PHY_CLRBITS(mac, 0x4c3, 0x8000);
 412         }
 413 }
 414
 415 static void
 416 bwi_phy_init_11b_rev2(struct bwi_mac *mac)
 417 {
 418         /* TODO:11B */
 419         if_printf(&mac->mac_sc->sc_ic.ic_if,
 420                   "%s is not implemented yet\n", __func__);
 421 }
 422
 423 static void
 424 bwi_phy_init_11b_rev4(struct bwi_mac *mac)
 425 {
 426         struct bwi_softc *sc = mac->mac_sc;
 427         struct bwi_rf *rf = &mac->mac_rf;
 428         uint16_t val, ofs;
 429         u_int chan;
 430
 431         CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
 432
 433         PHY_WRITE(mac, 0x20, 0x301c);
 434         PHY_WRITE(mac, 0x26, 0);
 435         PHY_WRITE(mac, 0x30, 0xc6);
 436         PHY_WRITE(mac, 0x88, 0x3e00);
 437
 438         for (ofs = 0, val = 0x3c3d; ofs < 30; ++ofs, val -= 0x202)
 439                 PHY_WRITE(mac, 0x89 + ofs, val);
 440
 441         CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
 442
 443         chan = rf->rf_curchan;
 444         if (chan == IEEE80211_CHAN_ANY)
 445                 chan = 6;       /* Force to channel 6 */
 446         bwi_rf_set_chan(mac, chan, 0);
 447
 448         if (rf->rf_type != BWI_RF_T_BCM2050) {
 449                 RF_WRITE(mac, 0x75, 0x80);
 450                 RF_WRITE(mac, 0x79, 0x81);
 451         }
 452
 453         RF_WRITE(mac, 0x50, 0x20);
 454         RF_WRITE(mac, 0x50, 0x23);
 455
 456         if (rf->rf_type == BWI_RF_T_BCM2050) {
 457                 RF_WRITE(mac, 0x50, 0x20);
 458                 RF_WRITE(mac, 0x5a, 0x70);
 459                 RF_WRITE(mac, 0x5b, 0x7b);
 460                 RF_WRITE(mac, 0x5c, 0xb0);
 461                 RF_WRITE(mac, 0x7a, 0xf);
 462                 PHY_WRITE(mac, 0x38, 0x677);
 463                 bwi_rf_init_bcm2050(mac);
 464         }
 465
 466         PHY_WRITE(mac, 0x14, 0x80);
 467         PHY_WRITE(mac, 0x32, 0xca);
 468         if (rf->rf_type == BWI_RF_T_BCM2050)
 469                 PHY_WRITE(mac, 0x32, 0xe0);
 470         PHY_WRITE(mac, 0x35, 0x7c2);
 471
 472         bwi_rf_lo_update(mac);
 473
 474         PHY_WRITE(mac, 0x26, 0xcc00);
 475         if (rf->rf_type == BWI_RF_T_BCM2050)
 476                 PHY_WRITE(mac, 0x26, 0xce00);
 477
 478         CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100);
 479
 480         PHY_WRITE(mac, 0x2a, 0x88a3);
 481         if (rf->rf_type == BWI_RF_T_BCM2050)
 482                 PHY_WRITE(mac, 0x2a, 0x88c2);
 483
 484         bwi_mac_set_tpctl_11bg(mac, NULL);
 485         if (sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
 486                 bwi_rf_calc_nrssi_slope(mac);
 487                 bwi_rf_set_nrssi_thr(mac);
 488         }
 489         bwi_mac_init_tpctl_11bg(mac);
 490 }
 491
 492 static void
 493 bwi_phy_init_11b_rev5(struct bwi_mac *mac)
 494 {
 495         struct bwi_softc *sc = mac->mac_sc;
 496         struct bwi_rf *rf = &mac->mac_rf;
 497         struct bwi_phy *phy = &mac->mac_phy;
 498         u_int orig_chan;
 499
 500         if (phy->phy_version == 1)
 501                 RF_SETBITS(mac, 0x7a, 0x50);
 502
 503         if (sc->sc_pci_subvid != PCI_VENDOR_BROADCOM &&
 504             sc->sc_pci_subdid != BWI_PCI_SUBDEVICE_BU4306) {
 505                 uint16_t ofs, val;
 506
 507                 val = 0x2120;
 508                 for (ofs = 0xa8; ofs < 0xc7; ++ofs) {
 509                         PHY_WRITE(mac, ofs, val);
 510                         val += 0x202;
 511                 }
 512         }
 513
 514         PHY_FILT_SETBITS(mac, 0x35, 0xf0ff, 0x700);
 515
 516         if (rf->rf_type == BWI_RF_T_BCM2050)
 517                 PHY_WRITE(mac, 0x38, 0x667);
 518
 519         if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 520                 if (rf->rf_type == BWI_RF_T_BCM2050) {
 521                         RF_SETBITS(mac, 0x7a, 0x20);
 522                         RF_SETBITS(mac, 0x51, 0x4);
 523                 }
 524
 525                 CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0);
 526
 527                 PHY_SETBITS(mac, 0x802, 0x100);
 528                 PHY_SETBITS(mac, 0x42b, 0x2000);
 529                 PHY_WRITE(mac, 0x1c, 0x186a);
 530
 531                 PHY_FILT_SETBITS(mac, 0x13, 0xff, 0x1900);
 532                 PHY_FILT_SETBITS(mac, 0x35, 0xffc0, 0x64);
 533                 PHY_FILT_SETBITS(mac, 0x5d, 0xff80, 0xa);
 534         }
 535
 536         /* TODO: bad_frame_preempt? */
 537
 538         if (phy->phy_version == 1) {
 539                 PHY_WRITE(mac, 0x26, 0xce00);
 540                 PHY_WRITE(mac, 0x21, 0x3763);
 541                 PHY_WRITE(mac, 0x22, 0x1bc3);
 542                 PHY_WRITE(mac, 0x23, 0x6f9);
 543                 PHY_WRITE(mac, 0x24, 0x37e);
 544         } else {
 545                 PHY_WRITE(mac, 0x26, 0xcc00);
 546         }
 547         PHY_WRITE(mac, 0x30, 0xc6);
 548
 549         CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
 550
 551         if (phy->phy_version == 1)
 552                 PHY_WRITE(mac, 0x20, 0x3e1c);
 553         else
 554                 PHY_WRITE(mac, 0x20, 0x301c);
 555
 556         if (phy->phy_version == 0)
 557                 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
 558
 559         /* Force to channel 7 */
 560         orig_chan = rf->rf_curchan;
 561         bwi_rf_set_chan(mac, 7, 0);
 562
 563         if (rf->rf_type != BWI_RF_T_BCM2050) {
 564                 RF_WRITE(mac, 0x75, 0x80);
 565                 RF_WRITE(mac, 0x79, 0x81);
 566         }
 567
 568         RF_WRITE(mac, 0x50, 0x20);
 569         RF_WRITE(mac, 0x50, 0x23);
 570
 571         if (rf->rf_type == BWI_RF_T_BCM2050) {
 572                 RF_WRITE(mac, 0x50, 0x20);
 573                 RF_WRITE(mac, 0x5a, 0x70);
 574         }
 575
 576         RF_WRITE(mac, 0x5b, 0x7b);
 577         RF_WRITE(mac, 0x5c, 0xb0);
 578         RF_SETBITS(mac, 0x7a, 0x7);
 579
 580         bwi_rf_set_chan(mac, orig_chan, 0);
 581
 582         PHY_WRITE(mac, 0x14, 0x80);
 583         PHY_WRITE(mac, 0x32, 0xca);
 584         PHY_WRITE(mac, 0x2a, 0x88a3);
 585
 586         bwi_mac_set_tpctl_11bg(mac, NULL);
 587
 588         if (rf->rf_type == BWI_RF_T_BCM2050)
 589                 RF_WRITE(mac, 0x5d, 0xd);
 590
 591         CSR_FILT_SETBITS_2(sc, BWI_PHY_MAGIC_REG1, 0xffc0, 0x4);
 592 }
 593
 594 static void
 595 bwi_phy_init_11b_rev6(struct bwi_mac *mac)
 596 {
 597         struct bwi_softc *sc = mac->mac_sc;
 598         struct bwi_rf *rf = &mac->mac_rf;
 599         struct bwi_phy *phy = &mac->mac_phy;
 600         uint16_t val, ofs;
 601         u_int orig_chan;
 602
 603         PHY_WRITE(mac, 0x3e, 0x817a);
 604         RF_SETBITS(mac, 0x7a, 0x58);
 605
 606         if (rf->rf_rev == 4 || rf->rf_rev == 5) {
 607                 RF_WRITE(mac, 0x51, 0x37);
 608                 RF_WRITE(mac, 0x52, 0x70);
 609                 RF_WRITE(mac, 0x53, 0xb3);
 610                 RF_WRITE(mac, 0x54, 0x9b);
 611                 RF_WRITE(mac, 0x5a, 0x88);
 612                 RF_WRITE(mac, 0x5b, 0x88);
 613                 RF_WRITE(mac, 0x5d, 0x88);
 614                 RF_WRITE(mac, 0x5e, 0x88);
 615                 RF_WRITE(mac, 0x7d, 0x88);
 616                 HFLAGS_SETBITS(mac, BWI_HFLAG_MAGIC1);
 617         } else if (rf->rf_rev == 8) {
 618                 RF_WRITE(mac, 0x51, 0);
 619                 RF_WRITE(mac, 0x52, 0x40);
 620                 RF_WRITE(mac, 0x53, 0xb7);
 621                 RF_WRITE(mac, 0x54, 0x98);
 622                 RF_WRITE(mac, 0x5a, 0x88);
 623                 RF_WRITE(mac, 0x5b, 0x6b);
 624                 RF_WRITE(mac, 0x5c, 0xf);
 625                 if (sc->sc_card_flags & BWI_CARD_F_ALT_IQ) {
 626                         RF_WRITE(mac, 0x5d, 0xfa);
 627                         RF_WRITE(mac, 0x5e, 0xd8);
 628                 } else {
 629                         RF_WRITE(mac, 0x5d, 0xf5);
 630                         RF_WRITE(mac, 0x5e, 0xb8);
 631                 }
 632                 RF_WRITE(mac, 0x73, 0x3);
 633                 RF_WRITE(mac, 0x7d, 0xa8);
 634                 RF_WRITE(mac, 0x7c, 0x1);
 635                 RF_WRITE(mac, 0x7e, 0x8);
 636         }
 637
 638         val = 0x1e1f;
 639         for (ofs = 0x88; ofs < 0x98; ++ofs) {
 640                 PHY_WRITE(mac, ofs, val);
 641                 val -= 0x202;
 642         }
 643
 644         val = 0x3e3f;
 645         for (ofs = 0x98; ofs < 0xa8; ++ofs) {
 646                 PHY_WRITE(mac, ofs, val);
 647                 val -= 0x202;
 648         }
 649
 650         val = 0x2120;
 651         for (ofs = 0xa8; ofs < 0xc8; ++ofs) {
 652                 PHY_WRITE(mac, ofs, (val & 0x3f3f));
 653                 val += 0x202;
 654         }
 655
 656         if (phy->phy_mode == IEEE80211_MODE_11G) {
 657                 RF_SETBITS(mac, 0x7a, 0x20);
 658                 RF_SETBITS(mac, 0x51, 0x4);
 659                 PHY_SETBITS(mac, 0x802, 0x100);
 660                 PHY_SETBITS(mac, 0x42b, 0x2000);
 661                 PHY_WRITE(mac, 0x5b, 0);
 662                 PHY_WRITE(mac, 0x5c, 0);
 663         }
 664
 665         /* Force to channel 7 */
 666         orig_chan = rf->rf_curchan;
 667         if (orig_chan >= 8)
 668                 bwi_rf_set_chan(mac, 1, 0);
 669         else
 670                 bwi_rf_set_chan(mac, 13, 0);
 671
 672         RF_WRITE(mac, 0x50, 0x20);
 673         RF_WRITE(mac, 0x50, 0x23);
 674
 675         DELAY(40);
 676
 677         if (rf->rf_rev < 6 || rf->rf_rev == 8) {
 678                 RF_SETBITS(mac, 0x7c, 0x2);
 679                 RF_WRITE(mac, 0x50, 0x20);
 680         }
 681         if (rf->rf_rev <= 2) {
 682                 RF_WRITE(mac, 0x7c, 0x20);
 683                 RF_WRITE(mac, 0x5a, 0x70);
 684                 RF_WRITE(mac, 0x5b, 0x7b);
 685                 RF_WRITE(mac, 0x5c, 0xb0);
 686         }
 687
 688         RF_FILT_SETBITS(mac, 0x7a, 0xf8, 0x7);
 689
 690         bwi_rf_set_chan(mac, orig_chan, 0);
 691
 692         PHY_WRITE(mac, 0x14, 0x200);
 693         if (rf->rf_rev >= 6)
 694                 PHY_WRITE(mac, 0x2a, 0x88c2);
 695         else
 696                 PHY_WRITE(mac, 0x2a, 0x8ac0);
 697         PHY_WRITE(mac, 0x38, 0x668);
 698
 699         bwi_mac_set_tpctl_11bg(mac, NULL);
 700
 701         if (rf->rf_rev <= 5) {
 702                 PHY_FILT_SETBITS(mac, 0x5d, 0xff80, 0x3);
 703                 if (rf->rf_rev <= 2)
 704                         RF_WRITE(mac, 0x5d, 0xd);
 705         }
 706
 707         if (phy->phy_version == 4) {
 708                 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL2);
 709                 PHY_CLRBITS(mac, 0x61, 0xf000);
 710         } else {
 711                 PHY_FILT_SETBITS(mac, 0x2, 0xffc0, 0x4);
 712         }
 713
 714         if (phy->phy_mode == IEEE80211_MODE_11B) {
 715                 CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC2);
 716                 PHY_WRITE(mac, 0x16, 0x410);
 717                 PHY_WRITE(mac, 0x17, 0x820);
 718                 PHY_WRITE(mac, 0x62, 0x7);
 719
 720                 bwi_rf_init_bcm2050(mac);
 721                 bwi_rf_lo_update(mac);
 722                 if (sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
 723                         bwi_rf_calc_nrssi_slope(mac);
 724                         bwi_rf_set_nrssi_thr(mac);
 725                 }
 726                 bwi_mac_init_tpctl_11bg(mac);
 727         } else {
 728                 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
 729         }
 730 }
 731
 732 static void
 733 bwi_phy_config_11g(struct bwi_mac *mac)
 734 {
 735         struct bwi_softc *sc = mac->mac_sc;
 736         struct bwi_phy *phy = &mac->mac_phy;
 737         const uint16_t *tbl;
 738         uint16_t wrd_ofs1, wrd_ofs2;
 739         int i, n;
 740
 741         if (phy->phy_rev == 1) {
 742                 PHY_WRITE(mac, 0x406, 0x4f19);
 743                 PHY_FILT_SETBITS(mac, 0x429, 0xfc3f, 0x340);
 744                 PHY_WRITE(mac, 0x42c, 0x5a);
 745                 PHY_WRITE(mac, 0x427, 0x1a);
 746
 747                 /* Fill frequency table */
 748                 for (i = 0; i < NELEM(bwi_phy_freq_11g_rev1); ++i) {
 749                         bwi_tbl_write_2(mac, BWI_PHYTBL_FREQ + i,
 750                                         bwi_phy_freq_11g_rev1[i]);
 751                 }
 752
 753                 /* Fill noise table */
 754                 for (i = 0; i < NELEM(bwi_phy_noise_11g_rev1); ++i) {
 755                         bwi_tbl_write_2(mac, BWI_PHYTBL_NOISE + i,
 756                                         bwi_phy_noise_11g_rev1[i]);
 757                 }
 758
 759                 /* Fill rotor table */
 760                 for (i = 0; i < NELEM(bwi_phy_rotor_11g_rev1); ++i) {
 761                         /* NB: data length is 4 bytes */
 762                         bwi_tbl_write_4(mac, BWI_PHYTBL_ROTOR + i,
 763                                         bwi_phy_rotor_11g_rev1[i]);
 764                 }
 765         } else {
 766                 bwi_nrssi_write(mac, 0xba98, (int16_t)0x7654); /* XXX */
 767
 768                 if (phy->phy_rev == 2) {
 769                         PHY_WRITE(mac, 0x4c0, 0x1861);
 770                         PHY_WRITE(mac, 0x4c1, 0x271);
 771                 } else if (phy->phy_rev > 2) {
 772                         PHY_WRITE(mac, 0x4c0, 0x98);
 773                         PHY_WRITE(mac, 0x4c1, 0x70);
 774                         PHY_WRITE(mac, 0x4c9, 0x80);
 775                 }
 776                 PHY_SETBITS(mac, 0x42b, 0x800);
 777
 778                 /* Fill RSSI table */
 779                 for (i = 0; i < 64; ++i)
 780                         bwi_tbl_write_2(mac, BWI_PHYTBL_RSSI + i, i);
 781
 782                 /* Fill noise table */
 783                 for (i = 0; i < sizeof(bwi_phy_noise_11g); ++i) {
 784                         bwi_tbl_write_2(mac, BWI_PHYTBL_NOISE + i,
 785                                         bwi_phy_noise_11g[i]);
 786                 }
 787         }
 788
 789         /*
 790          * Fill noise scale table
 791          */
 792         if (phy->phy_rev <= 2) {
 793                 tbl = bwi_phy_noise_scale_11g_rev2;
 794                 n = NELEM(bwi_phy_noise_scale_11g_rev2);
 795         } else if (phy->phy_rev >= 7 && (PHY_READ(mac, 0x449) & 0x200)) {
 796                 tbl = bwi_phy_noise_scale_11g_rev7;
 797                 n = NELEM(bwi_phy_noise_scale_11g_rev7);
 798         } else {
 799                 tbl = bwi_phy_noise_scale_11g;
 800                 n = NELEM(bwi_phy_noise_scale_11g);
 801         }
 802         for (i = 0; i < n; ++i)
 803                 bwi_tbl_write_2(mac, BWI_PHYTBL_NOISE_SCALE + i, tbl[i]);
 804
 805         /*
 806          * Fill sigma square table
 807          */
 808         if (phy->phy_rev == 2) {
 809                 tbl = bwi_phy_sigma_sq_11g_rev2;
 810                 n = NELEM(bwi_phy_sigma_sq_11g_rev2);
 811         } else if (phy->phy_rev > 2 && phy->phy_rev <= 8) {
 812                 tbl = bwi_phy_sigma_sq_11g_rev7;
 813                 n = NELEM(bwi_phy_sigma_sq_11g_rev7);
 814         } else {
 815                 tbl = NULL;
 816                 n = 0;
 817         }
 818         for (i = 0; i < n; ++i)
 819                 bwi_tbl_write_2(mac, BWI_PHYTBL_SIGMA_SQ + i, tbl[i]);
 820
 821         if (phy->phy_rev == 1) {
 822                 /* Fill delay table */
 823                 for (i = 0; i < NELEM(bwi_phy_delay_11g_rev1); ++i) {
 824                         bwi_tbl_write_4(mac, BWI_PHYTBL_DELAY + i,
 825                                         bwi_phy_delay_11g_rev1[i]);
 826                 }
 827
 828                 /* Fill WRSSI (Wide-Band RSSI) table */
 829                 for (i = 4; i < 20; ++i)
 830                         bwi_tbl_write_2(mac, BWI_PHYTBL_WRSSI_REV1 + i, 0x20);
 831
 832                 bwi_phy_config_agc(mac);
 833
 834                 wrd_ofs1 = 0x5001;
 835                 wrd_ofs2 = 0x5002;
 836         } else {
 837                 /* Fill WRSSI (Wide-Band RSSI) table */
 838                 for (i = 0; i < 0x20; ++i)
 839                         bwi_tbl_write_2(mac, BWI_PHYTBL_WRSSI + i, 0x820);
 840
 841                 bwi_phy_config_agc(mac);
 842
 843                 PHY_READ(mac, 0x400);   /* Dummy read */
 844                 PHY_WRITE(mac, 0x403, 0x1000);
 845                 bwi_tbl_write_2(mac, 0x3c02, 0xf);
 846                 bwi_tbl_write_2(mac, 0x3c03, 0x14);
 847
 848                 wrd_ofs1 = 0x401;
 849                 wrd_ofs2 = 0x402;
 850         }
 851
 852         if (!(BWI_IS_BRCM_BU4306(sc) && sc->sc_pci_revid == 0x17)) {
 853                 bwi_tbl_write_2(mac, wrd_ofs1, 0x2);
 854                 bwi_tbl_write_2(mac, wrd_ofs2, 0x1);
 855         }
 856
 857         /* phy->phy_flags & BWI_PHY_F_LINKED ? */
 858         if (sc->sc_card_flags & BWI_CARD_F_PA_GPIO9)
 859                 PHY_WRITE(mac, 0x46e, 0x3cf);
 860 }
 861
 862 /*
 863  * Configure Automatic Gain Controller
 864  */
 865 static void
 866 bwi_phy_config_agc(struct bwi_mac *mac)
 867 {
 868         struct bwi_phy *phy = &mac->mac_phy;
 869         uint16_t ofs;
 870
 871         ofs = phy->phy_rev == 1 ? 0x4c00 : 0;
 872
 873         bwi_tbl_write_2(mac, ofs, 0xfe);
 874         bwi_tbl_write_2(mac, ofs + 1, 0xd);
 875         bwi_tbl_write_2(mac, ofs + 2, 0x13);
 876         bwi_tbl_write_2(mac, ofs + 3, 0x19);
 877
 878         if (phy->phy_rev == 1) {
 879                 bwi_tbl_write_2(mac, 0x1800, 0x2710);
 880                 bwi_tbl_write_2(mac, 0x1801, 0x9b83);
 881                 bwi_tbl_write_2(mac, 0x1802, 0x9b83);
 882                 bwi_tbl_write_2(mac, 0x1803, 0xf8d);
 883                 PHY_WRITE(mac, 0x455, 0x4);
 884         }
 885
 886         PHY_FILT_SETBITS(mac, 0x4a5, 0xff, 0x5700);
 887         PHY_FILT_SETBITS(mac, 0x41a, 0xff80, 0xf);
 888         PHY_FILT_SETBITS(mac, 0x41a, 0xc07f, 0x2b80);
 889         PHY_FILT_SETBITS(mac, 0x48c, 0xf0ff, 0x300);
 890
 891         RF_SETBITS(mac, 0x7a, 0x8);
 892
 893         PHY_FILT_SETBITS(mac, 0x4a0, 0xfff0, 0x8);
 894         PHY_FILT_SETBITS(mac, 0x4a1, 0xf0ff, 0x600);
 895         PHY_FILT_SETBITS(mac, 0x4a2, 0xf0ff, 0x700);
 896         PHY_FILT_SETBITS(mac, 0x4a0, 0xf0ff, 0x100);
 897
 898         if (phy->phy_rev == 1)
 899                 PHY_FILT_SETBITS(mac, 0x4a2, 0xfff0, 0x7);
 900
 901         PHY_FILT_SETBITS(mac, 0x488, 0xff00, 0x1c);
 902         PHY_FILT_SETBITS(mac, 0x488, 0xc0ff, 0x200);
 903         PHY_FILT_SETBITS(mac, 0x496, 0xff00, 0x1c);
 904         PHY_FILT_SETBITS(mac, 0x489, 0xff00, 0x20);
 905         PHY_FILT_SETBITS(mac, 0x489, 0xc0ff, 0x200);
 906         PHY_FILT_SETBITS(mac, 0x482, 0xff00, 0x2e);
 907         PHY_FILT_SETBITS(mac, 0x496, 0xff, 0x1a00);
 908         PHY_FILT_SETBITS(mac, 0x481, 0xff00, 0x28);
 909         PHY_FILT_SETBITS(mac, 0x481, 0xff, 0x2c00);
 910
 911         if (phy->phy_rev == 1) {
 912                 PHY_WRITE(mac, 0x430, 0x92b);
 913                 PHY_FILT_SETBITS(mac, 0x41b, 0xffe1, 0x2);
 914         } else {
 915                 PHY_CLRBITS(mac, 0x41b, 0x1e);
 916                 PHY_WRITE(mac, 0x41f, 0x287a);
 917                 PHY_FILT_SETBITS(mac, 0x420, 0xfff0, 0x4);
 918
 919                 if (phy->phy_rev >= 6) {
 920                         PHY_WRITE(mac, 0x422, 0x287a);
 921                         PHY_FILT_SETBITS(mac, 0x420, 0xfff, 0x3000);
 922                 }
 923         }
 924
 925         PHY_FILT_SETBITS(mac, 0x4a8, 0x8080, 0x7874);
 926         PHY_WRITE(mac, 0x48e, 0x1c00);
 927
 928         if (phy->phy_rev == 1) {
 929                 PHY_FILT_SETBITS(mac, 0x4ab, 0xf0ff, 0x600);
 930                 PHY_WRITE(mac, 0x48b, 0x5e);
 931                 PHY_FILT_SETBITS(mac, 0x48c, 0xff00, 0x1e);
 932                 PHY_WRITE(mac, 0x48d, 0x2);
 933         }
 934
 935         bwi_tbl_write_2(mac, ofs + 0x800, 0);
 936         bwi_tbl_write_2(mac, ofs + 0x801, 7);
 937         bwi_tbl_write_2(mac, ofs + 0x802, 16);
 938         bwi_tbl_write_2(mac, ofs + 0x803, 28);
 939
 940         if (phy->phy_rev >= 6) {
 941                 PHY_CLRBITS(mac, 0x426, 0x3);
 942                 PHY_CLRBITS(mac, 0x426, 0x1000);
 943         }
 944 }
 945
 946 void
 947 bwi_set_gains(struct bwi_mac *mac, const struct bwi_gains *gains)
 948 {
 949         struct bwi_phy *phy = &mac->mac_phy;
 950         uint16_t tbl_gain_ofs1, tbl_gain_ofs2, tbl_gain;
 951         int i;
 952
 953         if (phy->phy_rev <= 1) {
 954                 tbl_gain_ofs1 = 0x5000;
 955                 tbl_gain_ofs2 = tbl_gain_ofs1 + 16;
 956         } else {
 957                 tbl_gain_ofs1 = 0x400;
 958                 tbl_gain_ofs2 = tbl_gain_ofs1 + 8;
 959         }
 960
 961         for (i = 0; i < 4; ++i) {
 962                 if (gains != NULL) {
 963                         tbl_gain = gains->tbl_gain1;
 964                 } else {
 965                         /* Bit swap */
 966                         tbl_gain = (i & 0x1) << 1;
 967                         tbl_gain |= (i & 0x2) >> 1;
 968                 }
 969                 bwi_tbl_write_2(mac, tbl_gain_ofs1 + i, tbl_gain);
 970         }
 971
 972         for (i = 0; i < 16; ++i) {
 973                 if (gains != NULL)
 974                         tbl_gain = gains->tbl_gain2;
 975                 else
 976                         tbl_gain = i;
 977                 bwi_tbl_write_2(mac, tbl_gain_ofs2 + i, tbl_gain);
 978         }
 979
 980         if (gains == NULL || (gains != NULL && gains->phy_gain != -1)) {
 981                 uint16_t phy_gain1, phy_gain2;
 982
 983                 if (gains != NULL) {
 984                         phy_gain1 =
 985                         ((uint16_t)gains->phy_gain << 14) |
 986                         ((uint16_t)gains->phy_gain << 6);
 987                         phy_gain2 = phy_gain1;
 988                 } else {
 989                         phy_gain1 = 0x4040;
 990                         phy_gain2 = 0x4000;
 991                 }
 992                 PHY_FILT_SETBITS(mac, 0x4a0, 0xbfbf, phy_gain1);
 993                 PHY_FILT_SETBITS(mac, 0x4a1, 0xbfbf, phy_gain1);
 994                 PHY_FILT_SETBITS(mac, 0x4a2, 0xbfbf, phy_gain2);
 995         }
 996         bwi_mac_dummy_xmit(mac);
 997 }
 998
 999 void
1000 bwi_phy_clear_state(struct bwi_phy *phy)
1001 {
1002         phy->phy_flags &= ~BWI_CLEAR_PHY_FLAGS;
1003 }