1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
30 * $DragonFly: src/sys/dev/drm/radeon_cp.c,v 1.1 2008/04/05 18:12:29 hasso Exp $
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
39 #define RADEON_FIFO_DEBUG 0
41 static int radeon_do_cleanup_cp(struct drm_device * dev);
43 /* CP microcode (from ATI) */
44 static const u32 R200_cp_microcode[][2] = {
45 {0x21007000, 0000000000},
46 {0x20007000, 0000000000},
47 {0x000000ab, 0x00000004},
48 {0x000000af, 0x00000004},
49 {0x66544a49, 0000000000},
50 {0x49494174, 0000000000},
51 {0x54517d83, 0000000000},
52 {0x498d8b64, 0000000000},
53 {0x49494949, 0000000000},
54 {0x49da493c, 0000000000},
55 {0x49989898, 0000000000},
56 {0xd34949d5, 0000000000},
57 {0x9dc90e11, 0000000000},
58 {0xce9b9b9b, 0000000000},
59 {0x000f0000, 0x00000016},
60 {0x352e232c, 0000000000},
61 {0x00000013, 0x00000004},
62 {0x000f0000, 0x00000016},
63 {0x352e272c, 0000000000},
64 {0x000f0001, 0x00000016},
65 {0x3239362f, 0000000000},
66 {0x000077ef, 0x00000002},
67 {0x00061000, 0x00000002},
68 {0x00000020, 0x0000001a},
69 {0x00004000, 0x0000001e},
70 {0x00061000, 0x00000002},
71 {0x00000020, 0x0000001a},
72 {0x00004000, 0x0000001e},
73 {0x00061000, 0x00000002},
74 {0x00000020, 0x0000001a},
75 {0x00004000, 0x0000001e},
76 {0x00000016, 0x00000004},
77 {0x0003802a, 0x00000002},
78 {0x040067e0, 0x00000002},
79 {0x00000016, 0x00000004},
80 {0x000077e0, 0x00000002},
81 {0x00065000, 0x00000002},
82 {0x000037e1, 0x00000002},
83 {0x040067e1, 0x00000006},
84 {0x000077e0, 0x00000002},
85 {0x000077e1, 0x00000002},
86 {0x000077e1, 0x00000006},
87 {0xffffffff, 0000000000},
88 {0x10000000, 0000000000},
89 {0x0003802a, 0x00000002},
90 {0x040067e0, 0x00000006},
91 {0x00007675, 0x00000002},
92 {0x00007676, 0x00000002},
93 {0x00007677, 0x00000002},
94 {0x00007678, 0x00000006},
95 {0x0003802b, 0x00000002},
96 {0x04002676, 0x00000002},
97 {0x00007677, 0x00000002},
98 {0x00007678, 0x00000006},
99 {0x0000002e, 0x00000018},
100 {0x0000002e, 0x00000018},
101 {0000000000, 0x00000006},
102 {0x0000002f, 0x00000018},
103 {0x0000002f, 0x00000018},
104 {0000000000, 0x00000006},
105 {0x01605000, 0x00000002},
106 {0x00065000, 0x00000002},
107 {0x00098000, 0x00000002},
108 {0x00061000, 0x00000002},
109 {0x64c0603d, 0x00000004},
110 {0x00080000, 0x00000016},
111 {0000000000, 0000000000},
112 {0x0400251d, 0x00000002},
113 {0x00007580, 0x00000002},
114 {0x00067581, 0x00000002},
115 {0x04002580, 0x00000002},
116 {0x00067581, 0x00000002},
117 {0x00000046, 0x00000004},
118 {0x00005000, 0000000000},
119 {0x00061000, 0x00000002},
120 {0x0000750e, 0x00000002},
121 {0x00019000, 0x00000002},
122 {0x00011055, 0x00000014},
123 {0x00000055, 0x00000012},
124 {0x0400250f, 0x00000002},
125 {0x0000504a, 0x00000004},
126 {0x00007565, 0x00000002},
127 {0x00007566, 0x00000002},
128 {0x00000051, 0x00000004},
129 {0x01e655b4, 0x00000002},
130 {0x4401b0dc, 0x00000002},
131 {0x01c110dc, 0x00000002},
132 {0x2666705d, 0x00000018},
133 {0x040c2565, 0x00000002},
134 {0x0000005d, 0x00000018},
135 {0x04002564, 0x00000002},
136 {0x00007566, 0x00000002},
137 {0x00000054, 0x00000004},
138 {0x00401060, 0x00000008},
139 {0x00101000, 0x00000002},
140 {0x000d80ff, 0x00000002},
141 {0x00800063, 0x00000008},
142 {0x000f9000, 0x00000002},
143 {0x000e00ff, 0x00000002},
144 {0000000000, 0x00000006},
145 {0x00000080, 0x00000018},
146 {0x00000054, 0x00000004},
147 {0x00007576, 0x00000002},
148 {0x00065000, 0x00000002},
149 {0x00009000, 0x00000002},
150 {0x00041000, 0x00000002},
151 {0x0c00350e, 0x00000002},
152 {0x00049000, 0x00000002},
153 {0x00051000, 0x00000002},
154 {0x01e785f8, 0x00000002},
155 {0x00200000, 0x00000002},
156 {0x00600073, 0x0000000c},
157 {0x00007563, 0x00000002},
158 {0x006075f0, 0x00000021},
159 {0x20007068, 0x00000004},
160 {0x00005068, 0x00000004},
161 {0x00007576, 0x00000002},
162 {0x00007577, 0x00000002},
163 {0x0000750e, 0x00000002},
164 {0x0000750f, 0x00000002},
165 {0x00a05000, 0x00000002},
166 {0x00600076, 0x0000000c},
167 {0x006075f0, 0x00000021},
168 {0x000075f8, 0x00000002},
169 {0x00000076, 0x00000004},
170 {0x000a750e, 0x00000002},
171 {0x0020750f, 0x00000002},
172 {0x00600079, 0x00000004},
173 {0x00007570, 0x00000002},
174 {0x00007571, 0x00000002},
175 {0x00007572, 0x00000006},
176 {0x00005000, 0x00000002},
177 {0x00a05000, 0x00000002},
178 {0x00007568, 0x00000002},
179 {0x00061000, 0x00000002},
180 {0x00000084, 0x0000000c},
181 {0x00058000, 0x00000002},
182 {0x0c607562, 0x00000002},
183 {0x00000086, 0x00000004},
184 {0x00600085, 0x00000004},
185 {0x400070dd, 0000000000},
186 {0x000380dd, 0x00000002},
187 {0x00000093, 0x0000001c},
188 {0x00065095, 0x00000018},
189 {0x040025bb, 0x00000002},
190 {0x00061096, 0x00000018},
191 {0x040075bc, 0000000000},
192 {0x000075bb, 0x00000002},
193 {0x000075bc, 0000000000},
194 {0x00090000, 0x00000006},
195 {0x00090000, 0x00000002},
196 {0x000d8002, 0x00000006},
197 {0x00005000, 0x00000002},
198 {0x00007821, 0x00000002},
199 {0x00007800, 0000000000},
200 {0x00007821, 0x00000002},
201 {0x00007800, 0000000000},
202 {0x01665000, 0x00000002},
203 {0x000a0000, 0x00000002},
204 {0x000671cc, 0x00000002},
205 {0x0286f1cd, 0x00000002},
206 {0x000000a3, 0x00000010},
207 {0x21007000, 0000000000},
208 {0x000000aa, 0x0000001c},
209 {0x00065000, 0x00000002},
210 {0x000a0000, 0x00000002},
211 {0x00061000, 0x00000002},
212 {0x000b0000, 0x00000002},
213 {0x38067000, 0x00000002},
214 {0x000a00a6, 0x00000004},
215 {0x20007000, 0000000000},
216 {0x01200000, 0x00000002},
217 {0x20077000, 0x00000002},
218 {0x01200000, 0x00000002},
219 {0x20007000, 0000000000},
220 {0x00061000, 0x00000002},
221 {0x0120751b, 0x00000002},
222 {0x8040750a, 0x00000002},
223 {0x8040750b, 0x00000002},
224 {0x00110000, 0x00000002},
225 {0x000380dd, 0x00000002},
226 {0x000000bd, 0x0000001c},
227 {0x00061096, 0x00000018},
228 {0x844075bd, 0x00000002},
229 {0x00061095, 0x00000018},
230 {0x840075bb, 0x00000002},
231 {0x00061096, 0x00000018},
232 {0x844075bc, 0x00000002},
233 {0x000000c0, 0x00000004},
234 {0x804075bd, 0x00000002},
235 {0x800075bb, 0x00000002},
236 {0x804075bc, 0x00000002},
237 {0x00108000, 0x00000002},
238 {0x01400000, 0x00000002},
239 {0x006000c4, 0x0000000c},
240 {0x20c07000, 0x00000020},
241 {0x000000c6, 0x00000012},
242 {0x00800000, 0x00000006},
243 {0x0080751d, 0x00000006},
244 {0x000025bb, 0x00000002},
245 {0x000040c0, 0x00000004},
246 {0x0000775c, 0x00000002},
247 {0x00a05000, 0x00000002},
248 {0x00661000, 0x00000002},
249 {0x0460275d, 0x00000020},
250 {0x00004000, 0000000000},
251 {0x00007999, 0x00000002},
252 {0x00a05000, 0x00000002},
253 {0x00661000, 0x00000002},
254 {0x0460299b, 0x00000020},
255 {0x00004000, 0000000000},
256 {0x01e00830, 0x00000002},
257 {0x21007000, 0000000000},
258 {0x00005000, 0x00000002},
259 {0x00038042, 0x00000002},
260 {0x040025e0, 0x00000002},
261 {0x000075e1, 0000000000},
262 {0x00000001, 0000000000},
263 {0x000380d9, 0x00000002},
264 {0x04007394, 0000000000},
265 {0000000000, 0000000000},
266 {0000000000, 0000000000},
267 {0000000000, 0000000000},
268 {0000000000, 0000000000},
269 {0000000000, 0000000000},
270 {0000000000, 0000000000},
271 {0000000000, 0000000000},
272 {0000000000, 0000000000},
273 {0000000000, 0000000000},
274 {0000000000, 0000000000},
275 {0000000000, 0000000000},
276 {0000000000, 0000000000},
277 {0000000000, 0000000000},
278 {0000000000, 0000000000},
279 {0000000000, 0000000000},
280 {0000000000, 0000000000},
281 {0000000000, 0000000000},
282 {0000000000, 0000000000},
283 {0000000000, 0000000000},
284 {0000000000, 0000000000},
285 {0000000000, 0000000000},
286 {0000000000, 0000000000},
287 {0000000000, 0000000000},
288 {0000000000, 0000000000},
289 {0000000000, 0000000000},
290 {0000000000, 0000000000},
291 {0000000000, 0000000000},
292 {0000000000, 0000000000},
293 {0000000000, 0000000000},
294 {0000000000, 0000000000},
295 {0000000000, 0000000000},
296 {0000000000, 0000000000},
297 {0000000000, 0000000000},
298 {0000000000, 0000000000},
299 {0000000000, 0000000000},
300 {0000000000, 0000000000},
303 static const u32 radeon_cp_microcode[][2] = {
304 {0x21007000, 0000000000},
305 {0x20007000, 0000000000},
306 {0x000000b4, 0x00000004},
307 {0x000000b8, 0x00000004},
308 {0x6f5b4d4c, 0000000000},
309 {0x4c4c427f, 0000000000},
310 {0x5b568a92, 0000000000},
311 {0x4ca09c6d, 0000000000},
312 {0xad4c4c4c, 0000000000},
313 {0x4ce1af3d, 0000000000},
314 {0xd8afafaf, 0000000000},
315 {0xd64c4cdc, 0000000000},
316 {0x4cd10d10, 0000000000},
317 {0x000f0000, 0x00000016},
318 {0x362f242d, 0000000000},
319 {0x00000012, 0x00000004},
320 {0x000f0000, 0x00000016},
321 {0x362f282d, 0000000000},
322 {0x000380e7, 0x00000002},
323 {0x04002c97, 0x00000002},
324 {0x000f0001, 0x00000016},
325 {0x333a3730, 0000000000},
326 {0x000077ef, 0x00000002},
327 {0x00061000, 0x00000002},
328 {0x00000021, 0x0000001a},
329 {0x00004000, 0x0000001e},
330 {0x00061000, 0x00000002},
331 {0x00000021, 0x0000001a},
332 {0x00004000, 0x0000001e},
333 {0x00061000, 0x00000002},
334 {0x00000021, 0x0000001a},
335 {0x00004000, 0x0000001e},
336 {0x00000017, 0x00000004},
337 {0x0003802b, 0x00000002},
338 {0x040067e0, 0x00000002},
339 {0x00000017, 0x00000004},
340 {0x000077e0, 0x00000002},
341 {0x00065000, 0x00000002},
342 {0x000037e1, 0x00000002},
343 {0x040067e1, 0x00000006},
344 {0x000077e0, 0x00000002},
345 {0x000077e1, 0x00000002},
346 {0x000077e1, 0x00000006},
347 {0xffffffff, 0000000000},
348 {0x10000000, 0000000000},
349 {0x0003802b, 0x00000002},
350 {0x040067e0, 0x00000006},
351 {0x00007675, 0x00000002},
352 {0x00007676, 0x00000002},
353 {0x00007677, 0x00000002},
354 {0x00007678, 0x00000006},
355 {0x0003802c, 0x00000002},
356 {0x04002676, 0x00000002},
357 {0x00007677, 0x00000002},
358 {0x00007678, 0x00000006},
359 {0x0000002f, 0x00000018},
360 {0x0000002f, 0x00000018},
361 {0000000000, 0x00000006},
362 {0x00000030, 0x00000018},
363 {0x00000030, 0x00000018},
364 {0000000000, 0x00000006},
365 {0x01605000, 0x00000002},
366 {0x00065000, 0x00000002},
367 {0x00098000, 0x00000002},
368 {0x00061000, 0x00000002},
369 {0x64c0603e, 0x00000004},
370 {0x000380e6, 0x00000002},
371 {0x040025c5, 0x00000002},
372 {0x00080000, 0x00000016},
373 {0000000000, 0000000000},
374 {0x0400251d, 0x00000002},
375 {0x00007580, 0x00000002},
376 {0x00067581, 0x00000002},
377 {0x04002580, 0x00000002},
378 {0x00067581, 0x00000002},
379 {0x00000049, 0x00000004},
380 {0x00005000, 0000000000},
381 {0x000380e6, 0x00000002},
382 {0x040025c5, 0x00000002},
383 {0x00061000, 0x00000002},
384 {0x0000750e, 0x00000002},
385 {0x00019000, 0x00000002},
386 {0x00011055, 0x00000014},
387 {0x00000055, 0x00000012},
388 {0x0400250f, 0x00000002},
389 {0x0000504f, 0x00000004},
390 {0x000380e6, 0x00000002},
391 {0x040025c5, 0x00000002},
392 {0x00007565, 0x00000002},
393 {0x00007566, 0x00000002},
394 {0x00000058, 0x00000004},
395 {0x000380e6, 0x00000002},
396 {0x040025c5, 0x00000002},
397 {0x01e655b4, 0x00000002},
398 {0x4401b0e4, 0x00000002},
399 {0x01c110e4, 0x00000002},
400 {0x26667066, 0x00000018},
401 {0x040c2565, 0x00000002},
402 {0x00000066, 0x00000018},
403 {0x04002564, 0x00000002},
404 {0x00007566, 0x00000002},
405 {0x0000005d, 0x00000004},
406 {0x00401069, 0x00000008},
407 {0x00101000, 0x00000002},
408 {0x000d80ff, 0x00000002},
409 {0x0080006c, 0x00000008},
410 {0x000f9000, 0x00000002},
411 {0x000e00ff, 0x00000002},
412 {0000000000, 0x00000006},
413 {0x0000008f, 0x00000018},
414 {0x0000005b, 0x00000004},
415 {0x000380e6, 0x00000002},
416 {0x040025c5, 0x00000002},
417 {0x00007576, 0x00000002},
418 {0x00065000, 0x00000002},
419 {0x00009000, 0x00000002},
420 {0x00041000, 0x00000002},
421 {0x0c00350e, 0x00000002},
422 {0x00049000, 0x00000002},
423 {0x00051000, 0x00000002},
424 {0x01e785f8, 0x00000002},
425 {0x00200000, 0x00000002},
426 {0x0060007e, 0x0000000c},
427 {0x00007563, 0x00000002},
428 {0x006075f0, 0x00000021},
429 {0x20007073, 0x00000004},
430 {0x00005073, 0x00000004},
431 {0x000380e6, 0x00000002},
432 {0x040025c5, 0x00000002},
433 {0x00007576, 0x00000002},
434 {0x00007577, 0x00000002},
435 {0x0000750e, 0x00000002},
436 {0x0000750f, 0x00000002},
437 {0x00a05000, 0x00000002},
438 {0x00600083, 0x0000000c},
439 {0x006075f0, 0x00000021},
440 {0x000075f8, 0x00000002},
441 {0x00000083, 0x00000004},
442 {0x000a750e, 0x00000002},
443 {0x000380e6, 0x00000002},
444 {0x040025c5, 0x00000002},
445 {0x0020750f, 0x00000002},
446 {0x00600086, 0x00000004},
447 {0x00007570, 0x00000002},
448 {0x00007571, 0x00000002},
449 {0x00007572, 0x00000006},
450 {0x000380e6, 0x00000002},
451 {0x040025c5, 0x00000002},
452 {0x00005000, 0x00000002},
453 {0x00a05000, 0x00000002},
454 {0x00007568, 0x00000002},
455 {0x00061000, 0x00000002},
456 {0x00000095, 0x0000000c},
457 {0x00058000, 0x00000002},
458 {0x0c607562, 0x00000002},
459 {0x00000097, 0x00000004},
460 {0x000380e6, 0x00000002},
461 {0x040025c5, 0x00000002},
462 {0x00600096, 0x00000004},
463 {0x400070e5, 0000000000},
464 {0x000380e6, 0x00000002},
465 {0x040025c5, 0x00000002},
466 {0x000380e5, 0x00000002},
467 {0x000000a8, 0x0000001c},
468 {0x000650aa, 0x00000018},
469 {0x040025bb, 0x00000002},
470 {0x000610ab, 0x00000018},
471 {0x040075bc, 0000000000},
472 {0x000075bb, 0x00000002},
473 {0x000075bc, 0000000000},
474 {0x00090000, 0x00000006},
475 {0x00090000, 0x00000002},
476 {0x000d8002, 0x00000006},
477 {0x00007832, 0x00000002},
478 {0x00005000, 0x00000002},
479 {0x000380e7, 0x00000002},
480 {0x04002c97, 0x00000002},
481 {0x00007820, 0x00000002},
482 {0x00007821, 0x00000002},
483 {0x00007800, 0000000000},
484 {0x01200000, 0x00000002},
485 {0x20077000, 0x00000002},
486 {0x01200000, 0x00000002},
487 {0x20007000, 0x00000002},
488 {0x00061000, 0x00000002},
489 {0x0120751b, 0x00000002},
490 {0x8040750a, 0x00000002},
491 {0x8040750b, 0x00000002},
492 {0x00110000, 0x00000002},
493 {0x000380e5, 0x00000002},
494 {0x000000c6, 0x0000001c},
495 {0x000610ab, 0x00000018},
496 {0x844075bd, 0x00000002},
497 {0x000610aa, 0x00000018},
498 {0x840075bb, 0x00000002},
499 {0x000610ab, 0x00000018},
500 {0x844075bc, 0x00000002},
501 {0x000000c9, 0x00000004},
502 {0x804075bd, 0x00000002},
503 {0x800075bb, 0x00000002},
504 {0x804075bc, 0x00000002},
505 {0x00108000, 0x00000002},
506 {0x01400000, 0x00000002},
507 {0x006000cd, 0x0000000c},
508 {0x20c07000, 0x00000020},
509 {0x000000cf, 0x00000012},
510 {0x00800000, 0x00000006},
511 {0x0080751d, 0x00000006},
512 {0000000000, 0000000000},
513 {0x0000775c, 0x00000002},
514 {0x00a05000, 0x00000002},
515 {0x00661000, 0x00000002},
516 {0x0460275d, 0x00000020},
517 {0x00004000, 0000000000},
518 {0x01e00830, 0x00000002},
519 {0x21007000, 0000000000},
520 {0x6464614d, 0000000000},
521 {0x69687420, 0000000000},
522 {0x00000073, 0000000000},
523 {0000000000, 0000000000},
524 {0x00005000, 0x00000002},
525 {0x000380d0, 0x00000002},
526 {0x040025e0, 0x00000002},
527 {0x000075e1, 0000000000},
528 {0x00000001, 0000000000},
529 {0x000380e0, 0x00000002},
530 {0x04002394, 0x00000002},
531 {0x00005000, 0000000000},
532 {0000000000, 0000000000},
533 {0000000000, 0000000000},
534 {0x00000008, 0000000000},
535 {0x00000004, 0000000000},
536 {0000000000, 0000000000},
537 {0000000000, 0000000000},
538 {0000000000, 0000000000},
539 {0000000000, 0000000000},
540 {0000000000, 0000000000},
541 {0000000000, 0000000000},
542 {0000000000, 0000000000},
543 {0000000000, 0000000000},
544 {0000000000, 0000000000},
545 {0000000000, 0000000000},
546 {0000000000, 0000000000},
547 {0000000000, 0000000000},
548 {0000000000, 0000000000},
549 {0000000000, 0000000000},
550 {0000000000, 0000000000},
551 {0000000000, 0000000000},
552 {0000000000, 0000000000},
553 {0000000000, 0000000000},
554 {0000000000, 0000000000},
555 {0000000000, 0000000000},
556 {0000000000, 0000000000},
557 {0000000000, 0000000000},
558 {0000000000, 0000000000},
559 {0000000000, 0000000000},
562 static const u32 R300_cp_microcode[][2] = {
563 { 0x4200e000, 0000000000 },
564 { 0x4000e000, 0000000000 },
565 { 0x000000af, 0x00000008 },
566 { 0x000000b3, 0x00000008 },
567 { 0x6c5a504f, 0000000000 },
568 { 0x4f4f497a, 0000000000 },
569 { 0x5a578288, 0000000000 },
570 { 0x4f91906a, 0000000000 },
571 { 0x4f4f4f4f, 0000000000 },
572 { 0x4fe24f44, 0000000000 },
573 { 0x4f9c9c9c, 0000000000 },
574 { 0xdc4f4fde, 0000000000 },
575 { 0xa1cd4f4f, 0000000000 },
576 { 0xd29d9d9d, 0000000000 },
577 { 0x4f0f9fd7, 0000000000 },
578 { 0x000ca000, 0x00000004 },
579 { 0x000d0012, 0x00000038 },
580 { 0x0000e8b4, 0x00000004 },
581 { 0x000d0014, 0x00000038 },
582 { 0x0000e8b6, 0x00000004 },
583 { 0x000d0016, 0x00000038 },
584 { 0x0000e854, 0x00000004 },
585 { 0x000d0018, 0x00000038 },
586 { 0x0000e855, 0x00000004 },
587 { 0x000d001a, 0x00000038 },
588 { 0x0000e856, 0x00000004 },
589 { 0x000d001c, 0x00000038 },
590 { 0x0000e857, 0x00000004 },
591 { 0x000d001e, 0x00000038 },
592 { 0x0000e824, 0x00000004 },
593 { 0x000d0020, 0x00000038 },
594 { 0x0000e825, 0x00000004 },
595 { 0x000d0022, 0x00000038 },
596 { 0x0000e830, 0x00000004 },
597 { 0x000d0024, 0x00000038 },
598 { 0x0000f0c0, 0x00000004 },
599 { 0x000d0026, 0x00000038 },
600 { 0x0000f0c1, 0x00000004 },
601 { 0x000d0028, 0x00000038 },
602 { 0x0000f041, 0x00000004 },
603 { 0x000d002a, 0x00000038 },
604 { 0x0000f184, 0x00000004 },
605 { 0x000d002c, 0x00000038 },
606 { 0x0000f185, 0x00000004 },
607 { 0x000d002e, 0x00000038 },
608 { 0x0000f186, 0x00000004 },
609 { 0x000d0030, 0x00000038 },
610 { 0x0000f187, 0x00000004 },
611 { 0x000d0032, 0x00000038 },
612 { 0x0000f180, 0x00000004 },
613 { 0x000d0034, 0x00000038 },
614 { 0x0000f393, 0x00000004 },
615 { 0x000d0036, 0x00000038 },
616 { 0x0000f38a, 0x00000004 },
617 { 0x000d0038, 0x00000038 },
618 { 0x0000f38e, 0x00000004 },
619 { 0x0000e821, 0x00000004 },
620 { 0x0140a000, 0x00000004 },
621 { 0x00000043, 0x00000018 },
622 { 0x00cce800, 0x00000004 },
623 { 0x001b0001, 0x00000004 },
624 { 0x08004800, 0x00000004 },
625 { 0x001b0001, 0x00000004 },
626 { 0x08004800, 0x00000004 },
627 { 0x001b0001, 0x00000004 },
628 { 0x08004800, 0x00000004 },
629 { 0x0000003a, 0x00000008 },
630 { 0x0000a000, 0000000000 },
631 { 0x02c0a000, 0x00000004 },
632 { 0x000ca000, 0x00000004 },
633 { 0x00130000, 0x00000004 },
634 { 0x000c2000, 0x00000004 },
635 { 0xc980c045, 0x00000008 },
636 { 0x2000451d, 0x00000004 },
637 { 0x0000e580, 0x00000004 },
638 { 0x000ce581, 0x00000004 },
639 { 0x08004580, 0x00000004 },
640 { 0x000ce581, 0x00000004 },
641 { 0x0000004c, 0x00000008 },
642 { 0x0000a000, 0000000000 },
643 { 0x000c2000, 0x00000004 },
644 { 0x0000e50e, 0x00000004 },
645 { 0x00032000, 0x00000004 },
646 { 0x00022056, 0x00000028 },
647 { 0x00000056, 0x00000024 },
648 { 0x0800450f, 0x00000004 },
649 { 0x0000a050, 0x00000008 },
650 { 0x0000e565, 0x00000004 },
651 { 0x0000e566, 0x00000004 },
652 { 0x00000057, 0x00000008 },
653 { 0x03cca5b4, 0x00000004 },
654 { 0x05432000, 0x00000004 },
655 { 0x00022000, 0x00000004 },
656 { 0x4ccce063, 0x00000030 },
657 { 0x08274565, 0x00000004 },
658 { 0x00000063, 0x00000030 },
659 { 0x08004564, 0x00000004 },
660 { 0x0000e566, 0x00000004 },
661 { 0x0000005a, 0x00000008 },
662 { 0x00802066, 0x00000010 },
663 { 0x00202000, 0x00000004 },
664 { 0x001b00ff, 0x00000004 },
665 { 0x01000069, 0x00000010 },
666 { 0x001f2000, 0x00000004 },
667 { 0x001c00ff, 0x00000004 },
668 { 0000000000, 0x0000000c },
669 { 0x00000085, 0x00000030 },
670 { 0x0000005a, 0x00000008 },
671 { 0x0000e576, 0x00000004 },
672 { 0x000ca000, 0x00000004 },
673 { 0x00012000, 0x00000004 },
674 { 0x00082000, 0x00000004 },
675 { 0x1800650e, 0x00000004 },
676 { 0x00092000, 0x00000004 },
677 { 0x000a2000, 0x00000004 },
678 { 0x000f0000, 0x00000004 },
679 { 0x00400000, 0x00000004 },
680 { 0x00000079, 0x00000018 },
681 { 0x0000e563, 0x00000004 },
682 { 0x00c0e5f9, 0x000000c2 },
683 { 0x0000006e, 0x00000008 },
684 { 0x0000a06e, 0x00000008 },
685 { 0x0000e576, 0x00000004 },
686 { 0x0000e577, 0x00000004 },
687 { 0x0000e50e, 0x00000004 },
688 { 0x0000e50f, 0x00000004 },
689 { 0x0140a000, 0x00000004 },
690 { 0x0000007c, 0x00000018 },
691 { 0x00c0e5f9, 0x000000c2 },
692 { 0x0000007c, 0x00000008 },
693 { 0x0014e50e, 0x00000004 },
694 { 0x0040e50f, 0x00000004 },
695 { 0x00c0007f, 0x00000008 },
696 { 0x0000e570, 0x00000004 },
697 { 0x0000e571, 0x00000004 },
698 { 0x0000e572, 0x0000000c },
699 { 0x0000a000, 0x00000004 },
700 { 0x0140a000, 0x00000004 },
701 { 0x0000e568, 0x00000004 },
702 { 0x000c2000, 0x00000004 },
703 { 0x00000089, 0x00000018 },
704 { 0x000b0000, 0x00000004 },
705 { 0x18c0e562, 0x00000004 },
706 { 0x0000008b, 0x00000008 },
707 { 0x00c0008a, 0x00000008 },
708 { 0x000700e4, 0x00000004 },
709 { 0x00000097, 0x00000038 },
710 { 0x000ca099, 0x00000030 },
711 { 0x080045bb, 0x00000004 },
712 { 0x000c209a, 0x00000030 },
713 { 0x0800e5bc, 0000000000 },
714 { 0x0000e5bb, 0x00000004 },
715 { 0x0000e5bc, 0000000000 },
716 { 0x00120000, 0x0000000c },
717 { 0x00120000, 0x00000004 },
718 { 0x001b0002, 0x0000000c },
719 { 0x0000a000, 0x00000004 },
720 { 0x0000e821, 0x00000004 },
721 { 0x0000e800, 0000000000 },
722 { 0x0000e821, 0x00000004 },
723 { 0x0000e82e, 0000000000 },
724 { 0x02cca000, 0x00000004 },
725 { 0x00140000, 0x00000004 },
726 { 0x000ce1cc, 0x00000004 },
727 { 0x050de1cd, 0x00000004 },
728 { 0x000000a7, 0x00000020 },
729 { 0x4200e000, 0000000000 },
730 { 0x000000ae, 0x00000038 },
731 { 0x000ca000, 0x00000004 },
732 { 0x00140000, 0x00000004 },
733 { 0x000c2000, 0x00000004 },
734 { 0x00160000, 0x00000004 },
735 { 0x700ce000, 0x00000004 },
736 { 0x001400aa, 0x00000008 },
737 { 0x4000e000, 0000000000 },
738 { 0x02400000, 0x00000004 },
739 { 0x400ee000, 0x00000004 },
740 { 0x02400000, 0x00000004 },
741 { 0x4000e000, 0000000000 },
742 { 0x000c2000, 0x00000004 },
743 { 0x0240e51b, 0x00000004 },
744 { 0x0080e50a, 0x00000005 },
745 { 0x0080e50b, 0x00000005 },
746 { 0x00220000, 0x00000004 },
747 { 0x000700e4, 0x00000004 },
748 { 0x000000c1, 0x00000038 },
749 { 0x000c209a, 0x00000030 },
750 { 0x0880e5bd, 0x00000005 },
751 { 0x000c2099, 0x00000030 },
752 { 0x0800e5bb, 0x00000005 },
753 { 0x000c209a, 0x00000030 },
754 { 0x0880e5bc, 0x00000005 },
755 { 0x000000c4, 0x00000008 },
756 { 0x0080e5bd, 0x00000005 },
757 { 0x0000e5bb, 0x00000005 },
758 { 0x0080e5bc, 0x00000005 },
759 { 0x00210000, 0x00000004 },
760 { 0x02800000, 0x00000004 },
761 { 0x00c000c8, 0x00000018 },
762 { 0x4180e000, 0x00000040 },
763 { 0x000000ca, 0x00000024 },
764 { 0x01000000, 0x0000000c },
765 { 0x0100e51d, 0x0000000c },
766 { 0x000045bb, 0x00000004 },
767 { 0x000080c4, 0x00000008 },
768 { 0x0000f3ce, 0x00000004 },
769 { 0x0140a000, 0x00000004 },
770 { 0x00cc2000, 0x00000004 },
771 { 0x08c053cf, 0x00000040 },
772 { 0x00008000, 0000000000 },
773 { 0x0000f3d2, 0x00000004 },
774 { 0x0140a000, 0x00000004 },
775 { 0x00cc2000, 0x00000004 },
776 { 0x08c053d3, 0x00000040 },
777 { 0x00008000, 0000000000 },
778 { 0x0000f39d, 0x00000004 },
779 { 0x0140a000, 0x00000004 },
780 { 0x00cc2000, 0x00000004 },
781 { 0x08c0539e, 0x00000040 },
782 { 0x00008000, 0000000000 },
783 { 0x03c00830, 0x00000004 },
784 { 0x4200e000, 0000000000 },
785 { 0x0000a000, 0x00000004 },
786 { 0x200045e0, 0x00000004 },
787 { 0x0000e5e1, 0000000000 },
788 { 0x00000001, 0000000000 },
789 { 0x000700e1, 0x00000004 },
790 { 0x0800e394, 0000000000 },
791 { 0000000000, 0000000000 },
792 { 0000000000, 0000000000 },
793 { 0000000000, 0000000000 },
794 { 0000000000, 0000000000 },
795 { 0000000000, 0000000000 },
796 { 0000000000, 0000000000 },
797 { 0000000000, 0000000000 },
798 { 0000000000, 0000000000 },
799 { 0000000000, 0000000000 },
800 { 0000000000, 0000000000 },
801 { 0000000000, 0000000000 },
802 { 0000000000, 0000000000 },
803 { 0000000000, 0000000000 },
804 { 0000000000, 0000000000 },
805 { 0000000000, 0000000000 },
806 { 0000000000, 0000000000 },
807 { 0000000000, 0000000000 },
808 { 0000000000, 0000000000 },
809 { 0000000000, 0000000000 },
810 { 0000000000, 0000000000 },
811 { 0000000000, 0000000000 },
812 { 0000000000, 0000000000 },
813 { 0000000000, 0000000000 },
814 { 0000000000, 0000000000 },
815 { 0000000000, 0000000000 },
816 { 0000000000, 0000000000 },
817 { 0000000000, 0000000000 },
818 { 0000000000, 0000000000 },
821 static u32 RADEON_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
824 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
825 ret = RADEON_READ(R520_MC_IND_DATA);
826 RADEON_WRITE(R520_MC_IND_INDEX, 0);
830 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
833 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
834 return RADEON_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
835 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
836 return RADEON_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
838 return RADEON_READ(RADEON_MC_FB_LOCATION);
841 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
843 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
844 RADEON_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
845 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
846 RADEON_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
848 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
851 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
853 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
854 RADEON_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
855 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
856 RADEON_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
858 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
861 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
863 drm_radeon_private_t *dev_priv = dev->dev_private;
865 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
866 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
869 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
871 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
872 return RADEON_READ(RADEON_PCIE_DATA);
875 static u32 RADEON_READ_IGPGART(drm_radeon_private_t *dev_priv, int addr)
878 RADEON_WRITE(RADEON_IGPGART_INDEX, addr & 0x7f);
879 ret = RADEON_READ(RADEON_IGPGART_DATA);
880 RADEON_WRITE(RADEON_IGPGART_INDEX, 0x7f);
884 #if RADEON_FIFO_DEBUG
885 static void radeon_status(drm_radeon_private_t * dev_priv)
887 printk("%s:\n", __FUNCTION__);
888 printk("RBBM_STATUS = 0x%08x\n",
889 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
890 printk("CP_RB_RTPR = 0x%08x\n",
891 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
892 printk("CP_RB_WTPR = 0x%08x\n",
893 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
894 printk("AIC_CNTL = 0x%08x\n",
895 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
896 printk("AIC_STAT = 0x%08x\n",
897 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
898 printk("AIC_PT_BASE = 0x%08x\n",
899 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
900 printk("TLB_ADDR = 0x%08x\n",
901 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
902 printk("TLB_DATA = 0x%08x\n",
903 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
907 /* ================================================================
908 * Engine, FIFO control
911 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
916 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
918 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
919 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
920 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
922 for (i = 0; i < dev_priv->usec_timeout; i++) {
923 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
924 & RADEON_RB3D_DC_BUSY)) {
930 #if RADEON_FIFO_DEBUG
931 DRM_ERROR("failed!\n");
932 radeon_status(dev_priv);
937 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
941 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
943 for (i = 0; i < dev_priv->usec_timeout; i++) {
944 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
945 & RADEON_RBBM_FIFOCNT_MASK);
946 if (slots >= entries)
951 #if RADEON_FIFO_DEBUG
952 DRM_ERROR("failed!\n");
953 radeon_status(dev_priv);
958 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
962 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
964 ret = radeon_do_wait_for_fifo(dev_priv, 64);
968 for (i = 0; i < dev_priv->usec_timeout; i++) {
969 if (!(RADEON_READ(RADEON_RBBM_STATUS)
970 & RADEON_RBBM_ACTIVE)) {
971 radeon_do_pixcache_flush(dev_priv);
977 #if RADEON_FIFO_DEBUG
978 DRM_ERROR("failed!\n");
979 radeon_status(dev_priv);
984 /* ================================================================
985 * CP control, initialization
988 /* Load the microcode for the CP */
989 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
994 radeon_do_wait_for_idle(dev_priv);
996 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
998 if (dev_priv->microcode_version == UCODE_R200) {
999 DRM_INFO("Loading R200 Microcode\n");
1000 for (i = 0; i < 256; i++) {
1001 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1002 R200_cp_microcode[i][1]);
1003 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1004 R200_cp_microcode[i][0]);
1006 } else if (dev_priv->microcode_version == UCODE_R300) {
1007 DRM_INFO("Loading R300 Microcode\n");
1008 for (i = 0; i < 256; i++) {
1009 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1010 R300_cp_microcode[i][1]);
1011 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1012 R300_cp_microcode[i][0]);
1015 for (i = 0; i < 256; i++) {
1016 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
1017 radeon_cp_microcode[i][1]);
1018 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
1019 radeon_cp_microcode[i][0]);
1024 /* Flush any pending commands to the CP. This should only be used just
1025 * prior to a wait for idle, as it informs the engine that the command
1028 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
1034 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
1035 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
1039 /* Wait for the CP to go idle.
1041 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
1048 RADEON_PURGE_CACHE();
1049 RADEON_PURGE_ZCACHE();
1050 RADEON_WAIT_UNTIL_IDLE();
1055 return radeon_do_wait_for_idle(dev_priv);
1058 /* Start the Command Processor.
1060 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
1065 radeon_do_wait_for_idle(dev_priv);
1067 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
1069 dev_priv->cp_running = 1;
1073 RADEON_PURGE_CACHE();
1074 RADEON_PURGE_ZCACHE();
1075 RADEON_WAIT_UNTIL_IDLE();
1081 /* Reset the Command Processor. This will not flush any pending
1082 * commands, so you must wait for the CP command stream to complete
1083 * before calling this routine.
1085 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
1090 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1091 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1092 SET_RING_HEAD(dev_priv, cur_read_ptr);
1093 dev_priv->ring.tail = cur_read_ptr;
1096 /* Stop the Command Processor. This will not flush any pending
1097 * commands, so you must flush the command stream and wait for the CP
1098 * to go idle before calling this routine.
1100 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
1104 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
1106 dev_priv->cp_running = 0;
1109 /* Reset the engine. This will stop the CP if it is running.
1111 static int radeon_do_engine_reset(struct drm_device * dev)
1113 drm_radeon_private_t *dev_priv = dev->dev_private;
1114 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
1117 radeon_do_pixcache_flush(dev_priv);
1119 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1120 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
1121 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
1123 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
1124 RADEON_FORCEON_MCLKA |
1125 RADEON_FORCEON_MCLKB |
1126 RADEON_FORCEON_YCLKA |
1127 RADEON_FORCEON_YCLKB |
1129 RADEON_FORCEON_AIC));
1131 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
1133 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
1134 RADEON_SOFT_RESET_CP |
1135 RADEON_SOFT_RESET_HI |
1136 RADEON_SOFT_RESET_SE |
1137 RADEON_SOFT_RESET_RE |
1138 RADEON_SOFT_RESET_PP |
1139 RADEON_SOFT_RESET_E2 |
1140 RADEON_SOFT_RESET_RB));
1141 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1142 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
1143 ~(RADEON_SOFT_RESET_CP |
1144 RADEON_SOFT_RESET_HI |
1145 RADEON_SOFT_RESET_SE |
1146 RADEON_SOFT_RESET_RE |
1147 RADEON_SOFT_RESET_PP |
1148 RADEON_SOFT_RESET_E2 |
1149 RADEON_SOFT_RESET_RB)));
1150 RADEON_READ(RADEON_RBBM_SOFT_RESET);
1152 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
1153 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
1154 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
1157 /* Reset the CP ring */
1158 radeon_do_cp_reset(dev_priv);
1160 /* The CP is no longer running after an engine reset */
1161 dev_priv->cp_running = 0;
1163 /* Reset any pending vertex, indirect buffers */
1164 radeon_freelist_reset(dev);
1169 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
1170 drm_radeon_private_t * dev_priv)
1172 u32 ring_start, cur_read_ptr;
1175 /* Initialize the memory controller. With new memory map, the fb location
1176 * is not changed, it should have been properly initialized already. Part
1177 * of the problem is that the code below is bogus, assuming the GART is
1178 * always appended to the fb which is not necessarily the case
1180 if (!dev_priv->new_memmap)
1181 radeon_write_fb_location(dev_priv,
1182 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
1183 | (dev_priv->fb_location >> 16));
1186 if (dev_priv->flags & RADEON_IS_AGP) {
1187 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
1188 radeon_write_agp_location(dev_priv,
1189 (((dev_priv->gart_vm_start - 1 +
1190 dev_priv->gart_size) & 0xffff0000) |
1191 (dev_priv->gart_vm_start >> 16)));
1193 ring_start = (dev_priv->cp_ring->offset
1195 + dev_priv->gart_vm_start);
1198 ring_start = (dev_priv->cp_ring->offset
1199 - (unsigned long)dev->sg->virtual
1200 + dev_priv->gart_vm_start);
1202 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
1204 /* Set the write pointer delay */
1205 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
1207 /* Initialize the ring buffer's read and write pointers */
1208 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
1209 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
1210 SET_RING_HEAD(dev_priv, cur_read_ptr);
1211 dev_priv->ring.tail = cur_read_ptr;
1214 if (dev_priv->flags & RADEON_IS_AGP) {
1215 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
1216 dev_priv->ring_rptr->offset
1217 - dev->agp->base + dev_priv->gart_vm_start);
1221 struct drm_sg_mem *entry = dev->sg;
1222 unsigned long tmp_ofs, page_ofs;
1224 tmp_ofs = dev_priv->ring_rptr->offset -
1225 (unsigned long)dev->sg->virtual;
1226 page_ofs = tmp_ofs >> PAGE_SHIFT;
1228 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
1229 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
1230 (unsigned long)entry->busaddr[page_ofs],
1231 entry->handle + tmp_ofs);
1234 /* Set ring buffer size */
1236 RADEON_WRITE(RADEON_CP_RB_CNTL,
1237 RADEON_BUF_SWAP_32BIT |
1238 (dev_priv->ring.fetch_size_l2ow << 18) |
1239 (dev_priv->ring.rptr_update_l2qw << 8) |
1240 dev_priv->ring.size_l2qw);
1242 RADEON_WRITE(RADEON_CP_RB_CNTL,
1243 (dev_priv->ring.fetch_size_l2ow << 18) |
1244 (dev_priv->ring.rptr_update_l2qw << 8) |
1245 dev_priv->ring.size_l2qw);
1248 /* Start with assuming that writeback doesn't work */
1249 dev_priv->writeback_works = 0;
1251 /* Initialize the scratch register pointer. This will cause
1252 * the scratch register values to be written out to memory
1253 * whenever they are updated.
1255 * We simply put this behind the ring read pointer, this works
1256 * with PCI GART as well as (whatever kind of) AGP GART
1258 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
1259 + RADEON_SCRATCH_REG_OFFSET);
1261 dev_priv->scratch = ((__volatile__ u32 *)
1262 dev_priv->ring_rptr->handle +
1263 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
1265 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
1267 /* Turn on bus mastering */
1268 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
1269 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
1271 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
1272 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
1274 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
1275 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
1276 dev_priv->sarea_priv->last_dispatch);
1278 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
1279 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
1281 radeon_do_wait_for_idle(dev_priv);
1283 /* Sync everything up */
1284 RADEON_WRITE(RADEON_ISYNC_CNTL,
1285 (RADEON_ISYNC_ANY2D_IDLE3D |
1286 RADEON_ISYNC_ANY3D_IDLE2D |
1287 RADEON_ISYNC_WAIT_IDLEGUI |
1288 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
1292 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
1296 /* Writeback doesn't seem to work everywhere, test it here and possibly
1297 * enable it if it appears to work
1299 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
1300 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
1302 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
1303 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
1309 if (tmp < dev_priv->usec_timeout) {
1310 dev_priv->writeback_works = 1;
1311 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
1313 dev_priv->writeback_works = 0;
1314 DRM_INFO("writeback test failed\n");
1316 if (radeon_no_wb == 1) {
1317 dev_priv->writeback_works = 0;
1318 DRM_INFO("writeback forced off\n");
1321 if (!dev_priv->writeback_works) {
1322 /* Disable writeback to avoid unnecessary bus master transfers */
1323 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
1324 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
1328 /* Enable or disable IGP GART on the chip */
1329 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
1333 tmp = RADEON_READ(RADEON_AIC_CNTL);
1334 DRM_DEBUG("setting igpgart AIC CNTL is %08X\n", tmp);
1336 DRM_DEBUG("programming igpgart %08X %08lX %08X\n",
1337 dev_priv->gart_vm_start,
1338 (long)dev_priv->gart_info.bus_addr,
1339 dev_priv->gart_size);
1341 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_18, 0x1000);
1342 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, 0x1);
1343 RADEON_WRITE_IGPGART(RADEON_IGPGART_CTRL, 0x42040800);
1344 RADEON_WRITE_IGPGART(RADEON_IGPGART_BASE_ADDR,
1345 dev_priv->gart_info.bus_addr);
1347 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_UNK_39);
1348 RADEON_WRITE_IGPGART(RADEON_IGPGART_UNK_39, temp);
1350 RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
1351 dev_priv->gart_size = 32*1024*1024;
1352 radeon_write_agp_location(dev_priv,
1353 (((dev_priv->gart_vm_start - 1 +
1354 dev_priv->gart_size) & 0xffff0000) |
1355 (dev_priv->gart_vm_start >> 16)));
1357 temp = RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_ENABLE);
1358 RADEON_WRITE_IGPGART(RADEON_IGPGART_ENABLE, temp);
1360 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1361 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x1);
1362 RADEON_READ_IGPGART(dev_priv, RADEON_IGPGART_FLUSH);
1363 RADEON_WRITE_IGPGART(RADEON_IGPGART_FLUSH, 0x0);
1367 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1369 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1372 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1373 dev_priv->gart_vm_start,
1374 (long)dev_priv->gart_info.bus_addr,
1375 dev_priv->gart_size);
1376 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1377 dev_priv->gart_vm_start);
1378 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1379 dev_priv->gart_info.bus_addr);
1380 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1381 dev_priv->gart_vm_start);
1382 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1383 dev_priv->gart_vm_start +
1384 dev_priv->gart_size - 1);
1386 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1388 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1389 RADEON_PCIE_TX_GART_EN);
1391 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1392 tmp & ~RADEON_PCIE_TX_GART_EN);
1396 /* Enable or disable PCI GART on the chip */
1397 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1401 if (dev_priv->flags & RADEON_IS_IGPGART) {
1402 radeon_set_igpgart(dev_priv, on);
1406 if (dev_priv->flags & RADEON_IS_PCIE) {
1407 radeon_set_pciegart(dev_priv, on);
1411 tmp = RADEON_READ(RADEON_AIC_CNTL);
1414 RADEON_WRITE(RADEON_AIC_CNTL,
1415 tmp | RADEON_PCIGART_TRANSLATE_EN);
1417 /* set PCI GART page-table base address
1419 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1421 /* set address range for PCI address translate
1423 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1424 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1425 + dev_priv->gart_size - 1);
1427 /* Turn off AGP aperture -- is this required for PCI GART?
1429 radeon_write_agp_location(dev_priv, 0xffffffc0);
1430 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1432 RADEON_WRITE(RADEON_AIC_CNTL,
1433 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1437 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
1439 drm_radeon_private_t *dev_priv = dev->dev_private;
1443 /* if we require new memory map but we don't have it fail */
1444 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1445 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1446 radeon_do_cleanup_cp(dev);
1450 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
1452 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1453 dev_priv->flags &= ~RADEON_IS_AGP;
1455 else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1458 DRM_DEBUG("Restoring AGP flag\n");
1459 dev_priv->flags |= RADEON_IS_AGP;
1462 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1463 DRM_ERROR("PCI GART memory not allocated!\n");
1464 radeon_do_cleanup_cp(dev);
1468 dev_priv->usec_timeout = init->usec_timeout;
1469 if (dev_priv->usec_timeout < 1 ||
1470 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1471 DRM_DEBUG("TIMEOUT problem!\n");
1472 radeon_do_cleanup_cp(dev);
1476 /* Enable vblank on CRTC1 for older X servers
1478 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1480 switch(init->func) {
1481 case RADEON_INIT_R200_CP:
1482 dev_priv->microcode_version = UCODE_R200;
1484 case RADEON_INIT_R300_CP:
1485 dev_priv->microcode_version = UCODE_R300;
1488 dev_priv->microcode_version = UCODE_R100;
1491 dev_priv->do_boxes = 0;
1492 dev_priv->cp_mode = init->cp_mode;
1494 /* We don't support anything other than bus-mastering ring mode,
1495 * but the ring can be in either AGP or PCI space for the ring
1498 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1499 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1500 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1501 radeon_do_cleanup_cp(dev);
1505 switch (init->fb_bpp) {
1507 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1511 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1514 dev_priv->front_offset = init->front_offset;
1515 dev_priv->front_pitch = init->front_pitch;
1516 dev_priv->back_offset = init->back_offset;
1517 dev_priv->back_pitch = init->back_pitch;
1519 switch (init->depth_bpp) {
1521 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1525 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1528 dev_priv->depth_offset = init->depth_offset;
1529 dev_priv->depth_pitch = init->depth_pitch;
1531 /* Hardware state for depth clears. Remove this if/when we no
1532 * longer clear the depth buffer with a 3D rectangle. Hard-code
1533 * all values to prevent unwanted 3D state from slipping through
1534 * and screwing with the clear operation.
1536 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1537 (dev_priv->color_fmt << 10) |
1538 (dev_priv->microcode_version ==
1539 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1541 dev_priv->depth_clear.rb3d_zstencilcntl =
1542 (dev_priv->depth_fmt |
1543 RADEON_Z_TEST_ALWAYS |
1544 RADEON_STENCIL_TEST_ALWAYS |
1545 RADEON_STENCIL_S_FAIL_REPLACE |
1546 RADEON_STENCIL_ZPASS_REPLACE |
1547 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1549 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1550 RADEON_BFACE_SOLID |
1551 RADEON_FFACE_SOLID |
1552 RADEON_FLAT_SHADE_VTX_LAST |
1553 RADEON_DIFFUSE_SHADE_FLAT |
1554 RADEON_ALPHA_SHADE_FLAT |
1555 RADEON_SPECULAR_SHADE_FLAT |
1556 RADEON_FOG_SHADE_FLAT |
1557 RADEON_VTX_PIX_CENTER_OGL |
1558 RADEON_ROUND_MODE_TRUNC |
1559 RADEON_ROUND_PREC_8TH_PIX);
1562 dev_priv->ring_offset = init->ring_offset;
1563 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1564 dev_priv->buffers_offset = init->buffers_offset;
1565 dev_priv->gart_textures_offset = init->gart_textures_offset;
1567 dev_priv->sarea = drm_getsarea(dev);
1568 if (!dev_priv->sarea) {
1569 DRM_ERROR("could not find sarea!\n");
1570 radeon_do_cleanup_cp(dev);
1574 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1575 if (!dev_priv->cp_ring) {
1576 DRM_ERROR("could not find cp ring region!\n");
1577 radeon_do_cleanup_cp(dev);
1580 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1581 if (!dev_priv->ring_rptr) {
1582 DRM_ERROR("could not find ring read pointer!\n");
1583 radeon_do_cleanup_cp(dev);
1586 dev->agp_buffer_token = init->buffers_offset;
1587 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1588 if (!dev->agp_buffer_map) {
1589 DRM_ERROR("could not find dma buffer region!\n");
1590 radeon_do_cleanup_cp(dev);
1594 if (init->gart_textures_offset) {
1595 dev_priv->gart_textures =
1596 drm_core_findmap(dev, init->gart_textures_offset);
1597 if (!dev_priv->gart_textures) {
1598 DRM_ERROR("could not find GART texture region!\n");
1599 radeon_do_cleanup_cp(dev);
1604 dev_priv->sarea_priv =
1605 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1606 init->sarea_priv_offset);
1609 if (dev_priv->flags & RADEON_IS_AGP) {
1610 drm_core_ioremap(dev_priv->cp_ring, dev);
1611 drm_core_ioremap(dev_priv->ring_rptr, dev);
1612 drm_core_ioremap(dev->agp_buffer_map, dev);
1613 if (!dev_priv->cp_ring->handle ||
1614 !dev_priv->ring_rptr->handle ||
1615 !dev->agp_buffer_map->handle) {
1616 DRM_ERROR("could not find ioremap agp regions!\n");
1617 radeon_do_cleanup_cp(dev);
1623 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1624 dev_priv->ring_rptr->handle =
1625 (void *)dev_priv->ring_rptr->offset;
1626 dev->agp_buffer_map->handle =
1627 (void *)dev->agp_buffer_map->offset;
1629 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1630 dev_priv->cp_ring->handle);
1631 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1632 dev_priv->ring_rptr->handle);
1633 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1634 dev->agp_buffer_map->handle);
1637 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1639 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1640 - dev_priv->fb_location;
1642 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1643 ((dev_priv->front_offset
1644 + dev_priv->fb_location) >> 10));
1646 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1647 ((dev_priv->back_offset
1648 + dev_priv->fb_location) >> 10));
1650 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1651 ((dev_priv->depth_offset
1652 + dev_priv->fb_location) >> 10));
1654 dev_priv->gart_size = init->gart_size;
1656 /* New let's set the memory map ... */
1657 if (dev_priv->new_memmap) {
1660 DRM_INFO("Setting GART location based on new memory map\n");
1662 /* If using AGP, try to locate the AGP aperture at the same
1663 * location in the card and on the bus, though we have to
1667 if (dev_priv->flags & RADEON_IS_AGP) {
1668 base = dev->agp->base;
1669 /* Check if valid */
1670 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1671 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1672 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1678 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1680 base = dev_priv->fb_location + dev_priv->fb_size;
1681 if (base < dev_priv->fb_location ||
1682 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1683 base = dev_priv->fb_location
1684 - dev_priv->gart_size;
1686 dev_priv->gart_vm_start = base & 0xffc00000u;
1687 if (dev_priv->gart_vm_start != base)
1688 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1689 base, dev_priv->gart_vm_start);
1691 DRM_INFO("Setting GART location based on old memory map\n");
1692 dev_priv->gart_vm_start = dev_priv->fb_location +
1693 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1697 if (dev_priv->flags & RADEON_IS_AGP)
1698 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1700 + dev_priv->gart_vm_start);
1703 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1704 - (unsigned long)dev->sg->virtual
1705 + dev_priv->gart_vm_start);
1707 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1708 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1709 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1710 dev_priv->gart_buffers_offset);
1712 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1713 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1714 + init->ring_size / sizeof(u32));
1715 dev_priv->ring.size = init->ring_size;
1716 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1718 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1719 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1721 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1722 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1724 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1726 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1729 if (dev_priv->flags & RADEON_IS_AGP) {
1730 /* Turn off PCI GART */
1731 radeon_set_pcigart(dev_priv, 0);
1735 /* if we have an offset set from userspace */
1736 if (dev_priv->pcigart_offset_set) {
1737 dev_priv->gart_info.bus_addr =
1738 dev_priv->pcigart_offset + dev_priv->fb_location;
1739 dev_priv->gart_info.mapping.offset =
1740 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1741 dev_priv->gart_info.mapping.size =
1742 dev_priv->gart_info.table_size;
1744 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1745 dev_priv->gart_info.addr =
1746 dev_priv->gart_info.mapping.handle;
1748 if (dev_priv->flags & RADEON_IS_PCIE)
1749 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1751 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1752 dev_priv->gart_info.gart_table_location =
1755 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1756 dev_priv->gart_info.addr,
1757 dev_priv->pcigart_offset);
1759 if (dev_priv->flags & RADEON_IS_IGPGART)
1760 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1762 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1763 dev_priv->gart_info.gart_table_location =
1765 dev_priv->gart_info.addr = NULL;
1766 dev_priv->gart_info.bus_addr = 0;
1767 if (dev_priv->flags & RADEON_IS_PCIE) {
1769 ("Cannot use PCI Express without GART in FB memory\n");
1770 radeon_do_cleanup_cp(dev);
1775 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1776 DRM_ERROR("failed to init PCI GART!\n");
1777 radeon_do_cleanup_cp(dev);
1781 /* Turn on PCI GART */
1782 radeon_set_pcigart(dev_priv, 1);
1785 radeon_cp_load_microcode(dev_priv);
1786 radeon_cp_init_ring_buffer(dev, dev_priv);
1788 dev_priv->last_buf = 0;
1790 radeon_do_engine_reset(dev);
1791 radeon_test_writeback(dev_priv);
1796 static int radeon_do_cleanup_cp(struct drm_device * dev)
1798 drm_radeon_private_t *dev_priv = dev->dev_private;
1801 /* Make sure interrupts are disabled here because the uninstall ioctl
1802 * may not have been called from userspace and after dev_private
1803 * is freed, it's too late.
1805 if (dev->irq_enabled)
1806 drm_irq_uninstall(dev);
1809 if (dev_priv->flags & RADEON_IS_AGP) {
1810 if (dev_priv->cp_ring != NULL) {
1811 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1812 dev_priv->cp_ring = NULL;
1814 if (dev_priv->ring_rptr != NULL) {
1815 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1816 dev_priv->ring_rptr = NULL;
1818 if (dev->agp_buffer_map != NULL) {
1819 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1820 dev->agp_buffer_map = NULL;
1826 if (dev_priv->gart_info.bus_addr) {
1827 /* Turn off PCI GART */
1828 radeon_set_pcigart(dev_priv, 0);
1829 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1830 DRM_ERROR("failed to cleanup PCI GART!\n");
1833 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1835 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1836 dev_priv->gart_info.addr = 0;
1839 /* only clear to the start of flags */
1840 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1845 /* This code will reinit the Radeon CP hardware after a resume from disc.
1846 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1847 * here we make sure that all Radeon hardware initialisation is re-done without
1848 * affecting running applications.
1850 * Charl P. Botha <http://cpbotha.net>
1852 static int radeon_do_resume_cp(struct drm_device * dev)
1854 drm_radeon_private_t *dev_priv = dev->dev_private;
1857 DRM_ERROR("Called with no initialization\n");
1861 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1864 if (dev_priv->flags & RADEON_IS_AGP) {
1865 /* Turn off PCI GART */
1866 radeon_set_pcigart(dev_priv, 0);
1870 /* Turn on PCI GART */
1871 radeon_set_pcigart(dev_priv, 1);
1874 radeon_cp_load_microcode(dev_priv);
1875 radeon_cp_init_ring_buffer(dev, dev_priv);
1877 radeon_do_engine_reset(dev);
1879 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1884 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1886 drm_radeon_init_t *init = data;
1888 LOCK_TEST_WITH_RETURN(dev, file_priv);
1890 if (init->func == RADEON_INIT_R300_CP)
1891 r300_init_reg_flags(dev);
1893 switch (init->func) {
1894 case RADEON_INIT_CP:
1895 case RADEON_INIT_R200_CP:
1896 case RADEON_INIT_R300_CP:
1897 return radeon_do_init_cp(dev, init);
1898 case RADEON_CLEANUP_CP:
1899 return radeon_do_cleanup_cp(dev);
1905 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1907 drm_radeon_private_t *dev_priv = dev->dev_private;
1910 LOCK_TEST_WITH_RETURN(dev, file_priv);
1912 if (dev_priv->cp_running) {
1913 DRM_DEBUG("while CP running\n");
1916 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1917 DRM_DEBUG("called with bogus CP mode (%d)\n",
1922 radeon_do_cp_start(dev_priv);
1927 /* Stop the CP. The engine must have been idled before calling this
1930 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1932 drm_radeon_private_t *dev_priv = dev->dev_private;
1933 drm_radeon_cp_stop_t *stop = data;
1937 LOCK_TEST_WITH_RETURN(dev, file_priv);
1939 if (!dev_priv->cp_running)
1942 /* Flush any pending CP commands. This ensures any outstanding
1943 * commands are exectuted by the engine before we turn it off.
1946 radeon_do_cp_flush(dev_priv);
1949 /* If we fail to make the engine go idle, we return an error
1950 * code so that the DRM ioctl wrapper can try again.
1953 ret = radeon_do_cp_idle(dev_priv);
1958 /* Finally, we can turn off the CP. If the engine isn't idle,
1959 * we will get some dropped triangles as they won't be fully
1960 * rendered before the CP is shut down.
1962 radeon_do_cp_stop(dev_priv);
1964 /* Reset the engine */
1965 radeon_do_engine_reset(dev);
1970 void radeon_do_release(struct drm_device * dev)
1972 drm_radeon_private_t *dev_priv = dev->dev_private;
1976 if (dev_priv->cp_running) {
1978 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1979 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1983 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1984 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1986 #elif defined(__DragonFly__)
1988 tsleep_interlock(&ret);
1990 tsleep(&ret, 0, "rdnrel", 1);
1994 tsleep(&ret, PZERO, "rdnrel", 1);
1998 radeon_do_cp_stop(dev_priv);
1999 radeon_do_engine_reset(dev);
2002 /* Disable *all* interrupts */
2003 if (dev_priv->mmio) /* remove this after permanent addmaps */
2004 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
2006 if (dev_priv->mmio) { /* remove all surfaces */
2007 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2008 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
2009 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
2011 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
2016 /* Free memory heap structures */
2017 radeon_mem_takedown(&(dev_priv->gart_heap));
2018 radeon_mem_takedown(&(dev_priv->fb_heap));
2020 /* deallocate kernel resources */
2021 radeon_do_cleanup_cp(dev);
2025 /* Just reset the CP ring. Called as part of an X Server engine reset.
2027 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
2029 drm_radeon_private_t *dev_priv = dev->dev_private;
2032 LOCK_TEST_WITH_RETURN(dev, file_priv);
2035 DRM_DEBUG("called before init done\n");
2039 radeon_do_cp_reset(dev_priv);
2041 /* The CP is no longer running after an engine reset */
2042 dev_priv->cp_running = 0;
2047 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
2049 drm_radeon_private_t *dev_priv = dev->dev_private;
2052 LOCK_TEST_WITH_RETURN(dev, file_priv);
2054 return radeon_do_cp_idle(dev_priv);
2057 /* Added by Charl P. Botha to call radeon_do_resume_cp().
2059 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
2062 return radeon_do_resume_cp(dev);
2065 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
2069 LOCK_TEST_WITH_RETURN(dev, file_priv);
2071 return radeon_do_engine_reset(dev);
2074 /* ================================================================
2078 /* KW: Deprecated to say the least:
2080 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
2085 /* ================================================================
2086 * Freelist management
2089 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
2090 * bufs until freelist code is used. Note this hides a problem with
2091 * the scratch register * (used to keep track of last buffer
2092 * completed) being written to before * the last buffer has actually
2093 * completed rendering.
2095 * KW: It's also a good way to find free buffers quickly.
2097 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
2098 * sleep. However, bugs in older versions of radeon_accel.c mean that
2099 * we essentially have to do this, else old clients will break.
2101 * However, it does leave open a potential deadlock where all the
2102 * buffers are held by other clients, which can't release them because
2103 * they can't get the lock.
2106 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
2108 struct drm_device_dma *dma = dev->dma;
2109 drm_radeon_private_t *dev_priv = dev->dev_private;
2110 drm_radeon_buf_priv_t *buf_priv;
2111 struct drm_buf *buf;
2115 if (++dev_priv->last_buf >= dma->buf_count)
2116 dev_priv->last_buf = 0;
2118 start = dev_priv->last_buf;
2120 for (t = 0; t < dev_priv->usec_timeout; t++) {
2121 u32 done_age = GET_SCRATCH(1);
2122 DRM_DEBUG("done_age = %d\n", done_age);
2123 for (i = start; i < dma->buf_count; i++) {
2124 buf = dma->buflist[i];
2125 buf_priv = buf->dev_private;
2126 if (buf->file_priv == NULL || (buf->pending &&
2129 dev_priv->stats.requested_bufs++;
2138 dev_priv->stats.freelist_loops++;
2142 DRM_DEBUG("returning NULL!\n");
2147 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
2149 struct drm_device_dma *dma = dev->dma;
2150 drm_radeon_private_t *dev_priv = dev->dev_private;
2151 drm_radeon_buf_priv_t *buf_priv;
2152 struct drm_buf *buf;
2155 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
2157 if (++dev_priv->last_buf >= dma->buf_count)
2158 dev_priv->last_buf = 0;
2160 start = dev_priv->last_buf;
2161 dev_priv->stats.freelist_loops++;
2163 for (t = 0; t < 2; t++) {
2164 for (i = start; i < dma->buf_count; i++) {
2165 buf = dma->buflist[i];
2166 buf_priv = buf->dev_private;
2167 if (buf->file_priv == 0 || (buf->pending &&
2170 dev_priv->stats.requested_bufs++;
2182 void radeon_freelist_reset(struct drm_device * dev)
2184 struct drm_device_dma *dma = dev->dma;
2185 drm_radeon_private_t *dev_priv = dev->dev_private;
2188 dev_priv->last_buf = 0;
2189 for (i = 0; i < dma->buf_count; i++) {
2190 struct drm_buf *buf = dma->buflist[i];
2191 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
2196 /* ================================================================
2197 * CP command submission
2200 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
2202 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2204 u32 last_head = GET_RING_HEAD(dev_priv);
2206 for (i = 0; i < dev_priv->usec_timeout; i++) {
2207 u32 head = GET_RING_HEAD(dev_priv);
2209 ring->space = (head - ring->tail) * sizeof(u32);
2210 if (ring->space <= 0)
2211 ring->space += ring->size;
2212 if (ring->space > n)
2215 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2217 if (head != last_head)
2224 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2225 #if RADEON_FIFO_DEBUG
2226 radeon_status(dev_priv);
2227 DRM_ERROR("failed!\n");
2232 static int radeon_cp_get_buffers(struct drm_device *dev,
2233 struct drm_file *file_priv,
2237 struct drm_buf *buf;
2239 for (i = d->granted_count; i < d->request_count; i++) {
2240 buf = radeon_freelist_get(dev);
2242 return -EBUSY; /* NOTE: broken client */
2244 buf->file_priv = file_priv;
2246 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2249 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2250 sizeof(buf->total)))
2258 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2260 struct drm_device_dma *dma = dev->dma;
2262 struct drm_dma *d = data;
2264 LOCK_TEST_WITH_RETURN(dev, file_priv);
2266 /* Please don't send us buffers.
2268 if (d->send_count != 0) {
2269 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2270 DRM_CURRENTPID, d->send_count);
2274 /* We'll send you buffers.
2276 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2277 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2278 DRM_CURRENTPID, d->request_count, dma->buf_count);
2282 d->granted_count = 0;
2284 if (d->request_count) {
2285 ret = radeon_cp_get_buffers(dev, file_priv, d);
2291 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2293 drm_radeon_private_t *dev_priv;
2296 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2297 if (dev_priv == NULL)
2300 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2301 dev->dev_private = (void *)dev_priv;
2302 dev_priv->flags = flags;
2304 switch (flags & RADEON_FAMILY_MASK) {
2316 dev_priv->flags |= RADEON_HAS_HIERZ;
2319 /* all other chips have no hierarchical z buffer */
2323 if (drm_device_is_agp(dev))
2324 dev_priv->flags |= RADEON_IS_AGP;
2325 else if (drm_device_is_pcie(dev))
2326 dev_priv->flags |= RADEON_IS_PCIE;
2328 dev_priv->flags |= RADEON_IS_PCI;
2330 DRM_DEBUG("%s card detected\n",
2331 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2335 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2336 * have to find them.
2338 int radeon_driver_firstopen(struct drm_device *dev)
2341 drm_local_map_t *map;
2342 drm_radeon_private_t *dev_priv = dev->dev_private;
2344 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2346 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2347 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2348 _DRM_READ_ONLY, &dev_priv->mmio);
2352 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2353 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2354 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2355 _DRM_WRITE_COMBINING, &map);
2362 int radeon_driver_unload(struct drm_device *dev)
2364 drm_radeon_private_t *dev_priv = dev->dev_private;
2367 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2369 dev->dev_private = NULL;