2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
40 #include <sys/mplock2.h>
43 #include <vm/vm_param.h>
45 #include <vm/vm_kern.h>
46 #include <vm/vm_extern.h>
48 #include <vm/vm_map.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine_base/apic/mpapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine/intr_machdep.h> /* IPIs */
70 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define BIOS_BASE (0xf0000)
77 #define BIOS_BASE2 (0xe0000)
78 #define BIOS_SIZE (0x10000)
79 #define BIOS_COUNT (BIOS_SIZE/4)
81 #define CMOS_REG (0x70)
82 #define CMOS_DATA (0x71)
83 #define BIOS_RESET (0x0f)
84 #define BIOS_WARM (0x0a)
86 #define PROCENTRY_FLAG_EN 0x01
87 #define PROCENTRY_FLAG_BP 0x02
88 #define IOAPICENTRY_FLAG_EN 0x01
91 /* MP Floating Pointer Structure */
92 typedef struct MPFPS {
105 /* MP Configuration Table Header */
106 typedef struct MPCTH {
108 u_short base_table_length;
112 u_char product_id[12];
113 u_int32_t oem_table_pointer;
114 u_short oem_table_size;
116 u_int32_t apic_address;
117 u_short extended_table_length;
118 u_char extended_table_checksum;
123 typedef struct PROCENTRY {
128 u_int32_t cpu_signature;
129 u_int32_t feature_flags;
134 typedef struct BUSENTRY {
140 typedef struct IOAPICENTRY {
145 u_int32_t apic_address;
146 } *io_apic_entry_ptr;
148 typedef struct INTENTRY {
158 /* descriptions of MP basetable entries */
159 typedef struct BASETABLE_ENTRY {
168 vm_size_t mp_cth_mapsz;
171 #define MPTABLE_POS_USE_DEFAULT(mpt) \
172 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
174 typedef int (*mptable_iter_func)(void *, const void *, int);
177 * this code MUST be enabled here and in mpboot.s.
178 * it follows the very early stages of AP boot by placing values in CMOS ram.
179 * it NORMALLY will never be needed and thus the primitive method for enabling.
182 #if defined(CHECK_POINTS)
183 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
184 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
186 #define CHECK_INIT(D); \
187 CHECK_WRITE(0x34, (D)); \
188 CHECK_WRITE(0x35, (D)); \
189 CHECK_WRITE(0x36, (D)); \
190 CHECK_WRITE(0x37, (D)); \
191 CHECK_WRITE(0x38, (D)); \
192 CHECK_WRITE(0x39, (D));
194 #define CHECK_PRINT(S); \
195 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
204 #else /* CHECK_POINTS */
206 #define CHECK_INIT(D)
207 #define CHECK_PRINT(S)
209 #endif /* CHECK_POINTS */
212 * Values to send to the POST hardware.
214 #define MP_BOOTADDRESS_POST 0x10
215 #define MP_PROBE_POST 0x11
216 #define MPTABLE_PASS1_POST 0x12
218 #define MP_START_POST 0x13
219 #define MP_ENABLE_POST 0x14
220 #define MPTABLE_PASS2_POST 0x15
222 #define START_ALL_APS_POST 0x16
223 #define INSTALL_AP_TRAMP_POST 0x17
224 #define START_AP_POST 0x18
226 #define MP_ANNOUNCE_POST 0x19
228 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
229 int current_postcode;
231 /** XXX FIXME: what system files declare these??? */
232 extern struct region_descriptor r_gdt, r_idt;
234 int mp_naps; /* # of Applications processors */
235 #ifdef SMP /* APIC-IO */
236 static int mp_nbusses; /* # of busses */
237 int mp_napics; /* # of IO APICs */
238 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
239 u_int32_t *io_apic_versions;
243 u_int32_t cpu_apic_versions[NAPICID]; /* populated during mptable scan */
245 extern int64_t tsc_offsets[];
247 extern u_long ebda_addr;
249 #ifdef SMP /* APIC-IO */
250 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
254 * APIC ID logical/physical mapping structures.
255 * We oversize these to simplify boot-time config.
257 int cpu_num_to_apic_id[NAPICID];
258 #ifdef SMP /* APIC-IO */
259 int io_num_to_apic_id[NAPICID];
261 int apic_id_to_logical[NAPICID];
263 /* AP uses this during bootstrap. Do not staticize. */
267 struct pcb stoppcbs[MAXCPU];
269 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
271 static basetable_entry basetable_entry_types[] =
273 {0, 20, "Processor"},
281 * Local data and functions.
284 static u_int boot_address;
285 static u_int base_memory;
286 static int mp_finish;
288 static void mp_enable(u_int boot_addr);
290 static int mptable_iterate_entries(const mpcth_t,
291 mptable_iter_func, void *);
292 static int mptable_search(void);
293 static long mptable_search_sig(u_int32_t target, int count);
294 static int mptable_hyperthread_fixup(cpumask_t, int);
295 #ifdef SMP /* APIC-IO */
296 static void mptable_pass1(struct mptable_pos *);
297 static void mptable_pass2(struct mptable_pos *);
298 static void mptable_default(int type);
299 static void mptable_fix(void);
301 static int mptable_map(struct mptable_pos *);
302 static void mptable_unmap(struct mptable_pos *);
303 static void mptable_imcr(struct mptable_pos *);
305 static int mptable_lapic_probe(struct lapic_enumerator *);
306 static void mptable_lapic_enumerate(struct lapic_enumerator *);
307 static void mptable_lapic_default(void);
309 #ifdef SMP /* APIC-IO */
310 static void setup_apic_irq_mapping(void);
311 static int apic_int_is_bus_type(int intr, int bus_type);
313 static int start_all_aps(u_int boot_addr);
315 static void install_ap_tramp(u_int boot_addr);
317 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
318 static int smitest(void);
320 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
321 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
322 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
323 static u_int bootMP_size;
325 static vm_paddr_t mptable_fps_phyaddr;
326 static int mptable_use_default;
329 * Calculate usable address in base memory for AP trampoline code.
332 mp_bootaddress(u_int basemem)
334 POSTCODE(MP_BOOTADDRESS_POST);
336 base_memory = basemem;
338 bootMP_size = mptramp_end - mptramp_start;
339 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
340 if (((basemem * 1024) - boot_address) < bootMP_size)
341 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
342 /* 3 levels of page table pages */
343 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
345 return mptramp_pagetables;
352 struct mptable_pos mpt;
355 KKASSERT(mptable_fps_phyaddr == 0);
357 mptable_fps_phyaddr = mptable_search();
358 if (mptable_fps_phyaddr == 0)
361 error = mptable_map(&mpt);
363 mptable_fps_phyaddr = 0;
367 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
368 kprintf("MPTABLE: use default configuration\n");
369 mptable_use_default = 1;
374 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
377 * Look for an Intel MP spec table (ie, SMP capable hardware).
385 POSTCODE(MP_PROBE_POST);
387 /* see if EBDA exists */
388 if (ebda_addr != 0) {
389 /* search first 1K of EBDA */
390 target = (u_int32_t)ebda_addr;
391 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
394 /* last 1K of base memory, effective 'top of base' passed in */
395 target = (u_int32_t)(base_memory - 0x400);
396 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
400 /* search the BIOS */
401 target = (u_int32_t)BIOS_BASE;
402 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
405 /* search the extended BIOS */
406 target = (u_int32_t)BIOS_BASE2;
407 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
415 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
417 int count, total_size;
418 const void *position;
420 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
421 total_size = cth->base_table_length - sizeof(struct MPCTH);
422 position = (const uint8_t *)cth + sizeof(struct MPCTH);
423 count = cth->entry_count;
428 KKASSERT(total_size >= 0);
429 if (total_size == 0) {
430 kprintf("invalid base MP table, "
431 "entry count and length mismatch\n");
435 type = *(const uint8_t *)position;
437 case 0: /* processor_entry */
438 case 1: /* bus_entry */
439 case 2: /* io_apic_entry */
440 case 3: /* int_entry */
441 case 4: /* int_entry */
444 kprintf("unknown base MP table entry type %d\n", type);
448 if (total_size < basetable_entry_types[type].length) {
449 kprintf("invalid base MP table length, "
450 "does not contain all entries\n");
453 total_size -= basetable_entry_types[type].length;
455 error = func(arg, position, type);
459 position = (const uint8_t *)position +
460 basetable_entry_types[type].length;
467 * Startup the SMP processors.
472 POSTCODE(MP_START_POST);
473 mp_enable(boot_address);
478 * Print various information about the SMP system hardware and setup.
485 POSTCODE(MP_ANNOUNCE_POST);
487 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
488 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
489 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
490 for (x = 1; x <= mp_naps; ++x) {
491 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
492 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
495 if (apic_io_enable) {
496 for (x = 0; x < mp_napics; ++x) {
497 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
498 kprintf(", version: 0x%08x", io_apic_versions[x]);
499 kprintf(", at 0x%08lx\n", io_apic_address[x]);
502 kprintf(" Warning: APIC I/O disabled\n");
507 * AP cpu's call this to sync up protected mode.
509 * WARNING! %gs is not set up on entry. This routine sets up %gs.
515 int x, myid = bootAP;
517 struct mdglobaldata *md;
518 struct privatespace *ps;
520 ps = &CPU_prvspace[myid];
522 gdt_segs[GPROC0_SEL].ssd_base =
523 (long) &ps->mdglobaldata.gd_common_tss;
524 ps->mdglobaldata.mi.gd_prvspace = ps;
526 /* We fill the 32-bit segment descriptors */
527 for (x = 0; x < NGDT; x++) {
528 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
529 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
531 /* And now a 64-bit one */
532 ssdtosyssd(&gdt_segs[GPROC0_SEL],
533 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
535 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
536 r_gdt.rd_base = (long) &gdt[myid * NGDT];
537 lgdt(&r_gdt); /* does magic intra-segment return */
539 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
540 wrmsr(MSR_FSBASE, 0); /* User value */
541 wrmsr(MSR_GSBASE, (u_int64_t)ps);
542 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
548 mdcpu->gd_currentldt = _default_ldt;
551 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
552 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
554 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
556 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
558 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
560 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
561 md->gd_common_tssd = *md->gd_tss_gdt;
563 /* double fault stack */
564 md->gd_common_tss.tss_ist1 =
565 (long)&md->mi.gd_prvspace->idlestack[
566 sizeof(md->mi.gd_prvspace->idlestack)];
571 * Set to a known state:
572 * Set by mpboot.s: CR0_PG, CR0_PE
573 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
576 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
579 /* Set up the fast syscall stuff */
580 msr = rdmsr(MSR_EFER) | EFER_SCE;
581 wrmsr(MSR_EFER, msr);
582 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
583 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
584 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
585 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
586 wrmsr(MSR_STAR, msr);
587 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
589 pmap_set_opt(); /* PSE/4MB pages, etc */
591 /* Initialize the PAT MSR. */
595 /* set up CPU registers and state */
598 /* set up SSE/NX registers */
601 /* set up FPU state on the AP */
602 npxinit(__INITIAL_NPXCW__);
604 /* disable the APIC, just to be SURE */
605 lapic->svr &= ~APIC_SVR_ENABLE;
607 /* data returned to BSP */
608 cpu_apic_versions[0] = lapic->version;
611 /*******************************************************************
612 * local functions and data
616 * start the SMP system
619 mp_enable(u_int boot_addr)
623 struct mptable_pos mpt;
625 POSTCODE(MP_ENABLE_POST);
632 if (mptable_fps_phyaddr) {
637 if (apic_io_enable) {
639 if (!mptable_fps_phyaddr)
640 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
645 * Examine the MP table for needed info
652 /* Post scan cleanup */
655 setup_apic_irq_mapping();
657 /* fill the LOGICAL io_apic_versions table */
658 for (apic = 0; apic < mp_napics; ++apic) {
659 ux = ioapic_read(ioapic[apic], IOAPIC_VER);
660 io_apic_versions[apic] = ux;
661 io_apic_set_id(apic, IO_TO_ID(apic));
664 /* program each IO APIC in the system */
665 for (apic = 0; apic < mp_napics; ++apic)
666 if (io_apic_setup(apic) < 0)
667 panic("IO APIC setup failure");
672 * These are required for SMP operation
675 /* install a 'Spurious INTerrupt' vector */
676 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
677 SDT_SYSIGT, SEL_KPL, 0);
679 /* install an inter-CPU IPI for TLB invalidation */
680 setidt(XINVLTLB_OFFSET, Xinvltlb,
681 SDT_SYSIGT, SEL_KPL, 0);
683 /* install an inter-CPU IPI for IPIQ messaging */
684 setidt(XIPIQ_OFFSET, Xipiq,
685 SDT_SYSIGT, SEL_KPL, 0);
687 /* install a timer vector */
688 setidt(XTIMER_OFFSET, Xtimer,
689 SDT_SYSIGT, SEL_KPL, 0);
691 /* install an inter-CPU IPI for CPU stop/restart */
692 setidt(XCPUSTOP_OFFSET, Xcpustop,
693 SDT_SYSIGT, SEL_KPL, 0);
695 /* start each Application Processor */
696 start_all_aps(boot_addr);
701 * look for the MP spec signature
704 /* string defined by the Intel MP Spec as identifying the MP table */
705 #define MP_SIG 0x5f504d5f /* _MP_ */
706 #define NEXT(X) ((X) += 4)
708 mptable_search_sig(u_int32_t target, int count)
714 KKASSERT(target != 0);
716 map_size = count * sizeof(u_int32_t);
717 addr = pmap_mapdev((vm_paddr_t)target, map_size);
720 for (x = 0; x < count; NEXT(x)) {
721 if (addr[x] == MP_SIG) {
722 /* make array index a byte index */
723 ret = target + (x * sizeof(u_int32_t));
728 pmap_unmapdev((vm_offset_t)addr, map_size);
733 typedef struct BUSDATA {
735 enum busTypes bus_type;
738 typedef struct INTDATA {
748 typedef struct BUSTYPENAME {
753 static bus_type_name bus_type_table[] =
759 {UNKNOWN_BUSTYPE, "---"},
762 {UNKNOWN_BUSTYPE, "---"},
763 {UNKNOWN_BUSTYPE, "---"},
764 {UNKNOWN_BUSTYPE, "---"},
765 {UNKNOWN_BUSTYPE, "---"},
766 {UNKNOWN_BUSTYPE, "---"},
768 {UNKNOWN_BUSTYPE, "---"},
769 {UNKNOWN_BUSTYPE, "---"},
770 {UNKNOWN_BUSTYPE, "---"},
771 {UNKNOWN_BUSTYPE, "---"},
773 {UNKNOWN_BUSTYPE, "---"}
776 /* from MP spec v1.4, table 5-1 */
777 static int default_data[7][5] =
779 /* nbus, id0, type0, id1, type1 */
780 {1, 0, ISA, 255, 255},
781 {1, 0, EISA, 255, 255},
782 {1, 0, EISA, 255, 255},
783 {1, 0, MCA, 255, 255},
785 {2, 0, EISA, 1, PCI},
790 static bus_datum *bus_data;
792 /* the IO INT data, one entry per possible APIC INTerrupt */
793 static io_int *io_apic_ints;
796 static int processor_entry (const struct PROCENTRY *entry, int cpu);
797 static int bus_entry (const struct BUSENTRY *entry, int bus);
798 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
799 static int int_entry (const struct INTENTRY *entry, int intr);
800 static int lookup_bus_type (char *name);
803 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
805 const struct IOAPICENTRY *ioapic_ent;
808 case 1: /* bus_entry */
812 case 2: /* io_apic_entry */
814 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
815 io_apic_address[mp_napics++] =
816 (vm_offset_t)ioapic_ent->apic_address;
820 case 3: /* int_entry */
828 * 1st pass on motherboard's Intel MP specification table.
837 mptable_pass1(struct mptable_pos *mpt)
842 POSTCODE(MPTABLE_PASS1_POST);
845 KKASSERT(fps != NULL);
847 /* clear various tables */
848 for (x = 0; x < NAPICID; ++x)
849 io_apic_address[x] = ~0; /* IO APIC address table */
855 /* check for use of 'default' configuration */
856 if (fps->mpfb1 != 0) {
857 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
858 mp_nbusses = default_data[fps->mpfb1 - 1][0];
864 error = mptable_iterate_entries(mpt->mp_cth,
865 mptable_ioapic_pass1_callback, NULL);
867 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
871 struct mptable_ioapic2_cbarg {
878 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
880 struct mptable_ioapic2_cbarg *arg = xarg;
884 if (bus_entry(pos, arg->bus))
889 if (io_apic_entry(pos, arg->apic))
894 if (int_entry(pos, arg->intr))
902 * 2nd pass on motherboard's Intel MP specification table.
905 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
906 * IO_TO_ID(N), logical IO to APIC ID table
911 mptable_pass2(struct mptable_pos *mpt)
913 struct mptable_ioapic2_cbarg arg;
917 POSTCODE(MPTABLE_PASS2_POST);
920 KKASSERT(fps != NULL);
922 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
924 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
925 M_DEVBUF, M_WAITOK | M_ZERO);
926 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
928 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
931 for (x = 0; x < mp_napics; x++)
932 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
934 /* clear various tables */
935 for (x = 0; x < NAPICID; ++x) {
936 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
937 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
940 /* clear bus data table */
941 for (x = 0; x < mp_nbusses; ++x)
942 bus_data[x].bus_id = 0xff;
944 /* clear IO APIC INT table */
945 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
946 io_apic_ints[x].int_type = 0xff;
947 io_apic_ints[x].int_vector = 0xff;
950 /* check for use of 'default' configuration */
951 if (fps->mpfb1 != 0) {
952 mptable_default(fps->mpfb1);
956 bzero(&arg, sizeof(arg));
957 error = mptable_iterate_entries(mpt->mp_cth,
958 mptable_ioapic_pass2_callback, &arg);
960 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
964 * Check if we should perform a hyperthreading "fix-up" to
965 * enumerate any logical CPU's that aren't already listed
968 * XXX: We assume that all of the physical CPUs in the
969 * system have the same number of logical CPUs.
971 * XXX: We assume that APIC ID's are allocated such that
972 * the APIC ID's for a physical processor are aligned
973 * with the number of logical CPU's in the processor.
976 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
978 int i, id, lcpus_max, logical_cpus;
980 if ((cpu_feature & CPUID_HTT) == 0)
983 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
987 if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
989 * INSTRUCTION SET REFERENCE, A-M (#253666)
990 * Page 3-181, Table 3-20
991 * "The nearest power-of-2 integer that is not smaller
992 * than EBX[23:16] is the number of unique initial APIC
993 * IDs reserved for addressing different logical
994 * processors in a physical package."
997 if ((1 << i) >= lcpus_max) {
1004 KKASSERT(cpu_count != 0);
1005 if (cpu_count == lcpus_max) {
1006 /* We have nothing to fix */
1008 } else if (cpu_count == 1) {
1009 /* XXX this may be incorrect */
1010 logical_cpus = lcpus_max;
1012 int cur, prev, dist;
1015 * Calculate the distances between two nearest
1016 * APIC IDs. If all such distances are same,
1017 * then it is the number of missing cpus that
1018 * we are going to fill later.
1020 dist = cur = prev = -1;
1021 for (id = 0; id < MAXCPU; ++id) {
1022 if ((id_mask & CPUMASK(id)) == 0)
1027 int new_dist = cur - prev;
1033 * Make sure that all distances
1034 * between two nearest APIC IDs
1037 if (dist != new_dist)
1045 /* Must be power of 2 */
1046 if (dist & (dist - 1))
1049 /* Can't exceed CPU package capacity */
1050 if (dist > lcpus_max)
1051 logical_cpus = lcpus_max;
1053 logical_cpus = dist;
1057 * For each APIC ID of a CPU that is set in the mask,
1058 * scan the other candidate APIC ID's for this
1059 * physical processor. If any of those ID's are
1060 * already in the table, then kill the fixup.
1062 for (id = 0; id < MAXCPU; id++) {
1063 if ((id_mask & CPUMASK(id)) == 0)
1065 /* First, make sure we are on a logical_cpus boundary. */
1066 if (id % logical_cpus != 0)
1068 for (i = id + 1; i < id + logical_cpus; i++)
1069 if ((id_mask & CPUMASK(i)) != 0)
1072 return logical_cpus;
1076 mptable_map(struct mptable_pos *mpt)
1080 vm_size_t cth_mapsz = 0;
1082 KKASSERT(mptable_fps_phyaddr != 0);
1084 bzero(mpt, sizeof(*mpt));
1086 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
1087 if (fps->pap != 0) {
1089 * Map configuration table header to get
1090 * the base table size
1092 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1093 cth_mapsz = cth->base_table_length;
1094 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1096 if (cth_mapsz < sizeof(*cth)) {
1097 kprintf("invalid base MP table length %d\n",
1099 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1104 * Map the base table
1106 cth = pmap_mapdev(fps->pap, cth_mapsz);
1111 mpt->mp_cth_mapsz = cth_mapsz;
1117 mptable_unmap(struct mptable_pos *mpt)
1119 if (mpt->mp_cth != NULL) {
1120 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1122 mpt->mp_cth_mapsz = 0;
1124 if (mpt->mp_fps != NULL) {
1125 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1131 assign_apic_irq(int apic, int intpin, int irq)
1135 if (int_to_apicintpin[irq].ioapic != -1)
1136 panic("assign_apic_irq: inconsistent table");
1138 int_to_apicintpin[irq].ioapic = apic;
1139 int_to_apicintpin[irq].int_pin = intpin;
1140 int_to_apicintpin[irq].apic_address = ioapic[apic];
1141 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1143 for (x = 0; x < nintrs; x++) {
1144 if ((io_apic_ints[x].int_type == 0 ||
1145 io_apic_ints[x].int_type == 3) &&
1146 io_apic_ints[x].int_vector == 0xff &&
1147 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1148 io_apic_ints[x].dst_apic_int == intpin)
1149 io_apic_ints[x].int_vector = irq;
1154 revoke_apic_irq(int irq)
1160 if (int_to_apicintpin[irq].ioapic == -1)
1161 panic("revoke_apic_irq: inconsistent table");
1163 oldapic = int_to_apicintpin[irq].ioapic;
1164 oldintpin = int_to_apicintpin[irq].int_pin;
1166 int_to_apicintpin[irq].ioapic = -1;
1167 int_to_apicintpin[irq].int_pin = 0;
1168 int_to_apicintpin[irq].apic_address = NULL;
1169 int_to_apicintpin[irq].redirindex = 0;
1171 for (x = 0; x < nintrs; x++) {
1172 if ((io_apic_ints[x].int_type == 0 ||
1173 io_apic_ints[x].int_type == 3) &&
1174 io_apic_ints[x].int_vector != 0xff &&
1175 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1176 io_apic_ints[x].dst_apic_int == oldintpin)
1177 io_apic_ints[x].int_vector = 0xff;
1185 allocate_apic_irq(int intr)
1191 if (io_apic_ints[intr].int_vector != 0xff)
1192 return; /* Interrupt handler already assigned */
1194 if (io_apic_ints[intr].int_type != 0 &&
1195 (io_apic_ints[intr].int_type != 3 ||
1196 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1197 io_apic_ints[intr].dst_apic_int == 0)))
1198 return; /* Not INT or ExtInt on != (0, 0) */
1201 while (irq < APIC_INTMAPSIZE &&
1202 int_to_apicintpin[irq].ioapic != -1)
1205 if (irq >= APIC_INTMAPSIZE)
1206 return; /* No free interrupt handlers */
1208 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1209 intpin = io_apic_ints[intr].dst_apic_int;
1211 assign_apic_irq(apic, intpin, irq);
1216 swap_apic_id(int apic, int oldid, int newid)
1223 return; /* Nothing to do */
1225 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1226 apic, oldid, newid);
1228 /* Swap physical APIC IDs in interrupt entries */
1229 for (x = 0; x < nintrs; x++) {
1230 if (io_apic_ints[x].dst_apic_id == oldid)
1231 io_apic_ints[x].dst_apic_id = newid;
1232 else if (io_apic_ints[x].dst_apic_id == newid)
1233 io_apic_ints[x].dst_apic_id = oldid;
1236 /* Swap physical APIC IDs in IO_TO_ID mappings */
1237 for (oapic = 0; oapic < mp_napics; oapic++)
1238 if (IO_TO_ID(oapic) == newid)
1241 if (oapic < mp_napics) {
1242 kprintf("Changing APIC ID for IO APIC #%d from "
1243 "%d to %d in MP table\n",
1244 oapic, newid, oldid);
1245 IO_TO_ID(oapic) = oldid;
1247 IO_TO_ID(apic) = newid;
1252 fix_id_to_io_mapping(void)
1256 for (x = 0; x < NAPICID; x++)
1259 for (x = 0; x <= mp_naps; x++) {
1260 if ((u_int)CPU_TO_ID(x) < NAPICID)
1261 ID_TO_IO(CPU_TO_ID(x)) = x;
1264 for (x = 0; x < mp_napics; x++) {
1265 if ((u_int)IO_TO_ID(x) < NAPICID)
1266 ID_TO_IO(IO_TO_ID(x)) = x;
1272 first_free_apic_id(void)
1276 for (freeid = 0; freeid < NAPICID; freeid++) {
1277 for (x = 0; x <= mp_naps; x++)
1278 if (CPU_TO_ID(x) == freeid)
1282 for (x = 0; x < mp_napics; x++)
1283 if (IO_TO_ID(x) == freeid)
1294 io_apic_id_acceptable(int apic, int id)
1296 int cpu; /* Logical CPU number */
1297 int oapic; /* Logical IO APIC number for other IO APIC */
1299 if ((u_int)id >= NAPICID)
1300 return 0; /* Out of range */
1302 for (cpu = 0; cpu <= mp_naps; cpu++) {
1303 if (CPU_TO_ID(cpu) == id)
1304 return 0; /* Conflict with CPU */
1307 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++) {
1308 if (IO_TO_ID(oapic) == id)
1309 return 0; /* Conflict with other APIC */
1312 return 1; /* ID is acceptable for IO APIC */
1317 io_apic_find_int_entry(int apic, int pin)
1321 /* search each of the possible INTerrupt sources */
1322 for (x = 0; x < nintrs; ++x) {
1323 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1324 (pin == io_apic_ints[x].dst_apic_int))
1325 return (&io_apic_ints[x]);
1331 * parse an Intel MP specification table
1338 int apic; /* IO APIC unit number */
1339 int freeid; /* Free physical APIC ID */
1340 int physid; /* Current physical IO APIC ID */
1342 int bus_0 = 0; /* Stop GCC warning */
1343 int bus_pci = 0; /* Stop GCC warning */
1347 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1348 * did it wrong. The MP spec says that when more than 1 PCI bus
1349 * exists the BIOS must begin with bus entries for the PCI bus and use
1350 * actual PCI bus numbering. This implies that when only 1 PCI bus
1351 * exists the BIOS can choose to ignore this ordering, and indeed many
1352 * MP motherboards do ignore it. This causes a problem when the PCI
1353 * sub-system makes requests of the MP sub-system based on PCI bus
1354 * numbers. So here we look for the situation and renumber the
1355 * busses and associated INTs in an effort to "make it right".
1358 /* find bus 0, PCI bus, count the number of PCI busses */
1359 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1360 if (bus_data[x].bus_id == 0) {
1363 if (bus_data[x].bus_type == PCI) {
1369 * bus_0 == slot of bus with ID of 0
1370 * bus_pci == slot of last PCI bus encountered
1373 /* check the 1 PCI bus case for sanity */
1374 /* if it is number 0 all is well */
1375 if (num_pci_bus == 1 &&
1376 bus_data[bus_pci].bus_id != 0) {
1378 /* mis-numbered, swap with whichever bus uses slot 0 */
1380 /* swap the bus entry types */
1381 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1382 bus_data[bus_0].bus_type = PCI;
1384 /* swap each relevant INTerrupt entry */
1385 id = bus_data[bus_pci].bus_id;
1386 for (x = 0; x < nintrs; ++x) {
1387 if (io_apic_ints[x].src_bus_id == id) {
1388 io_apic_ints[x].src_bus_id = 0;
1390 else if (io_apic_ints[x].src_bus_id == 0) {
1391 io_apic_ints[x].src_bus_id = id;
1396 /* Assign IO APIC IDs.
1398 * First try the existing ID. If a conflict is detected, try
1399 * the ID in the MP table. If a conflict is still detected, find
1402 * We cannot use the ID_TO_IO table before all conflicts has been
1403 * resolved and the table has been corrected.
1405 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1407 /* First try to use the value set by the BIOS */
1408 physid = io_apic_get_id(apic);
1409 if (io_apic_id_acceptable(apic, physid)) {
1410 if (IO_TO_ID(apic) != physid)
1411 swap_apic_id(apic, IO_TO_ID(apic), physid);
1415 /* Then check if the value in the MP table is acceptable */
1416 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1419 /* Last resort, find a free APIC ID and use it */
1420 freeid = first_free_apic_id();
1421 if (freeid >= NAPICID)
1422 panic("No free physical APIC IDs found");
1424 if (io_apic_id_acceptable(apic, freeid)) {
1425 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1428 panic("Free physical APIC ID not usable");
1430 fix_id_to_io_mapping();
1432 /* detect and fix broken Compaq MP table */
1433 if (apic_int_type(0, 0) == -1) {
1434 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1435 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1436 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1437 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1438 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1439 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1441 } else if (apic_int_type(0, 0) == 0) {
1442 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1443 for (x = 0; x < nintrs; ++x)
1444 if ((ID_TO_IO(io_apic_ints[x].dst_apic_id) == 0) &&
1445 (io_apic_ints[x].dst_apic_int) == 0) {
1446 io_apic_ints[x].int_type = 3;
1447 io_apic_ints[x].int_vector = 0xff;
1453 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1454 * controllers universally come in pairs. If IRQ 14 is specified
1455 * as an ISA interrupt, then IRQ 15 had better be too.
1457 * [ Shuttle XPC / AMD Athlon X2 ]
1458 * The MPTable is missing an entry for IRQ 15. Note that the
1459 * ACPI table has an entry for both 14 and 15.
1461 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1462 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1463 io14 = io_apic_find_int_entry(0, 14);
1464 io_apic_ints[nintrs] = *io14;
1465 io_apic_ints[nintrs].src_bus_irq = 15;
1466 io_apic_ints[nintrs].dst_apic_int = 15;
1471 /* Assign low level interrupt handlers */
1473 setup_apic_irq_mapping(void)
1479 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1480 int_to_apicintpin[x].ioapic = -1;
1481 int_to_apicintpin[x].int_pin = 0;
1482 int_to_apicintpin[x].apic_address = NULL;
1483 int_to_apicintpin[x].redirindex = 0;
1485 /* Default to masked */
1486 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1489 /* First assign ISA/EISA interrupts */
1490 for (x = 0; x < nintrs; x++) {
1491 int_vector = io_apic_ints[x].src_bus_irq;
1492 if (int_vector < APIC_INTMAPSIZE &&
1493 io_apic_ints[x].int_vector == 0xff &&
1494 int_to_apicintpin[int_vector].ioapic == -1 &&
1495 (apic_int_is_bus_type(x, ISA) ||
1496 apic_int_is_bus_type(x, EISA)) &&
1497 io_apic_ints[x].int_type == 0) {
1498 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1499 io_apic_ints[x].dst_apic_int,
1504 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1505 for (x = 0; x < nintrs; x++) {
1506 if (io_apic_ints[x].dst_apic_int == 0 &&
1507 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1508 io_apic_ints[x].int_vector == 0xff &&
1509 int_to_apicintpin[0].ioapic == -1 &&
1510 io_apic_ints[x].int_type == 3) {
1511 assign_apic_irq(0, 0, 0);
1516 /* Assign PCI interrupts */
1517 for (x = 0; x < nintrs; ++x) {
1518 if (io_apic_ints[x].int_type == 0 &&
1519 io_apic_ints[x].int_vector == 0xff &&
1520 apic_int_is_bus_type(x, PCI))
1521 allocate_apic_irq(x);
1526 mp_set_cpuids(int cpu_id, int apic_id)
1528 CPU_TO_ID(cpu_id) = apic_id;
1529 ID_TO_CPU(apic_id) = cpu_id;
1533 processor_entry(const struct PROCENTRY *entry, int cpu)
1537 /* check for usability */
1538 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1541 /* check for BSP flag */
1542 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1543 mp_set_cpuids(0, entry->apic_id);
1544 return 0; /* its already been counted */
1547 /* add another AP to list, if less than max number of CPUs */
1548 else if (cpu < MAXCPU) {
1549 mp_set_cpuids(cpu, entry->apic_id);
1557 bus_entry(const struct BUSENTRY *entry, int bus)
1562 /* encode the name into an index */
1563 for (x = 0; x < 6; ++x) {
1564 if ((c = entry->bus_type[x]) == ' ')
1570 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1571 panic("unknown bus type: '%s'", name);
1573 bus_data[bus].bus_id = entry->bus_id;
1574 bus_data[bus].bus_type = x;
1580 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1582 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1585 IO_TO_ID(apic) = entry->apic_id;
1586 ID_TO_IO(entry->apic_id) = apic;
1592 lookup_bus_type(char *name)
1596 for (x = 0; x < MAX_BUSTYPE; ++x)
1597 if (strcmp(bus_type_table[x].name, name) == 0)
1598 return bus_type_table[x].type;
1600 return UNKNOWN_BUSTYPE;
1604 int_entry(const struct INTENTRY *entry, int intr)
1608 io_apic_ints[intr].int_type = entry->int_type;
1609 io_apic_ints[intr].int_flags = entry->int_flags;
1610 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1611 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1612 if (entry->dst_apic_id == 255) {
1613 /* This signal goes to all IO APICS. Select an IO APIC
1614 with sufficient number of interrupt pins */
1615 for (apic = 0; apic < mp_napics; apic++)
1616 if (((ioapic_read(ioapic[apic], IOAPIC_VER) &
1617 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1618 entry->dst_apic_int)
1620 if (apic < mp_napics)
1621 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1623 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1625 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1626 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1632 apic_int_is_bus_type(int intr, int bus_type)
1636 for (bus = 0; bus < mp_nbusses; ++bus)
1637 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1638 && ((int) bus_data[bus].bus_type == bus_type))
1645 * Given a traditional ISA INT mask, return an APIC mask.
1648 isa_apic_mask(u_int isa_mask)
1653 #if defined(SKIP_IRQ15_REDIRECT)
1654 if (isa_mask == (1 << 15)) {
1655 kprintf("skipping ISA IRQ15 redirect\n");
1658 #endif /* SKIP_IRQ15_REDIRECT */
1660 isa_irq = ffs(isa_mask); /* find its bit position */
1661 if (isa_irq == 0) /* doesn't exist */
1663 --isa_irq; /* make it zero based */
1665 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1669 return (1 << apic_pin); /* convert pin# to a mask */
1673 * Determine which APIC pin an ISA/EISA INT is attached to.
1675 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1676 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1677 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1678 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1680 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1682 isa_apic_irq(int isa_irq)
1686 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1687 if (INTTYPE(intr) == 0) { /* standard INT */
1688 if (SRCBUSIRQ(intr) == isa_irq) {
1689 if (apic_int_is_bus_type(intr, ISA) ||
1690 apic_int_is_bus_type(intr, EISA)) {
1691 if (INTIRQ(intr) == 0xff)
1692 return -1; /* unassigned */
1693 return INTIRQ(intr); /* found */
1698 return -1; /* NOT found */
1703 * Determine which APIC pin a PCI INT is attached to.
1705 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1706 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1707 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1709 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1713 --pciInt; /* zero based */
1715 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1716 if ((INTTYPE(intr) == 0) /* standard INT */
1717 && (SRCBUSID(intr) == pciBus)
1718 && (SRCBUSDEVICE(intr) == pciDevice)
1719 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1720 if (apic_int_is_bus_type(intr, PCI)) {
1721 if (INTIRQ(intr) == 0xff) {
1722 kprintf("IOAPIC: pci_apic_irq() "
1724 return -1; /* unassigned */
1726 return INTIRQ(intr); /* exact match */
1731 return -1; /* NOT found */
1735 next_apic_irq(int irq)
1742 for (intr = 0; intr < nintrs; intr++) {
1743 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1745 bus = SRCBUSID(intr);
1746 bustype = apic_bus_type(bus);
1747 if (bustype != ISA &&
1753 if (intr >= nintrs) {
1756 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1757 if (INTTYPE(ointr) != 0)
1759 if (bus != SRCBUSID(ointr))
1761 if (bustype == PCI) {
1762 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1764 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1767 if (bustype == ISA || bustype == EISA) {
1768 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1771 if (INTPIN(intr) == INTPIN(ointr))
1775 if (ointr >= nintrs) {
1778 return INTIRQ(ointr);
1791 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1794 * Exactly what this means is unclear at this point. It is a solution
1795 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1796 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1797 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1801 undirect_isa_irq(int rirq)
1805 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1806 /** FIXME: tickle the MB redirector chip */
1810 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1817 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1820 undirect_pci_irq(int rirq)
1824 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1826 /** FIXME: tickle the MB redirector chip */
1830 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1838 * given a bus ID, return:
1839 * the bus type if found
1843 apic_bus_type(int id)
1847 for (x = 0; x < mp_nbusses; ++x)
1848 if (bus_data[x].bus_id == id)
1849 return bus_data[x].bus_type;
1855 * given a LOGICAL APIC# and pin#, return:
1856 * the associated src bus ID if found
1860 apic_src_bus_id(int apic, int pin)
1864 /* search each of the possible INTerrupt sources */
1865 for (x = 0; x < nintrs; ++x)
1866 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1867 (pin == io_apic_ints[x].dst_apic_int))
1868 return (io_apic_ints[x].src_bus_id);
1870 return -1; /* NOT found */
1874 * given a LOGICAL APIC# and pin#, return:
1875 * the associated src bus IRQ if found
1879 apic_src_bus_irq(int apic, int pin)
1883 for (x = 0; x < nintrs; x++)
1884 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1885 (pin == io_apic_ints[x].dst_apic_int))
1886 return (io_apic_ints[x].src_bus_irq);
1888 return -1; /* NOT found */
1893 * given a LOGICAL APIC# and pin#, return:
1894 * the associated INTerrupt type if found
1898 apic_int_type(int apic, int pin)
1902 /* search each of the possible INTerrupt sources */
1903 for (x = 0; x < nintrs; ++x) {
1904 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1905 (pin == io_apic_ints[x].dst_apic_int))
1906 return (io_apic_ints[x].int_type);
1908 return -1; /* NOT found */
1912 * Return the IRQ associated with an APIC pin
1915 apic_irq(int apic, int pin)
1920 for (x = 0; x < nintrs; ++x) {
1921 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1922 (pin == io_apic_ints[x].dst_apic_int)) {
1923 res = io_apic_ints[x].int_vector;
1926 if (apic != int_to_apicintpin[res].ioapic)
1927 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1928 if (pin != int_to_apicintpin[res].int_pin)
1929 panic("apic_irq inconsistent table (2)");
1938 * given a LOGICAL APIC# and pin#, return:
1939 * the associated trigger mode if found
1943 apic_trigger(int apic, int pin)
1947 /* search each of the possible INTerrupt sources */
1948 for (x = 0; x < nintrs; ++x)
1949 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1950 (pin == io_apic_ints[x].dst_apic_int))
1951 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1953 return -1; /* NOT found */
1958 * given a LOGICAL APIC# and pin#, return:
1959 * the associated 'active' level if found
1963 apic_polarity(int apic, int pin)
1967 /* search each of the possible INTerrupt sources */
1968 for (x = 0; x < nintrs; ++x)
1969 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1970 (pin == io_apic_ints[x].dst_apic_int))
1971 return (io_apic_ints[x].int_flags & 0x03);
1973 return -1; /* NOT found */
1977 * set data according to MP defaults
1978 * FIXME: probably not complete yet...
1981 mptable_default(int type)
1987 kprintf(" MP default config type: %d\n", type);
1990 kprintf(" bus: ISA, APIC: 82489DX\n");
1993 kprintf(" bus: EISA, APIC: 82489DX\n");
1996 kprintf(" bus: EISA, APIC: 82489DX\n");
1999 kprintf(" bus: MCA, APIC: 82489DX\n");
2002 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2005 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2008 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2011 kprintf(" future type\n");
2017 /* one and only IO APIC */
2018 io_apic_id = (ioapic_read(ioapic[0], IOAPIC_ID) & APIC_ID_MASK) >> 24;
2021 * sanity check, refer to MP spec section 3.6.6, last paragraph
2022 * necessary as some hardware isn't properly setting up the IO APIC
2024 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2025 if (io_apic_id != 2) {
2027 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2028 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2029 io_apic_set_id(0, 2);
2032 IO_TO_ID(0) = io_apic_id;
2033 ID_TO_IO(io_apic_id) = 0;
2035 /* fill out bus entries */
2044 bus_data[0].bus_id = default_data[type - 1][1];
2045 bus_data[0].bus_type = default_data[type - 1][2];
2046 bus_data[1].bus_id = default_data[type - 1][3];
2047 bus_data[1].bus_type = default_data[type - 1][4];
2050 /* case 4: case 7: MCA NOT supported */
2051 default: /* illegal/reserved */
2052 panic("BAD default MP config: %d", type);
2056 /* general cases from MP v1.4, table 5-2 */
2057 for (pin = 0; pin < 16; ++pin) {
2058 io_apic_ints[pin].int_type = 0;
2059 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2060 io_apic_ints[pin].src_bus_id = 0;
2061 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2062 io_apic_ints[pin].dst_apic_id = io_apic_id;
2063 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2066 /* special cases from MP v1.4, table 5-2 */
2068 io_apic_ints[2].int_type = 0xff; /* N/C */
2069 io_apic_ints[13].int_type = 0xff; /* N/C */
2070 #if !defined(APIC_MIXED_MODE)
2072 panic("sorry, can't support type 2 default yet");
2073 #endif /* APIC_MIXED_MODE */
2076 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2079 io_apic_ints[0].int_type = 0xff; /* N/C */
2081 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2085 * Map a physical memory address representing I/O into KVA. The I/O
2086 * block is assumed not to cross a page boundary.
2089 permanent_io_mapping(vm_paddr_t pa)
2091 KKASSERT(pa < 0x100000000LL);
2093 return pmap_mapdev_uncacheable(pa, PAGE_SIZE);
2097 * start each AP in our list
2100 start_all_aps(u_int boot_addr)
2102 vm_offset_t va = boot_address + KERNBASE;
2103 u_int64_t *pt4, *pt3, *pt2;
2109 u_char mpbiosreason;
2110 u_long mpbioswarmvec;
2111 struct mdglobaldata *gd;
2112 struct privatespace *ps;
2114 POSTCODE(START_ALL_APS_POST);
2116 /* Initialize BSP's local APIC */
2117 apic_initialize(TRUE);
2120 MachIntrABI.finalize();
2122 /* install the AP 1st level boot code */
2123 pmap_kenter(va, boot_address);
2124 cpu_invlpg((void *)va); /* JG XXX */
2125 bcopy(mptramp_start, (void *)va, bootMP_size);
2127 /* Locate the page tables, they'll be below the trampoline */
2128 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
2129 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
2130 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
2132 /* Create the initial 1GB replicated page tables */
2133 for (i = 0; i < 512; i++) {
2134 /* Each slot of the level 4 pages points to the same level 3 page */
2135 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
2136 pt4[i] |= PG_V | PG_RW | PG_U;
2138 /* Each slot of the level 3 pages points to the same level 2 page */
2139 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
2140 pt3[i] |= PG_V | PG_RW | PG_U;
2142 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
2143 pt2[i] = i * (2 * 1024 * 1024);
2144 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
2147 /* save the current value of the warm-start vector */
2148 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
2149 outb(CMOS_REG, BIOS_RESET);
2150 mpbiosreason = inb(CMOS_DATA);
2152 /* setup a vector to our boot code */
2153 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2154 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
2155 outb(CMOS_REG, BIOS_RESET);
2156 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2159 * If we have a TSC we can figure out the SMI interrupt rate.
2160 * The SMI does not necessarily use a constant rate. Spend
2161 * up to 250ms trying to figure it out.
2164 if (cpu_feature & CPUID_TSC) {
2165 set_apic_timer(275000);
2166 smilast = read_apic_timer();
2167 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2168 smicount = smitest();
2169 if (smibest == 0 || smilast - smicount < smibest)
2170 smibest = smilast - smicount;
2173 if (smibest > 250000)
2176 smibest = smibest * (int64_t)1000000 /
2177 get_apic_timer_frequency();
2181 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2182 1000000 / smibest, smibest);
2184 kprintf("SMP: Starting %d APs: ", mp_naps);
2186 for (x = 1; x <= mp_naps; ++x) {
2188 /* This is a bit verbose, it will go away soon. */
2190 /* first page of AP's private space */
2191 pg = x * x86_64_btop(sizeof(struct privatespace));
2193 /* allocate new private data page(s) */
2194 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2195 MDGLOBALDATA_BASEALLOC_SIZE);
2197 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2198 bzero(gd, sizeof(*gd));
2199 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2201 /* prime data page for it to use */
2202 mi_gdinit(&gd->mi, x);
2204 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2205 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2207 /* setup a vector to our boot code */
2208 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2209 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2210 outb(CMOS_REG, BIOS_RESET);
2211 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2214 * Setup the AP boot stack
2216 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2219 /* attempt to start the Application Processor */
2220 CHECK_INIT(99); /* setup checkpoints */
2221 if (!start_ap(gd, boot_addr, smibest)) {
2222 kprintf("\nAP #%d (PHY# %d) failed!\n",
2224 CHECK_PRINT("trace"); /* show checkpoints */
2225 /* better panic as the AP may be running loose */
2226 kprintf("panic y/n? [y] ");
2227 if (cngetc() != 'n')
2230 CHECK_PRINT("trace"); /* show checkpoints */
2232 /* record its version info */
2233 cpu_apic_versions[x] = cpu_apic_versions[0];
2236 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2239 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2240 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2243 ncpus2_shift = shift;
2244 ncpus2 = 1 << shift;
2245 ncpus2_mask = ncpus2 - 1;
2247 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2248 if ((1 << shift) < ncpus)
2250 ncpus_fit = 1 << shift;
2251 ncpus_fit_mask = ncpus_fit - 1;
2253 /* build our map of 'other' CPUs */
2254 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2255 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2256 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2258 /* fill in our (BSP) APIC version */
2259 cpu_apic_versions[0] = lapic->version;
2261 /* restore the warmstart vector */
2262 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2263 outb(CMOS_REG, BIOS_RESET);
2264 outb(CMOS_DATA, mpbiosreason);
2267 * NOTE! The idlestack for the BSP was setup by locore. Finish
2268 * up, clean out the P==V mapping we did earlier.
2272 /* number of APs actually started */
2278 * load the 1st level AP boot code into base memory.
2281 /* targets for relocation */
2282 extern void bigJump(void);
2283 extern void bootCodeSeg(void);
2284 extern void bootDataSeg(void);
2285 extern void MPentry(void);
2286 extern u_int MP_GDT;
2287 extern u_int mp_gdtbase;
2292 install_ap_tramp(u_int boot_addr)
2295 int size = *(int *) ((u_long) & bootMP_size);
2296 u_char *src = (u_char *) ((u_long) bootMP);
2297 u_char *dst = (u_char *) boot_addr + KERNBASE;
2298 u_int boot_base = (u_int) bootMP;
2303 POSTCODE(INSTALL_AP_TRAMP_POST);
2305 for (x = 0; x < size; ++x)
2309 * modify addresses in code we just moved to basemem. unfortunately we
2310 * need fairly detailed info about mpboot.s for this to work. changes
2311 * to mpboot.s might require changes here.
2314 /* boot code is located in KERNEL space */
2315 dst = (u_char *) boot_addr + KERNBASE;
2317 /* modify the lgdt arg */
2318 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2319 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2321 /* modify the ljmp target for MPentry() */
2322 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2323 *dst32 = ((u_int) MPentry - KERNBASE);
2325 /* modify the target for boot code segment */
2326 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2327 dst8 = (u_int8_t *) (dst16 + 1);
2328 *dst16 = (u_int) boot_addr & 0xffff;
2329 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2331 /* modify the target for boot data segment */
2332 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2333 dst8 = (u_int8_t *) (dst16 + 1);
2334 *dst16 = (u_int) boot_addr & 0xffff;
2335 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2341 * This function starts the AP (application processor) identified
2342 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2343 * to accomplish this. This is necessary because of the nuances
2344 * of the different hardware we might encounter. It ain't pretty,
2345 * but it seems to work.
2347 * NOTE: eventually an AP gets to ap_init(), which is called just
2348 * before the AP goes into the LWKT scheduler's idle loop.
2351 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2355 u_long icr_lo, icr_hi;
2357 POSTCODE(START_AP_POST);
2359 /* get the PHYSICAL APIC ID# */
2360 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2362 /* calculate the vector */
2363 vector = (boot_addr >> 12) & 0xff;
2365 /* We don't want anything interfering */
2368 /* Make sure the target cpu sees everything */
2372 * Try to detect when a SMI has occurred, wait up to 200ms.
2374 * If a SMI occurs during an AP reset but before we issue
2375 * the STARTUP command, the AP may brick. To work around
2376 * this problem we hold off doing the AP startup until
2377 * after we have detected the SMI. Hopefully another SMI
2378 * will not occur before we finish the AP startup.
2380 * Retries don't seem to help. SMIs have a window of opportunity
2381 * and if USB->legacy keyboard emulation is enabled in the BIOS
2382 * the interrupt rate can be quite high.
2384 * NOTE: Don't worry about the L1 cache load, it might bloat
2385 * ldelta a little but ndelta will be so huge when the SMI
2386 * occurs the detection logic will still work fine.
2389 set_apic_timer(200000);
2394 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2395 * and running the target CPU. OR this INIT IPI might be latched (P5
2396 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2399 * see apic/apicreg.h for icr bit definitions.
2401 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2405 * Setup the address for the target AP. We can setup
2406 * icr_hi once and then just trigger operations with
2409 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
2410 icr_hi |= (physical_cpu << 24);
2411 icr_lo = lapic->icr_lo & 0xfff00000;
2412 lapic->icr_hi = icr_hi;
2415 * Do an INIT IPI: assert RESET
2417 * Use edge triggered mode to assert INIT
2419 lapic->icr_lo = icr_lo | 0x00004500;
2420 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2424 * The spec calls for a 10ms delay but we may have to use a
2425 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2426 * interrupt. We have other loops here too and dividing by 2
2427 * doesn't seem to be enough even after subtracting 350us,
2428 * so we divide by 4.
2430 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2431 * interrupt was detected we use the full 10ms.
2435 else if (smibest < 150 * 4 + 350)
2437 else if ((smibest - 350) / 4 < 10000)
2438 u_sleep((smibest - 350) / 4);
2443 * Do an INIT IPI: deassert RESET
2445 * Use level triggered mode to deassert. It is unclear
2446 * why we need to do this.
2448 lapic->icr_lo = icr_lo | 0x00008500;
2449 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2451 u_sleep(150); /* wait 150us */
2454 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2455 * latched, (P5 bug) this 1st STARTUP would then terminate
2456 * immediately, and the previously started INIT IPI would continue. OR
2457 * the previous INIT IPI has already run. and this STARTUP IPI will
2458 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2461 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2462 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2464 u_sleep(200); /* wait ~200uS */
2467 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2468 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2469 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2470 * recognized after hardware RESET or INIT IPI.
2472 lapic->icr_lo = icr_lo | 0x00000600 | vector;
2473 while (lapic->icr_lo & APIC_DELSTAT_MASK)
2476 /* Resume normal operation */
2479 /* wait for it to start, see ap_init() */
2480 set_apic_timer(5000000);/* == 5 seconds */
2481 while (read_apic_timer()) {
2482 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2483 return 1; /* return SUCCESS */
2486 return 0; /* return FAILURE */
2501 while (read_apic_timer()) {
2503 for (count = 0; count < 100; ++count)
2504 ntsc = rdtsc(); /* force loop to occur */
2506 ndelta = ntsc - ltsc;
2507 if (ldelta > ndelta)
2509 if (ndelta > ldelta * 2)
2512 ldelta = ntsc - ltsc;
2515 return(read_apic_timer());
2519 * Synchronously flush the TLB on all other CPU's. The current cpu's
2520 * TLB is not flushed. If the caller wishes to flush the current cpu's
2521 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
2523 * NOTE: If for some reason we were unable to start all cpus we cannot
2524 * safely use broadcast IPIs.
2527 static cpumask_t smp_invltlb_req;
2529 #define SMP_INVLTLB_DEBUG
2535 struct mdglobaldata *md = mdcpu;
2536 #ifdef SMP_INVLTLB_DEBUG
2541 crit_enter_gd(&md->mi);
2542 md->gd_invltlb_ret = 0;
2543 ++md->mi.gd_cnt.v_smpinvltlb;
2544 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2545 #ifdef SMP_INVLTLB_DEBUG
2548 if (smp_startup_mask == smp_active_mask) {
2549 all_but_self_ipi(XINVLTLB_OFFSET);
2551 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2552 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2555 #ifdef SMP_INVLTLB_DEBUG
2557 kprintf("smp_invltlb: ipi sent\n");
2559 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2560 (smp_active_mask & ~md->mi.gd_cpumask)) {
2563 #ifdef SMP_INVLTLB_DEBUG
2565 if (++count == 400000000) {
2566 print_backtrace(-1);
2567 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2568 "rflags %016jx retry",
2569 (long)md->gd_invltlb_ret,
2570 (long)smp_invltlb_req,
2571 (intmax_t)read_rflags());
2572 __asm __volatile ("sti");
2575 lwkt_process_ipiq();
2577 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2578 ~md->mi.gd_cpumask &
2582 kprintf("bcpu %d\n", bcpu);
2583 xgd = globaldata_find(bcpu);
2584 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2587 Debugger("giving up");
2593 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2594 crit_exit_gd(&md->mi);
2601 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2602 * bother to bump the critical section count or nested interrupt count
2603 * so only do very low level operations here.
2606 smp_invltlb_intr(void)
2608 struct mdglobaldata *md = mdcpu;
2609 struct mdglobaldata *omd;
2614 mask = smp_invltlb_req;
2617 cpu = BSFCPUMASK(mask);
2618 mask &= ~CPUMASK(cpu);
2619 omd = (struct mdglobaldata *)globaldata_find(cpu);
2620 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2627 * When called the executing CPU will send an IPI to all other CPUs
2628 * requesting that they halt execution.
2630 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2632 * - Signals all CPUs in map to stop.
2633 * - Waits for each to stop.
2640 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2641 * from executing at same time.
2644 stop_cpus(cpumask_t map)
2646 map &= smp_active_mask;
2648 /* send the Xcpustop IPI to all CPUs in map */
2649 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2651 while ((stopped_cpus & map) != map)
2659 * Called by a CPU to restart stopped CPUs.
2661 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2663 * - Signals all CPUs in map to restart.
2664 * - Waits for each to restart.
2672 restart_cpus(cpumask_t map)
2674 /* signal other cpus to restart */
2675 started_cpus = map & smp_active_mask;
2677 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2684 * This is called once the mpboot code has gotten us properly relocated
2685 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2686 * and when it returns the scheduler will call the real cpu_idle() main
2687 * loop for the idlethread. Interrupts are disabled on entry and should
2688 * remain disabled at return.
2696 * Adjust smp_startup_mask to signal the BSP that we have started
2697 * up successfully. Note that we do not yet hold the BGL. The BSP
2698 * is waiting for our signal.
2700 * We can't set our bit in smp_active_mask yet because we are holding
2701 * interrupts physically disabled and remote cpus could deadlock
2702 * trying to send us an IPI.
2704 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2708 * Interlock for finalization. Wait until mp_finish is non-zero,
2709 * then get the MP lock.
2711 * Note: We are in a critical section.
2713 * Note: we are the idle thread, we can only spin.
2715 * Note: The load fence is memory volatile and prevents the compiler
2716 * from improperly caching mp_finish, and the cpu from improperly
2719 while (mp_finish == 0)
2721 while (try_mplock() == 0)
2724 if (cpu_feature & CPUID_TSC) {
2726 * The BSP is constantly updating tsc0_offset, figure out
2727 * the relative difference to synchronize ktrdump.
2729 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2732 /* BSP may have changed PTD while we're waiting for the lock */
2735 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2739 /* Build our map of 'other' CPUs. */
2740 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2742 kprintf(" %d", mycpu->gd_cpuid);
2744 /* A quick check from sanity claus */
2745 apic_id = (apic_id_to_logical[(lapic->id & 0xff000000) >> 24]);
2746 if (mycpu->gd_cpuid != apic_id) {
2747 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2748 kprintf("SMP: apic_id = %d lapicid %d\n",
2749 apic_id, (lapic->id & 0xff000000) >> 24);
2751 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2753 panic("cpuid mismatch! boom!!");
2756 /* Initialize AP's local APIC for irq's */
2757 apic_initialize(FALSE);
2759 /* Set memory range attributes for this CPU to match the BSP */
2760 mem_range_AP_init();
2763 * Once we go active we must process any IPIQ messages that may
2764 * have been queued, because no actual IPI will occur until we
2765 * set our bit in the smp_active_mask. If we don't the IPI
2766 * message interlock could be left set which would also prevent
2769 * The idle loop doesn't expect the BGL to be held and while
2770 * lwkt_switch() normally cleans things up this is a special case
2771 * because we returning almost directly into the idle loop.
2773 * The idle thread is never placed on the runq, make sure
2774 * nothing we've done put it there.
2776 KKASSERT(get_mplock_count(curthread) == 1);
2777 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2780 * Enable interrupts here. idle_restore will also do it, but
2781 * doing it here lets us clean up any strays that got posted to
2782 * the CPU during the AP boot while we are still in a critical
2785 __asm __volatile("sti; pause; pause"::);
2786 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2788 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2789 lwkt_process_ipiq();
2792 * Releasing the mp lock lets the BSP finish up the SMP init
2795 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2799 * Get SMP fully working before we start initializing devices.
2807 kprintf("Finish MP startup\n");
2808 if (cpu_feature & CPUID_TSC)
2809 tsc0_offset = rdtsc();
2812 while (smp_active_mask != smp_startup_mask) {
2814 if (cpu_feature & CPUID_TSC)
2815 tsc0_offset = rdtsc();
2817 while (try_mplock() == 0)
2821 kprintf("Active CPU Mask: %016jx\n",
2822 (uintmax_t)smp_active_mask);
2826 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2829 cpu_send_ipiq(int dcpu)
2831 if (CPUMASK(dcpu) & smp_active_mask)
2832 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2835 #if 0 /* single_apic_ipi_passive() not working yet */
2837 * Returns 0 on failure, 1 on success
2840 cpu_send_ipiq_passive(int dcpu)
2843 if (CPUMASK(dcpu) & smp_active_mask) {
2844 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2845 APIC_DELMODE_FIXED);
2851 struct mptable_lapic_cbarg1 {
2854 u_int ht_apicid_mask;
2858 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2860 const struct PROCENTRY *ent;
2861 struct mptable_lapic_cbarg1 *arg = xarg;
2867 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2871 if (ent->apic_id < 32) {
2872 arg->ht_apicid_mask |= 1 << ent->apic_id;
2873 } else if (arg->ht_fixup) {
2874 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2880 struct mptable_lapic_cbarg2 {
2887 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2889 const struct PROCENTRY *ent;
2890 struct mptable_lapic_cbarg2 *arg = xarg;
2896 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2897 KKASSERT(!arg->found_bsp);
2901 if (processor_entry(ent, arg->cpu))
2904 if (arg->logical_cpus) {
2905 struct PROCENTRY proc;
2909 * Create fake mptable processor entries
2910 * and feed them to processor_entry() to
2911 * enumerate the logical CPUs.
2913 bzero(&proc, sizeof(proc));
2915 proc.cpu_flags = PROCENTRY_FLAG_EN;
2916 proc.apic_id = ent->apic_id;
2918 for (i = 1; i < arg->logical_cpus; i++) {
2920 processor_entry(&proc, arg->cpu);
2928 mptable_imcr(struct mptable_pos *mpt)
2930 /* record whether PIC or virtual-wire mode */
2931 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2932 mpt->mp_fps->mpfb2 & 0x80);
2936 mptable_lapic_default(void)
2938 int ap_apicid, bsp_apicid;
2940 mp_naps = 1; /* exclude BSP */
2942 /* Map local apic before the id field is accessed */
2943 lapic_map(DEFAULT_APIC_BASE);
2945 bsp_apicid = APIC_ID(lapic->id);
2946 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2949 mp_set_cpuids(0, bsp_apicid);
2950 /* one and only AP */
2951 mp_set_cpuids(1, ap_apicid);
2957 * ID_TO_CPU(N), APIC ID to logical CPU table
2958 * CPU_TO_ID(N), logical CPU to APIC ID table
2961 mptable_lapic_enumerate(struct lapic_enumerator *e)
2963 struct mptable_pos mpt;
2964 struct mptable_lapic_cbarg1 arg1;
2965 struct mptable_lapic_cbarg2 arg2;
2967 int error, logical_cpus = 0;
2968 vm_offset_t lapic_addr;
2970 if (mptable_use_default) {
2971 mptable_lapic_default();
2975 error = mptable_map(&mpt);
2977 panic("mptable_lapic_enumerate mptable_map failed\n");
2978 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
2982 /* Save local apic address */
2983 lapic_addr = (vm_offset_t)cth->apic_address;
2984 KKASSERT(lapic_addr != 0);
2987 * Find out how many CPUs do we have
2989 bzero(&arg1, sizeof(arg1));
2990 arg1.ht_fixup = 1; /* Apply ht fixup by default */
2992 error = mptable_iterate_entries(cth,
2993 mptable_lapic_pass1_callback, &arg1);
2995 panic("mptable_iterate_entries(lapic_pass1) failed\n");
2996 KKASSERT(arg1.cpu_count != 0);
2998 /* See if we need to fixup HT logical CPUs. */
2999 if (arg1.ht_fixup) {
3000 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3002 if (logical_cpus != 0)
3003 arg1.cpu_count *= logical_cpus;
3005 mp_naps = arg1.cpu_count;
3007 /* Qualify the numbers again, after possible HT fixup */
3008 if (mp_naps > MAXCPU) {
3009 kprintf("Warning: only using %d of %d available CPUs!\n",
3015 --mp_naps; /* subtract the BSP */
3018 * Link logical CPU id to local apic id
3020 bzero(&arg2, sizeof(arg2));
3022 arg2.logical_cpus = logical_cpus;
3024 error = mptable_iterate_entries(cth,
3025 mptable_lapic_pass2_callback, &arg2);
3027 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3028 KKASSERT(arg2.found_bsp);
3030 /* Map local apic */
3031 lapic_map(lapic_addr);
3033 mptable_unmap(&mpt);
3036 struct mptable_lapic_probe_cbarg {
3042 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
3044 const struct PROCENTRY *ent;
3045 struct mptable_lapic_probe_cbarg *arg = xarg;
3051 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3055 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3056 if (arg->found_bsp) {
3057 kprintf("more than one BSP in base MP table\n");
3066 mptable_lapic_probe(struct lapic_enumerator *e)
3068 struct mptable_pos mpt;
3069 struct mptable_lapic_probe_cbarg arg;
3073 if (mptable_fps_phyaddr == 0)
3076 if (mptable_use_default)
3079 error = mptable_map(&mpt);
3082 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3087 if (cth->apic_address == 0)
3090 bzero(&arg, sizeof(arg));
3091 error = mptable_iterate_entries(cth,
3092 mptable_lapic_probe_callback, &arg);
3094 if (arg.cpu_count == 0) {
3095 kprintf("MP table contains no processor entries\n");
3097 } else if (!arg.found_bsp) {
3098 kprintf("MP table does not contains BSP entry\n");
3103 mptable_unmap(&mpt);
3107 static struct lapic_enumerator mptable_lapic_enumerator = {
3108 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3109 .lapic_probe = mptable_lapic_probe,
3110 .lapic_enumerate = mptable_lapic_enumerate
3114 mptable_lapic_enum_register(void)
3116 lapic_enumerator_register(&mptable_lapic_enumerator);
3118 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3119 mptable_lapic_enum_register, 0);