1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx *reg_equiv_address;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static unsigned int *reg_max_ref_width;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx *reg_equiv_init;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
136 static HARD_REG_SET reg_reloaded_valid;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead;
141 /* Indicate whether the register's current value is one that is not
142 safe to retain across a call, even for registers that are normally
144 static HARD_REG_SET reg_reloaded_call_part_clobbered;
146 /* Number of spill-regs so far; number of valid elements of spill_regs. */
149 /* In parallel with spill_regs, contains REG rtx's for those regs.
150 Holds the last rtx used for any given reg, or 0 if it has never
151 been used for spilling yet. This rtx is reused, provided it has
153 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
155 /* In parallel with spill_regs, contains nonzero for a spill reg
156 that was stored after the last time it was used.
157 The precise value is the insn generated to do the store. */
158 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
160 /* This is the register that was stored with spill_reg_store. This is a
161 copy of reload_out / reload_out_reg when the value was stored; if
162 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
163 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
165 /* This table is the inverse mapping of spill_regs:
166 indexed by hard reg number,
167 it contains the position of that reg in spill_regs,
168 or -1 for something that is not in spill_regs.
170 ?!? This is no longer accurate. */
171 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
173 /* This reg set indicates registers that can't be used as spill registers for
174 the currently processed insn. These are the hard registers which are live
175 during the insn, but not allocated to pseudos, as well as fixed
177 static HARD_REG_SET bad_spill_regs;
179 /* These are the hard registers that can't be used as spill register for any
180 insn. This includes registers used for user variables and registers that
181 we can't eliminate. A register that appears in this set also can't be used
182 to retry register allocation. */
183 static HARD_REG_SET bad_spill_regs_global;
185 /* Describes order of use of registers for reloading
186 of spilled pseudo-registers. `n_spills' is the number of
187 elements that are actually valid; new ones are added at the end.
189 Both spill_regs and spill_reg_order are used on two occasions:
190 once during find_reload_regs, where they keep track of the spill registers
191 for a single insn, but also during reload_as_needed where they show all
192 the registers ever used by reload. For the latter case, the information
193 is calculated during finish_spills. */
194 static short spill_regs[FIRST_PSEUDO_REGISTER];
196 /* This vector of reg sets indicates, for each pseudo, which hard registers
197 may not be used for retrying global allocation because the register was
198 formerly spilled from one of them. If we allowed reallocating a pseudo to
199 a register that it was already allocated to, reload might not
201 static HARD_REG_SET *pseudo_previous_regs;
203 /* This vector of reg sets indicates, for each pseudo, which hard
204 registers may not be used for retrying global allocation because they
205 are used as spill registers during one of the insns in which the
207 static HARD_REG_SET *pseudo_forbidden_regs;
209 /* All hard regs that have been used as spill registers for any insn are
210 marked in this set. */
211 static HARD_REG_SET used_spill_regs;
213 /* Index of last register assigned as a spill register. We allocate in
214 a round-robin fashion. */
215 static int last_spill_reg;
217 /* Nonzero if indirect addressing is supported on the machine; this means
218 that spilling (REG n) does not require reloading it into a register in
219 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
220 value indicates the level of indirect addressing supported, e.g., two
221 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
223 static char spill_indirect_levels;
225 /* Nonzero if indirect addressing is supported when the innermost MEM is
226 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
227 which these are valid is the same as spill_indirect_levels, above. */
228 char indirect_symref_ok;
230 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
231 char double_reg_address_ok;
233 /* Record the stack slot for each spilled hard register. */
234 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
236 /* Width allocated so far for that stack slot. */
237 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
239 /* Record which pseudos needed to be spilled. */
240 static regset_head spilled_pseudos;
242 /* Used for communication between order_regs_for_reload and count_pseudo.
243 Used to avoid counting one pseudo twice. */
244 static regset_head pseudos_counted;
246 /* First uid used by insns created by reload in this function.
247 Used in find_equiv_reg. */
248 int reload_first_uid;
250 /* Flag set by local-alloc or global-alloc if anything is live in
251 a call-clobbered reg across calls. */
252 int caller_save_needed;
254 /* Set to 1 while reload_as_needed is operating.
255 Required by some machines to handle any generated moves differently. */
256 int reload_in_progress = 0;
258 /* These arrays record the insn_code of insns that may be needed to
259 perform input and output reloads of special objects. They provide a
260 place to pass a scratch register. */
261 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
262 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
264 /* This obstack is used for allocation of rtl during register elimination.
265 The allocated storage can be freed once find_reloads has processed the
267 struct obstack reload_obstack;
269 /* Points to the beginning of the reload_obstack. All insn_chain structures
270 are allocated first. */
271 char *reload_startobj;
273 /* The point after all insn_chain structures. Used to quickly deallocate
274 memory allocated in copy_reloads during calculate_needs_all_insns. */
275 char *reload_firstobj;
277 /* This points before all local rtl generated by register elimination.
278 Used to quickly free all memory after processing one insn. */
279 static char *reload_insn_firstobj;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain *reload_insn_chain;
285 /* List of all insns needing reloads. */
286 static struct insn_chain *insns_need_reload;
288 /* This structure is used to record information about register eliminations.
289 Each array entry describes one possible way of eliminating a register
290 in favor of another. If there is more than one way of eliminating a
291 particular register, the most preferred should be specified first. */
295 int from; /* Register number to be eliminated. */
296 int to; /* Register number used as replacement. */
297 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
298 int can_eliminate; /* Nonzero if this elimination can be done. */
299 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
300 insns made by reload. */
301 HOST_WIDE_INT offset; /* Current offset between the two regs. */
302 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
303 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
304 rtx from_rtx; /* REG rtx for the register to be eliminated.
305 We cannot simply compare the number since
306 we might then spuriously replace a hard
307 register corresponding to a pseudo
308 assigned to the reg to be eliminated. */
309 rtx to_rtx; /* REG rtx for the replacement. */
312 static struct elim_table *reg_eliminate = 0;
314 /* This is an intermediate structure to initialize the table. It has
315 exactly the members provided by ELIMINABLE_REGS. */
316 static const struct elim_table_1
320 } reg_eliminate_1[] =
322 /* If a set of eliminable registers was specified, define the table from it.
323 Otherwise, default to the normal case of the frame pointer being
324 replaced by the stack pointer. */
326 #ifdef ELIMINABLE_REGS
329 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
332 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
334 /* Record the number of pending eliminations that have an offset not equal
335 to their initial offset. If nonzero, we use a new copy of each
336 replacement result in any insns encountered. */
337 int num_not_at_initial_offset;
339 /* Count the number of registers that we may be able to eliminate. */
340 static int num_eliminable;
341 /* And the number of registers that are equivalent to a constant that
342 can be eliminated to frame_pointer / arg_pointer + constant. */
343 static int num_eliminable_invariants;
345 /* For each label, we record the offset of each elimination. If we reach
346 a label by more than one path and an offset differs, we cannot do the
347 elimination. This information is indexed by the difference of the
348 number of the label and the first label number. We can't offset the
349 pointer itself as this can cause problems on machines with segmented
350 memory. The first table is an array of flags that records whether we
351 have yet encountered a label and the second table is an array of arrays,
352 one entry in the latter array for each elimination. */
354 static int first_label_num;
355 static char *offsets_known_at;
356 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
358 /* Number of labels in the current function. */
360 static int num_labels;
362 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
363 static void maybe_fix_stack_asms (void);
364 static void copy_reloads (struct insn_chain *);
365 static void calculate_needs_all_insns (int);
366 static int find_reg (struct insn_chain *, int);
367 static void find_reload_regs (struct insn_chain *);
368 static void select_reload_regs (void);
369 static void delete_caller_save_insns (void);
371 static void spill_failure (rtx, enum reg_class);
372 static void count_spilled_pseudo (int, int, int);
373 static void delete_dead_insn (rtx);
374 static void alter_reg (int, int);
375 static void set_label_offsets (rtx, rtx, int);
376 static void check_eliminable_occurrences (rtx);
377 static void elimination_effects (rtx, enum machine_mode);
378 static int eliminate_regs_in_insn (rtx, int);
379 static void update_eliminable_offsets (void);
380 static void mark_not_eliminable (rtx, rtx, void *);
381 static void set_initial_elim_offsets (void);
382 static void verify_initial_elim_offsets (void);
383 static void set_initial_label_offsets (void);
384 static void set_offsets_for_label (rtx);
385 static void init_elim_table (void);
386 static void update_eliminables (HARD_REG_SET *);
387 static void spill_hard_reg (unsigned int, int);
388 static int finish_spills (int);
389 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
390 static void scan_paradoxical_subregs (rtx);
391 static void count_pseudo (int);
392 static void order_regs_for_reload (struct insn_chain *);
393 static void reload_as_needed (int);
394 static void forget_old_reloads_1 (rtx, rtx, void *);
395 static int reload_reg_class_lower (const void *, const void *);
396 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
398 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
400 static int reload_reg_free_p (unsigned int, int, enum reload_type);
401 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
403 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
405 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
406 static int allocate_reload_reg (struct insn_chain *, int, int);
407 static int conflicts_with_override (rtx);
408 static void failed_reload (rtx, int);
409 static int set_reload_reg (int, int);
410 static void choose_reload_regs_init (struct insn_chain *, rtx *);
411 static void choose_reload_regs (struct insn_chain *);
412 static void merge_assigned_reloads (rtx);
413 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
415 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
417 static void do_input_reload (struct insn_chain *, struct reload *, int);
418 static void do_output_reload (struct insn_chain *, struct reload *, int);
419 static void emit_reload_insns (struct insn_chain *);
420 static void delete_output_reload (rtx, int, int);
421 static void delete_address_reloads (rtx, rtx);
422 static void delete_address_reloads_1 (rtx, rtx, rtx);
423 static rtx inc_for_reload (rtx, rtx, rtx, int);
425 static void add_auto_inc_notes (rtx, rtx);
427 static void copy_eh_notes (rtx, rtx);
429 /* Initialize the reload pass once per compilation. */
436 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
437 Set spill_indirect_levels to the number of levels such addressing is
438 permitted, zero if it is not permitted at all. */
441 = gen_rtx_MEM (Pmode,
444 LAST_VIRTUAL_REGISTER + 1),
446 spill_indirect_levels = 0;
448 while (memory_address_p (QImode, tem))
450 spill_indirect_levels++;
451 tem = gen_rtx_MEM (Pmode, tem);
454 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
456 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
457 indirect_symref_ok = memory_address_p (QImode, tem);
459 /* See if reg+reg is a valid (and offsettable) address. */
461 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
463 tem = gen_rtx_PLUS (Pmode,
464 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
465 gen_rtx_REG (Pmode, i));
467 /* This way, we make sure that reg+reg is an offsettable address. */
468 tem = plus_constant (tem, 4);
470 if (memory_address_p (QImode, tem))
472 double_reg_address_ok = 1;
477 /* Initialize obstack for our rtl allocation. */
478 gcc_obstack_init (&reload_obstack);
479 reload_startobj = obstack_alloc (&reload_obstack, 0);
481 INIT_REG_SET (&spilled_pseudos);
482 INIT_REG_SET (&pseudos_counted);
485 /* List of insn chains that are currently unused. */
486 static struct insn_chain *unused_insn_chains = 0;
488 /* Allocate an empty insn_chain structure. */
490 new_insn_chain (void)
492 struct insn_chain *c;
494 if (unused_insn_chains == 0)
496 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
497 INIT_REG_SET (&c->live_throughout);
498 INIT_REG_SET (&c->dead_or_set);
502 c = unused_insn_chains;
503 unused_insn_chains = c->next;
505 c->is_caller_save_insn = 0;
506 c->need_operand_change = 0;
512 /* Small utility function to set all regs in hard reg set TO which are
513 allocated to pseudos in regset FROM. */
516 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
520 EXECUTE_IF_SET_IN_REG_SET
521 (from, FIRST_PSEUDO_REGISTER, regno,
523 int r = reg_renumber[regno];
528 /* reload_combine uses the information from
529 BASIC_BLOCK->global_live_at_start, which might still
530 contain registers that have not actually been allocated
531 since they have an equivalence. */
532 if (! reload_completed)
537 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
539 SET_HARD_REG_BIT (*to, r + nregs);
544 /* Replace all pseudos found in LOC with their corresponding
548 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
561 unsigned int regno = REGNO (x);
563 if (regno < FIRST_PSEUDO_REGISTER)
566 x = eliminate_regs (x, mem_mode, usage);
570 replace_pseudos_in (loc, mem_mode, usage);
574 if (reg_equiv_constant[regno])
575 *loc = reg_equiv_constant[regno];
576 else if (reg_equiv_mem[regno])
577 *loc = reg_equiv_mem[regno];
578 else if (reg_equiv_address[regno])
579 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
580 else if (GET_CODE (regno_reg_rtx[regno]) != REG
581 || REGNO (regno_reg_rtx[regno]) != regno)
582 *loc = regno_reg_rtx[regno];
588 else if (code == MEM)
590 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
594 /* Process each of our operands recursively. */
595 fmt = GET_RTX_FORMAT (code);
596 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
598 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
599 else if (*fmt == 'E')
600 for (j = 0; j < XVECLEN (x, i); j++)
601 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
605 /* Global variables used by reload and its subroutines. */
607 /* Set during calculate_needs if an insn needs register elimination. */
608 static int something_needs_elimination;
609 /* Set during calculate_needs if an insn needs an operand changed. */
610 int something_needs_operands_changed;
612 /* Nonzero means we couldn't get enough spill regs. */
615 /* Main entry point for the reload pass.
617 FIRST is the first insn of the function being compiled.
619 GLOBAL nonzero means we were called from global_alloc
620 and should attempt to reallocate any pseudoregs that we
621 displace from hard regs we will use for reloads.
622 If GLOBAL is zero, we do not have enough information to do that,
623 so any pseudo reg that is spilled must go to the stack.
625 Return value is nonzero if reload failed
626 and we must not do any more for this function. */
629 reload (rtx first, int global)
633 struct elim_table *ep;
636 /* Make sure even insns with volatile mem refs are recognizable. */
641 reload_firstobj = obstack_alloc (&reload_obstack, 0);
643 /* Make sure that the last insn in the chain
644 is not something that needs reloading. */
645 emit_note (NOTE_INSN_DELETED);
647 /* Enable find_equiv_reg to distinguish insns made by reload. */
648 reload_first_uid = get_max_uid ();
650 #ifdef SECONDARY_MEMORY_NEEDED
651 /* Initialize the secondary memory table. */
652 clear_secondary_mem ();
655 /* We don't have a stack slot for any spill reg yet. */
656 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
657 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
659 /* Initialize the save area information for caller-save, in case some
663 /* Compute which hard registers are now in use
664 as homes for pseudo registers.
665 This is done here rather than (eg) in global_alloc
666 because this point is reached even if not optimizing. */
667 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
670 /* A function that receives a nonlocal goto must save all call-saved
672 if (current_function_has_nonlocal_label)
673 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
674 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
675 regs_ever_live[i] = 1;
677 #ifdef NON_SAVING_SETJMP
678 /* A function that calls setjmp should save and restore all the
679 call-saved registers on a system where longjmp clobbers them. */
680 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
682 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
683 if (! call_used_regs[i])
684 regs_ever_live[i] = 1;
688 /* Find all the pseudo registers that didn't get hard regs
689 but do have known equivalent constants or memory slots.
690 These include parameters (known equivalent to parameter slots)
691 and cse'd or loop-moved constant memory addresses.
693 Record constant equivalents in reg_equiv_constant
694 so they will be substituted by find_reloads.
695 Record memory equivalents in reg_mem_equiv so they can
696 be substituted eventually by altering the REG-rtx's. */
698 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
699 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
700 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
701 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
702 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
703 reg_old_renumber = xcalloc (max_regno, sizeof (short));
704 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
705 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
706 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
708 CLEAR_HARD_REG_SET (bad_spill_regs_global);
710 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
711 Also find all paradoxical subregs and find largest such for each pseudo.
712 On machines with small register classes, record hard registers that
713 are used for user variables. These can never be used for spills. */
715 num_eliminable_invariants = 0;
716 for (insn = first; insn; insn = NEXT_INSN (insn))
718 rtx set = single_set (insn);
720 /* We may introduce USEs that we want to remove at the end, so
721 we'll mark them with QImode. Make sure there are no
722 previously-marked insns left by say regmove. */
723 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
724 && GET_MODE (insn) != VOIDmode)
725 PUT_MODE (insn, VOIDmode);
727 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
729 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
731 #ifdef LEGITIMATE_PIC_OPERAND_P
732 && (! function_invariant_p (XEXP (note, 0))
734 /* A function invariant is often CONSTANT_P but may
735 include a register. We promise to only pass
736 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
737 || (CONSTANT_P (XEXP (note, 0))
738 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))))
742 rtx x = XEXP (note, 0);
743 i = REGNO (SET_DEST (set));
744 if (i > LAST_VIRTUAL_REGISTER)
746 /* It can happen that a REG_EQUIV note contains a MEM
747 that is not a legitimate memory operand. As later
748 stages of reload assume that all addresses found
749 in the reg_equiv_* arrays were originally legitimate,
750 we ignore such REG_EQUIV notes.
752 It also can happen that a REG_EQUIV note contains a MEM
753 that carries the /u flag, for example when GCSE turns
754 the load of a constant into a move from a pseudo that
755 already contains the constant and attaches a REG_EQUAL
756 note to the insn, which is later promoted to REQ_EQUIV
757 by local-alloc. If the destination pseudo happens not
758 to be assigned to a hard reg, it will be replaced by
759 the MEM as the destination of the move, thus generating
760 a store to a possibly read-only memory location. */
761 if (memory_operand (x, VOIDmode) && ! RTX_UNCHANGING_P (x))
763 /* Always unshare the equivalence, so we can
764 substitute into this insn without touching the
766 reg_equiv_memory_loc[i] = copy_rtx (x);
768 else if (function_invariant_p (x))
770 if (GET_CODE (x) == PLUS)
772 /* This is PLUS of frame pointer and a constant,
773 and might be shared. Unshare it. */
774 reg_equiv_constant[i] = copy_rtx (x);
775 num_eliminable_invariants++;
777 else if (x == frame_pointer_rtx
778 || x == arg_pointer_rtx)
780 reg_equiv_constant[i] = x;
781 num_eliminable_invariants++;
783 else if (LEGITIMATE_CONSTANT_P (x))
784 reg_equiv_constant[i] = x;
787 reg_equiv_memory_loc[i]
788 = force_const_mem (GET_MODE (SET_DEST (set)), x);
789 if (!reg_equiv_memory_loc[i])
796 /* If this register is being made equivalent to a MEM
797 and the MEM is not SET_SRC, the equivalencing insn
798 is one with the MEM as a SET_DEST and it occurs later.
799 So don't mark this insn now. */
800 if (GET_CODE (x) != MEM
801 || rtx_equal_p (SET_SRC (set), x))
803 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
808 /* If this insn is setting a MEM from a register equivalent to it,
809 this is the equivalencing insn. */
810 else if (set && GET_CODE (SET_DEST (set)) == MEM
811 && GET_CODE (SET_SRC (set)) == REG
812 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
813 && rtx_equal_p (SET_DEST (set),
814 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
815 reg_equiv_init[REGNO (SET_SRC (set))]
816 = gen_rtx_INSN_LIST (VOIDmode, insn,
817 reg_equiv_init[REGNO (SET_SRC (set))]);
820 scan_paradoxical_subregs (PATTERN (insn));
825 first_label_num = get_first_label_num ();
826 num_labels = max_label_num () - first_label_num;
828 /* Allocate the tables used to store offset information at labels. */
829 /* We used to use alloca here, but the size of what it would try to
830 allocate would occasionally cause it to exceed the stack limit and
831 cause a core dump. */
832 offsets_known_at = xmalloc (num_labels);
833 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
835 /* Alter each pseudo-reg rtx to contain its hard reg number.
836 Assign stack slots to the pseudos that lack hard regs or equivalents.
837 Do not touch virtual registers. */
839 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
842 /* If we have some registers we think can be eliminated, scan all insns to
843 see if there is an insn that sets one of these registers to something
844 other than itself plus a constant. If so, the register cannot be
845 eliminated. Doing this scan here eliminates an extra pass through the
846 main reload loop in the most common case where register elimination
848 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
849 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
850 || GET_CODE (insn) == CALL_INSN)
851 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
853 maybe_fix_stack_asms ();
855 insns_need_reload = 0;
856 something_needs_elimination = 0;
858 /* Initialize to -1, which means take the first spill register. */
861 /* Spill any hard regs that we know we can't eliminate. */
862 CLEAR_HARD_REG_SET (used_spill_regs);
863 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
864 if (! ep->can_eliminate)
865 spill_hard_reg (ep->from, 1);
867 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
868 if (frame_pointer_needed)
869 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
871 finish_spills (global);
873 /* From now on, we may need to generate moves differently. We may also
874 allow modifications of insns which cause them to not be recognized.
875 Any such modifications will be cleaned up during reload itself. */
876 reload_in_progress = 1;
878 /* This loop scans the entire function each go-round
879 and repeats until one repetition spills no additional hard regs. */
882 int something_changed;
885 HOST_WIDE_INT starting_frame_size;
887 /* Round size of stack frame to stack_alignment_needed. This must be done
888 here because the stack size may be a part of the offset computation
889 for register elimination, and there might have been new stack slots
890 created in the last iteration of this loop. */
891 if (cfun->stack_alignment_needed)
892 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
894 starting_frame_size = get_frame_size ();
896 set_initial_elim_offsets ();
897 set_initial_label_offsets ();
899 /* For each pseudo register that has an equivalent location defined,
900 try to eliminate any eliminable registers (such as the frame pointer)
901 assuming initial offsets for the replacement register, which
904 If the resulting location is directly addressable, substitute
905 the MEM we just got directly for the old REG.
907 If it is not addressable but is a constant or the sum of a hard reg
908 and constant, it is probably not addressable because the constant is
909 out of range, in that case record the address; we will generate
910 hairy code to compute the address in a register each time it is
911 needed. Similarly if it is a hard register, but one that is not
912 valid as an address register.
914 If the location is not addressable, but does not have one of the
915 above forms, assign a stack slot. We have to do this to avoid the
916 potential of producing lots of reloads if, e.g., a location involves
917 a pseudo that didn't get a hard register and has an equivalent memory
918 location that also involves a pseudo that didn't get a hard register.
920 Perhaps at some point we will improve reload_when_needed handling
921 so this problem goes away. But that's very hairy. */
923 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
924 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
926 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
928 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
930 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
931 else if (CONSTANT_P (XEXP (x, 0))
932 || (GET_CODE (XEXP (x, 0)) == REG
933 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
934 || (GET_CODE (XEXP (x, 0)) == PLUS
935 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
936 && (REGNO (XEXP (XEXP (x, 0), 0))
937 < FIRST_PSEUDO_REGISTER)
938 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
939 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
942 /* Make a new stack slot. Then indicate that something
943 changed so we go back and recompute offsets for
944 eliminable registers because the allocation of memory
945 below might change some offset. reg_equiv_{mem,address}
946 will be set up for this pseudo on the next pass around
948 reg_equiv_memory_loc[i] = 0;
949 reg_equiv_init[i] = 0;
954 if (caller_save_needed)
957 /* If we allocated another stack slot, redo elimination bookkeeping. */
958 if (starting_frame_size != get_frame_size ())
961 if (caller_save_needed)
963 save_call_clobbered_regs ();
964 /* That might have allocated new insn_chain structures. */
965 reload_firstobj = obstack_alloc (&reload_obstack, 0);
968 calculate_needs_all_insns (global);
970 CLEAR_REG_SET (&spilled_pseudos);
973 something_changed = 0;
975 /* If we allocated any new memory locations, make another pass
976 since it might have changed elimination offsets. */
977 if (starting_frame_size != get_frame_size ())
978 something_changed = 1;
981 HARD_REG_SET to_spill;
982 CLEAR_HARD_REG_SET (to_spill);
983 update_eliminables (&to_spill);
984 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
985 if (TEST_HARD_REG_BIT (to_spill, i))
987 spill_hard_reg (i, 1);
990 /* Regardless of the state of spills, if we previously had
991 a register that we thought we could eliminate, but now can
992 not eliminate, we must run another pass.
994 Consider pseudos which have an entry in reg_equiv_* which
995 reference an eliminable register. We must make another pass
996 to update reg_equiv_* so that we do not substitute in the
997 old value from when we thought the elimination could be
999 something_changed = 1;
1003 select_reload_regs ();
1007 if (insns_need_reload != 0 || did_spill)
1008 something_changed |= finish_spills (global);
1010 if (! something_changed)
1013 if (caller_save_needed)
1014 delete_caller_save_insns ();
1016 obstack_free (&reload_obstack, reload_firstobj);
1019 /* If global-alloc was run, notify it of any register eliminations we have
1022 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1023 if (ep->can_eliminate)
1024 mark_elimination (ep->from, ep->to);
1026 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1027 If that insn didn't set the register (i.e., it copied the register to
1028 memory), just delete that insn instead of the equivalencing insn plus
1029 anything now dead. If we call delete_dead_insn on that insn, we may
1030 delete the insn that actually sets the register if the register dies
1031 there and that is incorrect. */
1033 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1035 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1038 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1040 rtx equiv_insn = XEXP (list, 0);
1042 /* If we already deleted the insn or if it may trap, we can't
1043 delete it. The latter case shouldn't happen, but can
1044 if an insn has a variable address, gets a REG_EH_REGION
1045 note added to it, and then gets converted into an load
1046 from a constant address. */
1047 if (GET_CODE (equiv_insn) == NOTE
1048 || can_throw_internal (equiv_insn))
1050 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1051 delete_dead_insn (equiv_insn);
1054 PUT_CODE (equiv_insn, NOTE);
1055 NOTE_SOURCE_FILE (equiv_insn) = 0;
1056 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1062 /* Use the reload registers where necessary
1063 by generating move instructions to move the must-be-register
1064 values into or out of the reload registers. */
1066 if (insns_need_reload != 0 || something_needs_elimination
1067 || something_needs_operands_changed)
1069 HOST_WIDE_INT old_frame_size = get_frame_size ();
1071 reload_as_needed (global);
1073 if (old_frame_size != get_frame_size ())
1077 verify_initial_elim_offsets ();
1080 /* If we were able to eliminate the frame pointer, show that it is no
1081 longer live at the start of any basic block. If it ls live by
1082 virtue of being in a pseudo, that pseudo will be marked live
1083 and hence the frame pointer will be known to be live via that
1086 if (! frame_pointer_needed)
1088 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1089 HARD_FRAME_POINTER_REGNUM);
1091 /* Come here (with failure set nonzero) if we can't get enough spill regs
1092 and we decide not to abort about it. */
1095 CLEAR_REG_SET (&spilled_pseudos);
1096 reload_in_progress = 0;
1098 /* Now eliminate all pseudo regs by modifying them into
1099 their equivalent memory references.
1100 The REG-rtx's for the pseudos are modified in place,
1101 so all insns that used to refer to them now refer to memory.
1103 For a reg that has a reg_equiv_address, all those insns
1104 were changed by reloading so that no insns refer to it any longer;
1105 but the DECL_RTL of a variable decl may refer to it,
1106 and if so this causes the debugging info to mention the variable. */
1108 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1112 if (reg_equiv_mem[i])
1113 addr = XEXP (reg_equiv_mem[i], 0);
1115 if (reg_equiv_address[i])
1116 addr = reg_equiv_address[i];
1120 if (reg_renumber[i] < 0)
1122 rtx reg = regno_reg_rtx[i];
1124 REG_USERVAR_P (reg) = 0;
1125 PUT_CODE (reg, MEM);
1126 XEXP (reg, 0) = addr;
1127 if (reg_equiv_memory_loc[i])
1128 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1131 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg)
1132 = MEM_SCALAR_P (reg) = 0;
1133 MEM_ATTRS (reg) = 0;
1136 else if (reg_equiv_mem[i])
1137 XEXP (reg_equiv_mem[i], 0) = addr;
1141 /* We must set reload_completed now since the cleanup_subreg_operands call
1142 below will re-recognize each insn and reload may have generated insns
1143 which are only valid during and after reload. */
1144 reload_completed = 1;
1146 /* Make a pass over all the insns and delete all USEs which we inserted
1147 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1148 notes. Delete all CLOBBER insns, except those that refer to the return
1149 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1150 from misarranging variable-array code, and simplify (subreg (reg))
1151 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1152 are no longer useful or accurate. Strip and regenerate REG_INC notes
1153 that may have been moved around. */
1155 for (insn = first; insn; insn = NEXT_INSN (insn))
1160 if (GET_CODE (insn) == CALL_INSN)
1161 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1162 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1164 if ((GET_CODE (PATTERN (insn)) == USE
1165 /* We mark with QImode USEs introduced by reload itself. */
1166 && (GET_MODE (insn) == QImode
1167 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1168 || (GET_CODE (PATTERN (insn)) == CLOBBER
1169 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM
1170 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1171 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1172 && XEXP (XEXP (PATTERN (insn), 0), 0)
1173 != stack_pointer_rtx))
1174 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1175 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1181 /* Some CLOBBERs may survive until here and still reference unassigned
1182 pseudos with const equivalent, which may in turn cause ICE in later
1183 passes if the reference remains in place. */
1184 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1185 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1186 VOIDmode, PATTERN (insn));
1188 pnote = ®_NOTES (insn);
1191 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1192 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1193 || REG_NOTE_KIND (*pnote) == REG_INC
1194 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1195 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1196 *pnote = XEXP (*pnote, 1);
1198 pnote = &XEXP (*pnote, 1);
1202 add_auto_inc_notes (insn, PATTERN (insn));
1205 /* And simplify (subreg (reg)) if it appears as an operand. */
1206 cleanup_subreg_operands (insn);
1209 /* If we are doing stack checking, give a warning if this function's
1210 frame size is larger than we expect. */
1211 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1213 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1214 static int verbose_warned = 0;
1216 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1217 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1218 size += UNITS_PER_WORD;
1220 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1222 warning ("frame size too large for reliable stack checking");
1223 if (! verbose_warned)
1225 warning ("try reducing the number of local variables");
1231 /* Indicate that we no longer have known memory locations or constants. */
1232 if (reg_equiv_constant)
1233 free (reg_equiv_constant);
1234 reg_equiv_constant = 0;
1235 if (reg_equiv_memory_loc)
1236 free (reg_equiv_memory_loc);
1237 reg_equiv_memory_loc = 0;
1239 if (offsets_known_at)
1240 free (offsets_known_at);
1244 free (reg_equiv_mem);
1245 free (reg_equiv_init);
1246 free (reg_equiv_address);
1247 free (reg_max_ref_width);
1248 free (reg_old_renumber);
1249 free (pseudo_previous_regs);
1250 free (pseudo_forbidden_regs);
1252 CLEAR_HARD_REG_SET (used_spill_regs);
1253 for (i = 0; i < n_spills; i++)
1254 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1256 /* Free all the insn_chain structures at once. */
1257 obstack_free (&reload_obstack, reload_startobj);
1258 unused_insn_chains = 0;
1259 fixup_abnormal_edges ();
1261 /* Replacing pseudos with their memory equivalents might have
1262 created shared rtx. Subsequent passes would get confused
1263 by this, so unshare everything here. */
1264 unshare_all_rtl_again (first);
1266 #ifdef STACK_BOUNDARY
1267 /* init_emit has set the alignment of the hard frame pointer
1268 to STACK_BOUNDARY. It is very likely no longer valid if
1269 the hard frame pointer was used for register allocation. */
1270 if (!frame_pointer_needed)
1271 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1277 /* Yet another special case. Unfortunately, reg-stack forces people to
1278 write incorrect clobbers in asm statements. These clobbers must not
1279 cause the register to appear in bad_spill_regs, otherwise we'll call
1280 fatal_insn later. We clear the corresponding regnos in the live
1281 register sets to avoid this.
1282 The whole thing is rather sick, I'm afraid. */
1285 maybe_fix_stack_asms (void)
1288 const char *constraints[MAX_RECOG_OPERANDS];
1289 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1290 struct insn_chain *chain;
1292 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1295 HARD_REG_SET clobbered, allowed;
1298 if (! INSN_P (chain->insn)
1299 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1301 pat = PATTERN (chain->insn);
1302 if (GET_CODE (pat) != PARALLEL)
1305 CLEAR_HARD_REG_SET (clobbered);
1306 CLEAR_HARD_REG_SET (allowed);
1308 /* First, make a mask of all stack regs that are clobbered. */
1309 for (i = 0; i < XVECLEN (pat, 0); i++)
1311 rtx t = XVECEXP (pat, 0, i);
1312 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1313 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1316 /* Get the operand values and constraints out of the insn. */
1317 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1318 constraints, operand_mode);
1320 /* For every operand, see what registers are allowed. */
1321 for (i = 0; i < noperands; i++)
1323 const char *p = constraints[i];
1324 /* For every alternative, we compute the class of registers allowed
1325 for reloading in CLS, and merge its contents into the reg set
1327 int cls = (int) NO_REGS;
1333 if (c == '\0' || c == ',' || c == '#')
1335 /* End of one alternative - mark the regs in the current
1336 class, and reset the class. */
1337 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1343 } while (c != '\0' && c != ',');
1351 case '=': case '+': case '*': case '%': case '?': case '!':
1352 case '0': case '1': case '2': case '3': case '4': case 'm':
1353 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1354 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1355 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1360 cls = (int) reg_class_subunion[cls]
1361 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1366 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1370 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1371 cls = (int) reg_class_subunion[cls]
1372 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1374 cls = (int) reg_class_subunion[cls]
1375 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1377 p += CONSTRAINT_LEN (c, p);
1380 /* Those of the registers which are clobbered, but allowed by the
1381 constraints, must be usable as reload registers. So clear them
1382 out of the life information. */
1383 AND_HARD_REG_SET (allowed, clobbered);
1384 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1385 if (TEST_HARD_REG_BIT (allowed, i))
1387 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1388 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1395 /* Copy the global variables n_reloads and rld into the corresponding elts
1398 copy_reloads (struct insn_chain *chain)
1400 chain->n_reloads = n_reloads;
1401 chain->rld = obstack_alloc (&reload_obstack,
1402 n_reloads * sizeof (struct reload));
1403 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1404 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1407 /* Walk the chain of insns, and determine for each whether it needs reloads
1408 and/or eliminations. Build the corresponding insns_need_reload list, and
1409 set something_needs_elimination as appropriate. */
1411 calculate_needs_all_insns (int global)
1413 struct insn_chain **pprev_reload = &insns_need_reload;
1414 struct insn_chain *chain, *next = 0;
1416 something_needs_elimination = 0;
1418 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1419 for (chain = reload_insn_chain; chain != 0; chain = next)
1421 rtx insn = chain->insn;
1425 /* Clear out the shortcuts. */
1426 chain->n_reloads = 0;
1427 chain->need_elim = 0;
1428 chain->need_reload = 0;
1429 chain->need_operand_change = 0;
1431 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1432 include REG_LABEL), we need to see what effects this has on the
1433 known offsets at labels. */
1435 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1436 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1437 set_label_offsets (insn, insn, 0);
1441 rtx old_body = PATTERN (insn);
1442 int old_code = INSN_CODE (insn);
1443 rtx old_notes = REG_NOTES (insn);
1444 int did_elimination = 0;
1445 int operands_changed = 0;
1446 rtx set = single_set (insn);
1448 /* Skip insns that only set an equivalence. */
1449 if (set && GET_CODE (SET_DEST (set)) == REG
1450 && reg_renumber[REGNO (SET_DEST (set))] < 0
1451 && reg_equiv_constant[REGNO (SET_DEST (set))])
1454 /* If needed, eliminate any eliminable registers. */
1455 if (num_eliminable || num_eliminable_invariants)
1456 did_elimination = eliminate_regs_in_insn (insn, 0);
1458 /* Analyze the instruction. */
1459 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1460 global, spill_reg_order);
1462 /* If a no-op set needs more than one reload, this is likely
1463 to be something that needs input address reloads. We
1464 can't get rid of this cleanly later, and it is of no use
1465 anyway, so discard it now.
1466 We only do this when expensive_optimizations is enabled,
1467 since this complements reload inheritance / output
1468 reload deletion, and it can make debugging harder. */
1469 if (flag_expensive_optimizations && n_reloads > 1)
1471 rtx set = single_set (insn);
1473 && SET_SRC (set) == SET_DEST (set)
1474 && GET_CODE (SET_SRC (set)) == REG
1475 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1478 /* Delete it from the reload chain. */
1480 chain->prev->next = next;
1482 reload_insn_chain = next;
1484 next->prev = chain->prev;
1485 chain->next = unused_insn_chains;
1486 unused_insn_chains = chain;
1491 update_eliminable_offsets ();
1493 /* Remember for later shortcuts which insns had any reloads or
1494 register eliminations. */
1495 chain->need_elim = did_elimination;
1496 chain->need_reload = n_reloads > 0;
1497 chain->need_operand_change = operands_changed;
1499 /* Discard any register replacements done. */
1500 if (did_elimination)
1502 obstack_free (&reload_obstack, reload_insn_firstobj);
1503 PATTERN (insn) = old_body;
1504 INSN_CODE (insn) = old_code;
1505 REG_NOTES (insn) = old_notes;
1506 something_needs_elimination = 1;
1509 something_needs_operands_changed |= operands_changed;
1513 copy_reloads (chain);
1514 *pprev_reload = chain;
1515 pprev_reload = &chain->next_need_reload;
1522 /* Comparison function for qsort to decide which of two reloads
1523 should be handled first. *P1 and *P2 are the reload numbers. */
1526 reload_reg_class_lower (const void *r1p, const void *r2p)
1528 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1531 /* Consider required reloads before optional ones. */
1532 t = rld[r1].optional - rld[r2].optional;
1536 /* Count all solitary classes before non-solitary ones. */
1537 t = ((reg_class_size[(int) rld[r2].class] == 1)
1538 - (reg_class_size[(int) rld[r1].class] == 1));
1542 /* Aside from solitaires, consider all multi-reg groups first. */
1543 t = rld[r2].nregs - rld[r1].nregs;
1547 /* Consider reloads in order of increasing reg-class number. */
1548 t = (int) rld[r1].class - (int) rld[r2].class;
1552 /* If reloads are equally urgent, sort by reload number,
1553 so that the results of qsort leave nothing to chance. */
1557 /* The cost of spilling each hard reg. */
1558 static int spill_cost[FIRST_PSEUDO_REGISTER];
1560 /* When spilling multiple hard registers, we use SPILL_COST for the first
1561 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1562 only the first hard reg for a multi-reg pseudo. */
1563 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1565 /* Update the spill cost arrays, considering that pseudo REG is live. */
1568 count_pseudo (int reg)
1570 int freq = REG_FREQ (reg);
1571 int r = reg_renumber[reg];
1574 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1575 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1578 SET_REGNO_REG_SET (&pseudos_counted, reg);
1583 spill_add_cost[r] += freq;
1585 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1587 spill_cost[r + nregs] += freq;
1590 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1591 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1594 order_regs_for_reload (struct insn_chain *chain)
1597 HARD_REG_SET used_by_pseudos;
1598 HARD_REG_SET used_by_pseudos2;
1600 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1602 memset (spill_cost, 0, sizeof spill_cost);
1603 memset (spill_add_cost, 0, sizeof spill_add_cost);
1605 /* Count number of uses of each hard reg by pseudo regs allocated to it
1606 and then order them by decreasing use. First exclude hard registers
1607 that are live in or across this insn. */
1609 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1610 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1611 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1612 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1614 /* Now find out which pseudos are allocated to it, and update
1616 CLEAR_REG_SET (&pseudos_counted);
1618 EXECUTE_IF_SET_IN_REG_SET
1619 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1623 EXECUTE_IF_SET_IN_REG_SET
1624 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1628 CLEAR_REG_SET (&pseudos_counted);
1631 /* Vector of reload-numbers showing the order in which the reloads should
1633 static short reload_order[MAX_RELOADS];
1635 /* This is used to keep track of the spill regs used in one insn. */
1636 static HARD_REG_SET used_spill_regs_local;
1638 /* We decided to spill hard register SPILLED, which has a size of
1639 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1640 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1641 update SPILL_COST/SPILL_ADD_COST. */
1644 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1646 int r = reg_renumber[reg];
1647 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1649 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1650 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1653 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1655 spill_add_cost[r] -= REG_FREQ (reg);
1657 spill_cost[r + nregs] -= REG_FREQ (reg);
1660 /* Find reload register to use for reload number ORDER. */
1663 find_reg (struct insn_chain *chain, int order)
1665 int rnum = reload_order[order];
1666 struct reload *rl = rld + rnum;
1667 int best_cost = INT_MAX;
1671 HARD_REG_SET not_usable;
1672 HARD_REG_SET used_by_other_reload;
1674 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1675 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1676 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1678 CLEAR_HARD_REG_SET (used_by_other_reload);
1679 for (k = 0; k < order; k++)
1681 int other = reload_order[k];
1683 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1684 for (j = 0; j < rld[other].nregs; j++)
1685 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1688 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1690 unsigned int regno = i;
1692 if (! TEST_HARD_REG_BIT (not_usable, regno)
1693 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1694 && HARD_REGNO_MODE_OK (regno, rl->mode))
1696 int this_cost = spill_cost[regno];
1698 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1700 for (j = 1; j < this_nregs; j++)
1702 this_cost += spill_add_cost[regno + j];
1703 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1704 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1709 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1711 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1713 if (this_cost < best_cost
1714 /* Among registers with equal cost, prefer caller-saved ones, or
1715 use REG_ALLOC_ORDER if it is defined. */
1716 || (this_cost == best_cost
1717 #ifdef REG_ALLOC_ORDER
1718 && (inv_reg_alloc_order[regno]
1719 < inv_reg_alloc_order[best_reg])
1721 && call_used_regs[regno]
1722 && ! call_used_regs[best_reg]
1727 best_cost = this_cost;
1735 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1737 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1738 rl->regno = best_reg;
1740 EXECUTE_IF_SET_IN_REG_SET
1741 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1743 count_spilled_pseudo (best_reg, rl->nregs, j);
1746 EXECUTE_IF_SET_IN_REG_SET
1747 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1749 count_spilled_pseudo (best_reg, rl->nregs, j);
1752 for (i = 0; i < rl->nregs; i++)
1754 if (spill_cost[best_reg + i] != 0
1755 || spill_add_cost[best_reg + i] != 0)
1757 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1762 /* Find more reload regs to satisfy the remaining need of an insn, which
1764 Do it by ascending class number, since otherwise a reg
1765 might be spilled for a big class and might fail to count
1766 for a smaller class even though it belongs to that class. */
1769 find_reload_regs (struct insn_chain *chain)
1773 /* In order to be certain of getting the registers we need,
1774 we must sort the reloads into order of increasing register class.
1775 Then our grabbing of reload registers will parallel the process
1776 that provided the reload registers. */
1777 for (i = 0; i < chain->n_reloads; i++)
1779 /* Show whether this reload already has a hard reg. */
1780 if (chain->rld[i].reg_rtx)
1782 int regno = REGNO (chain->rld[i].reg_rtx);
1783 chain->rld[i].regno = regno;
1785 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1788 chain->rld[i].regno = -1;
1789 reload_order[i] = i;
1792 n_reloads = chain->n_reloads;
1793 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1795 CLEAR_HARD_REG_SET (used_spill_regs_local);
1798 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1800 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1802 /* Compute the order of preference for hard registers to spill. */
1804 order_regs_for_reload (chain);
1806 for (i = 0; i < n_reloads; i++)
1808 int r = reload_order[i];
1810 /* Ignore reloads that got marked inoperative. */
1811 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1812 && ! rld[r].optional
1813 && rld[r].regno == -1)
1814 if (! find_reg (chain, i))
1816 spill_failure (chain->insn, rld[r].class);
1822 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1823 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1825 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1829 select_reload_regs (void)
1831 struct insn_chain *chain;
1833 /* Try to satisfy the needs for each insn. */
1834 for (chain = insns_need_reload; chain != 0;
1835 chain = chain->next_need_reload)
1836 find_reload_regs (chain);
1839 /* Delete all insns that were inserted by emit_caller_save_insns during
1842 delete_caller_save_insns (void)
1844 struct insn_chain *c = reload_insn_chain;
1848 while (c != 0 && c->is_caller_save_insn)
1850 struct insn_chain *next = c->next;
1853 if (c == reload_insn_chain)
1854 reload_insn_chain = next;
1858 next->prev = c->prev;
1860 c->prev->next = next;
1861 c->next = unused_insn_chains;
1862 unused_insn_chains = c;
1870 /* Handle the failure to find a register to spill.
1871 INSN should be one of the insns which needed this particular spill reg. */
1874 spill_failure (rtx insn, enum reg_class class)
1876 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1877 if (asm_noperands (PATTERN (insn)) >= 0)
1878 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1879 reg_class_names[class]);
1882 error ("unable to find a register to spill in class `%s'",
1883 reg_class_names[class]);
1884 fatal_insn ("this is the insn:", insn);
1888 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1889 data that is dead in INSN. */
1892 delete_dead_insn (rtx insn)
1894 rtx prev = prev_real_insn (insn);
1897 /* If the previous insn sets a register that dies in our insn, delete it
1899 if (prev && GET_CODE (PATTERN (prev)) == SET
1900 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1901 && reg_mentioned_p (prev_dest, PATTERN (insn))
1902 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1903 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1904 delete_dead_insn (prev);
1906 PUT_CODE (insn, NOTE);
1907 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1908 NOTE_SOURCE_FILE (insn) = 0;
1911 /* Modify the home of pseudo-reg I.
1912 The new home is present in reg_renumber[I].
1914 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1915 or it may be -1, meaning there is none or it is not relevant.
1916 This is used so that all pseudos spilled from a given hard reg
1917 can share one stack slot. */
1920 alter_reg (int i, int from_reg)
1922 /* When outputting an inline function, this can happen
1923 for a reg that isn't actually used. */
1924 if (regno_reg_rtx[i] == 0)
1927 /* If the reg got changed to a MEM at rtl-generation time,
1929 if (GET_CODE (regno_reg_rtx[i]) != REG)
1932 /* Modify the reg-rtx to contain the new hard reg
1933 number or else to contain its pseudo reg number. */
1934 REGNO (regno_reg_rtx[i])
1935 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1937 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1938 allocate a stack slot for it. */
1940 if (reg_renumber[i] < 0
1941 && REG_N_REFS (i) > 0
1942 && reg_equiv_constant[i] == 0
1943 && reg_equiv_memory_loc[i] == 0)
1946 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1947 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1950 /* Each pseudo reg has an inherent size which comes from its own mode,
1951 and a total size which provides room for paradoxical subregs
1952 which refer to the pseudo reg in wider modes.
1954 We can use a slot already allocated if it provides both
1955 enough inherent space and enough total space.
1956 Otherwise, we allocate a new slot, making sure that it has no less
1957 inherent space, and no less total space, then the previous slot. */
1960 /* No known place to spill from => no slot to reuse. */
1961 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1962 inherent_size == total_size ? 0 : -1);
1963 if (BYTES_BIG_ENDIAN)
1964 /* Cancel the big-endian correction done in assign_stack_local.
1965 Get the address of the beginning of the slot.
1966 This is so we can do a big-endian correction unconditionally
1968 adjust = inherent_size - total_size;
1970 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1972 /* Nothing can alias this slot except this pseudo. */
1973 set_mem_alias_set (x, new_alias_set ());
1976 /* Reuse a stack slot if possible. */
1977 else if (spill_stack_slot[from_reg] != 0
1978 && spill_stack_slot_width[from_reg] >= total_size
1979 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1981 x = spill_stack_slot[from_reg];
1983 /* Allocate a bigger slot. */
1986 /* Compute maximum size needed, both for inherent size
1987 and for total size. */
1988 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1991 if (spill_stack_slot[from_reg])
1993 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1995 mode = GET_MODE (spill_stack_slot[from_reg]);
1996 if (spill_stack_slot_width[from_reg] > total_size)
1997 total_size = spill_stack_slot_width[from_reg];
2000 /* Make a slot with that size. */
2001 x = assign_stack_local (mode, total_size,
2002 inherent_size == total_size ? 0 : -1);
2005 /* All pseudos mapped to this slot can alias each other. */
2006 if (spill_stack_slot[from_reg])
2007 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2009 set_mem_alias_set (x, new_alias_set ());
2011 if (BYTES_BIG_ENDIAN)
2013 /* Cancel the big-endian correction done in assign_stack_local.
2014 Get the address of the beginning of the slot.
2015 This is so we can do a big-endian correction unconditionally
2017 adjust = GET_MODE_SIZE (mode) - total_size;
2020 = adjust_address_nv (x, mode_for_size (total_size
2026 spill_stack_slot[from_reg] = stack_slot;
2027 spill_stack_slot_width[from_reg] = total_size;
2030 /* On a big endian machine, the "address" of the slot
2031 is the address of the low part that fits its inherent mode. */
2032 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2033 adjust += (total_size - inherent_size);
2035 /* If we have any adjustment to make, or if the stack slot is the
2036 wrong mode, make a new stack slot. */
2037 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2039 /* If we have a decl for the original register, set it for the
2040 memory. If this is a shared MEM, make a copy. */
2041 if (REG_EXPR (regno_reg_rtx[i])
2042 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2044 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2046 /* We can do this only for the DECLs home pseudo, not for
2047 any copies of it, since otherwise when the stack slot
2048 is reused, nonoverlapping_memrefs_p might think they
2050 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i)
2052 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2055 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2059 /* Save the stack slot for later. */
2060 reg_equiv_memory_loc[i] = x;
2064 /* Mark the slots in regs_ever_live for the hard regs
2065 used by pseudo-reg number REGNO. */
2068 mark_home_live (int regno)
2072 i = reg_renumber[regno];
2075 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2077 regs_ever_live[i++] = 1;
2080 /* This function handles the tracking of elimination offsets around branches.
2082 X is a piece of RTL being scanned.
2084 INSN is the insn that it came from, if any.
2086 INITIAL_P is nonzero if we are to set the offset to be the initial
2087 offset and zero if we are setting the offset of the label to be the
2091 set_label_offsets (rtx x, rtx insn, int initial_p)
2093 enum rtx_code code = GET_CODE (x);
2096 struct elim_table *p;
2101 if (LABEL_REF_NONLOCAL_P (x))
2106 /* ... fall through ... */
2109 /* If we know nothing about this label, set the desired offsets. Note
2110 that this sets the offset at a label to be the offset before a label
2111 if we don't know anything about the label. This is not correct for
2112 the label after a BARRIER, but is the best guess we can make. If
2113 we guessed wrong, we will suppress an elimination that might have
2114 been possible had we been able to guess correctly. */
2116 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2118 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2119 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2120 = (initial_p ? reg_eliminate[i].initial_offset
2121 : reg_eliminate[i].offset);
2122 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2125 /* Otherwise, if this is the definition of a label and it is
2126 preceded by a BARRIER, set our offsets to the known offset of
2130 && (tem = prev_nonnote_insn (insn)) != 0
2131 && GET_CODE (tem) == BARRIER)
2132 set_offsets_for_label (insn);
2134 /* If neither of the above cases is true, compare each offset
2135 with those previously recorded and suppress any eliminations
2136 where the offsets disagree. */
2138 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2139 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2140 != (initial_p ? reg_eliminate[i].initial_offset
2141 : reg_eliminate[i].offset))
2142 reg_eliminate[i].can_eliminate = 0;
2147 set_label_offsets (PATTERN (insn), insn, initial_p);
2149 /* ... fall through ... */
2153 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2154 and hence must have all eliminations at their initial offsets. */
2155 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2156 if (REG_NOTE_KIND (tem) == REG_LABEL)
2157 set_label_offsets (XEXP (tem, 0), insn, 1);
2163 /* Each of the labels in the parallel or address vector must be
2164 at their initial offsets. We want the first field for PARALLEL
2165 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2167 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2168 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2173 /* We only care about setting PC. If the source is not RETURN,
2174 IF_THEN_ELSE, or a label, disable any eliminations not at
2175 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2176 isn't one of those possibilities. For branches to a label,
2177 call ourselves recursively.
2179 Note that this can disable elimination unnecessarily when we have
2180 a non-local goto since it will look like a non-constant jump to
2181 someplace in the current function. This isn't a significant
2182 problem since such jumps will normally be when all elimination
2183 pairs are back to their initial offsets. */
2185 if (SET_DEST (x) != pc_rtx)
2188 switch (GET_CODE (SET_SRC (x)))
2195 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2199 tem = XEXP (SET_SRC (x), 1);
2200 if (GET_CODE (tem) == LABEL_REF)
2201 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2202 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2205 tem = XEXP (SET_SRC (x), 2);
2206 if (GET_CODE (tem) == LABEL_REF)
2207 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2208 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2216 /* If we reach here, all eliminations must be at their initial
2217 offset because we are doing a jump to a variable address. */
2218 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2219 if (p->offset != p->initial_offset)
2220 p->can_eliminate = 0;
2228 /* Scan X and replace any eliminable registers (such as fp) with a
2229 replacement (such as sp), plus an offset.
2231 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2232 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2233 MEM, we are allowed to replace a sum of a register and the constant zero
2234 with the register, which we cannot do outside a MEM. In addition, we need
2235 to record the fact that a register is referenced outside a MEM.
2237 If INSN is an insn, it is the insn containing X. If we replace a REG
2238 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2239 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2240 the REG is being modified.
2242 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2243 That's used when we eliminate in expressions stored in notes.
2244 This means, do not set ref_outside_mem even if the reference
2247 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2248 replacements done assuming all offsets are at their initial values. If
2249 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2250 encounter, return the actual location so that find_reloads will do
2251 the proper thing. */
2254 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2256 enum rtx_code code = GET_CODE (x);
2257 struct elim_table *ep;
2264 if (! current_function_decl)
2284 /* This is only for the benefit of the debugging backends, which call
2285 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2286 removed after CSE. */
2287 new = eliminate_regs (XEXP (x, 0), 0, insn);
2288 if (GET_CODE (new) == MEM)
2289 return XEXP (new, 0);
2295 /* First handle the case where we encounter a bare register that
2296 is eliminable. Replace it with a PLUS. */
2297 if (regno < FIRST_PSEUDO_REGISTER)
2299 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2301 if (ep->from_rtx == x && ep->can_eliminate)
2302 return plus_constant (ep->to_rtx, ep->previous_offset);
2305 else if (reg_renumber && reg_renumber[regno] < 0
2306 && reg_equiv_constant && reg_equiv_constant[regno]
2307 && ! CONSTANT_P (reg_equiv_constant[regno]))
2308 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2312 /* You might think handling MINUS in a manner similar to PLUS is a
2313 good idea. It is not. It has been tried multiple times and every
2314 time the change has had to have been reverted.
2316 Other parts of reload know a PLUS is special (gen_reload for example)
2317 and require special code to handle code a reloaded PLUS operand.
2319 Also consider backends where the flags register is clobbered by a
2320 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2321 lea instruction comes to mind). If we try to reload a MINUS, we
2322 may kill the flags register that was holding a useful value.
2324 So, please before trying to handle MINUS, consider reload as a
2325 whole instead of this little section as well as the backend issues. */
2327 /* If this is the sum of an eliminable register and a constant, rework
2329 if (GET_CODE (XEXP (x, 0)) == REG
2330 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2331 && CONSTANT_P (XEXP (x, 1)))
2333 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2335 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2337 /* The only time we want to replace a PLUS with a REG (this
2338 occurs when the constant operand of the PLUS is the negative
2339 of the offset) is when we are inside a MEM. We won't want
2340 to do so at other times because that would change the
2341 structure of the insn in a way that reload can't handle.
2342 We special-case the commonest situation in
2343 eliminate_regs_in_insn, so just replace a PLUS with a
2344 PLUS here, unless inside a MEM. */
2345 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2346 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2349 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2350 plus_constant (XEXP (x, 1),
2351 ep->previous_offset));
2354 /* If the register is not eliminable, we are done since the other
2355 operand is a constant. */
2359 /* If this is part of an address, we want to bring any constant to the
2360 outermost PLUS. We will do this by doing register replacement in
2361 our operands and seeing if a constant shows up in one of them.
2363 Note that there is no risk of modifying the structure of the insn,
2364 since we only get called for its operands, thus we are either
2365 modifying the address inside a MEM, or something like an address
2366 operand of a load-address insn. */
2369 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2370 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2372 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2374 /* If one side is a PLUS and the other side is a pseudo that
2375 didn't get a hard register but has a reg_equiv_constant,
2376 we must replace the constant here since it may no longer
2377 be in the position of any operand. */
2378 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2379 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2380 && reg_renumber[REGNO (new1)] < 0
2381 && reg_equiv_constant != 0
2382 && reg_equiv_constant[REGNO (new1)] != 0)
2383 new1 = reg_equiv_constant[REGNO (new1)];
2384 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2385 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2386 && reg_renumber[REGNO (new0)] < 0
2387 && reg_equiv_constant[REGNO (new0)] != 0)
2388 new0 = reg_equiv_constant[REGNO (new0)];
2390 new = form_sum (new0, new1);
2392 /* As above, if we are not inside a MEM we do not want to
2393 turn a PLUS into something else. We might try to do so here
2394 for an addition of 0 if we aren't optimizing. */
2395 if (! mem_mode && GET_CODE (new) != PLUS)
2396 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2404 /* If this is the product of an eliminable register and a
2405 constant, apply the distribute law and move the constant out
2406 so that we have (plus (mult ..) ..). This is needed in order
2407 to keep load-address insns valid. This case is pathological.
2408 We ignore the possibility of overflow here. */
2409 if (GET_CODE (XEXP (x, 0)) == REG
2410 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2411 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2412 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2414 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2417 /* Refs inside notes don't count for this purpose. */
2418 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2419 || GET_CODE (insn) == INSN_LIST)))
2420 ep->ref_outside_mem = 1;
2423 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2424 ep->previous_offset * INTVAL (XEXP (x, 1)));
2427 /* ... fall through ... */
2431 /* See comments before PLUS about handling MINUS. */
2433 case DIV: case UDIV:
2434 case MOD: case UMOD:
2435 case AND: case IOR: case XOR:
2436 case ROTATERT: case ROTATE:
2437 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2439 case GE: case GT: case GEU: case GTU:
2440 case LE: case LT: case LEU: case LTU:
2442 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2444 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2446 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2447 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2452 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2455 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2456 if (new != XEXP (x, 0))
2458 /* If this is a REG_DEAD note, it is not valid anymore.
2459 Using the eliminated version could result in creating a
2460 REG_DEAD note for the stack or frame pointer. */
2461 if (GET_MODE (x) == REG_DEAD)
2463 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2466 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2470 /* ... fall through ... */
2473 /* Now do eliminations in the rest of the chain. If this was
2474 an EXPR_LIST, this might result in allocating more memory than is
2475 strictly needed, but it simplifies the code. */
2478 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2479 if (new != XEXP (x, 1))
2481 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2489 case STRICT_LOW_PART:
2491 case SIGN_EXTEND: case ZERO_EXTEND:
2492 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2493 case FLOAT: case FIX:
2494 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2502 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2503 if (new != XEXP (x, 0))
2504 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2508 /* Similar to above processing, but preserve SUBREG_BYTE.
2509 Convert (subreg (mem)) to (mem) if not paradoxical.
2510 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2511 pseudo didn't get a hard reg, we must replace this with the
2512 eliminated version of the memory location because push_reload
2513 may do the replacement in certain circumstances. */
2514 if (GET_CODE (SUBREG_REG (x)) == REG
2515 && (GET_MODE_SIZE (GET_MODE (x))
2516 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2517 && reg_equiv_memory_loc != 0
2518 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2520 new = SUBREG_REG (x);
2523 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2525 if (new != SUBREG_REG (x))
2527 int x_size = GET_MODE_SIZE (GET_MODE (x));
2528 int new_size = GET_MODE_SIZE (GET_MODE (new));
2530 if (GET_CODE (new) == MEM
2531 && ((x_size < new_size
2532 #ifdef WORD_REGISTER_OPERATIONS
2533 /* On these machines, combine can create rtl of the form
2534 (set (subreg:m1 (reg:m2 R) 0) ...)
2535 where m1 < m2, and expects something interesting to
2536 happen to the entire word. Moreover, it will use the
2537 (reg:m2 R) later, expecting all bits to be preserved.
2538 So if the number of words is the same, preserve the
2539 subreg so that push_reload can see it. */
2540 && ! ((x_size - 1) / UNITS_PER_WORD
2541 == (new_size -1 ) / UNITS_PER_WORD)
2544 || x_size == new_size)
2546 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2548 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2554 /* This is only for the benefit of the debugging backends, which call
2555 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2556 removed after CSE. */
2557 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2558 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2560 /* Our only special processing is to pass the mode of the MEM to our
2561 recursive call and copy the flags. While we are here, handle this
2562 case more efficiently. */
2564 replace_equiv_address_nv (x,
2565 eliminate_regs (XEXP (x, 0),
2566 GET_MODE (x), insn));
2569 /* Handle insn_list USE that a call to a pure function may generate. */
2570 new = eliminate_regs (XEXP (x, 0), 0, insn);
2571 if (new != XEXP (x, 0))
2572 return gen_rtx_USE (GET_MODE (x), new);
2584 /* Process each of our operands recursively. If any have changed, make a
2586 fmt = GET_RTX_FORMAT (code);
2587 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2591 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2592 if (new != XEXP (x, i) && ! copied)
2594 rtx new_x = rtx_alloc (code);
2595 memcpy (new_x, x, RTX_SIZE (code));
2601 else if (*fmt == 'E')
2604 for (j = 0; j < XVECLEN (x, i); j++)
2606 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2607 if (new != XVECEXP (x, i, j) && ! copied_vec)
2609 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2613 rtx new_x = rtx_alloc (code);
2614 memcpy (new_x, x, RTX_SIZE (code));
2618 XVEC (x, i) = new_v;
2621 XVECEXP (x, i, j) = new;
2629 /* Scan rtx X for modifications of elimination target registers. Update
2630 the table of eliminables to reflect the changed state. MEM_MODE is
2631 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2634 elimination_effects (rtx x, enum machine_mode mem_mode)
2636 enum rtx_code code = GET_CODE (x);
2637 struct elim_table *ep;
2664 /* First handle the case where we encounter a bare register that
2665 is eliminable. Replace it with a PLUS. */
2666 if (regno < FIRST_PSEUDO_REGISTER)
2668 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2670 if (ep->from_rtx == x && ep->can_eliminate)
2673 ep->ref_outside_mem = 1;
2678 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2679 && reg_equiv_constant[regno]
2680 && ! function_invariant_p (reg_equiv_constant[regno]))
2681 elimination_effects (reg_equiv_constant[regno], mem_mode);
2690 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2691 if (ep->to_rtx == XEXP (x, 0))
2693 int size = GET_MODE_SIZE (mem_mode);
2695 /* If more bytes than MEM_MODE are pushed, account for them. */
2696 #ifdef PUSH_ROUNDING
2697 if (ep->to_rtx == stack_pointer_rtx)
2698 size = PUSH_ROUNDING (size);
2700 if (code == PRE_DEC || code == POST_DEC)
2702 else if (code == PRE_INC || code == POST_INC)
2704 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2705 && GET_CODE (XEXP (x, 1)) == PLUS
2706 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2707 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2708 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2711 /* These two aren't unary operators. */
2712 if (code == POST_MODIFY || code == PRE_MODIFY)
2715 /* Fall through to generic unary operation case. */
2716 case STRICT_LOW_PART:
2718 case SIGN_EXTEND: case ZERO_EXTEND:
2719 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2720 case FLOAT: case FIX:
2721 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2729 elimination_effects (XEXP (x, 0), mem_mode);
2733 if (GET_CODE (SUBREG_REG (x)) == REG
2734 && (GET_MODE_SIZE (GET_MODE (x))
2735 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2736 && reg_equiv_memory_loc != 0
2737 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2740 elimination_effects (SUBREG_REG (x), mem_mode);
2744 /* If using a register that is the source of an eliminate we still
2745 think can be performed, note it cannot be performed since we don't
2746 know how this register is used. */
2747 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2748 if (ep->from_rtx == XEXP (x, 0))
2749 ep->can_eliminate = 0;
2751 elimination_effects (XEXP (x, 0), mem_mode);
2755 /* If clobbering a register that is the replacement register for an
2756 elimination we still think can be performed, note that it cannot
2757 be performed. Otherwise, we need not be concerned about it. */
2758 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2759 if (ep->to_rtx == XEXP (x, 0))
2760 ep->can_eliminate = 0;
2762 elimination_effects (XEXP (x, 0), mem_mode);
2766 /* Check for setting a register that we know about. */
2767 if (GET_CODE (SET_DEST (x)) == REG)
2769 /* See if this is setting the replacement register for an
2772 If DEST is the hard frame pointer, we do nothing because we
2773 assume that all assignments to the frame pointer are for
2774 non-local gotos and are being done at a time when they are valid
2775 and do not disturb anything else. Some machines want to
2776 eliminate a fake argument pointer (or even a fake frame pointer)
2777 with either the real frame or the stack pointer. Assignments to
2778 the hard frame pointer must not prevent this elimination. */
2780 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2782 if (ep->to_rtx == SET_DEST (x)
2783 && SET_DEST (x) != hard_frame_pointer_rtx)
2785 /* If it is being incremented, adjust the offset. Otherwise,
2786 this elimination can't be done. */
2787 rtx src = SET_SRC (x);
2789 if (GET_CODE (src) == PLUS
2790 && XEXP (src, 0) == SET_DEST (x)
2791 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2792 ep->offset -= INTVAL (XEXP (src, 1));
2794 ep->can_eliminate = 0;
2798 elimination_effects (SET_DEST (x), 0);
2799 elimination_effects (SET_SRC (x), 0);
2803 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2806 /* Our only special processing is to pass the mode of the MEM to our
2808 elimination_effects (XEXP (x, 0), GET_MODE (x));
2815 fmt = GET_RTX_FORMAT (code);
2816 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2819 elimination_effects (XEXP (x, i), mem_mode);
2820 else if (*fmt == 'E')
2821 for (j = 0; j < XVECLEN (x, i); j++)
2822 elimination_effects (XVECEXP (x, i, j), mem_mode);
2826 /* Descend through rtx X and verify that no references to eliminable registers
2827 remain. If any do remain, mark the involved register as not
2831 check_eliminable_occurrences (rtx x)
2840 code = GET_CODE (x);
2842 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2844 struct elim_table *ep;
2846 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2847 if (ep->from_rtx == x && ep->can_eliminate)
2848 ep->can_eliminate = 0;
2852 fmt = GET_RTX_FORMAT (code);
2853 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2856 check_eliminable_occurrences (XEXP (x, i));
2857 else if (*fmt == 'E')
2860 for (j = 0; j < XVECLEN (x, i); j++)
2861 check_eliminable_occurrences (XVECEXP (x, i, j));
2866 /* Scan INSN and eliminate all eliminable registers in it.
2868 If REPLACE is nonzero, do the replacement destructively. Also
2869 delete the insn as dead it if it is setting an eliminable register.
2871 If REPLACE is zero, do all our allocations in reload_obstack.
2873 If no eliminations were done and this insn doesn't require any elimination
2874 processing (these are not identical conditions: it might be updating sp,
2875 but not referencing fp; this needs to be seen during reload_as_needed so
2876 that the offset between fp and sp can be taken into consideration), zero
2877 is returned. Otherwise, 1 is returned. */
2880 eliminate_regs_in_insn (rtx insn, int replace)
2882 int icode = recog_memoized (insn);
2883 rtx old_body = PATTERN (insn);
2884 int insn_is_asm = asm_noperands (old_body) >= 0;
2885 rtx old_set = single_set (insn);
2889 rtx substed_operand[MAX_RECOG_OPERANDS];
2890 rtx orig_operand[MAX_RECOG_OPERANDS];
2891 struct elim_table *ep;
2893 if (! insn_is_asm && icode < 0)
2895 if (GET_CODE (PATTERN (insn)) == USE
2896 || GET_CODE (PATTERN (insn)) == CLOBBER
2897 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2898 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2899 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2904 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2905 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2907 /* Check for setting an eliminable register. */
2908 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2909 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2911 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2912 /* If this is setting the frame pointer register to the
2913 hardware frame pointer register and this is an elimination
2914 that will be done (tested above), this insn is really
2915 adjusting the frame pointer downward to compensate for
2916 the adjustment done before a nonlocal goto. */
2917 if (ep->from == FRAME_POINTER_REGNUM
2918 && ep->to == HARD_FRAME_POINTER_REGNUM)
2920 rtx base = SET_SRC (old_set);
2921 rtx base_insn = insn;
2922 HOST_WIDE_INT offset = 0;
2924 while (base != ep->to_rtx)
2926 rtx prev_insn, prev_set;
2928 if (GET_CODE (base) == PLUS
2929 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2931 offset += INTVAL (XEXP (base, 1));
2932 base = XEXP (base, 0);
2934 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2935 && (prev_set = single_set (prev_insn)) != 0
2936 && rtx_equal_p (SET_DEST (prev_set), base))
2938 base = SET_SRC (prev_set);
2939 base_insn = prev_insn;
2945 if (base == ep->to_rtx)
2948 = plus_constant (ep->to_rtx, offset - ep->offset);
2950 new_body = old_body;
2953 new_body = copy_insn (old_body);
2954 if (REG_NOTES (insn))
2955 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2957 PATTERN (insn) = new_body;
2958 old_set = single_set (insn);
2960 /* First see if this insn remains valid when we
2961 make the change. If not, keep the INSN_CODE
2962 the same and let reload fit it up. */
2963 validate_change (insn, &SET_SRC (old_set), src, 1);
2964 validate_change (insn, &SET_DEST (old_set),
2966 if (! apply_change_group ())
2968 SET_SRC (old_set) = src;
2969 SET_DEST (old_set) = ep->to_rtx;
2978 /* In this case this insn isn't serving a useful purpose. We
2979 will delete it in reload_as_needed once we know that this
2980 elimination is, in fact, being done.
2982 If REPLACE isn't set, we can't delete this insn, but needn't
2983 process it since it won't be used unless something changes. */
2986 delete_dead_insn (insn);
2994 /* We allow one special case which happens to work on all machines we
2995 currently support: a single set with the source being a PLUS of an
2996 eliminable register and a constant. */
2998 && GET_CODE (SET_DEST (old_set)) == REG
2999 && GET_CODE (SET_SRC (old_set)) == PLUS
3000 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3001 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3002 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3004 rtx reg = XEXP (SET_SRC (old_set), 0);
3005 HOST_WIDE_INT offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3007 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3008 if (ep->from_rtx == reg && ep->can_eliminate)
3010 offset += ep->offset;
3015 /* We assume here that if we need a PARALLEL with
3016 CLOBBERs for this assignment, we can do with the
3017 MATCH_SCRATCHes that add_clobbers allocates.
3018 There's not much we can do if that doesn't work. */
3019 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3023 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3026 rtvec vec = rtvec_alloc (num_clobbers + 1);
3028 vec->elem[0] = PATTERN (insn);
3029 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3030 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3032 if (INSN_CODE (insn) < 0)
3037 new_body = old_body;
3040 new_body = copy_insn (old_body);
3041 if (REG_NOTES (insn))
3042 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3044 PATTERN (insn) = new_body;
3045 old_set = single_set (insn);
3047 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3048 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3051 /* This can't have an effect on elimination offsets, so skip right
3057 /* Determine the effects of this insn on elimination offsets. */
3058 elimination_effects (old_body, 0);
3060 /* Eliminate all eliminable registers occurring in operands that
3061 can be handled by reload. */
3062 extract_insn (insn);
3063 for (i = 0; i < recog_data.n_operands; i++)
3065 orig_operand[i] = recog_data.operand[i];
3066 substed_operand[i] = recog_data.operand[i];
3068 /* For an asm statement, every operand is eliminable. */
3069 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3071 /* Check for setting a register that we know about. */
3072 if (recog_data.operand_type[i] != OP_IN
3073 && GET_CODE (orig_operand[i]) == REG)
3075 /* If we are assigning to a register that can be eliminated, it
3076 must be as part of a PARALLEL, since the code above handles
3077 single SETs. We must indicate that we can no longer
3078 eliminate this reg. */
3079 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3081 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3082 ep->can_eliminate = 0;
3085 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3086 replace ? insn : NULL_RTX);
3087 if (substed_operand[i] != orig_operand[i])
3089 /* Terminate the search in check_eliminable_occurrences at
3091 *recog_data.operand_loc[i] = 0;
3093 /* If an output operand changed from a REG to a MEM and INSN is an
3094 insn, write a CLOBBER insn. */
3095 if (recog_data.operand_type[i] != OP_IN
3096 && GET_CODE (orig_operand[i]) == REG
3097 && GET_CODE (substed_operand[i]) == MEM
3099 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3104 for (i = 0; i < recog_data.n_dups; i++)
3105 *recog_data.dup_loc[i]
3106 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3108 /* If any eliminable remain, they aren't eliminable anymore. */
3109 check_eliminable_occurrences (old_body);
3111 /* Substitute the operands; the new values are in the substed_operand
3113 for (i = 0; i < recog_data.n_operands; i++)
3114 *recog_data.operand_loc[i] = substed_operand[i];
3115 for (i = 0; i < recog_data.n_dups; i++)
3116 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3118 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3119 re-recognize the insn. We do this in case we had a simple addition
3120 but now can do this as a load-address. This saves an insn in this
3122 If re-recognition fails, the old insn code number will still be used,
3123 and some register operands may have changed into PLUS expressions.
3124 These will be handled by find_reloads by loading them into a register
3129 /* If we aren't replacing things permanently and we changed something,
3130 make another copy to ensure that all the RTL is new. Otherwise
3131 things can go wrong if find_reload swaps commutative operands
3132 and one is inside RTL that has been copied while the other is not. */
3133 new_body = old_body;
3136 new_body = copy_insn (old_body);
3137 if (REG_NOTES (insn))
3138 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3140 PATTERN (insn) = new_body;
3142 /* If we had a move insn but now we don't, rerecognize it. This will
3143 cause spurious re-recognition if the old move had a PARALLEL since
3144 the new one still will, but we can't call single_set without
3145 having put NEW_BODY into the insn and the re-recognition won't
3146 hurt in this rare case. */
3147 /* ??? Why this huge if statement - why don't we just rerecognize the
3151 && ((GET_CODE (SET_SRC (old_set)) == REG
3152 && (GET_CODE (new_body) != SET
3153 || GET_CODE (SET_SRC (new_body)) != REG))
3154 /* If this was a load from or store to memory, compare
3155 the MEM in recog_data.operand to the one in the insn.
3156 If they are not equal, then rerecognize the insn. */
3158 && ((GET_CODE (SET_SRC (old_set)) == MEM
3159 && SET_SRC (old_set) != recog_data.operand[1])
3160 || (GET_CODE (SET_DEST (old_set)) == MEM
3161 && SET_DEST (old_set) != recog_data.operand[0])))
3162 /* If this was an add insn before, rerecognize. */
3163 || GET_CODE (SET_SRC (old_set)) == PLUS))
3165 int new_icode = recog (PATTERN (insn), insn, 0);
3167 INSN_CODE (insn) = icode;
3171 /* Restore the old body. If there were any changes to it, we made a copy
3172 of it while the changes were still in place, so we'll correctly return
3173 a modified insn below. */
3176 /* Restore the old body. */
3177 for (i = 0; i < recog_data.n_operands; i++)
3178 *recog_data.operand_loc[i] = orig_operand[i];
3179 for (i = 0; i < recog_data.n_dups; i++)
3180 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3183 /* Update all elimination pairs to reflect the status after the current
3184 insn. The changes we make were determined by the earlier call to
3185 elimination_effects.
3187 We also detect cases where register elimination cannot be done,
3188 namely, if a register would be both changed and referenced outside a MEM
3189 in the resulting insn since such an insn is often undefined and, even if
3190 not, we cannot know what meaning will be given to it. Note that it is
3191 valid to have a register used in an address in an insn that changes it
3192 (presumably with a pre- or post-increment or decrement).
3194 If anything changes, return nonzero. */
3196 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3198 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3199 ep->can_eliminate = 0;
3201 ep->ref_outside_mem = 0;
3203 if (ep->previous_offset != ep->offset)
3208 /* If we changed something, perform elimination in REG_NOTES. This is
3209 needed even when REPLACE is zero because a REG_DEAD note might refer
3210 to a register that we eliminate and could cause a different number
3211 of spill registers to be needed in the final reload pass than in
3213 if (val && REG_NOTES (insn) != 0)
3214 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3219 /* Loop through all elimination pairs.
3220 Recalculate the number not at initial offset.
3222 Compute the maximum offset (minimum offset if the stack does not
3223 grow downward) for each elimination pair. */
3226 update_eliminable_offsets (void)
3228 struct elim_table *ep;
3230 num_not_at_initial_offset = 0;
3231 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3233 ep->previous_offset = ep->offset;
3234 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3235 num_not_at_initial_offset++;
3239 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3240 replacement we currently believe is valid, mark it as not eliminable if X
3241 modifies DEST in any way other than by adding a constant integer to it.
3243 If DEST is the frame pointer, we do nothing because we assume that
3244 all assignments to the hard frame pointer are nonlocal gotos and are being
3245 done at a time when they are valid and do not disturb anything else.
3246 Some machines want to eliminate a fake argument pointer with either the
3247 frame or stack pointer. Assignments to the hard frame pointer must not
3248 prevent this elimination.
3250 Called via note_stores from reload before starting its passes to scan
3251 the insns of the function. */
3254 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3258 /* A SUBREG of a hard register here is just changing its mode. We should
3259 not see a SUBREG of an eliminable hard register, but check just in
3261 if (GET_CODE (dest) == SUBREG)
3262 dest = SUBREG_REG (dest);
3264 if (dest == hard_frame_pointer_rtx)
3267 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3268 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3269 && (GET_CODE (x) != SET
3270 || GET_CODE (SET_SRC (x)) != PLUS
3271 || XEXP (SET_SRC (x), 0) != dest
3272 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3274 reg_eliminate[i].can_eliminate_previous
3275 = reg_eliminate[i].can_eliminate = 0;
3280 /* Verify that the initial elimination offsets did not change since the
3281 last call to set_initial_elim_offsets. This is used to catch cases
3282 where something illegal happened during reload_as_needed that could
3283 cause incorrect code to be generated if we did not check for it. */
3286 verify_initial_elim_offsets (void)
3290 #ifdef ELIMINABLE_REGS
3291 struct elim_table *ep;
3293 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3295 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3296 if (t != ep->initial_offset)
3300 INITIAL_FRAME_POINTER_OFFSET (t);
3301 if (t != reg_eliminate[0].initial_offset)
3306 /* Reset all offsets on eliminable registers to their initial values. */
3309 set_initial_elim_offsets (void)
3311 struct elim_table *ep = reg_eliminate;
3313 #ifdef ELIMINABLE_REGS
3314 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3316 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3317 ep->previous_offset = ep->offset = ep->initial_offset;
3320 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3321 ep->previous_offset = ep->offset = ep->initial_offset;
3324 num_not_at_initial_offset = 0;
3327 /* Initialize the known label offsets.
3328 Set a known offset for each forced label to be at the initial offset
3329 of each elimination. We do this because we assume that all
3330 computed jumps occur from a location where each elimination is
3331 at its initial offset.
3332 For all other labels, show that we don't know the offsets. */
3335 set_initial_label_offsets (void)
3338 memset (offsets_known_at, 0, num_labels);
3340 for (x = forced_labels; x; x = XEXP (x, 1))
3342 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3345 /* Set all elimination offsets to the known values for the code label given
3349 set_offsets_for_label (rtx insn)
3352 int label_nr = CODE_LABEL_NUMBER (insn);
3353 struct elim_table *ep;
3355 num_not_at_initial_offset = 0;
3356 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3358 ep->offset = ep->previous_offset
3359 = offsets_at[label_nr - first_label_num][i];
3360 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3361 num_not_at_initial_offset++;
3365 /* See if anything that happened changes which eliminations are valid.
3366 For example, on the SPARC, whether or not the frame pointer can
3367 be eliminated can depend on what registers have been used. We need
3368 not check some conditions again (such as flag_omit_frame_pointer)
3369 since they can't have changed. */
3372 update_eliminables (HARD_REG_SET *pset)
3374 int previous_frame_pointer_needed = frame_pointer_needed;
3375 struct elim_table *ep;
3377 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3378 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3379 #ifdef ELIMINABLE_REGS
3380 || ! CAN_ELIMINATE (ep->from, ep->to)
3383 ep->can_eliminate = 0;
3385 /* Look for the case where we have discovered that we can't replace
3386 register A with register B and that means that we will now be
3387 trying to replace register A with register C. This means we can
3388 no longer replace register C with register B and we need to disable
3389 such an elimination, if it exists. This occurs often with A == ap,
3390 B == sp, and C == fp. */
3392 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3394 struct elim_table *op;
3397 if (! ep->can_eliminate && ep->can_eliminate_previous)
3399 /* Find the current elimination for ep->from, if there is a
3401 for (op = reg_eliminate;
3402 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3403 if (op->from == ep->from && op->can_eliminate)
3409 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3411 for (op = reg_eliminate;
3412 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3413 if (op->from == new_to && op->to == ep->to)
3414 op->can_eliminate = 0;
3418 /* See if any registers that we thought we could eliminate the previous
3419 time are no longer eliminable. If so, something has changed and we
3420 must spill the register. Also, recompute the number of eliminable
3421 registers and see if the frame pointer is needed; it is if there is
3422 no elimination of the frame pointer that we can perform. */
3424 frame_pointer_needed = 1;
3425 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3427 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3428 && ep->to != HARD_FRAME_POINTER_REGNUM)
3429 frame_pointer_needed = 0;
3431 if (! ep->can_eliminate && ep->can_eliminate_previous)
3433 ep->can_eliminate_previous = 0;
3434 SET_HARD_REG_BIT (*pset, ep->from);
3439 /* If we didn't need a frame pointer last time, but we do now, spill
3440 the hard frame pointer. */
3441 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3442 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3445 /* Initialize the table of registers to eliminate. */
3448 init_elim_table (void)
3450 struct elim_table *ep;
3451 #ifdef ELIMINABLE_REGS
3452 const struct elim_table_1 *ep1;
3456 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3458 /* Does this function require a frame pointer? */
3460 frame_pointer_needed = (! flag_omit_frame_pointer
3461 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3462 and restore sp for alloca. So we can't eliminate
3463 the frame pointer in that case. At some point,
3464 we should improve this by emitting the
3465 sp-adjusting insns for this case. */
3466 || (current_function_calls_alloca
3467 && EXIT_IGNORE_STACK)
3468 || FRAME_POINTER_REQUIRED);
3472 #ifdef ELIMINABLE_REGS
3473 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3474 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3476 ep->from = ep1->from;
3478 ep->can_eliminate = ep->can_eliminate_previous
3479 = (CAN_ELIMINATE (ep->from, ep->to)
3480 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3483 reg_eliminate[0].from = reg_eliminate_1[0].from;
3484 reg_eliminate[0].to = reg_eliminate_1[0].to;
3485 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3486 = ! frame_pointer_needed;
3489 /* Count the number of eliminable registers and build the FROM and TO
3490 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3491 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3492 We depend on this. */
3493 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3495 num_eliminable += ep->can_eliminate;
3496 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3497 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3501 /* Kick all pseudos out of hard register REGNO.
3503 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3504 because we found we can't eliminate some register. In the case, no pseudos
3505 are allowed to be in the register, even if they are only in a block that
3506 doesn't require spill registers, unlike the case when we are spilling this
3507 hard reg to produce another spill register.
3509 Return nonzero if any pseudos needed to be kicked out. */
3512 spill_hard_reg (unsigned int regno, int cant_eliminate)
3518 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3519 regs_ever_live[regno] = 1;
3522 /* Spill every pseudo reg that was allocated to this reg
3523 or to something that overlaps this reg. */
3525 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3526 if (reg_renumber[i] >= 0
3527 && (unsigned int) reg_renumber[i] <= regno
3528 && ((unsigned int) reg_renumber[i]
3529 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3530 PSEUDO_REGNO_MODE (i))
3532 SET_REGNO_REG_SET (&spilled_pseudos, i);
3535 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3536 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3539 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3541 IOR_HARD_REG_SET (*set1, *set2);
3544 /* After find_reload_regs has been run for all insn that need reloads,
3545 and/or spill_hard_regs was called, this function is used to actually
3546 spill pseudo registers and try to reallocate them. It also sets up the
3547 spill_regs array for use by choose_reload_regs. */
3550 finish_spills (int global)
3552 struct insn_chain *chain;
3553 int something_changed = 0;
3556 /* Build the spill_regs array for the function. */
3557 /* If there are some registers still to eliminate and one of the spill regs
3558 wasn't ever used before, additional stack space may have to be
3559 allocated to store this register. Thus, we may have changed the offset
3560 between the stack and frame pointers, so mark that something has changed.
3562 One might think that we need only set VAL to 1 if this is a call-used
3563 register. However, the set of registers that must be saved by the
3564 prologue is not identical to the call-used set. For example, the
3565 register used by the call insn for the return PC is a call-used register,
3566 but must be saved by the prologue. */
3569 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3570 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3572 spill_reg_order[i] = n_spills;
3573 spill_regs[n_spills++] = i;
3574 if (num_eliminable && ! regs_ever_live[i])
3575 something_changed = 1;
3576 regs_ever_live[i] = 1;
3579 spill_reg_order[i] = -1;
3581 EXECUTE_IF_SET_IN_REG_SET
3582 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3584 /* Record the current hard register the pseudo is allocated to in
3585 pseudo_previous_regs so we avoid reallocating it to the same
3586 hard reg in a later pass. */
3587 if (reg_renumber[i] < 0)
3590 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3591 /* Mark it as no longer having a hard register home. */
3592 reg_renumber[i] = -1;
3593 /* We will need to scan everything again. */
3594 something_changed = 1;
3597 /* Retry global register allocation if possible. */
3600 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3601 /* For every insn that needs reloads, set the registers used as spill
3602 regs in pseudo_forbidden_regs for every pseudo live across the
3604 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3606 EXECUTE_IF_SET_IN_REG_SET
3607 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3609 ior_hard_reg_set (pseudo_forbidden_regs + i,
3610 &chain->used_spill_regs);
3612 EXECUTE_IF_SET_IN_REG_SET
3613 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3615 ior_hard_reg_set (pseudo_forbidden_regs + i,
3616 &chain->used_spill_regs);
3620 /* Retry allocating the spilled pseudos. For each reg, merge the
3621 various reg sets that indicate which hard regs can't be used,
3622 and call retry_global_alloc.
3623 We change spill_pseudos here to only contain pseudos that did not
3624 get a new hard register. */
3625 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3626 if (reg_old_renumber[i] != reg_renumber[i])
3628 HARD_REG_SET forbidden;
3629 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3630 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3631 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3632 retry_global_alloc (i, forbidden);
3633 if (reg_renumber[i] >= 0)
3634 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3638 /* Fix up the register information in the insn chain.
3639 This involves deleting those of the spilled pseudos which did not get
3640 a new hard register home from the live_{before,after} sets. */
3641 for (chain = reload_insn_chain; chain; chain = chain->next)
3643 HARD_REG_SET used_by_pseudos;
3644 HARD_REG_SET used_by_pseudos2;
3646 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3647 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3649 /* Mark any unallocated hard regs as available for spills. That
3650 makes inheritance work somewhat better. */
3651 if (chain->need_reload)
3653 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3654 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3655 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3657 /* Save the old value for the sanity test below. */
3658 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3660 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3661 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3662 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3663 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3665 /* Make sure we only enlarge the set. */
3666 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3672 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3673 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3675 int regno = reg_renumber[i];
3676 if (reg_old_renumber[i] == regno)
3679 alter_reg (i, reg_old_renumber[i]);
3680 reg_old_renumber[i] = regno;
3684 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3686 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3687 i, reg_renumber[i]);
3691 return something_changed;
3694 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3695 Also mark any hard registers used to store user variables as
3696 forbidden from being used for spill registers. */
3699 scan_paradoxical_subregs (rtx x)
3703 enum rtx_code code = GET_CODE (x);
3709 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3710 && REG_USERVAR_P (x))
3711 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3720 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3728 if (GET_CODE (SUBREG_REG (x)) == REG
3729 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3730 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3731 = GET_MODE_SIZE (GET_MODE (x));
3738 fmt = GET_RTX_FORMAT (code);
3739 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3742 scan_paradoxical_subregs (XEXP (x, i));
3743 else if (fmt[i] == 'E')
3746 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3747 scan_paradoxical_subregs (XVECEXP (x, i, j));
3752 /* Reload pseudo-registers into hard regs around each insn as needed.
3753 Additional register load insns are output before the insn that needs it
3754 and perhaps store insns after insns that modify the reloaded pseudo reg.
3756 reg_last_reload_reg and reg_reloaded_contents keep track of
3757 which registers are already available in reload registers.
3758 We update these for the reloads that we perform,
3759 as the insns are scanned. */
3762 reload_as_needed (int live_known)
3764 struct insn_chain *chain;
3765 #if defined (AUTO_INC_DEC)
3770 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3771 memset (spill_reg_store, 0, sizeof spill_reg_store);
3772 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3773 reg_has_output_reload = xmalloc (max_regno);
3774 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3775 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3777 set_initial_elim_offsets ();
3779 for (chain = reload_insn_chain; chain; chain = chain->next)
3782 rtx insn = chain->insn;
3783 rtx old_next = NEXT_INSN (insn);
3785 /* If we pass a label, copy the offsets from the label information
3786 into the current offsets of each elimination. */
3787 if (GET_CODE (insn) == CODE_LABEL)
3788 set_offsets_for_label (insn);
3790 else if (INSN_P (insn))
3792 rtx oldpat = copy_rtx (PATTERN (insn));
3794 /* If this is a USE and CLOBBER of a MEM, ensure that any
3795 references to eliminable registers have been removed. */
3797 if ((GET_CODE (PATTERN (insn)) == USE
3798 || GET_CODE (PATTERN (insn)) == CLOBBER)
3799 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3800 XEXP (XEXP (PATTERN (insn), 0), 0)
3801 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3802 GET_MODE (XEXP (PATTERN (insn), 0)),
3805 /* If we need to do register elimination processing, do so.
3806 This might delete the insn, in which case we are done. */
3807 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3809 eliminate_regs_in_insn (insn, 1);
3810 if (GET_CODE (insn) == NOTE)
3812 update_eliminable_offsets ();
3817 /* If need_elim is nonzero but need_reload is zero, one might think
3818 that we could simply set n_reloads to 0. However, find_reloads
3819 could have done some manipulation of the insn (such as swapping
3820 commutative operands), and these manipulations are lost during
3821 the first pass for every insn that needs register elimination.
3822 So the actions of find_reloads must be redone here. */
3824 if (! chain->need_elim && ! chain->need_reload
3825 && ! chain->need_operand_change)
3827 /* First find the pseudo regs that must be reloaded for this insn.
3828 This info is returned in the tables reload_... (see reload.h).
3829 Also modify the body of INSN by substituting RELOAD
3830 rtx's for those pseudo regs. */
3833 memset (reg_has_output_reload, 0, max_regno);
3834 CLEAR_HARD_REG_SET (reg_is_output_reload);
3836 find_reloads (insn, 1, spill_indirect_levels, live_known,
3842 rtx next = NEXT_INSN (insn);
3845 prev = PREV_INSN (insn);
3847 /* Now compute which reload regs to reload them into. Perhaps
3848 reusing reload regs from previous insns, or else output
3849 load insns to reload them. Maybe output store insns too.
3850 Record the choices of reload reg in reload_reg_rtx. */
3851 choose_reload_regs (chain);
3853 /* Merge any reloads that we didn't combine for fear of
3854 increasing the number of spill registers needed but now
3855 discover can be safely merged. */
3856 if (SMALL_REGISTER_CLASSES)
3857 merge_assigned_reloads (insn);
3859 /* Generate the insns to reload operands into or out of
3860 their reload regs. */
3861 emit_reload_insns (chain);
3863 /* Substitute the chosen reload regs from reload_reg_rtx
3864 into the insn's body (or perhaps into the bodies of other
3865 load and store insn that we just made for reloading
3866 and that we moved the structure into). */
3867 subst_reloads (insn);
3869 /* If this was an ASM, make sure that all the reload insns
3870 we have generated are valid. If not, give an error
3873 if (asm_noperands (PATTERN (insn)) >= 0)
3874 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3875 if (p != insn && INSN_P (p)
3876 && GET_CODE (PATTERN (p)) != USE
3877 && (recog_memoized (p) < 0
3878 || (extract_insn (p), ! constrain_operands (1))))
3880 error_for_asm (insn,
3881 "`asm' operand requires impossible reload");
3886 if (num_eliminable && chain->need_elim)
3887 update_eliminable_offsets ();
3889 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3890 is no longer validly lying around to save a future reload.
3891 Note that this does not detect pseudos that were reloaded
3892 for this insn in order to be stored in
3893 (obeying register constraints). That is correct; such reload
3894 registers ARE still valid. */
3895 note_stores (oldpat, forget_old_reloads_1, NULL);
3897 /* There may have been CLOBBER insns placed after INSN. So scan
3898 between INSN and NEXT and use them to forget old reloads. */
3899 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3900 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3901 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3904 /* Likewise for regs altered by auto-increment in this insn.
3905 REG_INC notes have been changed by reloading:
3906 find_reloads_address_1 records substitutions for them,
3907 which have been performed by subst_reloads above. */
3908 for (i = n_reloads - 1; i >= 0; i--)
3910 rtx in_reg = rld[i].in_reg;
3913 enum rtx_code code = GET_CODE (in_reg);
3914 /* PRE_INC / PRE_DEC will have the reload register ending up
3915 with the same value as the stack slot, but that doesn't
3916 hold true for POST_INC / POST_DEC. Either we have to
3917 convert the memory access to a true POST_INC / POST_DEC,
3918 or we can't use the reload register for inheritance. */
3919 if ((code == POST_INC || code == POST_DEC)
3920 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3921 REGNO (rld[i].reg_rtx))
3922 /* Make sure it is the inc/dec pseudo, and not
3923 some other (e.g. output operand) pseudo. */
3924 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3925 == REGNO (XEXP (in_reg, 0))))
3928 rtx reload_reg = rld[i].reg_rtx;
3929 enum machine_mode mode = GET_MODE (reload_reg);
3933 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3935 /* We really want to ignore REG_INC notes here, so
3936 use PATTERN (p) as argument to reg_set_p . */
3937 if (reg_set_p (reload_reg, PATTERN (p)))
3939 n = count_occurrences (PATTERN (p), reload_reg, 0);
3944 n = validate_replace_rtx (reload_reg,
3945 gen_rtx (code, mode,
3949 /* We must also verify that the constraints
3950 are met after the replacement. */
3953 n = constrain_operands (1);
3957 /* If the constraints were not met, then
3958 undo the replacement. */
3961 validate_replace_rtx (gen_rtx (code, mode,
3973 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3975 /* Mark this as having an output reload so that the
3976 REG_INC processing code below won't invalidate
3977 the reload for inheritance. */
3978 SET_HARD_REG_BIT (reg_is_output_reload,
3979 REGNO (reload_reg));
3980 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3983 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3986 else if ((code == PRE_INC || code == PRE_DEC)
3987 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3988 REGNO (rld[i].reg_rtx))
3989 /* Make sure it is the inc/dec pseudo, and not
3990 some other (e.g. output operand) pseudo. */
3991 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3992 == REGNO (XEXP (in_reg, 0))))
3994 SET_HARD_REG_BIT (reg_is_output_reload,
3995 REGNO (rld[i].reg_rtx));
3996 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4000 /* If a pseudo that got a hard register is auto-incremented,
4001 we must purge records of copying it into pseudos without
4003 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4004 if (REG_NOTE_KIND (x) == REG_INC)
4006 /* See if this pseudo reg was reloaded in this insn.
4007 If so, its last-reload info is still valid
4008 because it is based on this insn's reload. */
4009 for (i = 0; i < n_reloads; i++)
4010 if (rld[i].out == XEXP (x, 0))
4014 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4018 /* A reload reg's contents are unknown after a label. */
4019 if (GET_CODE (insn) == CODE_LABEL)
4020 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4022 /* Don't assume a reload reg is still good after a call insn
4023 if it is a call-used reg, or if it contains a value that will
4024 be partially clobbered by the call. */
4025 else if (GET_CODE (insn) == CALL_INSN)
4027 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4028 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4033 free (reg_last_reload_reg);
4034 free (reg_has_output_reload);
4037 /* Discard all record of any value reloaded from X,
4038 or reloaded in X from someplace else;
4039 unless X is an output reload reg of the current insn.
4041 X may be a hard reg (the reload reg)
4042 or it may be a pseudo reg that was reloaded from. */
4045 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4046 void *data ATTRIBUTE_UNUSED)
4051 /* note_stores does give us subregs of hard regs,
4052 subreg_regno_offset will abort if it is not a hard reg. */
4053 while (GET_CODE (x) == SUBREG)
4055 /* We ignore the subreg offset when calculating the regno,
4056 because we are using the entire underlying hard register
4061 if (GET_CODE (x) != REG)
4066 if (regno >= FIRST_PSEUDO_REGISTER)
4072 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4073 /* Storing into a spilled-reg invalidates its contents.
4074 This can happen if a block-local pseudo is allocated to that reg
4075 and it wasn't spilled because this block's total need is 0.
4076 Then some insn might have an optional reload and use this reg. */
4077 for (i = 0; i < nr; i++)
4078 /* But don't do this if the reg actually serves as an output
4079 reload reg in the current instruction. */
4081 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4083 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4084 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4085 spill_reg_store[regno + i] = 0;
4089 /* Since value of X has changed,
4090 forget any value previously copied from it. */
4093 /* But don't forget a copy if this is the output reload
4094 that establishes the copy's validity. */
4095 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4096 reg_last_reload_reg[regno + nr] = 0;
4099 /* The following HARD_REG_SETs indicate when each hard register is
4100 used for a reload of various parts of the current insn. */
4102 /* If reg is unavailable for all reloads. */
4103 static HARD_REG_SET reload_reg_unavailable;
4104 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4105 static HARD_REG_SET reload_reg_used;
4106 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4107 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4108 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4109 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4110 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4111 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4112 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4113 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4114 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4115 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4116 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4117 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4118 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4119 static HARD_REG_SET reload_reg_used_in_op_addr;
4120 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4121 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4122 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4123 static HARD_REG_SET reload_reg_used_in_insn;
4124 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4125 static HARD_REG_SET reload_reg_used_in_other_addr;
4127 /* If reg is in use as a reload reg for any sort of reload. */
4128 static HARD_REG_SET reload_reg_used_at_all;
4130 /* If reg is use as an inherited reload. We just mark the first register
4132 static HARD_REG_SET reload_reg_used_for_inherit;
4134 /* Records which hard regs are used in any way, either as explicit use or
4135 by being allocated to a pseudo during any point of the current insn. */
4136 static HARD_REG_SET reg_used_in_insn;
4138 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4139 TYPE. MODE is used to indicate how many consecutive regs are
4143 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4144 enum machine_mode mode)
4146 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4149 for (i = regno; i < nregs + regno; i++)
4154 SET_HARD_REG_BIT (reload_reg_used, i);
4157 case RELOAD_FOR_INPUT_ADDRESS:
4158 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4161 case RELOAD_FOR_INPADDR_ADDRESS:
4162 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4165 case RELOAD_FOR_OUTPUT_ADDRESS:
4166 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4169 case RELOAD_FOR_OUTADDR_ADDRESS:
4170 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4173 case RELOAD_FOR_OPERAND_ADDRESS:
4174 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4177 case RELOAD_FOR_OPADDR_ADDR:
4178 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4181 case RELOAD_FOR_OTHER_ADDRESS:
4182 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4185 case RELOAD_FOR_INPUT:
4186 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4189 case RELOAD_FOR_OUTPUT:
4190 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4193 case RELOAD_FOR_INSN:
4194 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4198 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4202 /* Similarly, but show REGNO is no longer in use for a reload. */
4205 clear_reload_reg_in_use (unsigned int regno, int opnum,
4206 enum reload_type type, enum machine_mode mode)
4208 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4209 unsigned int start_regno, end_regno, r;
4211 /* A complication is that for some reload types, inheritance might
4212 allow multiple reloads of the same types to share a reload register.
4213 We set check_opnum if we have to check only reloads with the same
4214 operand number, and check_any if we have to check all reloads. */
4215 int check_opnum = 0;
4217 HARD_REG_SET *used_in_set;
4222 used_in_set = &reload_reg_used;
4225 case RELOAD_FOR_INPUT_ADDRESS:
4226 used_in_set = &reload_reg_used_in_input_addr[opnum];
4229 case RELOAD_FOR_INPADDR_ADDRESS:
4231 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4234 case RELOAD_FOR_OUTPUT_ADDRESS:
4235 used_in_set = &reload_reg_used_in_output_addr[opnum];
4238 case RELOAD_FOR_OUTADDR_ADDRESS:
4240 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4243 case RELOAD_FOR_OPERAND_ADDRESS:
4244 used_in_set = &reload_reg_used_in_op_addr;
4247 case RELOAD_FOR_OPADDR_ADDR:
4249 used_in_set = &reload_reg_used_in_op_addr_reload;
4252 case RELOAD_FOR_OTHER_ADDRESS:
4253 used_in_set = &reload_reg_used_in_other_addr;
4257 case RELOAD_FOR_INPUT:
4258 used_in_set = &reload_reg_used_in_input[opnum];
4261 case RELOAD_FOR_OUTPUT:
4262 used_in_set = &reload_reg_used_in_output[opnum];
4265 case RELOAD_FOR_INSN:
4266 used_in_set = &reload_reg_used_in_insn;
4271 /* We resolve conflicts with remaining reloads of the same type by
4272 excluding the intervals of reload registers by them from the
4273 interval of freed reload registers. Since we only keep track of
4274 one set of interval bounds, we might have to exclude somewhat
4275 more than what would be necessary if we used a HARD_REG_SET here.
4276 But this should only happen very infrequently, so there should
4277 be no reason to worry about it. */
4279 start_regno = regno;
4280 end_regno = regno + nregs;
4281 if (check_opnum || check_any)
4283 for (i = n_reloads - 1; i >= 0; i--)
4285 if (rld[i].when_needed == type
4286 && (check_any || rld[i].opnum == opnum)
4289 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4290 unsigned int conflict_end
4292 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4294 /* If there is an overlap with the first to-be-freed register,
4295 adjust the interval start. */
4296 if (conflict_start <= start_regno && conflict_end > start_regno)
4297 start_regno = conflict_end;
4298 /* Otherwise, if there is a conflict with one of the other
4299 to-be-freed registers, adjust the interval end. */
4300 if (conflict_start > start_regno && conflict_start < end_regno)
4301 end_regno = conflict_start;
4306 for (r = start_regno; r < end_regno; r++)
4307 CLEAR_HARD_REG_BIT (*used_in_set, r);
4310 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4311 specified by OPNUM and TYPE. */
4314 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4318 /* In use for a RELOAD_OTHER means it's not available for anything. */
4319 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4320 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4326 /* In use for anything means we can't use it for RELOAD_OTHER. */
4327 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4328 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4329 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4330 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4333 for (i = 0; i < reload_n_operands; i++)
4334 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4335 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4336 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4337 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4338 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4339 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4344 case RELOAD_FOR_INPUT:
4345 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4346 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4349 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4352 /* If it is used for some other input, can't use it. */
4353 for (i = 0; i < reload_n_operands; i++)
4354 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4357 /* If it is used in a later operand's address, can't use it. */
4358 for (i = opnum + 1; i < reload_n_operands; i++)
4359 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4360 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4365 case RELOAD_FOR_INPUT_ADDRESS:
4366 /* Can't use a register if it is used for an input address for this
4367 operand or used as an input in an earlier one. */
4368 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4369 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4372 for (i = 0; i < opnum; i++)
4373 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4378 case RELOAD_FOR_INPADDR_ADDRESS:
4379 /* Can't use a register if it is used for an input address
4380 for this operand or used as an input in an earlier
4382 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4385 for (i = 0; i < opnum; i++)
4386 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4391 case RELOAD_FOR_OUTPUT_ADDRESS:
4392 /* Can't use a register if it is used for an output address for this
4393 operand or used as an output in this or a later operand. Note
4394 that multiple output operands are emitted in reverse order, so
4395 the conflicting ones are those with lower indices. */
4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4399 for (i = 0; i <= opnum; i++)
4400 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4405 case RELOAD_FOR_OUTADDR_ADDRESS:
4406 /* Can't use a register if it is used for an output address
4407 for this operand or used as an output in this or a
4408 later operand. Note that multiple output operands are
4409 emitted in reverse order, so the conflicting ones are
4410 those with lower indices. */
4411 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4414 for (i = 0; i <= opnum; i++)
4415 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4420 case RELOAD_FOR_OPERAND_ADDRESS:
4421 for (i = 0; i < reload_n_operands; i++)
4422 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4425 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4426 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4428 case RELOAD_FOR_OPADDR_ADDR:
4429 for (i = 0; i < reload_n_operands; i++)
4430 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4433 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4435 case RELOAD_FOR_OUTPUT:
4436 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4437 outputs, or an operand address for this or an earlier output.
4438 Note that multiple output operands are emitted in reverse order,
4439 so the conflicting ones are those with higher indices. */
4440 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4443 for (i = 0; i < reload_n_operands; i++)
4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4447 for (i = opnum; i < reload_n_operands; i++)
4448 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4449 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4454 case RELOAD_FOR_INSN:
4455 for (i = 0; i < reload_n_operands; i++)
4456 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4457 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4460 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4461 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4463 case RELOAD_FOR_OTHER_ADDRESS:
4464 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4469 /* Return 1 if the value in reload reg REGNO, as used by a reload
4470 needed for the part of the insn specified by OPNUM and TYPE,
4471 is still available in REGNO at the end of the insn.
4473 We can assume that the reload reg was already tested for availability
4474 at the time it is needed, and we should not check this again,
4475 in case the reg has already been marked in use. */
4478 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4485 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4486 its value must reach the end. */
4489 /* If this use is for part of the insn,
4490 its value reaches if no subsequent part uses the same register.
4491 Just like the above function, don't try to do this with lots
4494 case RELOAD_FOR_OTHER_ADDRESS:
4495 /* Here we check for everything else, since these don't conflict
4496 with anything else and everything comes later. */
4498 for (i = 0; i < reload_n_operands; i++)
4499 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4500 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4501 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4502 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4503 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4504 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4507 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4508 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4509 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4510 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4512 case RELOAD_FOR_INPUT_ADDRESS:
4513 case RELOAD_FOR_INPADDR_ADDRESS:
4514 /* Similar, except that we check only for this and subsequent inputs
4515 and the address of only subsequent inputs and we do not need
4516 to check for RELOAD_OTHER objects since they are known not to
4519 for (i = opnum; i < reload_n_operands; i++)
4520 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4523 for (i = opnum + 1; i < reload_n_operands; i++)
4524 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4528 for (i = 0; i < reload_n_operands; i++)
4529 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4530 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4531 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4534 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4537 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4538 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4539 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4541 case RELOAD_FOR_INPUT:
4542 /* Similar to input address, except we start at the next operand for
4543 both input and input address and we do not check for
4544 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4547 for (i = opnum + 1; i < reload_n_operands; i++)
4548 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4549 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4550 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4553 /* ... fall through ... */
4555 case RELOAD_FOR_OPERAND_ADDRESS:
4556 /* Check outputs and their addresses. */
4558 for (i = 0; i < reload_n_operands; i++)
4559 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4560 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4561 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4564 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4566 case RELOAD_FOR_OPADDR_ADDR:
4567 for (i = 0; i < reload_n_operands; i++)
4568 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4569 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4573 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4574 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4575 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4577 case RELOAD_FOR_INSN:
4578 /* These conflict with other outputs with RELOAD_OTHER. So
4579 we need only check for output addresses. */
4581 opnum = reload_n_operands;
4583 /* ... fall through ... */
4585 case RELOAD_FOR_OUTPUT:
4586 case RELOAD_FOR_OUTPUT_ADDRESS:
4587 case RELOAD_FOR_OUTADDR_ADDRESS:
4588 /* We already know these can't conflict with a later output. So the
4589 only thing to check are later output addresses.
4590 Note that multiple output operands are emitted in reverse order,
4591 so the conflicting ones are those with lower indices. */
4592 for (i = 0; i < opnum; i++)
4593 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4594 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4603 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4606 This function uses the same algorithm as reload_reg_free_p above. */
4609 reloads_conflict (int r1, int r2)
4611 enum reload_type r1_type = rld[r1].when_needed;
4612 enum reload_type r2_type = rld[r2].when_needed;
4613 int r1_opnum = rld[r1].opnum;
4614 int r2_opnum = rld[r2].opnum;
4616 /* RELOAD_OTHER conflicts with everything. */
4617 if (r2_type == RELOAD_OTHER)
4620 /* Otherwise, check conflicts differently for each type. */
4624 case RELOAD_FOR_INPUT:
4625 return (r2_type == RELOAD_FOR_INSN
4626 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4627 || r2_type == RELOAD_FOR_OPADDR_ADDR
4628 || r2_type == RELOAD_FOR_INPUT
4629 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4630 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4631 && r2_opnum > r1_opnum));
4633 case RELOAD_FOR_INPUT_ADDRESS:
4634 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4635 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4637 case RELOAD_FOR_INPADDR_ADDRESS:
4638 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4639 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4641 case RELOAD_FOR_OUTPUT_ADDRESS:
4642 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4643 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4645 case RELOAD_FOR_OUTADDR_ADDRESS:
4646 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4647 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4649 case RELOAD_FOR_OPERAND_ADDRESS:
4650 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4651 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4653 case RELOAD_FOR_OPADDR_ADDR:
4654 return (r2_type == RELOAD_FOR_INPUT
4655 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4657 case RELOAD_FOR_OUTPUT:
4658 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4659 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4660 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4661 && r2_opnum >= r1_opnum));
4663 case RELOAD_FOR_INSN:
4664 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4665 || r2_type == RELOAD_FOR_INSN
4666 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4668 case RELOAD_FOR_OTHER_ADDRESS:
4669 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4679 /* Indexed by reload number, 1 if incoming value
4680 inherited from previous insns. */
4681 char reload_inherited[MAX_RELOADS];
4683 /* For an inherited reload, this is the insn the reload was inherited from,
4684 if we know it. Otherwise, this is 0. */
4685 rtx reload_inheritance_insn[MAX_RELOADS];
4687 /* If nonzero, this is a place to get the value of the reload,
4688 rather than using reload_in. */
4689 rtx reload_override_in[MAX_RELOADS];
4691 /* For each reload, the hard register number of the register used,
4692 or -1 if we did not need a register for this reload. */
4693 int reload_spill_index[MAX_RELOADS];
4695 /* Subroutine of free_for_value_p, used to check a single register.
4696 START_REGNO is the starting regno of the full reload register
4697 (possibly comprising multiple hard registers) that we are considering. */
4700 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4701 enum reload_type type, rtx value, rtx out,
4702 int reloadnum, int ignore_address_reloads)
4705 /* Set if we see an input reload that must not share its reload register
4706 with any new earlyclobber, but might otherwise share the reload
4707 register with an output or input-output reload. */
4708 int check_earlyclobber = 0;
4712 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4715 if (out == const0_rtx)
4721 /* We use some pseudo 'time' value to check if the lifetimes of the
4722 new register use would overlap with the one of a previous reload
4723 that is not read-only or uses a different value.
4724 The 'time' used doesn't have to be linear in any shape or form, just
4726 Some reload types use different 'buckets' for each operand.
4727 So there are MAX_RECOG_OPERANDS different time values for each
4729 We compute TIME1 as the time when the register for the prospective
4730 new reload ceases to be live, and TIME2 for each existing
4731 reload as the time when that the reload register of that reload
4733 Where there is little to be gained by exact lifetime calculations,
4734 we just make conservative assumptions, i.e. a longer lifetime;
4735 this is done in the 'default:' cases. */
4738 case RELOAD_FOR_OTHER_ADDRESS:
4739 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4740 time1 = copy ? 0 : 1;
4743 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4745 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4746 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4747 respectively, to the time values for these, we get distinct time
4748 values. To get distinct time values for each operand, we have to
4749 multiply opnum by at least three. We round that up to four because
4750 multiply by four is often cheaper. */
4751 case RELOAD_FOR_INPADDR_ADDRESS:
4752 time1 = opnum * 4 + 2;
4754 case RELOAD_FOR_INPUT_ADDRESS:
4755 time1 = opnum * 4 + 3;
4757 case RELOAD_FOR_INPUT:
4758 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4759 executes (inclusive). */
4760 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4762 case RELOAD_FOR_OPADDR_ADDR:
4764 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4765 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4767 case RELOAD_FOR_OPERAND_ADDRESS:
4768 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4770 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4772 case RELOAD_FOR_OUTADDR_ADDRESS:
4773 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4775 case RELOAD_FOR_OUTPUT_ADDRESS:
4776 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4779 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4782 for (i = 0; i < n_reloads; i++)
4784 rtx reg = rld[i].reg_rtx;
4785 if (reg && GET_CODE (reg) == REG
4786 && ((unsigned) regno - true_regnum (reg)
4787 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1)
4790 rtx other_input = rld[i].in;
4792 /* If the other reload loads the same input value, that
4793 will not cause a conflict only if it's loading it into
4794 the same register. */
4795 if (true_regnum (reg) != start_regno)
4796 other_input = NULL_RTX;
4797 if (! other_input || ! rtx_equal_p (other_input, value)
4798 || rld[i].out || out)
4801 switch (rld[i].when_needed)
4803 case RELOAD_FOR_OTHER_ADDRESS:
4806 case RELOAD_FOR_INPADDR_ADDRESS:
4807 /* find_reloads makes sure that a
4808 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4809 by at most one - the first -
4810 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4811 address reload is inherited, the address address reload
4812 goes away, so we can ignore this conflict. */
4813 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4814 && ignore_address_reloads
4815 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4816 Then the address address is still needed to store
4817 back the new address. */
4818 && ! rld[reloadnum].out)
4820 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4821 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4823 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4824 && ignore_address_reloads
4825 /* Unless we are reloading an auto_inc expression. */
4826 && ! rld[reloadnum].out)
4828 time2 = rld[i].opnum * 4 + 2;
4830 case RELOAD_FOR_INPUT_ADDRESS:
4831 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4832 && ignore_address_reloads
4833 && ! rld[reloadnum].out)
4835 time2 = rld[i].opnum * 4 + 3;
4837 case RELOAD_FOR_INPUT:
4838 time2 = rld[i].opnum * 4 + 4;
4839 check_earlyclobber = 1;
4841 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4842 == MAX_RECOG_OPERAND * 4 */
4843 case RELOAD_FOR_OPADDR_ADDR:
4844 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4845 && ignore_address_reloads
4846 && ! rld[reloadnum].out)
4848 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4850 case RELOAD_FOR_OPERAND_ADDRESS:
4851 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4852 check_earlyclobber = 1;
4854 case RELOAD_FOR_INSN:
4855 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4857 case RELOAD_FOR_OUTPUT:
4858 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4859 instruction is executed. */
4860 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4862 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4863 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4865 case RELOAD_FOR_OUTADDR_ADDRESS:
4866 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4867 && ignore_address_reloads
4868 && ! rld[reloadnum].out)
4870 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4872 case RELOAD_FOR_OUTPUT_ADDRESS:
4873 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4876 /* If there is no conflict in the input part, handle this
4877 like an output reload. */
4878 if (! rld[i].in || rtx_equal_p (other_input, value))
4880 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4881 /* Earlyclobbered outputs must conflict with inputs. */
4882 if (earlyclobber_operand_p (rld[i].out))
4883 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4888 /* RELOAD_OTHER might be live beyond instruction execution,
4889 but this is not obvious when we set time2 = 1. So check
4890 here if there might be a problem with the new reload
4891 clobbering the register used by the RELOAD_OTHER. */
4899 && (! rld[i].in || rld[i].out
4900 || ! rtx_equal_p (other_input, value)))
4901 || (out && rld[reloadnum].out_reg
4902 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4908 /* Earlyclobbered outputs must conflict with inputs. */
4909 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4915 /* Return 1 if the value in reload reg REGNO, as used by a reload
4916 needed for the part of the insn specified by OPNUM and TYPE,
4917 may be used to load VALUE into it.
4919 MODE is the mode in which the register is used, this is needed to
4920 determine how many hard regs to test.
4922 Other read-only reloads with the same value do not conflict
4923 unless OUT is nonzero and these other reloads have to live while
4924 output reloads live.
4925 If OUT is CONST0_RTX, this is a special case: it means that the
4926 test should not be for using register REGNO as reload register, but
4927 for copying from register REGNO into the reload register.
4929 RELOADNUM is the number of the reload we want to load this value for;
4930 a reload does not conflict with itself.
4932 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4933 reloads that load an address for the very reload we are considering.
4935 The caller has to make sure that there is no conflict with the return
4939 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4940 enum reload_type type, rtx value, rtx out, int reloadnum,
4941 int ignore_address_reloads)
4943 int nregs = HARD_REGNO_NREGS (regno, mode);
4945 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4946 value, out, reloadnum,
4947 ignore_address_reloads))
4952 /* Determine whether the reload reg X overlaps any rtx'es used for
4953 overriding inheritance. Return nonzero if so. */
4956 conflicts_with_override (rtx x)
4959 for (i = 0; i < n_reloads; i++)
4960 if (reload_override_in[i]
4961 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4966 /* Give an error message saying we failed to find a reload for INSN,
4967 and clear out reload R. */
4969 failed_reload (rtx insn, int r)
4971 if (asm_noperands (PATTERN (insn)) < 0)
4972 /* It's the compiler's fault. */
4973 fatal_insn ("could not find a spill register", insn);
4975 /* It's the user's fault; the operand's mode and constraint
4976 don't match. Disable this reload so we don't crash in final. */
4977 error_for_asm (insn,
4978 "`asm' operand constraint incompatible with operand size");
4982 rld[r].optional = 1;
4983 rld[r].secondary_p = 1;
4986 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4987 for reload R. If it's valid, get an rtx for it. Return nonzero if
4990 set_reload_reg (int i, int r)
4993 rtx reg = spill_reg_rtx[i];
4995 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4996 spill_reg_rtx[i] = reg
4997 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4999 regno = true_regnum (reg);
5001 /* Detect when the reload reg can't hold the reload mode.
5002 This used to be one `if', but Sequent compiler can't handle that. */
5003 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5005 enum machine_mode test_mode = VOIDmode;
5007 test_mode = GET_MODE (rld[r].in);
5008 /* If rld[r].in has VOIDmode, it means we will load it
5009 in whatever mode the reload reg has: to wit, rld[r].mode.
5010 We have already tested that for validity. */
5011 /* Aside from that, we need to test that the expressions
5012 to reload from or into have modes which are valid for this
5013 reload register. Otherwise the reload insns would be invalid. */
5014 if (! (rld[r].in != 0 && test_mode != VOIDmode
5015 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5016 if (! (rld[r].out != 0
5017 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5019 /* The reg is OK. */
5022 /* Mark as in use for this insn the reload regs we use
5024 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5025 rld[r].when_needed, rld[r].mode);
5027 rld[r].reg_rtx = reg;
5028 reload_spill_index[r] = spill_regs[i];
5035 /* Find a spill register to use as a reload register for reload R.
5036 LAST_RELOAD is nonzero if this is the last reload for the insn being
5039 Set rld[R].reg_rtx to the register allocated.
5041 We return 1 if successful, or 0 if we couldn't find a spill reg and
5042 we didn't change anything. */
5045 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5050 /* If we put this reload ahead, thinking it is a group,
5051 then insist on finding a group. Otherwise we can grab a
5052 reg that some other reload needs.
5053 (That can happen when we have a 68000 DATA_OR_FP_REG
5054 which is a group of data regs or one fp reg.)
5055 We need not be so restrictive if there are no more reloads
5058 ??? Really it would be nicer to have smarter handling
5059 for that kind of reg class, where a problem like this is normal.
5060 Perhaps those classes should be avoided for reloading
5061 by use of more alternatives. */
5063 int force_group = rld[r].nregs > 1 && ! last_reload;
5065 /* If we want a single register and haven't yet found one,
5066 take any reg in the right class and not in use.
5067 If we want a consecutive group, here is where we look for it.
5069 We use two passes so we can first look for reload regs to
5070 reuse, which are already in use for other reloads in this insn,
5071 and only then use additional registers.
5072 I think that maximizing reuse is needed to make sure we don't
5073 run out of reload regs. Suppose we have three reloads, and
5074 reloads A and B can share regs. These need two regs.
5075 Suppose A and B are given different regs.
5076 That leaves none for C. */
5077 for (pass = 0; pass < 2; pass++)
5079 /* I is the index in spill_regs.
5080 We advance it round-robin between insns to use all spill regs
5081 equally, so that inherited reloads have a chance
5082 of leapfrogging each other. */
5086 for (count = 0; count < n_spills; count++)
5088 int class = (int) rld[r].class;
5094 regnum = spill_regs[i];
5096 if ((reload_reg_free_p (regnum, rld[r].opnum,
5099 /* We check reload_reg_used to make sure we
5100 don't clobber the return register. */
5101 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5102 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5103 rld[r].when_needed, rld[r].in,
5105 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5106 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5107 /* Look first for regs to share, then for unshared. But
5108 don't share regs used for inherited reloads; they are
5109 the ones we want to preserve. */
5111 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5113 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5116 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5117 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5118 (on 68000) got us two FP regs. If NR is 1,
5119 we would reject both of them. */
5122 /* If we need only one reg, we have already won. */
5125 /* But reject a single reg if we demand a group. */
5130 /* Otherwise check that as many consecutive regs as we need
5131 are available here. */
5134 int regno = regnum + nr - 1;
5135 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5136 && spill_reg_order[regno] >= 0
5137 && reload_reg_free_p (regno, rld[r].opnum,
5138 rld[r].when_needed)))
5147 /* If we found something on pass 1, omit pass 2. */
5148 if (count < n_spills)
5152 /* We should have found a spill register by now. */
5153 if (count >= n_spills)
5156 /* I is the index in SPILL_REG_RTX of the reload register we are to
5157 allocate. Get an rtx for it and find its register number. */
5159 return set_reload_reg (i, r);
5162 /* Initialize all the tables needed to allocate reload registers.
5163 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5164 is the array we use to restore the reg_rtx field for every reload. */
5167 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5171 for (i = 0; i < n_reloads; i++)
5172 rld[i].reg_rtx = save_reload_reg_rtx[i];
5174 memset (reload_inherited, 0, MAX_RELOADS);
5175 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5176 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5178 CLEAR_HARD_REG_SET (reload_reg_used);
5179 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5180 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5181 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5182 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5183 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5185 CLEAR_HARD_REG_SET (reg_used_in_insn);
5188 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5189 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5190 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5191 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5192 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5193 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5196 for (i = 0; i < reload_n_operands; i++)
5198 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5199 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5200 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5201 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5202 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5203 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5206 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5208 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5210 for (i = 0; i < n_reloads; i++)
5211 /* If we have already decided to use a certain register,
5212 don't use it in another way. */
5214 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5215 rld[i].when_needed, rld[i].mode);
5218 /* Assign hard reg targets for the pseudo-registers we must reload
5219 into hard regs for this insn.
5220 Also output the instructions to copy them in and out of the hard regs.
5222 For machines with register classes, we are responsible for
5223 finding a reload reg in the proper class. */
5226 choose_reload_regs (struct insn_chain *chain)
5228 rtx insn = chain->insn;
5230 unsigned int max_group_size = 1;
5231 enum reg_class group_class = NO_REGS;
5232 int pass, win, inheritance;
5234 rtx save_reload_reg_rtx[MAX_RELOADS];
5236 /* In order to be certain of getting the registers we need,
5237 we must sort the reloads into order of increasing register class.
5238 Then our grabbing of reload registers will parallel the process
5239 that provided the reload registers.
5241 Also note whether any of the reloads wants a consecutive group of regs.
5242 If so, record the maximum size of the group desired and what
5243 register class contains all the groups needed by this insn. */
5245 for (j = 0; j < n_reloads; j++)
5247 reload_order[j] = j;
5248 reload_spill_index[j] = -1;
5250 if (rld[j].nregs > 1)
5252 max_group_size = MAX (rld[j].nregs, max_group_size);
5254 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5257 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5261 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5263 /* If -O, try first with inheritance, then turning it off.
5264 If not -O, don't do inheritance.
5265 Using inheritance when not optimizing leads to paradoxes
5266 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5267 because one side of the comparison might be inherited. */
5269 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5271 choose_reload_regs_init (chain, save_reload_reg_rtx);
5273 /* Process the reloads in order of preference just found.
5274 Beyond this point, subregs can be found in reload_reg_rtx.
5276 This used to look for an existing reloaded home for all of the
5277 reloads, and only then perform any new reloads. But that could lose
5278 if the reloads were done out of reg-class order because a later
5279 reload with a looser constraint might have an old home in a register
5280 needed by an earlier reload with a tighter constraint.
5282 To solve this, we make two passes over the reloads, in the order
5283 described above. In the first pass we try to inherit a reload
5284 from a previous insn. If there is a later reload that needs a
5285 class that is a proper subset of the class being processed, we must
5286 also allocate a spill register during the first pass.
5288 Then make a second pass over the reloads to allocate any reloads
5289 that haven't been given registers yet. */
5291 for (j = 0; j < n_reloads; j++)
5293 int r = reload_order[j];
5294 rtx search_equiv = NULL_RTX;
5296 /* Ignore reloads that got marked inoperative. */
5297 if (rld[r].out == 0 && rld[r].in == 0
5298 && ! rld[r].secondary_p)
5301 /* If find_reloads chose to use reload_in or reload_out as a reload
5302 register, we don't need to chose one. Otherwise, try even if it
5303 found one since we might save an insn if we find the value lying
5305 Try also when reload_in is a pseudo without a hard reg. */
5306 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5307 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5308 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5309 && GET_CODE (rld[r].in) != MEM
5310 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5313 #if 0 /* No longer needed for correct operation.
5314 It might give better code, or might not; worth an experiment? */
5315 /* If this is an optional reload, we can't inherit from earlier insns
5316 until we are sure that any non-optional reloads have been allocated.
5317 The following code takes advantage of the fact that optional reloads
5318 are at the end of reload_order. */
5319 if (rld[r].optional != 0)
5320 for (i = 0; i < j; i++)
5321 if ((rld[reload_order[i]].out != 0
5322 || rld[reload_order[i]].in != 0
5323 || rld[reload_order[i]].secondary_p)
5324 && ! rld[reload_order[i]].optional
5325 && rld[reload_order[i]].reg_rtx == 0)
5326 allocate_reload_reg (chain, reload_order[i], 0);
5329 /* First see if this pseudo is already available as reloaded
5330 for a previous insn. We cannot try to inherit for reloads
5331 that are smaller than the maximum number of registers needed
5332 for groups unless the register we would allocate cannot be used
5335 We could check here to see if this is a secondary reload for
5336 an object that is already in a register of the desired class.
5337 This would avoid the need for the secondary reload register.
5338 But this is complex because we can't easily determine what
5339 objects might want to be loaded via this reload. So let a
5340 register be allocated here. In `emit_reload_insns' we suppress
5341 one of the loads in the case described above. */
5347 enum machine_mode mode = VOIDmode;
5351 else if (GET_CODE (rld[r].in) == REG)
5353 regno = REGNO (rld[r].in);
5354 mode = GET_MODE (rld[r].in);
5356 else if (GET_CODE (rld[r].in_reg) == REG)
5358 regno = REGNO (rld[r].in_reg);
5359 mode = GET_MODE (rld[r].in_reg);
5361 else if (GET_CODE (rld[r].in_reg) == SUBREG
5362 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5364 byte = SUBREG_BYTE (rld[r].in_reg);
5365 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5366 if (regno < FIRST_PSEUDO_REGISTER)
5367 regno = subreg_regno (rld[r].in_reg);
5368 mode = GET_MODE (rld[r].in_reg);
5371 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5372 || GET_CODE (rld[r].in_reg) == PRE_DEC
5373 || GET_CODE (rld[r].in_reg) == POST_INC
5374 || GET_CODE (rld[r].in_reg) == POST_DEC)
5375 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5377 regno = REGNO (XEXP (rld[r].in_reg, 0));
5378 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5379 rld[r].out = rld[r].in;
5383 /* This won't work, since REGNO can be a pseudo reg number.
5384 Also, it takes much more hair to keep track of all the things
5385 that can invalidate an inherited reload of part of a pseudoreg. */
5386 else if (GET_CODE (rld[r].in) == SUBREG
5387 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5388 regno = subreg_regno (rld[r].in);
5391 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5393 enum reg_class class = rld[r].class, last_class;
5394 rtx last_reg = reg_last_reload_reg[regno];
5395 enum machine_mode need_mode;
5397 i = REGNO (last_reg);
5398 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5399 last_class = REGNO_REG_CLASS (i);
5405 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5406 GET_MODE_CLASS (mode));
5409 #ifdef CANNOT_CHANGE_MODE_CLASS
5410 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5414 (GET_MODE_SIZE (GET_MODE (last_reg))
5415 >= GET_MODE_SIZE (need_mode))
5416 #ifdef CANNOT_CHANGE_MODE_CLASS
5419 && reg_reloaded_contents[i] == regno
5420 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5421 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5422 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5423 /* Even if we can't use this register as a reload
5424 register, we might use it for reload_override_in,
5425 if copying it to the desired class is cheap
5427 || ((REGISTER_MOVE_COST (mode, last_class, class)
5428 < MEMORY_MOVE_COST (mode, class, 1))
5429 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5430 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5434 #ifdef SECONDARY_MEMORY_NEEDED
5435 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5440 && (rld[r].nregs == max_group_size
5441 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5443 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5444 rld[r].when_needed, rld[r].in,
5447 /* If a group is needed, verify that all the subsequent
5448 registers still have their values intact. */
5449 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5452 for (k = 1; k < nr; k++)
5453 if (reg_reloaded_contents[i + k] != regno
5454 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5462 last_reg = (GET_MODE (last_reg) == mode
5463 ? last_reg : gen_rtx_REG (mode, i));
5466 for (k = 0; k < nr; k++)
5467 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5470 /* We found a register that contains the
5471 value we need. If this register is the
5472 same as an `earlyclobber' operand of the
5473 current insn, just mark it as a place to
5474 reload from since we can't use it as the
5475 reload register itself. */
5477 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5478 if (reg_overlap_mentioned_for_reload_p
5479 (reg_last_reload_reg[regno],
5480 reload_earlyclobbers[i1]))
5483 if (i1 != n_earlyclobbers
5484 || ! (free_for_value_p (i, rld[r].mode,
5486 rld[r].when_needed, rld[r].in,
5488 /* Don't use it if we'd clobber a pseudo reg. */
5489 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5491 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5492 /* Don't clobber the frame pointer. */
5493 || (i == HARD_FRAME_POINTER_REGNUM
5494 && frame_pointer_needed
5496 /* Don't really use the inherited spill reg
5497 if we need it wider than we've got it. */
5498 || (GET_MODE_SIZE (rld[r].mode)
5499 > GET_MODE_SIZE (mode))
5502 /* If find_reloads chose reload_out as reload
5503 register, stay with it - that leaves the
5504 inherited register for subsequent reloads. */
5505 || (rld[r].out && rld[r].reg_rtx
5506 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5508 if (! rld[r].optional)
5510 reload_override_in[r] = last_reg;
5511 reload_inheritance_insn[r]
5512 = reg_reloaded_insn[i];
5518 /* We can use this as a reload reg. */
5519 /* Mark the register as in use for this part of
5521 mark_reload_reg_in_use (i,
5525 rld[r].reg_rtx = last_reg;
5526 reload_inherited[r] = 1;
5527 reload_inheritance_insn[r]
5528 = reg_reloaded_insn[i];
5529 reload_spill_index[r] = i;
5530 for (k = 0; k < nr; k++)
5531 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5539 /* Here's another way to see if the value is already lying around. */
5542 && ! reload_inherited[r]
5544 && (CONSTANT_P (rld[r].in)
5545 || GET_CODE (rld[r].in) == PLUS
5546 || GET_CODE (rld[r].in) == REG
5547 || GET_CODE (rld[r].in) == MEM)
5548 && (rld[r].nregs == max_group_size
5549 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5550 search_equiv = rld[r].in;
5551 /* If this is an output reload from a simple move insn, look
5552 if an equivalence for the input is available. */
5553 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5555 rtx set = single_set (insn);
5558 && rtx_equal_p (rld[r].out, SET_DEST (set))
5559 && CONSTANT_P (SET_SRC (set)))
5560 search_equiv = SET_SRC (set);
5566 = find_equiv_reg (search_equiv, insn, rld[r].class,
5567 -1, NULL, 0, rld[r].mode);
5572 if (GET_CODE (equiv) == REG)
5573 regno = REGNO (equiv);
5574 else if (GET_CODE (equiv) == SUBREG)
5576 /* This must be a SUBREG of a hard register.
5577 Make a new REG since this might be used in an
5578 address and not all machines support SUBREGs
5580 regno = subreg_regno (equiv);
5581 equiv = gen_rtx_REG (rld[r].mode, regno);
5587 /* If we found a spill reg, reject it unless it is free
5588 and of the desired class. */
5592 int bad_for_class = 0;
5593 int max_regno = regno + rld[r].nregs;
5595 for (i = regno; i < max_regno; i++)
5597 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5599 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5604 && ! free_for_value_p (regno, rld[r].mode,
5605 rld[r].opnum, rld[r].when_needed,
5606 rld[r].in, rld[r].out, r, 1))
5611 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5614 /* We found a register that contains the value we need.
5615 If this register is the same as an `earlyclobber' operand
5616 of the current insn, just mark it as a place to reload from
5617 since we can't use it as the reload register itself. */
5620 for (i = 0; i < n_earlyclobbers; i++)
5621 if (reg_overlap_mentioned_for_reload_p (equiv,
5622 reload_earlyclobbers[i]))
5624 if (! rld[r].optional)
5625 reload_override_in[r] = equiv;
5630 /* If the equiv register we have found is explicitly clobbered
5631 in the current insn, it depends on the reload type if we
5632 can use it, use it for reload_override_in, or not at all.
5633 In particular, we then can't use EQUIV for a
5634 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5638 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5639 switch (rld[r].when_needed)
5641 case RELOAD_FOR_OTHER_ADDRESS:
5642 case RELOAD_FOR_INPADDR_ADDRESS:
5643 case RELOAD_FOR_INPUT_ADDRESS:
5644 case RELOAD_FOR_OPADDR_ADDR:
5647 case RELOAD_FOR_INPUT:
5648 case RELOAD_FOR_OPERAND_ADDRESS:
5649 if (! rld[r].optional)
5650 reload_override_in[r] = equiv;
5656 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5657 switch (rld[r].when_needed)
5659 case RELOAD_FOR_OTHER_ADDRESS:
5660 case RELOAD_FOR_INPADDR_ADDRESS:
5661 case RELOAD_FOR_INPUT_ADDRESS:
5662 case RELOAD_FOR_OPADDR_ADDR:
5663 case RELOAD_FOR_OPERAND_ADDRESS:
5664 case RELOAD_FOR_INPUT:
5667 if (! rld[r].optional)
5668 reload_override_in[r] = equiv;
5676 /* If we found an equivalent reg, say no code need be generated
5677 to load it, and use it as our reload reg. */
5679 && (regno != HARD_FRAME_POINTER_REGNUM
5680 || !frame_pointer_needed))
5682 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5684 rld[r].reg_rtx = equiv;
5685 reload_inherited[r] = 1;
5687 /* If reg_reloaded_valid is not set for this register,
5688 there might be a stale spill_reg_store lying around.
5689 We must clear it, since otherwise emit_reload_insns
5690 might delete the store. */
5691 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5692 spill_reg_store[regno] = NULL_RTX;
5693 /* If any of the hard registers in EQUIV are spill
5694 registers, mark them as in use for this insn. */
5695 for (k = 0; k < nr; k++)
5697 i = spill_reg_order[regno + k];
5700 mark_reload_reg_in_use (regno, rld[r].opnum,
5703 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5710 /* If we found a register to use already, or if this is an optional
5711 reload, we are done. */
5712 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5716 /* No longer needed for correct operation. Might or might
5717 not give better code on the average. Want to experiment? */
5719 /* See if there is a later reload that has a class different from our
5720 class that intersects our class or that requires less register
5721 than our reload. If so, we must allocate a register to this
5722 reload now, since that reload might inherit a previous reload
5723 and take the only available register in our class. Don't do this
5724 for optional reloads since they will force all previous reloads
5725 to be allocated. Also don't do this for reloads that have been
5728 for (i = j + 1; i < n_reloads; i++)
5730 int s = reload_order[i];
5732 if ((rld[s].in == 0 && rld[s].out == 0
5733 && ! rld[s].secondary_p)
5737 if ((rld[s].class != rld[r].class
5738 && reg_classes_intersect_p (rld[r].class,
5740 || rld[s].nregs < rld[r].nregs)
5747 allocate_reload_reg (chain, r, j == n_reloads - 1);
5751 /* Now allocate reload registers for anything non-optional that
5752 didn't get one yet. */
5753 for (j = 0; j < n_reloads; j++)
5755 int r = reload_order[j];
5757 /* Ignore reloads that got marked inoperative. */
5758 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5761 /* Skip reloads that already have a register allocated or are
5763 if (rld[r].reg_rtx != 0 || rld[r].optional)
5766 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5770 /* If that loop got all the way, we have won. */
5777 /* Loop around and try without any inheritance. */
5782 /* First undo everything done by the failed attempt
5783 to allocate with inheritance. */
5784 choose_reload_regs_init (chain, save_reload_reg_rtx);
5786 /* Some sanity tests to verify that the reloads found in the first
5787 pass are identical to the ones we have now. */
5788 if (chain->n_reloads != n_reloads)
5791 for (i = 0; i < n_reloads; i++)
5793 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5795 if (chain->rld[i].when_needed != rld[i].when_needed)
5797 for (j = 0; j < n_spills; j++)
5798 if (spill_regs[j] == chain->rld[i].regno)
5799 if (! set_reload_reg (j, i))
5800 failed_reload (chain->insn, i);
5804 /* If we thought we could inherit a reload, because it seemed that
5805 nothing else wanted the same reload register earlier in the insn,
5806 verify that assumption, now that all reloads have been assigned.
5807 Likewise for reloads where reload_override_in has been set. */
5809 /* If doing expensive optimizations, do one preliminary pass that doesn't
5810 cancel any inheritance, but removes reloads that have been needed only
5811 for reloads that we know can be inherited. */
5812 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5814 for (j = 0; j < n_reloads; j++)
5816 int r = reload_order[j];
5818 if (reload_inherited[r] && rld[r].reg_rtx)
5819 check_reg = rld[r].reg_rtx;
5820 else if (reload_override_in[r]
5821 && (GET_CODE (reload_override_in[r]) == REG
5822 || GET_CODE (reload_override_in[r]) == SUBREG))
5823 check_reg = reload_override_in[r];
5826 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5827 rld[r].opnum, rld[r].when_needed, rld[r].in,
5828 (reload_inherited[r]
5829 ? rld[r].out : const0_rtx),
5834 reload_inherited[r] = 0;
5835 reload_override_in[r] = 0;
5837 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5838 reload_override_in, then we do not need its related
5839 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5840 likewise for other reload types.
5841 We handle this by removing a reload when its only replacement
5842 is mentioned in reload_in of the reload we are going to inherit.
5843 A special case are auto_inc expressions; even if the input is
5844 inherited, we still need the address for the output. We can
5845 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5846 If we succeeded removing some reload and we are doing a preliminary
5847 pass just to remove such reloads, make another pass, since the
5848 removal of one reload might allow us to inherit another one. */
5850 && rld[r].out != rld[r].in
5851 && remove_address_replacements (rld[r].in) && pass)
5856 /* Now that reload_override_in is known valid,
5857 actually override reload_in. */
5858 for (j = 0; j < n_reloads; j++)
5859 if (reload_override_in[j])
5860 rld[j].in = reload_override_in[j];
5862 /* If this reload won't be done because it has been canceled or is
5863 optional and not inherited, clear reload_reg_rtx so other
5864 routines (such as subst_reloads) don't get confused. */
5865 for (j = 0; j < n_reloads; j++)
5866 if (rld[j].reg_rtx != 0
5867 && ((rld[j].optional && ! reload_inherited[j])
5868 || (rld[j].in == 0 && rld[j].out == 0
5869 && ! rld[j].secondary_p)))
5871 int regno = true_regnum (rld[j].reg_rtx);
5873 if (spill_reg_order[regno] >= 0)
5874 clear_reload_reg_in_use (regno, rld[j].opnum,
5875 rld[j].when_needed, rld[j].mode);
5877 reload_spill_index[j] = -1;
5880 /* Record which pseudos and which spill regs have output reloads. */
5881 for (j = 0; j < n_reloads; j++)
5883 int r = reload_order[j];
5885 i = reload_spill_index[r];
5887 /* I is nonneg if this reload uses a register.
5888 If rld[r].reg_rtx is 0, this is an optional reload
5889 that we opted to ignore. */
5890 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5891 && rld[r].reg_rtx != 0)
5893 int nregno = REGNO (rld[r].out_reg);
5896 if (nregno < FIRST_PSEUDO_REGISTER)
5897 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5900 reg_has_output_reload[nregno + nr] = 1;
5904 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5906 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5909 if (rld[r].when_needed != RELOAD_OTHER
5910 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5911 && rld[r].when_needed != RELOAD_FOR_INSN)
5917 /* Deallocate the reload register for reload R. This is called from
5918 remove_address_replacements. */
5921 deallocate_reload_reg (int r)
5925 if (! rld[r].reg_rtx)
5927 regno = true_regnum (rld[r].reg_rtx);
5929 if (spill_reg_order[regno] >= 0)
5930 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5932 reload_spill_index[r] = -1;
5935 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5936 reloads of the same item for fear that we might not have enough reload
5937 registers. However, normally they will get the same reload register
5938 and hence actually need not be loaded twice.
5940 Here we check for the most common case of this phenomenon: when we have
5941 a number of reloads for the same object, each of which were allocated
5942 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5943 reload, and is not modified in the insn itself. If we find such,
5944 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5945 This will not increase the number of spill registers needed and will
5946 prevent redundant code. */
5949 merge_assigned_reloads (rtx insn)
5953 /* Scan all the reloads looking for ones that only load values and
5954 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5955 assigned and not modified by INSN. */
5957 for (i = 0; i < n_reloads; i++)
5959 int conflicting_input = 0;
5960 int max_input_address_opnum = -1;
5961 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5963 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5964 || rld[i].out != 0 || rld[i].reg_rtx == 0
5965 || reg_set_p (rld[i].reg_rtx, insn))
5968 /* Look at all other reloads. Ensure that the only use of this
5969 reload_reg_rtx is in a reload that just loads the same value
5970 as we do. Note that any secondary reloads must be of the identical
5971 class since the values, modes, and result registers are the
5972 same, so we need not do anything with any secondary reloads. */
5974 for (j = 0; j < n_reloads; j++)
5976 if (i == j || rld[j].reg_rtx == 0
5977 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5981 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5982 && rld[j].opnum > max_input_address_opnum)
5983 max_input_address_opnum = rld[j].opnum;
5985 /* If the reload regs aren't exactly the same (e.g, different modes)
5986 or if the values are different, we can't merge this reload.
5987 But if it is an input reload, we might still merge
5988 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5990 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5991 || rld[j].out != 0 || rld[j].in == 0
5992 || ! rtx_equal_p (rld[i].in, rld[j].in))
5994 if (rld[j].when_needed != RELOAD_FOR_INPUT
5995 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5996 || rld[i].opnum > rld[j].opnum)
5997 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5999 conflicting_input = 1;
6000 if (min_conflicting_input_opnum > rld[j].opnum)
6001 min_conflicting_input_opnum = rld[j].opnum;
6005 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6006 we, in fact, found any matching reloads. */
6009 && max_input_address_opnum <= min_conflicting_input_opnum)
6011 for (j = 0; j < n_reloads; j++)
6012 if (i != j && rld[j].reg_rtx != 0
6013 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6014 && (! conflicting_input
6015 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6016 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6018 rld[i].when_needed = RELOAD_OTHER;
6020 reload_spill_index[j] = -1;
6021 transfer_replacements (i, j);
6024 /* If this is now RELOAD_OTHER, look for any reloads that load
6025 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6026 if they were for inputs, RELOAD_OTHER for outputs. Note that
6027 this test is equivalent to looking for reloads for this operand
6029 /* We must take special care when there are two or more reloads to
6030 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6031 same value or a part of it; we must not change its type if there
6032 is a conflicting input. */
6034 if (rld[i].when_needed == RELOAD_OTHER)
6035 for (j = 0; j < n_reloads; j++)
6037 && rld[j].when_needed != RELOAD_OTHER
6038 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6039 && (! conflicting_input
6040 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6041 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6042 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6048 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6049 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6050 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6052 /* Check to see if we accidentally converted two reloads
6053 that use the same reload register with different inputs
6054 to the same type. If so, the resulting code won't work,
6057 for (k = 0; k < j; k++)
6058 if (rld[k].in != 0 && rld[k].reg_rtx != 0
6059 && rld[k].when_needed == rld[j].when_needed
6060 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx)
6061 && ! rtx_equal_p (rld[k].in, rld[j].in))
6068 /* These arrays are filled by emit_reload_insns and its subroutines. */
6069 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6070 static rtx other_input_address_reload_insns = 0;
6071 static rtx other_input_reload_insns = 0;
6072 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6073 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6074 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6075 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6076 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6077 static rtx operand_reload_insns = 0;
6078 static rtx other_operand_reload_insns = 0;
6079 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6081 /* Values to be put in spill_reg_store are put here first. */
6082 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6083 static HARD_REG_SET reg_reloaded_died;
6085 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6086 has the number J. OLD contains the value to be used as input. */
6089 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6092 rtx insn = chain->insn;
6093 rtx reloadreg = rl->reg_rtx;
6094 rtx oldequiv_reg = 0;
6097 enum machine_mode mode;
6100 /* Determine the mode to reload in.
6101 This is very tricky because we have three to choose from.
6102 There is the mode the insn operand wants (rl->inmode).
6103 There is the mode of the reload register RELOADREG.
6104 There is the intrinsic mode of the operand, which we could find
6105 by stripping some SUBREGs.
6106 It turns out that RELOADREG's mode is irrelevant:
6107 we can change that arbitrarily.
6109 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6110 then the reload reg may not support QImode moves, so use SImode.
6111 If foo is in memory due to spilling a pseudo reg, this is safe,
6112 because the QImode value is in the least significant part of a
6113 slot big enough for a SImode. If foo is some other sort of
6114 memory reference, then it is impossible to reload this case,
6115 so previous passes had better make sure this never happens.
6117 Then consider a one-word union which has SImode and one of its
6118 members is a float, being fetched as (SUBREG:SF union:SI).
6119 We must fetch that as SFmode because we could be loading into
6120 a float-only register. In this case OLD's mode is correct.
6122 Consider an immediate integer: it has VOIDmode. Here we need
6123 to get a mode from something else.
6125 In some cases, there is a fourth mode, the operand's
6126 containing mode. If the insn specifies a containing mode for
6127 this operand, it overrides all others.
6129 I am not sure whether the algorithm here is always right,
6130 but it does the right things in those cases. */
6132 mode = GET_MODE (old);
6133 if (mode == VOIDmode)
6136 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6137 /* If we need a secondary register for this operation, see if
6138 the value is already in a register in that class. Don't
6139 do this if the secondary register will be used as a scratch
6142 if (rl->secondary_in_reload >= 0
6143 && rl->secondary_in_icode == CODE_FOR_nothing
6146 = find_equiv_reg (old, insn,
6147 rld[rl->secondary_in_reload].class,
6151 /* If reloading from memory, see if there is a register
6152 that already holds the same value. If so, reload from there.
6153 We can pass 0 as the reload_reg_p argument because
6154 any other reload has either already been emitted,
6155 in which case find_equiv_reg will see the reload-insn,
6156 or has yet to be emitted, in which case it doesn't matter
6157 because we will use this equiv reg right away. */
6159 if (oldequiv == 0 && optimize
6160 && (GET_CODE (old) == MEM
6161 || (GET_CODE (old) == REG
6162 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6163 && reg_renumber[REGNO (old)] < 0)))
6164 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6168 unsigned int regno = true_regnum (oldequiv);
6170 /* Don't use OLDEQUIV if any other reload changes it at an
6171 earlier stage of this insn or at this stage. */
6172 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6173 rl->in, const0_rtx, j, 0))
6176 /* If it is no cheaper to copy from OLDEQUIV into the
6177 reload register than it would be to move from memory,
6178 don't use it. Likewise, if we need a secondary register
6182 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6183 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6185 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6186 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6187 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6191 #ifdef SECONDARY_MEMORY_NEEDED
6192 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6200 /* delete_output_reload is only invoked properly if old contains
6201 the original pseudo register. Since this is replaced with a
6202 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6203 find the pseudo in RELOAD_IN_REG. */
6205 && reload_override_in[j]
6206 && GET_CODE (rl->in_reg) == REG)
6213 else if (GET_CODE (oldequiv) == REG)
6214 oldequiv_reg = oldequiv;
6215 else if (GET_CODE (oldequiv) == SUBREG)
6216 oldequiv_reg = SUBREG_REG (oldequiv);
6218 /* If we are reloading from a register that was recently stored in
6219 with an output-reload, see if we can prove there was
6220 actually no need to store the old value in it. */
6222 if (optimize && GET_CODE (oldequiv) == REG
6223 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6224 && spill_reg_store[REGNO (oldequiv)]
6225 && GET_CODE (old) == REG
6226 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6227 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6229 delete_output_reload (insn, j, REGNO (oldequiv));
6231 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6232 then load RELOADREG from OLDEQUIV. Note that we cannot use
6233 gen_lowpart_common since it can do the wrong thing when
6234 RELOADREG has a multi-word mode. Note that RELOADREG
6235 must always be a REG here. */
6237 if (GET_MODE (reloadreg) != mode)
6238 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6239 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6240 oldequiv = SUBREG_REG (oldequiv);
6241 if (GET_MODE (oldequiv) != VOIDmode
6242 && mode != GET_MODE (oldequiv))
6243 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6245 /* Switch to the right place to emit the reload insns. */
6246 switch (rl->when_needed)
6249 where = &other_input_reload_insns;
6251 case RELOAD_FOR_INPUT:
6252 where = &input_reload_insns[rl->opnum];
6254 case RELOAD_FOR_INPUT_ADDRESS:
6255 where = &input_address_reload_insns[rl->opnum];
6257 case RELOAD_FOR_INPADDR_ADDRESS:
6258 where = &inpaddr_address_reload_insns[rl->opnum];
6260 case RELOAD_FOR_OUTPUT_ADDRESS:
6261 where = &output_address_reload_insns[rl->opnum];
6263 case RELOAD_FOR_OUTADDR_ADDRESS:
6264 where = &outaddr_address_reload_insns[rl->opnum];
6266 case RELOAD_FOR_OPERAND_ADDRESS:
6267 where = &operand_reload_insns;
6269 case RELOAD_FOR_OPADDR_ADDR:
6270 where = &other_operand_reload_insns;
6272 case RELOAD_FOR_OTHER_ADDRESS:
6273 where = &other_input_address_reload_insns;
6279 push_to_sequence (*where);
6281 /* Auto-increment addresses must be reloaded in a special way. */
6282 if (rl->out && ! rl->out_reg)
6284 /* We are not going to bother supporting the case where a
6285 incremented register can't be copied directly from
6286 OLDEQUIV since this seems highly unlikely. */
6287 if (rl->secondary_in_reload >= 0)
6290 if (reload_inherited[j])
6291 oldequiv = reloadreg;
6293 old = XEXP (rl->in_reg, 0);
6295 if (optimize && GET_CODE (oldequiv) == REG
6296 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6297 && spill_reg_store[REGNO (oldequiv)]
6298 && GET_CODE (old) == REG
6299 && (dead_or_set_p (insn,
6300 spill_reg_stored_to[REGNO (oldequiv)])
6301 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6303 delete_output_reload (insn, j, REGNO (oldequiv));
6305 /* Prevent normal processing of this reload. */
6307 /* Output a special code sequence for this case. */
6308 new_spill_reg_store[REGNO (reloadreg)]
6309 = inc_for_reload (reloadreg, oldequiv, rl->out,
6313 /* If we are reloading a pseudo-register that was set by the previous
6314 insn, see if we can get rid of that pseudo-register entirely
6315 by redirecting the previous insn into our reload register. */
6317 else if (optimize && GET_CODE (old) == REG
6318 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6319 && dead_or_set_p (insn, old)
6320 /* This is unsafe if some other reload
6321 uses the same reg first. */
6322 && ! conflicts_with_override (reloadreg)
6323 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6324 rl->when_needed, old, rl->out, j, 0))
6326 rtx temp = PREV_INSN (insn);
6327 while (temp && GET_CODE (temp) == NOTE)
6328 temp = PREV_INSN (temp);
6330 && GET_CODE (temp) == INSN
6331 && GET_CODE (PATTERN (temp)) == SET
6332 && SET_DEST (PATTERN (temp)) == old
6333 /* Make sure we can access insn_operand_constraint. */
6334 && asm_noperands (PATTERN (temp)) < 0
6335 /* This is unsafe if operand occurs more than once in current
6336 insn. Perhaps some occurrences aren't reloaded. */
6337 && count_occurrences (PATTERN (insn), old, 0) == 1)
6339 rtx old = SET_DEST (PATTERN (temp));
6340 /* Store into the reload register instead of the pseudo. */
6341 SET_DEST (PATTERN (temp)) = reloadreg;
6343 /* Verify that resulting insn is valid. */
6344 extract_insn (temp);
6345 if (constrain_operands (1))
6347 /* If the previous insn is an output reload, the source is
6348 a reload register, and its spill_reg_store entry will
6349 contain the previous destination. This is now
6351 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6352 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6354 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6355 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6358 /* If these are the only uses of the pseudo reg,
6359 pretend for GDB it lives in the reload reg we used. */
6360 if (REG_N_DEATHS (REGNO (old)) == 1
6361 && REG_N_SETS (REGNO (old)) == 1)
6363 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6364 alter_reg (REGNO (old), -1);
6370 SET_DEST (PATTERN (temp)) = old;
6375 /* We can't do that, so output an insn to load RELOADREG. */
6377 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6378 /* If we have a secondary reload, pick up the secondary register
6379 and icode, if any. If OLDEQUIV and OLD are different or
6380 if this is an in-out reload, recompute whether or not we
6381 still need a secondary register and what the icode should
6382 be. If we still need a secondary register and the class or
6383 icode is different, go back to reloading from OLD if using
6384 OLDEQUIV means that we got the wrong type of register. We
6385 cannot have different class or icode due to an in-out reload
6386 because we don't make such reloads when both the input and
6387 output need secondary reload registers. */
6389 if (! special && rl->secondary_in_reload >= 0)
6391 rtx second_reload_reg = 0;
6392 int secondary_reload = rl->secondary_in_reload;
6393 rtx real_oldequiv = oldequiv;
6396 enum insn_code icode;
6398 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6399 and similarly for OLD.
6400 See comments in get_secondary_reload in reload.c. */
6401 /* If it is a pseudo that cannot be replaced with its
6402 equivalent MEM, we must fall back to reload_in, which
6403 will have all the necessary substitutions registered.
6404 Likewise for a pseudo that can't be replaced with its
6405 equivalent constant.
6407 Take extra care for subregs of such pseudos. Note that
6408 we cannot use reg_equiv_mem in this case because it is
6409 not in the right mode. */
6412 if (GET_CODE (tmp) == SUBREG)
6413 tmp = SUBREG_REG (tmp);
6414 if (GET_CODE (tmp) == REG
6415 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6416 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6417 || reg_equiv_constant[REGNO (tmp)] != 0))
6419 if (! reg_equiv_mem[REGNO (tmp)]
6420 || num_not_at_initial_offset
6421 || GET_CODE (oldequiv) == SUBREG)
6422 real_oldequiv = rl->in;
6424 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6428 if (GET_CODE (tmp) == SUBREG)
6429 tmp = SUBREG_REG (tmp);
6430 if (GET_CODE (tmp) == REG
6431 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6432 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6433 || reg_equiv_constant[REGNO (tmp)] != 0))
6435 if (! reg_equiv_mem[REGNO (tmp)]
6436 || num_not_at_initial_offset
6437 || GET_CODE (old) == SUBREG)
6440 real_old = reg_equiv_mem[REGNO (tmp)];
6443 second_reload_reg = rld[secondary_reload].reg_rtx;
6444 icode = rl->secondary_in_icode;
6446 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6447 || (rl->in != 0 && rl->out != 0))
6449 enum reg_class new_class
6450 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6451 mode, real_oldequiv);
6453 if (new_class == NO_REGS)
6454 second_reload_reg = 0;
6457 enum insn_code new_icode;
6458 enum machine_mode new_mode;
6460 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6461 REGNO (second_reload_reg)))
6462 oldequiv = old, real_oldequiv = real_old;
6465 new_icode = reload_in_optab[(int) mode];
6466 if (new_icode != CODE_FOR_nothing
6467 && ((insn_data[(int) new_icode].operand[0].predicate
6468 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6470 || (insn_data[(int) new_icode].operand[1].predicate
6471 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6472 (real_oldequiv, mode)))))
6473 new_icode = CODE_FOR_nothing;
6475 if (new_icode == CODE_FOR_nothing)
6478 new_mode = insn_data[(int) new_icode].operand[2].mode;
6480 if (GET_MODE (second_reload_reg) != new_mode)
6482 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6484 oldequiv = old, real_oldequiv = real_old;
6487 = reload_adjust_reg_for_mode (second_reload_reg,
6494 /* If we still need a secondary reload register, check
6495 to see if it is being used as a scratch or intermediate
6496 register and generate code appropriately. If we need
6497 a scratch register, use REAL_OLDEQUIV since the form of
6498 the insn may depend on the actual address if it is
6501 if (second_reload_reg)
6503 if (icode != CODE_FOR_nothing)
6505 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6506 second_reload_reg));
6511 /* See if we need a scratch register to load the
6512 intermediate register (a tertiary reload). */
6513 enum insn_code tertiary_icode
6514 = rld[secondary_reload].secondary_in_icode;
6516 if (tertiary_icode != CODE_FOR_nothing)
6518 rtx third_reload_reg
6519 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6521 emit_insn ((GEN_FCN (tertiary_icode)
6522 (second_reload_reg, real_oldequiv,
6523 third_reload_reg)));
6526 gen_reload (second_reload_reg, real_oldequiv,
6530 oldequiv = second_reload_reg;
6536 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6538 rtx real_oldequiv = oldequiv;
6540 if ((GET_CODE (oldequiv) == REG
6541 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6542 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6543 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6544 || (GET_CODE (oldequiv) == SUBREG
6545 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6546 && (REGNO (SUBREG_REG (oldequiv))
6547 >= FIRST_PSEUDO_REGISTER)
6548 && ((reg_equiv_memory_loc
6549 [REGNO (SUBREG_REG (oldequiv))] != 0)
6550 || (reg_equiv_constant
6551 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6552 || (CONSTANT_P (oldequiv)
6553 && (PREFERRED_RELOAD_CLASS (oldequiv,
6554 REGNO_REG_CLASS (REGNO (reloadreg)))
6556 real_oldequiv = rl->in;
6557 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6561 if (flag_non_call_exceptions)
6562 copy_eh_notes (insn, get_insns ());
6564 /* End this sequence. */
6565 *where = get_insns ();
6568 /* Update reload_override_in so that delete_address_reloads_1
6569 can see the actual register usage. */
6571 reload_override_in[j] = oldequiv;
6574 /* Generate insns to for the output reload RL, which is for the insn described
6575 by CHAIN and has the number J. */
6577 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6580 rtx reloadreg = rl->reg_rtx;
6581 rtx insn = chain->insn;
6584 enum machine_mode mode = GET_MODE (old);
6587 if (rl->when_needed == RELOAD_OTHER)
6590 push_to_sequence (output_reload_insns[rl->opnum]);
6592 /* Determine the mode to reload in.
6593 See comments above (for input reloading). */
6595 if (mode == VOIDmode)
6597 /* VOIDmode should never happen for an output. */
6598 if (asm_noperands (PATTERN (insn)) < 0)
6599 /* It's the compiler's fault. */
6600 fatal_insn ("VOIDmode on an output", insn);
6601 error_for_asm (insn, "output operand is constant in `asm'");
6602 /* Prevent crash--use something we know is valid. */
6604 old = gen_rtx_REG (mode, REGNO (reloadreg));
6607 if (GET_MODE (reloadreg) != mode)
6608 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6610 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6612 /* If we need two reload regs, set RELOADREG to the intermediate
6613 one, since it will be stored into OLD. We might need a secondary
6614 register only for an input reload, so check again here. */
6616 if (rl->secondary_out_reload >= 0)
6620 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6621 && reg_equiv_mem[REGNO (old)] != 0)
6622 real_old = reg_equiv_mem[REGNO (old)];
6624 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6628 rtx second_reloadreg = reloadreg;
6629 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6631 /* See if RELOADREG is to be used as a scratch register
6632 or as an intermediate register. */
6633 if (rl->secondary_out_icode != CODE_FOR_nothing)
6635 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6636 (real_old, second_reloadreg, reloadreg)));
6641 /* See if we need both a scratch and intermediate reload
6644 int secondary_reload = rl->secondary_out_reload;
6645 enum insn_code tertiary_icode
6646 = rld[secondary_reload].secondary_out_icode;
6648 if (GET_MODE (reloadreg) != mode)
6649 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6651 if (tertiary_icode != CODE_FOR_nothing)
6654 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6657 /* Copy primary reload reg to secondary reload reg.
6658 (Note that these have been swapped above, then
6659 secondary reload reg to OLD using our insn.) */
6661 /* If REAL_OLD is a paradoxical SUBREG, remove it
6662 and try to put the opposite SUBREG on
6664 if (GET_CODE (real_old) == SUBREG
6665 && (GET_MODE_SIZE (GET_MODE (real_old))
6666 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6667 && 0 != (tem = gen_lowpart_common
6668 (GET_MODE (SUBREG_REG (real_old)),
6670 real_old = SUBREG_REG (real_old), reloadreg = tem;
6672 gen_reload (reloadreg, second_reloadreg,
6673 rl->opnum, rl->when_needed);
6674 emit_insn ((GEN_FCN (tertiary_icode)
6675 (real_old, reloadreg, third_reloadreg)));
6680 /* Copy between the reload regs here and then to
6683 gen_reload (reloadreg, second_reloadreg,
6684 rl->opnum, rl->when_needed);
6690 /* Output the last reload insn. */
6695 /* Don't output the last reload if OLD is not the dest of
6696 INSN and is in the src and is clobbered by INSN. */
6697 if (! flag_expensive_optimizations
6698 || GET_CODE (old) != REG
6699 || !(set = single_set (insn))
6700 || rtx_equal_p (old, SET_DEST (set))
6701 || !reg_mentioned_p (old, SET_SRC (set))
6702 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6703 gen_reload (old, reloadreg, rl->opnum,
6707 /* Look at all insns we emitted, just to be safe. */
6708 for (p = get_insns (); p; p = NEXT_INSN (p))
6711 rtx pat = PATTERN (p);
6713 /* If this output reload doesn't come from a spill reg,
6714 clear any memory of reloaded copies of the pseudo reg.
6715 If this output reload comes from a spill reg,
6716 reg_has_output_reload will make this do nothing. */
6717 note_stores (pat, forget_old_reloads_1, NULL);
6719 if (reg_mentioned_p (rl->reg_rtx, pat))
6721 rtx set = single_set (insn);
6722 if (reload_spill_index[j] < 0
6724 && SET_SRC (set) == rl->reg_rtx)
6726 int src = REGNO (SET_SRC (set));
6728 reload_spill_index[j] = src;
6729 SET_HARD_REG_BIT (reg_is_output_reload, src);
6730 if (find_regno_note (insn, REG_DEAD, src))
6731 SET_HARD_REG_BIT (reg_reloaded_died, src);
6733 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6735 int s = rl->secondary_out_reload;
6736 set = single_set (p);
6737 /* If this reload copies only to the secondary reload
6738 register, the secondary reload does the actual
6740 if (s >= 0 && set == NULL_RTX)
6741 /* We can't tell what function the secondary reload
6742 has and where the actual store to the pseudo is
6743 made; leave new_spill_reg_store alone. */
6746 && SET_SRC (set) == rl->reg_rtx
6747 && SET_DEST (set) == rld[s].reg_rtx)
6749 /* Usually the next instruction will be the
6750 secondary reload insn; if we can confirm
6751 that it is, setting new_spill_reg_store to
6752 that insn will allow an extra optimization. */
6753 rtx s_reg = rld[s].reg_rtx;
6754 rtx next = NEXT_INSN (p);
6755 rld[s].out = rl->out;
6756 rld[s].out_reg = rl->out_reg;
6757 set = single_set (next);
6758 if (set && SET_SRC (set) == s_reg
6759 && ! new_spill_reg_store[REGNO (s_reg)])
6761 SET_HARD_REG_BIT (reg_is_output_reload,
6763 new_spill_reg_store[REGNO (s_reg)] = next;
6767 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6772 if (rl->when_needed == RELOAD_OTHER)
6774 emit_insn (other_output_reload_insns[rl->opnum]);
6775 other_output_reload_insns[rl->opnum] = get_insns ();
6778 output_reload_insns[rl->opnum] = get_insns ();
6780 if (flag_non_call_exceptions)
6781 copy_eh_notes (insn, get_insns ());
6786 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6787 and has the number J. */
6789 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6791 rtx insn = chain->insn;
6792 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6793 ? rl->in_reg : rl->in);
6796 /* AUTO_INC reloads need to be handled even if inherited. We got an
6797 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6798 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6799 && ! rtx_equal_p (rl->reg_rtx, old)
6800 && rl->reg_rtx != 0)
6801 emit_input_reload_insns (chain, rld + j, old, j);
6803 /* When inheriting a wider reload, we have a MEM in rl->in,
6804 e.g. inheriting a SImode output reload for
6805 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6806 if (optimize && reload_inherited[j] && rl->in
6807 && GET_CODE (rl->in) == MEM
6808 && GET_CODE (rl->in_reg) == MEM
6809 && reload_spill_index[j] >= 0
6810 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6811 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6813 /* If we are reloading a register that was recently stored in with an
6814 output-reload, see if we can prove there was
6815 actually no need to store the old value in it. */
6818 && (reload_inherited[j] || reload_override_in[j])
6820 && GET_CODE (rl->reg_rtx) == REG
6821 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6823 /* There doesn't seem to be any reason to restrict this to pseudos
6824 and doing so loses in the case where we are copying from a
6825 register of the wrong class. */
6826 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6827 >= FIRST_PSEUDO_REGISTER)
6829 /* The insn might have already some references to stackslots
6830 replaced by MEMs, while reload_out_reg still names the
6832 && (dead_or_set_p (insn,
6833 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6834 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6836 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6839 /* Do output reloading for reload RL, which is for the insn described by
6840 CHAIN and has the number J.
6841 ??? At some point we need to support handling output reloads of
6842 JUMP_INSNs or insns that set cc0. */
6844 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6847 rtx insn = chain->insn;
6848 /* If this is an output reload that stores something that is
6849 not loaded in this same reload, see if we can eliminate a previous
6851 rtx pseudo = rl->out_reg;
6855 && GET_CODE (pseudo) == REG
6856 && ! rtx_equal_p (rl->in_reg, pseudo)
6857 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6858 && reg_last_reload_reg[REGNO (pseudo)])
6860 int pseudo_no = REGNO (pseudo);
6861 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6863 /* We don't need to test full validity of last_regno for
6864 inherit here; we only want to know if the store actually
6865 matches the pseudo. */
6866 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6867 && reg_reloaded_contents[last_regno] == pseudo_no
6868 && spill_reg_store[last_regno]
6869 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6870 delete_output_reload (insn, j, last_regno);
6875 || rl->reg_rtx == old
6876 || rl->reg_rtx == 0)
6879 /* An output operand that dies right away does need a reload,
6880 but need not be copied from it. Show the new location in the
6882 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6883 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6885 XEXP (note, 0) = rl->reg_rtx;
6888 /* Likewise for a SUBREG of an operand that dies. */
6889 else if (GET_CODE (old) == SUBREG
6890 && GET_CODE (SUBREG_REG (old)) == REG
6891 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6894 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6898 else if (GET_CODE (old) == SCRATCH)
6899 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6900 but we don't want to make an output reload. */
6903 /* If is a JUMP_INSN, we can't support output reloads yet. */
6904 if (GET_CODE (insn) == JUMP_INSN)
6907 emit_output_reload_insns (chain, rld + j, j);
6910 /* Output insns to reload values in and out of the chosen reload regs. */
6913 emit_reload_insns (struct insn_chain *chain)
6915 rtx insn = chain->insn;
6919 CLEAR_HARD_REG_SET (reg_reloaded_died);
6921 for (j = 0; j < reload_n_operands; j++)
6922 input_reload_insns[j] = input_address_reload_insns[j]
6923 = inpaddr_address_reload_insns[j]
6924 = output_reload_insns[j] = output_address_reload_insns[j]
6925 = outaddr_address_reload_insns[j]
6926 = other_output_reload_insns[j] = 0;
6927 other_input_address_reload_insns = 0;
6928 other_input_reload_insns = 0;
6929 operand_reload_insns = 0;
6930 other_operand_reload_insns = 0;
6932 /* Dump reloads into the dump file. */
6935 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6936 debug_reload_to_stream (rtl_dump_file);
6939 /* Now output the instructions to copy the data into and out of the
6940 reload registers. Do these in the order that the reloads were reported,
6941 since reloads of base and index registers precede reloads of operands
6942 and the operands may need the base and index registers reloaded. */
6944 for (j = 0; j < n_reloads; j++)
6947 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6948 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6950 do_input_reload (chain, rld + j, j);
6951 do_output_reload (chain, rld + j, j);
6954 /* Now write all the insns we made for reloads in the order expected by
6955 the allocation functions. Prior to the insn being reloaded, we write
6956 the following reloads:
6958 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6960 RELOAD_OTHER reloads.
6962 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6963 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6964 RELOAD_FOR_INPUT reload for the operand.
6966 RELOAD_FOR_OPADDR_ADDRS reloads.
6968 RELOAD_FOR_OPERAND_ADDRESS reloads.
6970 After the insn being reloaded, we write the following:
6972 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6973 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6974 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6975 reloads for the operand. The RELOAD_OTHER output reloads are
6976 output in descending order by reload number. */
6978 emit_insn_before (other_input_address_reload_insns, insn);
6979 emit_insn_before (other_input_reload_insns, insn);
6981 for (j = 0; j < reload_n_operands; j++)
6983 emit_insn_before (inpaddr_address_reload_insns[j], insn);
6984 emit_insn_before (input_address_reload_insns[j], insn);
6985 emit_insn_before (input_reload_insns[j], insn);
6988 emit_insn_before (other_operand_reload_insns, insn);
6989 emit_insn_before (operand_reload_insns, insn);
6991 for (j = 0; j < reload_n_operands; j++)
6993 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
6994 x = emit_insn_after (output_address_reload_insns[j], x);
6995 x = emit_insn_after (output_reload_insns[j], x);
6996 emit_insn_after (other_output_reload_insns[j], x);
6999 /* For all the spill regs newly reloaded in this instruction,
7000 record what they were reloaded from, so subsequent instructions
7001 can inherit the reloads.
7003 Update spill_reg_store for the reloads of this insn.
7004 Copy the elements that were updated in the loop above. */
7006 for (j = 0; j < n_reloads; j++)
7008 int r = reload_order[j];
7009 int i = reload_spill_index[r];
7011 /* If this is a non-inherited input reload from a pseudo, we must
7012 clear any memory of a previous store to the same pseudo. Only do
7013 something if there will not be an output reload for the pseudo
7015 if (rld[r].in_reg != 0
7016 && ! (reload_inherited[r] || reload_override_in[r]))
7018 rtx reg = rld[r].in_reg;
7020 if (GET_CODE (reg) == SUBREG)
7021 reg = SUBREG_REG (reg);
7023 if (GET_CODE (reg) == REG
7024 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7025 && ! reg_has_output_reload[REGNO (reg)])
7027 int nregno = REGNO (reg);
7029 if (reg_last_reload_reg[nregno])
7031 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7033 if (reg_reloaded_contents[last_regno] == nregno)
7034 spill_reg_store[last_regno] = 0;
7039 /* I is nonneg if this reload used a register.
7040 If rld[r].reg_rtx is 0, this is an optional reload
7041 that we opted to ignore. */
7043 if (i >= 0 && rld[r].reg_rtx != 0)
7045 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7047 int part_reaches_end = 0;
7048 int all_reaches_end = 1;
7050 /* For a multi register reload, we need to check if all or part
7051 of the value lives to the end. */
7052 for (k = 0; k < nr; k++)
7054 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7055 rld[r].when_needed))
7056 part_reaches_end = 1;
7058 all_reaches_end = 0;
7061 /* Ignore reloads that don't reach the end of the insn in
7063 if (all_reaches_end)
7065 /* First, clear out memory of what used to be in this spill reg.
7066 If consecutive registers are used, clear them all. */
7068 for (k = 0; k < nr; k++)
7070 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7071 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7074 /* Maybe the spill reg contains a copy of reload_out. */
7076 && (GET_CODE (rld[r].out) == REG
7080 || GET_CODE (rld[r].out_reg) == REG))
7082 rtx out = (GET_CODE (rld[r].out) == REG
7086 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7087 int nregno = REGNO (out);
7088 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7089 : HARD_REGNO_NREGS (nregno,
7090 GET_MODE (rld[r].reg_rtx)));
7092 spill_reg_store[i] = new_spill_reg_store[i];
7093 spill_reg_stored_to[i] = out;
7094 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7096 /* If NREGNO is a hard register, it may occupy more than
7097 one register. If it does, say what is in the
7098 rest of the registers assuming that both registers
7099 agree on how many words the object takes. If not,
7100 invalidate the subsequent registers. */
7102 if (nregno < FIRST_PSEUDO_REGISTER)
7103 for (k = 1; k < nnr; k++)
7104 reg_last_reload_reg[nregno + k]
7106 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7109 /* Now do the inverse operation. */
7110 for (k = 0; k < nr; k++)
7112 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7113 reg_reloaded_contents[i + k]
7114 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7117 reg_reloaded_insn[i + k] = insn;
7118 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7119 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7120 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7124 /* Maybe the spill reg contains a copy of reload_in. Only do
7125 something if there will not be an output reload for
7126 the register being reloaded. */
7127 else if (rld[r].out_reg == 0
7129 && ((GET_CODE (rld[r].in) == REG
7130 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7131 && ! reg_has_output_reload[REGNO (rld[r].in)])
7132 || (GET_CODE (rld[r].in_reg) == REG
7133 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7134 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7140 if (GET_CODE (rld[r].in) == REG
7141 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7143 else if (GET_CODE (rld[r].in_reg) == REG)
7146 in = XEXP (rld[r].in_reg, 0);
7147 nregno = REGNO (in);
7149 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7150 : HARD_REGNO_NREGS (nregno,
7151 GET_MODE (rld[r].reg_rtx)));
7153 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7155 if (nregno < FIRST_PSEUDO_REGISTER)
7156 for (k = 1; k < nnr; k++)
7157 reg_last_reload_reg[nregno + k]
7159 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7162 /* Unless we inherited this reload, show we haven't
7163 recently done a store.
7164 Previous stores of inherited auto_inc expressions
7165 also have to be discarded. */
7166 if (! reload_inherited[r]
7167 || (rld[r].out && ! rld[r].out_reg))
7168 spill_reg_store[i] = 0;
7170 for (k = 0; k < nr; k++)
7172 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7173 reg_reloaded_contents[i + k]
7174 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7177 reg_reloaded_insn[i + k] = insn;
7178 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7179 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7180 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7185 /* However, if part of the reload reaches the end, then we must
7186 invalidate the old info for the part that survives to the end. */
7187 else if (part_reaches_end)
7189 for (k = 0; k < nr; k++)
7190 if (reload_reg_reaches_end_p (i + k,
7192 rld[r].when_needed))
7193 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7197 /* The following if-statement was #if 0'd in 1.34 (or before...).
7198 It's reenabled in 1.35 because supposedly nothing else
7199 deals with this problem. */
7201 /* If a register gets output-reloaded from a non-spill register,
7202 that invalidates any previous reloaded copy of it.
7203 But forget_old_reloads_1 won't get to see it, because
7204 it thinks only about the original insn. So invalidate it here. */
7205 if (i < 0 && rld[r].out != 0
7206 && (GET_CODE (rld[r].out) == REG
7207 || (GET_CODE (rld[r].out) == MEM
7208 && GET_CODE (rld[r].out_reg) == REG)))
7210 rtx out = (GET_CODE (rld[r].out) == REG
7211 ? rld[r].out : rld[r].out_reg);
7212 int nregno = REGNO (out);
7213 if (nregno >= FIRST_PSEUDO_REGISTER)
7215 rtx src_reg, store_insn = NULL_RTX;
7217 reg_last_reload_reg[nregno] = 0;
7219 /* If we can find a hard register that is stored, record
7220 the storing insn so that we may delete this insn with
7221 delete_output_reload. */
7222 src_reg = rld[r].reg_rtx;
7224 /* If this is an optional reload, try to find the source reg
7225 from an input reload. */
7228 rtx set = single_set (insn);
7229 if (set && SET_DEST (set) == rld[r].out)
7233 src_reg = SET_SRC (set);
7235 for (k = 0; k < n_reloads; k++)
7237 if (rld[k].in == src_reg)
7239 src_reg = rld[k].reg_rtx;
7246 store_insn = new_spill_reg_store[REGNO (src_reg)];
7247 if (src_reg && GET_CODE (src_reg) == REG
7248 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7250 int src_regno = REGNO (src_reg);
7251 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7252 /* The place where to find a death note varies with
7253 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7254 necessarily checked exactly in the code that moves
7255 notes, so just check both locations. */
7256 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7257 if (! note && store_insn)
7258 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7261 spill_reg_store[src_regno + nr] = store_insn;
7262 spill_reg_stored_to[src_regno + nr] = out;
7263 reg_reloaded_contents[src_regno + nr] = nregno;
7264 reg_reloaded_insn[src_regno + nr] = store_insn;
7265 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7266 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7267 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7268 GET_MODE (src_reg)))
7269 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7271 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7273 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7275 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7277 reg_last_reload_reg[nregno] = src_reg;
7278 /* We have to set reg_has_output_reload here, or else
7279 forget_old_reloads_1 will clear reg_last_reload_reg
7281 reg_has_output_reload[nregno] = 1;
7286 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7288 while (num_regs-- > 0)
7289 reg_last_reload_reg[nregno + num_regs] = 0;
7293 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7296 /* Emit code to perform a reload from IN (which may be a reload register) to
7297 OUT (which may also be a reload register). IN or OUT is from operand
7298 OPNUM with reload type TYPE.
7300 Returns first insn emitted. */
7303 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7305 rtx last = get_last_insn ();
7308 /* If IN is a paradoxical SUBREG, remove it and try to put the
7309 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7310 if (GET_CODE (in) == SUBREG
7311 && (GET_MODE_SIZE (GET_MODE (in))
7312 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7313 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7314 in = SUBREG_REG (in), out = tem;
7315 else if (GET_CODE (out) == SUBREG
7316 && (GET_MODE_SIZE (GET_MODE (out))
7317 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7318 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7319 out = SUBREG_REG (out), in = tem;
7321 /* How to do this reload can get quite tricky. Normally, we are being
7322 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7323 register that didn't get a hard register. In that case we can just
7324 call emit_move_insn.
7326 We can also be asked to reload a PLUS that adds a register or a MEM to
7327 another register, constant or MEM. This can occur during frame pointer
7328 elimination and while reloading addresses. This case is handled by
7329 trying to emit a single insn to perform the add. If it is not valid,
7330 we use a two insn sequence.
7332 Finally, we could be called to handle an 'o' constraint by putting
7333 an address into a register. In that case, we first try to do this
7334 with a named pattern of "reload_load_address". If no such pattern
7335 exists, we just emit a SET insn and hope for the best (it will normally
7336 be valid on machines that use 'o').
7338 This entire process is made complex because reload will never
7339 process the insns we generate here and so we must ensure that
7340 they will fit their constraints and also by the fact that parts of
7341 IN might be being reloaded separately and replaced with spill registers.
7342 Because of this, we are, in some sense, just guessing the right approach
7343 here. The one listed above seems to work.
7345 ??? At some point, this whole thing needs to be rethought. */
7347 if (GET_CODE (in) == PLUS
7348 && (GET_CODE (XEXP (in, 0)) == REG
7349 || GET_CODE (XEXP (in, 0)) == SUBREG
7350 || GET_CODE (XEXP (in, 0)) == MEM)
7351 && (GET_CODE (XEXP (in, 1)) == REG
7352 || GET_CODE (XEXP (in, 1)) == SUBREG
7353 || CONSTANT_P (XEXP (in, 1))
7354 || GET_CODE (XEXP (in, 1)) == MEM))
7356 /* We need to compute the sum of a register or a MEM and another
7357 register, constant, or MEM, and put it into the reload
7358 register. The best possible way of doing this is if the machine
7359 has a three-operand ADD insn that accepts the required operands.
7361 The simplest approach is to try to generate such an insn and see if it
7362 is recognized and matches its constraints. If so, it can be used.
7364 It might be better not to actually emit the insn unless it is valid,
7365 but we need to pass the insn as an operand to `recog' and
7366 `extract_insn' and it is simpler to emit and then delete the insn if
7367 not valid than to dummy things up. */
7369 rtx op0, op1, tem, insn;
7372 op0 = find_replacement (&XEXP (in, 0));
7373 op1 = find_replacement (&XEXP (in, 1));
7375 /* Since constraint checking is strict, commutativity won't be
7376 checked, so we need to do that here to avoid spurious failure
7377 if the add instruction is two-address and the second operand
7378 of the add is the same as the reload reg, which is frequently
7379 the case. If the insn would be A = B + A, rearrange it so
7380 it will be A = A + B as constrain_operands expects. */
7382 if (GET_CODE (XEXP (in, 1)) == REG
7383 && REGNO (out) == REGNO (XEXP (in, 1)))
7384 tem = op0, op0 = op1, op1 = tem;
7386 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7387 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7389 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7390 code = recog_memoized (insn);
7394 extract_insn (insn);
7395 /* We want constrain operands to treat this insn strictly in
7396 its validity determination, i.e., the way it would after reload
7398 if (constrain_operands (1))
7402 delete_insns_since (last);
7404 /* If that failed, we must use a conservative two-insn sequence.
7406 Use a move to copy one operand into the reload register. Prefer
7407 to reload a constant, MEM or pseudo since the move patterns can
7408 handle an arbitrary operand. If OP1 is not a constant, MEM or
7409 pseudo and OP1 is not a valid operand for an add instruction, then
7412 After reloading one of the operands into the reload register, add
7413 the reload register to the output register.
7415 If there is another way to do this for a specific machine, a
7416 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7419 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7421 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7422 || (GET_CODE (op1) == REG
7423 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7424 || (code != CODE_FOR_nothing
7425 && ! ((*insn_data[code].operand[2].predicate)
7426 (op1, insn_data[code].operand[2].mode))))
7427 tem = op0, op0 = op1, op1 = tem;
7429 gen_reload (out, op0, opnum, type);
7431 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7432 This fixes a problem on the 32K where the stack pointer cannot
7433 be used as an operand of an add insn. */
7435 if (rtx_equal_p (op0, op1))
7438 insn = emit_insn (gen_add2_insn (out, op1));
7440 /* If that failed, copy the address register to the reload register.
7441 Then add the constant to the reload register. */
7443 code = recog_memoized (insn);
7447 extract_insn (insn);
7448 /* We want constrain operands to treat this insn strictly in
7449 its validity determination, i.e., the way it would after reload
7451 if (constrain_operands (1))
7453 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7455 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7460 delete_insns_since (last);
7462 gen_reload (out, op1, opnum, type);
7463 insn = emit_insn (gen_add2_insn (out, op0));
7464 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7467 #ifdef SECONDARY_MEMORY_NEEDED
7468 /* If we need a memory location to do the move, do it that way. */
7469 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG)
7470 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7471 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG)
7472 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7473 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7474 REGNO_REG_CLASS (reg_or_subregno (out)),
7477 /* Get the memory to use and rewrite both registers to its mode. */
7478 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7480 if (GET_MODE (loc) != GET_MODE (out))
7481 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7483 if (GET_MODE (loc) != GET_MODE (in))
7484 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7486 gen_reload (loc, in, opnum, type);
7487 gen_reload (out, loc, opnum, type);
7491 /* If IN is a simple operand, use gen_move_insn. */
7492 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7493 emit_insn (gen_move_insn (out, in));
7495 #ifdef HAVE_reload_load_address
7496 else if (HAVE_reload_load_address)
7497 emit_insn (gen_reload_load_address (out, in));
7500 /* Otherwise, just write (set OUT IN) and hope for the best. */
7502 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7504 /* Return the first insn emitted.
7505 We can not just return get_last_insn, because there may have
7506 been multiple instructions emitted. Also note that gen_move_insn may
7507 emit more than one insn itself, so we can not assume that there is one
7508 insn emitted per emit_insn_before call. */
7510 return last ? NEXT_INSN (last) : get_insns ();
7513 /* Delete a previously made output-reload whose result we now believe
7514 is not needed. First we double-check.
7516 INSN is the insn now being processed.
7517 LAST_RELOAD_REG is the hard register number for which we want to delete
7518 the last output reload.
7519 J is the reload-number that originally used REG. The caller has made
7520 certain that reload J doesn't use REG any longer for input. */
7523 delete_output_reload (rtx insn, int j, int last_reload_reg)
7525 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7526 rtx reg = spill_reg_stored_to[last_reload_reg];
7529 int n_inherited = 0;
7533 /* It is possible that this reload has been only used to set another reload
7534 we eliminated earlier and thus deleted this instruction too. */
7535 if (INSN_DELETED_P (output_reload_insn))
7538 /* Get the raw pseudo-register referred to. */
7540 while (GET_CODE (reg) == SUBREG)
7541 reg = SUBREG_REG (reg);
7542 substed = reg_equiv_memory_loc[REGNO (reg)];
7544 /* This is unsafe if the operand occurs more often in the current
7545 insn than it is inherited. */
7546 for (k = n_reloads - 1; k >= 0; k--)
7548 rtx reg2 = rld[k].in;
7551 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7552 reg2 = rld[k].in_reg;
7554 if (rld[k].out && ! rld[k].out_reg)
7555 reg2 = XEXP (rld[k].in_reg, 0);
7557 while (GET_CODE (reg2) == SUBREG)
7558 reg2 = SUBREG_REG (reg2);
7559 if (rtx_equal_p (reg2, reg))
7561 if (reload_inherited[k] || reload_override_in[k] || k == j)
7564 reg2 = rld[k].out_reg;
7567 while (GET_CODE (reg2) == SUBREG)
7568 reg2 = XEXP (reg2, 0);
7569 if (rtx_equal_p (reg2, reg))
7576 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7578 n_occurrences += count_occurrences (PATTERN (insn),
7579 eliminate_regs (substed, 0,
7581 if (n_occurrences > n_inherited)
7584 /* If the pseudo-reg we are reloading is no longer referenced
7585 anywhere between the store into it and here,
7586 and no jumps or labels intervene, then the value can get
7587 here through the reload reg alone.
7588 Otherwise, give up--return. */
7589 for (i1 = NEXT_INSN (output_reload_insn);
7590 i1 != insn; i1 = NEXT_INSN (i1))
7592 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7594 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7595 && reg_mentioned_p (reg, PATTERN (i1)))
7597 /* If this is USE in front of INSN, we only have to check that
7598 there are no more references than accounted for by inheritance. */
7599 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7601 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7602 i1 = NEXT_INSN (i1);
7604 if (n_occurrences <= n_inherited && i1 == insn)
7610 /* We will be deleting the insn. Remove the spill reg information. */
7611 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; )
7613 spill_reg_store[last_reload_reg + k] = 0;
7614 spill_reg_stored_to[last_reload_reg + k] = 0;
7617 /* The caller has already checked that REG dies or is set in INSN.
7618 It has also checked that we are optimizing, and thus some
7619 inaccuracies in the debugging information are acceptable.
7620 So we could just delete output_reload_insn. But in some cases
7621 we can improve the debugging information without sacrificing
7622 optimization - maybe even improving the code: See if the pseudo
7623 reg has been completely replaced with reload regs. If so, delete
7624 the store insn and forget we had a stack slot for the pseudo. */
7625 if (rld[j].out != rld[j].in
7626 && REG_N_DEATHS (REGNO (reg)) == 1
7627 && REG_N_SETS (REGNO (reg)) == 1
7628 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7629 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7633 /* We know that it was used only between here and the beginning of
7634 the current basic block. (We also know that the last use before
7635 INSN was the output reload we are thinking of deleting, but never
7636 mind that.) Search that range; see if any ref remains. */
7637 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7639 rtx set = single_set (i2);
7641 /* Uses which just store in the pseudo don't count,
7642 since if they are the only uses, they are dead. */
7643 if (set != 0 && SET_DEST (set) == reg)
7645 if (GET_CODE (i2) == CODE_LABEL
7646 || GET_CODE (i2) == JUMP_INSN)
7648 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7649 && reg_mentioned_p (reg, PATTERN (i2)))
7651 /* Some other ref remains; just delete the output reload we
7653 delete_address_reloads (output_reload_insn, insn);
7654 delete_insn (output_reload_insn);
7659 /* Delete the now-dead stores into this pseudo. Note that this
7660 loop also takes care of deleting output_reload_insn. */
7661 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7663 rtx set = single_set (i2);
7665 if (set != 0 && SET_DEST (set) == reg)
7667 delete_address_reloads (i2, insn);
7670 if (GET_CODE (i2) == CODE_LABEL
7671 || GET_CODE (i2) == JUMP_INSN)
7675 /* For the debugging info, say the pseudo lives in this reload reg. */
7676 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7677 alter_reg (REGNO (reg), -1);
7681 delete_address_reloads (output_reload_insn, insn);
7682 delete_insn (output_reload_insn);
7686 /* We are going to delete DEAD_INSN. Recursively delete loads of
7687 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7688 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7690 delete_address_reloads (rtx dead_insn, rtx current_insn)
7692 rtx set = single_set (dead_insn);
7693 rtx set2, dst, prev, next;
7696 rtx dst = SET_DEST (set);
7697 if (GET_CODE (dst) == MEM)
7698 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7700 /* If we deleted the store from a reloaded post_{in,de}c expression,
7701 we can delete the matching adds. */
7702 prev = PREV_INSN (dead_insn);
7703 next = NEXT_INSN (dead_insn);
7704 if (! prev || ! next)
7706 set = single_set (next);
7707 set2 = single_set (prev);
7709 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7710 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7711 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7713 dst = SET_DEST (set);
7714 if (! rtx_equal_p (dst, SET_DEST (set2))
7715 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7716 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7717 || (INTVAL (XEXP (SET_SRC (set), 1))
7718 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7720 delete_related_insns (prev);
7721 delete_related_insns (next);
7724 /* Subfunction of delete_address_reloads: process registers found in X. */
7726 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7728 rtx prev, set, dst, i2;
7730 enum rtx_code code = GET_CODE (x);
7734 const char *fmt = GET_RTX_FORMAT (code);
7735 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7738 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7739 else if (fmt[i] == 'E')
7741 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7742 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7749 if (spill_reg_order[REGNO (x)] < 0)
7752 /* Scan backwards for the insn that sets x. This might be a way back due
7754 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7756 code = GET_CODE (prev);
7757 if (code == CODE_LABEL || code == JUMP_INSN)
7759 if (GET_RTX_CLASS (code) != 'i')
7761 if (reg_set_p (x, PATTERN (prev)))
7763 if (reg_referenced_p (x, PATTERN (prev)))
7766 if (! prev || INSN_UID (prev) < reload_first_uid)
7768 /* Check that PREV only sets the reload register. */
7769 set = single_set (prev);
7772 dst = SET_DEST (set);
7773 if (GET_CODE (dst) != REG
7774 || ! rtx_equal_p (dst, x))
7776 if (! reg_set_p (dst, PATTERN (dead_insn)))
7778 /* Check if DST was used in a later insn -
7779 it might have been inherited. */
7780 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7782 if (GET_CODE (i2) == CODE_LABEL)
7786 if (reg_referenced_p (dst, PATTERN (i2)))
7788 /* If there is a reference to the register in the current insn,
7789 it might be loaded in a non-inherited reload. If no other
7790 reload uses it, that means the register is set before
7792 if (i2 == current_insn)
7794 for (j = n_reloads - 1; j >= 0; j--)
7795 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7796 || reload_override_in[j] == dst)
7798 for (j = n_reloads - 1; j >= 0; j--)
7799 if (rld[j].in && rld[j].reg_rtx == dst)
7806 if (GET_CODE (i2) == JUMP_INSN)
7808 /* If DST is still live at CURRENT_INSN, check if it is used for
7809 any reload. Note that even if CURRENT_INSN sets DST, we still
7810 have to check the reloads. */
7811 if (i2 == current_insn)
7813 for (j = n_reloads - 1; j >= 0; j--)
7814 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7815 || reload_override_in[j] == dst)
7817 /* ??? We can't finish the loop here, because dst might be
7818 allocated to a pseudo in this block if no reload in this
7819 block needs any of the classes containing DST - see
7820 spill_hard_reg. There is no easy way to tell this, so we
7821 have to scan till the end of the basic block. */
7823 if (reg_set_p (dst, PATTERN (i2)))
7827 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7828 reg_reloaded_contents[REGNO (dst)] = -1;
7832 /* Output reload-insns to reload VALUE into RELOADREG.
7833 VALUE is an autoincrement or autodecrement RTX whose operand
7834 is a register or memory location;
7835 so reloading involves incrementing that location.
7836 IN is either identical to VALUE, or some cheaper place to reload from.
7838 INC_AMOUNT is the number to increment or decrement by (always positive).
7839 This cannot be deduced from VALUE.
7841 Return the instruction that stores into RELOADREG. */
7844 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7846 /* REG or MEM to be copied and incremented. */
7847 rtx incloc = XEXP (value, 0);
7848 /* Nonzero if increment after copying. */
7849 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7855 rtx real_in = in == value ? XEXP (in, 0) : in;
7857 /* No hard register is equivalent to this register after
7858 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7859 we could inc/dec that register as well (maybe even using it for
7860 the source), but I'm not sure it's worth worrying about. */
7861 if (GET_CODE (incloc) == REG)
7862 reg_last_reload_reg[REGNO (incloc)] = 0;
7864 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7865 inc_amount = -inc_amount;
7867 inc = GEN_INT (inc_amount);
7869 /* If this is post-increment, first copy the location to the reload reg. */
7870 if (post && real_in != reloadreg)
7871 emit_insn (gen_move_insn (reloadreg, real_in));
7875 /* See if we can directly increment INCLOC. Use a method similar to
7876 that in gen_reload. */
7878 last = get_last_insn ();
7879 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7880 gen_rtx_PLUS (GET_MODE (incloc),
7883 code = recog_memoized (add_insn);
7886 extract_insn (add_insn);
7887 if (constrain_operands (1))
7889 /* If this is a pre-increment and we have incremented the value
7890 where it lives, copy the incremented value to RELOADREG to
7891 be used as an address. */
7894 emit_insn (gen_move_insn (reloadreg, incloc));
7899 delete_insns_since (last);
7902 /* If couldn't do the increment directly, must increment in RELOADREG.
7903 The way we do this depends on whether this is pre- or post-increment.
7904 For pre-increment, copy INCLOC to the reload register, increment it
7905 there, then save back. */
7909 if (in != reloadreg)
7910 emit_insn (gen_move_insn (reloadreg, real_in));
7911 emit_insn (gen_add2_insn (reloadreg, inc));
7912 store = emit_insn (gen_move_insn (incloc, reloadreg));
7917 Because this might be a jump insn or a compare, and because RELOADREG
7918 may not be available after the insn in an input reload, we must do
7919 the incrementation before the insn being reloaded for.
7921 We have already copied IN to RELOADREG. Increment the copy in
7922 RELOADREG, save that back, then decrement RELOADREG so it has
7923 the original value. */
7925 emit_insn (gen_add2_insn (reloadreg, inc));
7926 store = emit_insn (gen_move_insn (incloc, reloadreg));
7927 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7935 add_auto_inc_notes (rtx insn, rtx x)
7937 enum rtx_code code = GET_CODE (x);
7941 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7944 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7948 /* Scan all the operand sub-expressions. */
7949 fmt = GET_RTX_FORMAT (code);
7950 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7953 add_auto_inc_notes (insn, XEXP (x, i));
7954 else if (fmt[i] == 'E')
7955 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7956 add_auto_inc_notes (insn, XVECEXP (x, i, j));
7961 /* Copy EH notes from an insn to its reloads. */
7963 copy_eh_notes (rtx insn, rtx x)
7965 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
7968 for (; x != 0; x = NEXT_INSN (x))
7970 if (may_trap_p (PATTERN (x)))
7972 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
7978 /* This is used by reload pass, that does emit some instructions after
7979 abnormal calls moving basic block end, but in fact it wants to emit
7980 them on the edge. Looks for abnormal call edges, find backward the
7981 proper call and fix the damage.
7983 Similar handle instructions throwing exceptions internally. */
7985 fixup_abnormal_edges (void)
7987 bool inserted = false;
7994 /* Look for cases we are interested in - calls or instructions causing
7996 for (e = bb->succ; e; e = e->succ_next)
7998 if (e->flags & EDGE_ABNORMAL_CALL)
8000 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8001 == (EDGE_ABNORMAL | EDGE_EH))
8004 if (e && GET_CODE (BB_END (bb)) != CALL_INSN
8005 && !can_throw_internal (BB_END (bb)))
8007 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8009 for (e = bb->succ; e; e = e->succ_next)
8010 if (e->flags & EDGE_FALLTHRU)
8012 /* Get past the new insns generated. Allow notes, as the insns may
8013 be already deleted. */
8014 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
8015 && !can_throw_internal (insn)
8016 && insn != BB_HEAD (bb))
8017 insn = PREV_INSN (insn);
8018 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
8022 insn = NEXT_INSN (insn);
8023 while (insn && insn != stop)
8025 next = NEXT_INSN (insn);
8030 /* Sometimes there's still the return value USE.
8031 If it's placed after a trapping call (i.e. that
8032 call is the last insn anyway), we have no fallthru
8033 edge. Simply delete this use and don't try to insert
8034 on the non-existent edge. */
8035 if (GET_CODE (PATTERN (insn)) != USE)
8037 /* We're not deleting it, we're moving it. */
8038 INSN_DELETED_P (insn) = 0;
8039 PREV_INSN (insn) = NULL_RTX;
8040 NEXT_INSN (insn) = NULL_RTX;
8042 insert_insn_on_edge (insn, e);
8049 /* We've possibly turned single trapping insn into multiple ones. */
8050 if (flag_non_call_exceptions)
8053 blocks = sbitmap_alloc (last_basic_block);
8054 sbitmap_ones (blocks);
8055 find_many_sub_basic_blocks (blocks);
8058 commit_edge_insertions ();
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