sys/dev/drm/amd/include/asic_reg/smu/smu_7_1_1_enum.h

   1 /*
   2  * SMU_7_1_1 Register documentation
   3  *
   4  * Copyright (C) 2014  Advanced Micro Devices, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #ifndef SMU_7_1_1_ENUM_H
  25 #define SMU_7_1_1_ENUM_H
  26
  27 #define CG_SRBM_START_ADDR                        0x600
  28 #define CG_SRBM_END_ADDR                          0x8ff
  29 #define RCU_CCF_DWORDS0                           0x80
  30 #define RCU_CCF_BITS0                             0x1000
  31 #define RCU_CCF_DWORDS1                           0x0
  32 #define RCU_CCF_BITS1                             0x0
  33 #define RCU_SAM_BYTES                             0x0
  34 #define RCU_SAM_RTL_BYTES                         0x0
  35 #define RCU_SMU_BYTES                             0x0
  36 #define RCU_SMU_RTL_BYTES                         0x0
  37 #define SFP_CHAIN_ADDR                            0x0
  38 #define SFP_BYTES                                 0x80
  39 #define SFP_SADR                                  0x180
  40 #define SFP_EADR                                  0x1ff
  41 #define SAMU_KEY_CHAIN_ADR                        0x0
  42 #define SAMU_KEY_SADR                             0x0
  43 #define SAMU_KEY_EADR                             0x0
  44 #define SMU_KEY_CHAIN_ADR                         0x0
  45 #define SMU_KEY_SADR                              0x0
  46 #define SMU_KEY_EADR                              0x0
  47 #define SMC_MSG_TEST                              0x1
  48 #define SMC_MSG_PHY_LN_OFF                        0x2
  49 #define SMC_MSG_PHY_LN_ON                         0x3
  50 #define SMC_MSG_DDI_PHY_OFF                       0x4
  51 #define SMC_MSG_DDI_PHY_ON                        0x5
  52 #define SMC_MSG_CASCADE_PLL_OFF                   0x6
  53 #define SMC_MSG_CASCADE_PLL_ON                    0x7
  54 #define SMC_MSG_PWR_OFF_x16                       0x8
  55 #define SMC_MSG_CONFIG_LCLK_DPM                   0x9
  56 #define SMC_MSG_FLUSH_DATA_CACHE                  0xa
  57 #define SMC_MSG_FLUSH_INSTRUCTION_CACHE           0xb
  58 #define SMC_MSG_CONFIG_VPC_ACCUMULATOR            0xc
  59 #define SMC_MSG_CONFIG_BAPM                       0xd
  60 #define SMC_MSG_CONFIG_TDC_LIMIT                  0xe
  61 #define SMC_MSG_CONFIG_LPMx                       0xf
  62 #define SMC_MSG_CONFIG_HTC_LIMIT                  0x10
  63 #define SMC_MSG_CONFIG_THERMAL_CNTL               0x11
  64 #define SMC_MSG_CONFIG_VOLTAGE_CNTL               0x12
  65 #define SMC_MSG_CONFIG_TDP_CNTL                   0x13
  66 #define SMC_MSG_EN_PM_CNTL                        0x14
  67 #define SMC_MSG_DIS_PM_CNTL                       0x15
  68 #define SMC_MSG_CONFIG_NBDPM                      0x16
  69 #define SMC_MSG_CONFIG_LOADLINE                   0x17
  70 #define SMC_MSG_ADJUST_LOADLINE                   0x18
  71 #define SMC_MSG_RESET                             0x20
  72 #define SMC_MSG_VOLTAGE                           0x25
  73 #define SMC_VERSION_MAJOR                         0x7
  74 #define SMC_VERSION_MINOR                         0x0
  75 #define SMC_HEADER_SIZE                           0x40
  76 #define ROM_SIGNATURE                             0xaa55
  77 typedef enum SurfaceEndian {
  78         ENDIAN_NONE                                      = 0x0,
  79         ENDIAN_8IN16                                     = 0x1,
  80         ENDIAN_8IN32                                     = 0x2,
  81         ENDIAN_8IN64                                     = 0x3,
  82 } SurfaceEndian;
  83 typedef enum ArrayMode {
  84         ARRAY_LINEAR_GENERAL                             = 0x0,
  85         ARRAY_LINEAR_ALIGNED                             = 0x1,
  86         ARRAY_1D_TILED_THIN1                             = 0x2,
  87         ARRAY_1D_TILED_THICK                             = 0x3,
  88         ARRAY_2D_TILED_THIN1                             = 0x4,
  89         ARRAY_PRT_TILED_THIN1                            = 0x5,
  90         ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
  91         ARRAY_2D_TILED_THICK                             = 0x7,
  92         ARRAY_2D_TILED_XTHICK                            = 0x8,
  93         ARRAY_PRT_TILED_THICK                            = 0x9,
  94         ARRAY_PRT_2D_TILED_THICK                         = 0xa,
  95         ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
  96         ARRAY_3D_TILED_THIN1                             = 0xc,
  97         ARRAY_3D_TILED_THICK                             = 0xd,
  98         ARRAY_3D_TILED_XTHICK                            = 0xe,
  99         ARRAY_PRT_3D_TILED_THICK                         = 0xf,
 100 } ArrayMode;
 101 typedef enum PipeTiling {
 102         CONFIG_1_PIPE                                    = 0x0,
 103         CONFIG_2_PIPE                                    = 0x1,
 104         CONFIG_4_PIPE                                    = 0x2,
 105         CONFIG_8_PIPE                                    = 0x3,
 106 } PipeTiling;
 107 typedef enum BankTiling {
 108         CONFIG_4_BANK                                    = 0x0,
 109         CONFIG_8_BANK                                    = 0x1,
 110 } BankTiling;
 111 typedef enum GroupInterleave {
 112         CONFIG_256B_GROUP                                = 0x0,
 113         CONFIG_512B_GROUP                                = 0x1,
 114 } GroupInterleave;
 115 typedef enum RowTiling {
 116         CONFIG_1KB_ROW                                   = 0x0,
 117         CONFIG_2KB_ROW                                   = 0x1,
 118         CONFIG_4KB_ROW                                   = 0x2,
 119         CONFIG_8KB_ROW                                   = 0x3,
 120         CONFIG_1KB_ROW_OPT                               = 0x4,
 121         CONFIG_2KB_ROW_OPT                               = 0x5,
 122         CONFIG_4KB_ROW_OPT                               = 0x6,
 123         CONFIG_8KB_ROW_OPT                               = 0x7,
 124 } RowTiling;
 125 typedef enum BankSwapBytes {
 126         CONFIG_128B_SWAPS                                = 0x0,
 127         CONFIG_256B_SWAPS                                = 0x1,
 128         CONFIG_512B_SWAPS                                = 0x2,
 129         CONFIG_1KB_SWAPS                                 = 0x3,
 130 } BankSwapBytes;
 131 typedef enum SampleSplitBytes {
 132         CONFIG_1KB_SPLIT                                 = 0x0,
 133         CONFIG_2KB_SPLIT                                 = 0x1,
 134         CONFIG_4KB_SPLIT                                 = 0x2,
 135         CONFIG_8KB_SPLIT                                 = 0x3,
 136 } SampleSplitBytes;
 137 typedef enum NumPipes {
 138         ADDR_CONFIG_1_PIPE                               = 0x0,
 139         ADDR_CONFIG_2_PIPE                               = 0x1,
 140         ADDR_CONFIG_4_PIPE                               = 0x2,
 141         ADDR_CONFIG_8_PIPE                               = 0x3,
 142 } NumPipes;
 143 typedef enum PipeInterleaveSize {
 144         ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
 145         ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
 146 } PipeInterleaveSize;
 147 typedef enum BankInterleaveSize {
 148         ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
 149         ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
 150         ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
 151         ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
 152 } BankInterleaveSize;
 153 typedef enum NumShaderEngines {
 154         ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
 155         ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
 156 } NumShaderEngines;
 157 typedef enum ShaderEngineTileSize {
 158         ADDR_CONFIG_SE_TILE_16                           = 0x0,
 159         ADDR_CONFIG_SE_TILE_32                           = 0x1,
 160 } ShaderEngineTileSize;
 161 typedef enum NumGPUs {
 162         ADDR_CONFIG_1_GPU                                = 0x0,
 163         ADDR_CONFIG_2_GPU                                = 0x1,
 164         ADDR_CONFIG_4_GPU                                = 0x2,
 165 } NumGPUs;
 166 typedef enum MultiGPUTileSize {
 167         ADDR_CONFIG_GPU_TILE_16                          = 0x0,
 168         ADDR_CONFIG_GPU_TILE_32                          = 0x1,
 169         ADDR_CONFIG_GPU_TILE_64                          = 0x2,
 170         ADDR_CONFIG_GPU_TILE_128                         = 0x3,
 171 } MultiGPUTileSize;
 172 typedef enum RowSize {
 173         ADDR_CONFIG_1KB_ROW                              = 0x0,
 174         ADDR_CONFIG_2KB_ROW                              = 0x1,
 175         ADDR_CONFIG_4KB_ROW                              = 0x2,
 176 } RowSize;
 177 typedef enum NumLowerPipes {
 178         ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
 179         ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
 180 } NumLowerPipes;
 181 typedef enum DebugBlockId {
 182         DBG_CLIENT_BLKID_RESERVED                        = 0x0,
 183         DBG_CLIENT_BLKID_dbg                             = 0x1,
 184         DBG_CLIENT_BLKID_uvdu_0                          = 0x2,
 185         DBG_CLIENT_BLKID_uvdu_1                          = 0x3,
 186         DBG_CLIENT_BLKID_uvdu_2                          = 0x4,
 187         DBG_CLIENT_BLKID_uvdu_3                          = 0x5,
 188         DBG_CLIENT_BLKID_uvdu_4                          = 0x6,
 189         DBG_CLIENT_BLKID_uvdu_5                          = 0x7,
 190         DBG_CLIENT_BLKID_uvdu_6                          = 0x8,
 191         DBG_CLIENT_BLKID_uvdb_0                          = 0x9,
 192         DBG_CLIENT_BLKID_uvdc_0                          = 0xa,
 193         DBG_CLIENT_BLKID_uvdc_1                          = 0xb,
 194         DBG_CLIENT_BLKID_uvdf_0                          = 0xc,
 195         DBG_CLIENT_BLKID_uvdf_1                          = 0xd,
 196         DBG_CLIENT_BLKID_uvdm_0                          = 0xe,
 197         DBG_CLIENT_BLKID_uvdm_1                          = 0xf,
 198         DBG_CLIENT_BLKID_uvdm_2                          = 0x10,
 199         DBG_CLIENT_BLKID_uvdm_3                          = 0x11,
 200         DBG_CLIENT_BLKID_vcea_0                          = 0x12,
 201         DBG_CLIENT_BLKID_vcea_1                          = 0x13,
 202         DBG_CLIENT_BLKID_vcea_2                          = 0x14,
 203         DBG_CLIENT_BLKID_vcea_3                          = 0x15,
 204         DBG_CLIENT_BLKID_vceb_0                          = 0x16,
 205         DBG_CLIENT_BLKID_vcec_0                          = 0x17,
 206         DBG_CLIENT_BLKID_dco                             = 0x18,
 207         DBG_CLIENT_BLKID_xdma                            = 0x19,
 208         DBG_CLIENT_BLKID_dci_pg                          = 0x1a,
 209         DBG_CLIENT_BLKID_smu_0                           = 0x1b,
 210         DBG_CLIENT_BLKID_smu_1                           = 0x1c,
 211         DBG_CLIENT_BLKID_smu_2                           = 0x1d,
 212         DBG_CLIENT_BLKID_gck                             = 0x1e,
 213         DBG_CLIENT_BLKID_tmonw0                          = 0x1f,
 214         DBG_CLIENT_BLKID_tmonw1                          = 0x20,
 215         DBG_CLIENT_BLKID_grbm                            = 0x21,
 216         DBG_CLIENT_BLKID_rlc                             = 0x22,
 217         DBG_CLIENT_BLKID_ds0                             = 0x23,
 218         DBG_CLIENT_BLKID_cpg_0                           = 0x24,
 219         DBG_CLIENT_BLKID_cpg_1                           = 0x25,
 220         DBG_CLIENT_BLKID_cpc_0                           = 0x26,
 221         DBG_CLIENT_BLKID_cpc_1                           = 0x27,
 222         DBG_CLIENT_BLKID_cpf_0                           = 0x28,
 223         DBG_CLIENT_BLKID_cpf_1                           = 0x29,
 224         DBG_CLIENT_BLKID_scf0                            = 0x2a,
 225         DBG_CLIENT_BLKID_scf1                            = 0x2b,
 226         DBG_CLIENT_BLKID_scf2                            = 0x2c,
 227         DBG_CLIENT_BLKID_scf3                            = 0x2d,
 228         DBG_CLIENT_BLKID_pc0                             = 0x2e,
 229         DBG_CLIENT_BLKID_pc1                             = 0x2f,
 230         DBG_CLIENT_BLKID_pc2                             = 0x30,
 231         DBG_CLIENT_BLKID_pc3                             = 0x31,
 232         DBG_CLIENT_BLKID_vgt0                            = 0x32,
 233         DBG_CLIENT_BLKID_vgt1                            = 0x33,
 234         DBG_CLIENT_BLKID_vgt2                            = 0x34,
 235         DBG_CLIENT_BLKID_vgt3                            = 0x35,
 236         DBG_CLIENT_BLKID_sx00                            = 0x36,
 237         DBG_CLIENT_BLKID_sx10                            = 0x37,
 238         DBG_CLIENT_BLKID_sx20                            = 0x38,
 239         DBG_CLIENT_BLKID_sx30                            = 0x39,
 240         DBG_CLIENT_BLKID_cb001                           = 0x3a,
 241         DBG_CLIENT_BLKID_cb200                           = 0x3b,
 242         DBG_CLIENT_BLKID_cb201                           = 0x3c,
 243         DBG_CLIENT_BLKID_cbr0                            = 0x3d,
 244         DBG_CLIENT_BLKID_cb000                           = 0x3e,
 245         DBG_CLIENT_BLKID_cb101                           = 0x3f,
 246         DBG_CLIENT_BLKID_cb300                           = 0x40,
 247         DBG_CLIENT_BLKID_cb301                           = 0x41,
 248         DBG_CLIENT_BLKID_cbr1                            = 0x42,
 249         DBG_CLIENT_BLKID_cb100                           = 0x43,
 250         DBG_CLIENT_BLKID_ia0                             = 0x44,
 251         DBG_CLIENT_BLKID_ia1                             = 0x45,
 252         DBG_CLIENT_BLKID_bci0                            = 0x46,
 253         DBG_CLIENT_BLKID_bci1                            = 0x47,
 254         DBG_CLIENT_BLKID_bci2                            = 0x48,
 255         DBG_CLIENT_BLKID_bci3                            = 0x49,
 256         DBG_CLIENT_BLKID_pa0                             = 0x4a,
 257         DBG_CLIENT_BLKID_pa1                             = 0x4b,
 258         DBG_CLIENT_BLKID_spim0                           = 0x4c,
 259         DBG_CLIENT_BLKID_spim1                           = 0x4d,
 260         DBG_CLIENT_BLKID_spim2                           = 0x4e,
 261         DBG_CLIENT_BLKID_spim3                           = 0x4f,
 262         DBG_CLIENT_BLKID_sdma                            = 0x50,
 263         DBG_CLIENT_BLKID_ih                              = 0x51,
 264         DBG_CLIENT_BLKID_sem                             = 0x52,
 265         DBG_CLIENT_BLKID_srbm                            = 0x53,
 266         DBG_CLIENT_BLKID_hdp                             = 0x54,
 267         DBG_CLIENT_BLKID_acp_0                           = 0x55,
 268         DBG_CLIENT_BLKID_acp_1                           = 0x56,
 269         DBG_CLIENT_BLKID_sam                             = 0x57,
 270         DBG_CLIENT_BLKID_mcc0                            = 0x58,
 271         DBG_CLIENT_BLKID_mcc1                            = 0x59,
 272         DBG_CLIENT_BLKID_mcc2                            = 0x5a,
 273         DBG_CLIENT_BLKID_mcc3                            = 0x5b,
 274         DBG_CLIENT_BLKID_mcd0                            = 0x5c,
 275         DBG_CLIENT_BLKID_mcd1                            = 0x5d,
 276         DBG_CLIENT_BLKID_mcd2                            = 0x5e,
 277         DBG_CLIENT_BLKID_mcd3                            = 0x5f,
 278         DBG_CLIENT_BLKID_mcb                             = 0x60,
 279         DBG_CLIENT_BLKID_vmc                             = 0x61,
 280         DBG_CLIENT_BLKID_gmcon                           = 0x62,
 281         DBG_CLIENT_BLKID_gdc_0                           = 0x63,
 282         DBG_CLIENT_BLKID_gdc_1                           = 0x64,
 283         DBG_CLIENT_BLKID_gdc_2                           = 0x65,
 284         DBG_CLIENT_BLKID_gdc_3                           = 0x66,
 285         DBG_CLIENT_BLKID_gdc_4                           = 0x67,
 286         DBG_CLIENT_BLKID_gdc_5                           = 0x68,
 287         DBG_CLIENT_BLKID_gdc_6                           = 0x69,
 288         DBG_CLIENT_BLKID_gdc_7                           = 0x6a,
 289         DBG_CLIENT_BLKID_gdc_8                           = 0x6b,
 290         DBG_CLIENT_BLKID_gdc_9                           = 0x6c,
 291         DBG_CLIENT_BLKID_gdc_10                          = 0x6d,
 292         DBG_CLIENT_BLKID_gdc_11                          = 0x6e,
 293         DBG_CLIENT_BLKID_gdc_12                          = 0x6f,
 294         DBG_CLIENT_BLKID_gdc_13                          = 0x70,
 295         DBG_CLIENT_BLKID_gdc_14                          = 0x71,
 296         DBG_CLIENT_BLKID_gdc_15                          = 0x72,
 297         DBG_CLIENT_BLKID_gdc_16                          = 0x73,
 298         DBG_CLIENT_BLKID_gdc_17                          = 0x74,
 299         DBG_CLIENT_BLKID_gdc_18                          = 0x75,
 300         DBG_CLIENT_BLKID_gdc_19                          = 0x76,
 301         DBG_CLIENT_BLKID_gdc_20                          = 0x77,
 302         DBG_CLIENT_BLKID_gdc_21                          = 0x78,
 303         DBG_CLIENT_BLKID_gdc_22                          = 0x79,
 304         DBG_CLIENT_BLKID_gdc_23                          = 0x7a,
 305         DBG_CLIENT_BLKID_gdc_24                          = 0x7b,
 306         DBG_CLIENT_BLKID_gdc_25                          = 0x7c,
 307         DBG_CLIENT_BLKID_gdc_26                          = 0x7d,
 308         DBG_CLIENT_BLKID_gdc_27                          = 0x7e,
 309         DBG_CLIENT_BLKID_gdc_28                          = 0x7f,
 310         DBG_CLIENT_BLKID_wd                              = 0x80,
 311         DBG_CLIENT_BLKID_sdma_0                          = 0x81,
 312         DBG_CLIENT_BLKID_sdma_1                          = 0x82,
 313         DBG_CLIENT_BLKID_sammsp                          = 0x83,
 314         DBG_CLIENT_BLKID_dci_0                           = 0x84,
 315         DBG_CLIENT_BLKID_dccg0_0                         = 0x85,
 316         DBG_CLIENT_BLKID_dcfe01_0                        = 0x86,
 317         DBG_CLIENT_BLKID_dcfe02_0                        = 0x87,
 318         DBG_CLIENT_BLKID_dcfe03_0                        = 0x88,
 319         DBG_CLIENT_BLKID_dccg0_1                         = 0x89,
 320 } DebugBlockId;
 321 typedef enum DebugBlockId_OLD {
 322         DBG_BLOCK_ID_RESERVED                            = 0x0,
 323         DBG_BLOCK_ID_DBG                                 = 0x1,
 324         DBG_BLOCK_ID_VMC                                 = 0x2,
 325         DBG_BLOCK_ID_PDMA                                = 0x3,
 326         DBG_BLOCK_ID_CG                                  = 0x4,
 327         DBG_BLOCK_ID_SRBM                                = 0x5,
 328         DBG_BLOCK_ID_GRBM                                = 0x6,
 329         DBG_BLOCK_ID_RLC                                 = 0x7,
 330         DBG_BLOCK_ID_CSC                                 = 0x8,
 331         DBG_BLOCK_ID_SEM                                 = 0x9,
 332         DBG_BLOCK_ID_IH                                  = 0xa,
 333         DBG_BLOCK_ID_SC                                  = 0xb,
 334         DBG_BLOCK_ID_SQ                                  = 0xc,
 335         DBG_BLOCK_ID_AVP                                 = 0xd,
 336         DBG_BLOCK_ID_GMCON                               = 0xe,
 337         DBG_BLOCK_ID_SMU                                 = 0xf,
 338         DBG_BLOCK_ID_DMA0                                = 0x10,
 339         DBG_BLOCK_ID_DMA1                                = 0x11,
 340         DBG_BLOCK_ID_SPIM                                = 0x12,
 341         DBG_BLOCK_ID_GDS                                 = 0x13,
 342         DBG_BLOCK_ID_SPIS                                = 0x14,
 343         DBG_BLOCK_ID_UNUSED0                             = 0x15,
 344         DBG_BLOCK_ID_PA0                                 = 0x16,
 345         DBG_BLOCK_ID_PA1                                 = 0x17,
 346         DBG_BLOCK_ID_CP0                                 = 0x18,
 347         DBG_BLOCK_ID_CP1                                 = 0x19,
 348         DBG_BLOCK_ID_CP2                                 = 0x1a,
 349         DBG_BLOCK_ID_UNUSED1                             = 0x1b,
 350         DBG_BLOCK_ID_UVDU                                = 0x1c,
 351         DBG_BLOCK_ID_UVDM                                = 0x1d,
 352         DBG_BLOCK_ID_VCE                                 = 0x1e,
 353         DBG_BLOCK_ID_UNUSED2                             = 0x1f,
 354         DBG_BLOCK_ID_VGT0                                = 0x20,
 355         DBG_BLOCK_ID_VGT1                                = 0x21,
 356         DBG_BLOCK_ID_IA                                  = 0x22,
 357         DBG_BLOCK_ID_UNUSED3                             = 0x23,
 358         DBG_BLOCK_ID_SCT0                                = 0x24,
 359         DBG_BLOCK_ID_SCT1                                = 0x25,
 360         DBG_BLOCK_ID_SPM0                                = 0x26,
 361         DBG_BLOCK_ID_SPM1                                = 0x27,
 362         DBG_BLOCK_ID_TCAA                                = 0x28,
 363         DBG_BLOCK_ID_TCAB                                = 0x29,
 364         DBG_BLOCK_ID_TCCA                                = 0x2a,
 365         DBG_BLOCK_ID_TCCB                                = 0x2b,
 366         DBG_BLOCK_ID_MCC0                                = 0x2c,
 367         DBG_BLOCK_ID_MCC1                                = 0x2d,
 368         DBG_BLOCK_ID_MCC2                                = 0x2e,
 369         DBG_BLOCK_ID_MCC3                                = 0x2f,
 370         DBG_BLOCK_ID_SX0                                 = 0x30,
 371         DBG_BLOCK_ID_SX1                                 = 0x31,
 372         DBG_BLOCK_ID_SX2                                 = 0x32,
 373         DBG_BLOCK_ID_SX3                                 = 0x33,
 374         DBG_BLOCK_ID_UNUSED4                             = 0x34,
 375         DBG_BLOCK_ID_UNUSED5                             = 0x35,
 376         DBG_BLOCK_ID_UNUSED6                             = 0x36,
 377         DBG_BLOCK_ID_UNUSED7                             = 0x37,
 378         DBG_BLOCK_ID_PC0                                 = 0x38,
 379         DBG_BLOCK_ID_PC1                                 = 0x39,
 380         DBG_BLOCK_ID_UNUSED8                             = 0x3a,
 381         DBG_BLOCK_ID_UNUSED9                             = 0x3b,
 382         DBG_BLOCK_ID_UNUSED10                            = 0x3c,
 383         DBG_BLOCK_ID_UNUSED11                            = 0x3d,
 384         DBG_BLOCK_ID_MCB                                 = 0x3e,
 385         DBG_BLOCK_ID_UNUSED12                            = 0x3f,
 386         DBG_BLOCK_ID_SCB0                                = 0x40,
 387         DBG_BLOCK_ID_SCB1                                = 0x41,
 388         DBG_BLOCK_ID_UNUSED13                            = 0x42,
 389         DBG_BLOCK_ID_UNUSED14                            = 0x43,
 390         DBG_BLOCK_ID_SCF0                                = 0x44,
 391         DBG_BLOCK_ID_SCF1                                = 0x45,
 392         DBG_BLOCK_ID_UNUSED15                            = 0x46,
 393         DBG_BLOCK_ID_UNUSED16                            = 0x47,
 394         DBG_BLOCK_ID_BCI0                                = 0x48,
 395         DBG_BLOCK_ID_BCI1                                = 0x49,
 396         DBG_BLOCK_ID_BCI2                                = 0x4a,
 397         DBG_BLOCK_ID_BCI3                                = 0x4b,
 398         DBG_BLOCK_ID_UNUSED17                            = 0x4c,
 399         DBG_BLOCK_ID_UNUSED18                            = 0x4d,
 400         DBG_BLOCK_ID_UNUSED19                            = 0x4e,
 401         DBG_BLOCK_ID_UNUSED20                            = 0x4f,
 402         DBG_BLOCK_ID_CB00                                = 0x50,
 403         DBG_BLOCK_ID_CB01                                = 0x51,
 404         DBG_BLOCK_ID_CB02                                = 0x52,
 405         DBG_BLOCK_ID_CB03                                = 0x53,
 406         DBG_BLOCK_ID_CB04                                = 0x54,
 407         DBG_BLOCK_ID_UNUSED21                            = 0x55,
 408         DBG_BLOCK_ID_UNUSED22                            = 0x56,
 409         DBG_BLOCK_ID_UNUSED23                            = 0x57,
 410         DBG_BLOCK_ID_CB10                                = 0x58,
 411         DBG_BLOCK_ID_CB11                                = 0x59,
 412         DBG_BLOCK_ID_CB12                                = 0x5a,
 413         DBG_BLOCK_ID_CB13                                = 0x5b,
 414         DBG_BLOCK_ID_CB14                                = 0x5c,
 415         DBG_BLOCK_ID_UNUSED24                            = 0x5d,
 416         DBG_BLOCK_ID_UNUSED25                            = 0x5e,
 417         DBG_BLOCK_ID_UNUSED26                            = 0x5f,
 418         DBG_BLOCK_ID_TCP0                                = 0x60,
 419         DBG_BLOCK_ID_TCP1                                = 0x61,
 420         DBG_BLOCK_ID_TCP2                                = 0x62,
 421         DBG_BLOCK_ID_TCP3                                = 0x63,
 422         DBG_BLOCK_ID_TCP4                                = 0x64,
 423         DBG_BLOCK_ID_TCP5                                = 0x65,
 424         DBG_BLOCK_ID_TCP6                                = 0x66,
 425         DBG_BLOCK_ID_TCP7                                = 0x67,
 426         DBG_BLOCK_ID_TCP8                                = 0x68,
 427         DBG_BLOCK_ID_TCP9                                = 0x69,
 428         DBG_BLOCK_ID_TCP10                               = 0x6a,
 429         DBG_BLOCK_ID_TCP11                               = 0x6b,
 430         DBG_BLOCK_ID_TCP12                               = 0x6c,
 431         DBG_BLOCK_ID_TCP13                               = 0x6d,
 432         DBG_BLOCK_ID_TCP14                               = 0x6e,
 433         DBG_BLOCK_ID_TCP15                               = 0x6f,
 434         DBG_BLOCK_ID_TCP16                               = 0x70,
 435         DBG_BLOCK_ID_TCP17                               = 0x71,
 436         DBG_BLOCK_ID_TCP18                               = 0x72,
 437         DBG_BLOCK_ID_TCP19                               = 0x73,
 438         DBG_BLOCK_ID_TCP20                               = 0x74,
 439         DBG_BLOCK_ID_TCP21                               = 0x75,
 440         DBG_BLOCK_ID_TCP22                               = 0x76,
 441         DBG_BLOCK_ID_TCP23                               = 0x77,
 442         DBG_BLOCK_ID_TCP_RESERVED0                       = 0x78,
 443         DBG_BLOCK_ID_TCP_RESERVED1                       = 0x79,
 444         DBG_BLOCK_ID_TCP_RESERVED2                       = 0x7a,
 445         DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7b,
 446         DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7c,
 447         DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7d,
 448         DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7e,
 449         DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7f,
 450         DBG_BLOCK_ID_DB00                                = 0x80,
 451         DBG_BLOCK_ID_DB01                                = 0x81,
 452         DBG_BLOCK_ID_DB02                                = 0x82,
 453         DBG_BLOCK_ID_DB03                                = 0x83,
 454         DBG_BLOCK_ID_DB04                                = 0x84,
 455         DBG_BLOCK_ID_UNUSED27                            = 0x85,
 456         DBG_BLOCK_ID_UNUSED28                            = 0x86,
 457         DBG_BLOCK_ID_UNUSED29                            = 0x87,
 458         DBG_BLOCK_ID_DB10                                = 0x88,
 459         DBG_BLOCK_ID_DB11                                = 0x89,
 460         DBG_BLOCK_ID_DB12                                = 0x8a,
 461         DBG_BLOCK_ID_DB13                                = 0x8b,
 462         DBG_BLOCK_ID_DB14                                = 0x8c,
 463         DBG_BLOCK_ID_UNUSED30                            = 0x8d,
 464         DBG_BLOCK_ID_UNUSED31                            = 0x8e,
 465         DBG_BLOCK_ID_UNUSED32                            = 0x8f,
 466         DBG_BLOCK_ID_TCC0                                = 0x90,
 467         DBG_BLOCK_ID_TCC1                                = 0x91,
 468         DBG_BLOCK_ID_TCC2                                = 0x92,
 469         DBG_BLOCK_ID_TCC3                                = 0x93,
 470         DBG_BLOCK_ID_TCC4                                = 0x94,
 471         DBG_BLOCK_ID_TCC5                                = 0x95,
 472         DBG_BLOCK_ID_TCC6                                = 0x96,
 473         DBG_BLOCK_ID_TCC7                                = 0x97,
 474         DBG_BLOCK_ID_SPS00                               = 0x98,
 475         DBG_BLOCK_ID_SPS01                               = 0x99,
 476         DBG_BLOCK_ID_SPS02                               = 0x9a,
 477         DBG_BLOCK_ID_SPS10                               = 0x9b,
 478         DBG_BLOCK_ID_SPS11                               = 0x9c,
 479         DBG_BLOCK_ID_SPS12                               = 0x9d,
 480         DBG_BLOCK_ID_UNUSED33                            = 0x9e,
 481         DBG_BLOCK_ID_UNUSED34                            = 0x9f,
 482         DBG_BLOCK_ID_TA00                                = 0xa0,
 483         DBG_BLOCK_ID_TA01                                = 0xa1,
 484         DBG_BLOCK_ID_TA02                                = 0xa2,
 485         DBG_BLOCK_ID_TA03                                = 0xa3,
 486         DBG_BLOCK_ID_TA04                                = 0xa4,
 487         DBG_BLOCK_ID_TA05                                = 0xa5,
 488         DBG_BLOCK_ID_TA06                                = 0xa6,
 489         DBG_BLOCK_ID_TA07                                = 0xa7,
 490         DBG_BLOCK_ID_TA08                                = 0xa8,
 491         DBG_BLOCK_ID_TA09                                = 0xa9,
 492         DBG_BLOCK_ID_TA0A                                = 0xaa,
 493         DBG_BLOCK_ID_TA0B                                = 0xab,
 494         DBG_BLOCK_ID_UNUSED35                            = 0xac,
 495         DBG_BLOCK_ID_UNUSED36                            = 0xad,
 496         DBG_BLOCK_ID_UNUSED37                            = 0xae,
 497         DBG_BLOCK_ID_UNUSED38                            = 0xaf,
 498         DBG_BLOCK_ID_TA10                                = 0xb0,
 499         DBG_BLOCK_ID_TA11                                = 0xb1,
 500         DBG_BLOCK_ID_TA12                                = 0xb2,
 501         DBG_BLOCK_ID_TA13                                = 0xb3,
 502         DBG_BLOCK_ID_TA14                                = 0xb4,
 503         DBG_BLOCK_ID_TA15                                = 0xb5,
 504         DBG_BLOCK_ID_TA16                                = 0xb6,
 505         DBG_BLOCK_ID_TA17                                = 0xb7,
 506         DBG_BLOCK_ID_TA18                                = 0xb8,
 507         DBG_BLOCK_ID_TA19                                = 0xb9,
 508         DBG_BLOCK_ID_TA1A                                = 0xba,
 509         DBG_BLOCK_ID_TA1B                                = 0xbb,
 510         DBG_BLOCK_ID_UNUSED39                            = 0xbc,
 511         DBG_BLOCK_ID_UNUSED40                            = 0xbd,
 512         DBG_BLOCK_ID_UNUSED41                            = 0xbe,
 513         DBG_BLOCK_ID_UNUSED42                            = 0xbf,
 514         DBG_BLOCK_ID_TD00                                = 0xc0,
 515         DBG_BLOCK_ID_TD01                                = 0xc1,
 516         DBG_BLOCK_ID_TD02                                = 0xc2,
 517         DBG_BLOCK_ID_TD03                                = 0xc3,
 518         DBG_BLOCK_ID_TD04                                = 0xc4,
 519         DBG_BLOCK_ID_TD05                                = 0xc5,
 520         DBG_BLOCK_ID_TD06                                = 0xc6,
 521         DBG_BLOCK_ID_TD07                                = 0xc7,
 522         DBG_BLOCK_ID_TD08                                = 0xc8,
 523         DBG_BLOCK_ID_TD09                                = 0xc9,
 524         DBG_BLOCK_ID_TD0A                                = 0xca,
 525         DBG_BLOCK_ID_TD0B                                = 0xcb,
 526         DBG_BLOCK_ID_UNUSED43                            = 0xcc,
 527         DBG_BLOCK_ID_UNUSED44                            = 0xcd,
 528         DBG_BLOCK_ID_UNUSED45                            = 0xce,
 529         DBG_BLOCK_ID_UNUSED46                            = 0xcf,
 530         DBG_BLOCK_ID_TD10                                = 0xd0,
 531         DBG_BLOCK_ID_TD11                                = 0xd1,
 532         DBG_BLOCK_ID_TD12                                = 0xd2,
 533         DBG_BLOCK_ID_TD13                                = 0xd3,
 534         DBG_BLOCK_ID_TD14                                = 0xd4,
 535         DBG_BLOCK_ID_TD15                                = 0xd5,
 536         DBG_BLOCK_ID_TD16                                = 0xd6,
 537         DBG_BLOCK_ID_TD17                                = 0xd7,
 538         DBG_BLOCK_ID_TD18                                = 0xd8,
 539         DBG_BLOCK_ID_TD19                                = 0xd9,
 540         DBG_BLOCK_ID_TD1A                                = 0xda,
 541         DBG_BLOCK_ID_TD1B                                = 0xdb,
 542         DBG_BLOCK_ID_UNUSED47                            = 0xdc,
 543         DBG_BLOCK_ID_UNUSED48                            = 0xdd,
 544         DBG_BLOCK_ID_UNUSED49                            = 0xde,
 545         DBG_BLOCK_ID_UNUSED50                            = 0xdf,
 546         DBG_BLOCK_ID_MCD0                                = 0xe0,
 547         DBG_BLOCK_ID_MCD1                                = 0xe1,
 548         DBG_BLOCK_ID_MCD2                                = 0xe2,
 549         DBG_BLOCK_ID_MCD3                                = 0xe3,
 550         DBG_BLOCK_ID_MCD4                                = 0xe4,
 551         DBG_BLOCK_ID_MCD5                                = 0xe5,
 552         DBG_BLOCK_ID_UNUSED51                            = 0xe6,
 553         DBG_BLOCK_ID_UNUSED52                            = 0xe7,
 554 } DebugBlockId_OLD;
 555 typedef enum DebugBlockId_BY2 {
 556         DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
 557         DBG_BLOCK_ID_VMC_BY2                             = 0x1,
 558         DBG_BLOCK_ID_CG_BY2                              = 0x2,
 559         DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
 560         DBG_BLOCK_ID_CSC_BY2                             = 0x4,
 561         DBG_BLOCK_ID_IH_BY2                              = 0x5,
 562         DBG_BLOCK_ID_SQ_BY2                              = 0x6,
 563         DBG_BLOCK_ID_GMCON_BY2                           = 0x7,
 564         DBG_BLOCK_ID_DMA0_BY2                            = 0x8,
 565         DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
 566         DBG_BLOCK_ID_SPIS_BY2                            = 0xa,
 567         DBG_BLOCK_ID_PA0_BY2                             = 0xb,
 568         DBG_BLOCK_ID_CP0_BY2                             = 0xc,
 569         DBG_BLOCK_ID_CP2_BY2                             = 0xd,
 570         DBG_BLOCK_ID_UVDU_BY2                            = 0xe,
 571         DBG_BLOCK_ID_VCE_BY2                             = 0xf,
 572         DBG_BLOCK_ID_VGT0_BY2                            = 0x10,
 573         DBG_BLOCK_ID_IA_BY2                              = 0x11,
 574         DBG_BLOCK_ID_SCT0_BY2                            = 0x12,
 575         DBG_BLOCK_ID_SPM0_BY2                            = 0x13,
 576         DBG_BLOCK_ID_TCAA_BY2                            = 0x14,
 577         DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
 578         DBG_BLOCK_ID_MCC0_BY2                            = 0x16,
 579         DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
 580         DBG_BLOCK_ID_SX0_BY2                             = 0x18,
 581         DBG_BLOCK_ID_SX2_BY2                             = 0x19,
 582         DBG_BLOCK_ID_UNUSED4_BY2                         = 0x1a,
 583         DBG_BLOCK_ID_UNUSED6_BY2                         = 0x1b,
 584         DBG_BLOCK_ID_PC0_BY2                             = 0x1c,
 585         DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1d,
 586         DBG_BLOCK_ID_UNUSED10_BY2                        = 0x1e,
 587         DBG_BLOCK_ID_MCB_BY2                             = 0x1f,
 588         DBG_BLOCK_ID_SCB0_BY2                            = 0x20,
 589         DBG_BLOCK_ID_UNUSED13_BY2                        = 0x21,
 590         DBG_BLOCK_ID_SCF0_BY2                            = 0x22,
 591         DBG_BLOCK_ID_UNUSED15_BY2                        = 0x23,
 592         DBG_BLOCK_ID_BCI0_BY2                            = 0x24,
 593         DBG_BLOCK_ID_BCI2_BY2                            = 0x25,
 594         DBG_BLOCK_ID_UNUSED17_BY2                        = 0x26,
 595         DBG_BLOCK_ID_UNUSED19_BY2                        = 0x27,
 596         DBG_BLOCK_ID_CB00_BY2                            = 0x28,
 597         DBG_BLOCK_ID_CB02_BY2                            = 0x29,
 598         DBG_BLOCK_ID_CB04_BY2                            = 0x2a,
 599         DBG_BLOCK_ID_UNUSED22_BY2                        = 0x2b,
 600         DBG_BLOCK_ID_CB10_BY2                            = 0x2c,
 601         DBG_BLOCK_ID_CB12_BY2                            = 0x2d,
 602         DBG_BLOCK_ID_CB14_BY2                            = 0x2e,
 603         DBG_BLOCK_ID_UNUSED25_BY2                        = 0x2f,
 604         DBG_BLOCK_ID_TCP0_BY2                            = 0x30,
 605         DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
 606         DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
 607         DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
 608         DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
 609         DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
 610         DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
 611         DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
 612         DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
 613         DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
 614         DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
 615         DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
 616         DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
 617         DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
 618         DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
 619         DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
 620         DBG_BLOCK_ID_DB00_BY2                            = 0x40,
 621         DBG_BLOCK_ID_DB02_BY2                            = 0x41,
 622         DBG_BLOCK_ID_DB04_BY2                            = 0x42,
 623         DBG_BLOCK_ID_UNUSED28_BY2                        = 0x43,
 624         DBG_BLOCK_ID_DB10_BY2                            = 0x44,
 625         DBG_BLOCK_ID_DB12_BY2                            = 0x45,
 626         DBG_BLOCK_ID_DB14_BY2                            = 0x46,
 627         DBG_BLOCK_ID_UNUSED31_BY2                        = 0x47,
 628         DBG_BLOCK_ID_TCC0_BY2                            = 0x48,
 629         DBG_BLOCK_ID_TCC2_BY2                            = 0x49,
 630         DBG_BLOCK_ID_TCC4_BY2                            = 0x4a,
 631         DBG_BLOCK_ID_TCC6_BY2                            = 0x4b,
 632         DBG_BLOCK_ID_SPS00_BY2                           = 0x4c,
 633         DBG_BLOCK_ID_SPS02_BY2                           = 0x4d,
 634         DBG_BLOCK_ID_SPS11_BY2                           = 0x4e,
 635         DBG_BLOCK_ID_UNUSED33_BY2                        = 0x4f,
 636         DBG_BLOCK_ID_TA00_BY2                            = 0x50,
 637         DBG_BLOCK_ID_TA02_BY2                            = 0x51,
 638         DBG_BLOCK_ID_TA04_BY2                            = 0x52,
 639         DBG_BLOCK_ID_TA06_BY2                            = 0x53,
 640         DBG_BLOCK_ID_TA08_BY2                            = 0x54,
 641         DBG_BLOCK_ID_TA0A_BY2                            = 0x55,
 642         DBG_BLOCK_ID_UNUSED35_BY2                        = 0x56,
 643         DBG_BLOCK_ID_UNUSED37_BY2                        = 0x57,
 644         DBG_BLOCK_ID_TA10_BY2                            = 0x58,
 645         DBG_BLOCK_ID_TA12_BY2                            = 0x59,
 646         DBG_BLOCK_ID_TA14_BY2                            = 0x5a,
 647         DBG_BLOCK_ID_TA16_BY2                            = 0x5b,
 648         DBG_BLOCK_ID_TA18_BY2                            = 0x5c,
 649         DBG_BLOCK_ID_TA1A_BY2                            = 0x5d,
 650         DBG_BLOCK_ID_UNUSED39_BY2                        = 0x5e,
 651         DBG_BLOCK_ID_UNUSED41_BY2                        = 0x5f,
 652         DBG_BLOCK_ID_TD00_BY2                            = 0x60,
 653         DBG_BLOCK_ID_TD02_BY2                            = 0x61,
 654         DBG_BLOCK_ID_TD04_BY2                            = 0x62,
 655         DBG_BLOCK_ID_TD06_BY2                            = 0x63,
 656         DBG_BLOCK_ID_TD08_BY2                            = 0x64,
 657         DBG_BLOCK_ID_TD0A_BY2                            = 0x65,
 658         DBG_BLOCK_ID_UNUSED43_BY2                        = 0x66,
 659         DBG_BLOCK_ID_UNUSED45_BY2                        = 0x67,
 660         DBG_BLOCK_ID_TD10_BY2                            = 0x68,
 661         DBG_BLOCK_ID_TD12_BY2                            = 0x69,
 662         DBG_BLOCK_ID_TD14_BY2                            = 0x6a,
 663         DBG_BLOCK_ID_TD16_BY2                            = 0x6b,
 664         DBG_BLOCK_ID_TD18_BY2                            = 0x6c,
 665         DBG_BLOCK_ID_TD1A_BY2                            = 0x6d,
 666         DBG_BLOCK_ID_UNUSED47_BY2                        = 0x6e,
 667         DBG_BLOCK_ID_UNUSED49_BY2                        = 0x6f,
 668         DBG_BLOCK_ID_MCD0_BY2                            = 0x70,
 669         DBG_BLOCK_ID_MCD2_BY2                            = 0x71,
 670         DBG_BLOCK_ID_MCD4_BY2                            = 0x72,
 671         DBG_BLOCK_ID_UNUSED51_BY2                        = 0x73,
 672 } DebugBlockId_BY2;
 673 typedef enum DebugBlockId_BY4 {
 674         DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
 675         DBG_BLOCK_ID_CG_BY4                              = 0x1,
 676         DBG_BLOCK_ID_CSC_BY4                             = 0x2,
 677         DBG_BLOCK_ID_SQ_BY4                              = 0x3,
 678         DBG_BLOCK_ID_DMA0_BY4                            = 0x4,
 679         DBG_BLOCK_ID_SPIS_BY4                            = 0x5,
 680         DBG_BLOCK_ID_CP0_BY4                             = 0x6,
 681         DBG_BLOCK_ID_UVDU_BY4                            = 0x7,
 682         DBG_BLOCK_ID_VGT0_BY4                            = 0x8,
 683         DBG_BLOCK_ID_SCT0_BY4                            = 0x9,
 684         DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
 685         DBG_BLOCK_ID_MCC0_BY4                            = 0xb,
 686         DBG_BLOCK_ID_SX0_BY4                             = 0xc,
 687         DBG_BLOCK_ID_UNUSED4_BY4                         = 0xd,
 688         DBG_BLOCK_ID_PC0_BY4                             = 0xe,
 689         DBG_BLOCK_ID_UNUSED10_BY4                        = 0xf,
 690         DBG_BLOCK_ID_SCB0_BY4                            = 0x10,
 691         DBG_BLOCK_ID_SCF0_BY4                            = 0x11,
 692         DBG_BLOCK_ID_BCI0_BY4                            = 0x12,
 693         DBG_BLOCK_ID_UNUSED17_BY4                        = 0x13,
 694         DBG_BLOCK_ID_CB00_BY4                            = 0x14,
 695         DBG_BLOCK_ID_CB04_BY4                            = 0x15,
 696         DBG_BLOCK_ID_CB10_BY4                            = 0x16,
 697         DBG_BLOCK_ID_CB14_BY4                            = 0x17,
 698         DBG_BLOCK_ID_TCP0_BY4                            = 0x18,
 699         DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
 700         DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
 701         DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
 702         DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
 703         DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
 704         DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
 705         DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
 706         DBG_BLOCK_ID_DB_BY4                              = 0x20,
 707         DBG_BLOCK_ID_DB04_BY4                            = 0x21,
 708         DBG_BLOCK_ID_DB10_BY4                            = 0x22,
 709         DBG_BLOCK_ID_DB14_BY4                            = 0x23,
 710         DBG_BLOCK_ID_TCC0_BY4                            = 0x24,
 711         DBG_BLOCK_ID_TCC4_BY4                            = 0x25,
 712         DBG_BLOCK_ID_SPS00_BY4                           = 0x26,
 713         DBG_BLOCK_ID_SPS11_BY4                           = 0x27,
 714         DBG_BLOCK_ID_TA00_BY4                            = 0x28,
 715         DBG_BLOCK_ID_TA04_BY4                            = 0x29,
 716         DBG_BLOCK_ID_TA08_BY4                            = 0x2a,
 717         DBG_BLOCK_ID_UNUSED35_BY4                        = 0x2b,
 718         DBG_BLOCK_ID_TA10_BY4                            = 0x2c,
 719         DBG_BLOCK_ID_TA14_BY4                            = 0x2d,
 720         DBG_BLOCK_ID_TA18_BY4                            = 0x2e,
 721         DBG_BLOCK_ID_UNUSED39_BY4                        = 0x2f,
 722         DBG_BLOCK_ID_TD00_BY4                            = 0x30,
 723         DBG_BLOCK_ID_TD04_BY4                            = 0x31,
 724         DBG_BLOCK_ID_TD08_BY4                            = 0x32,
 725         DBG_BLOCK_ID_UNUSED43_BY4                        = 0x33,
 726         DBG_BLOCK_ID_TD10_BY4                            = 0x34,
 727         DBG_BLOCK_ID_TD14_BY4                            = 0x35,
 728         DBG_BLOCK_ID_TD18_BY4                            = 0x36,
 729         DBG_BLOCK_ID_UNUSED47_BY4                        = 0x37,
 730         DBG_BLOCK_ID_MCD0_BY4                            = 0x38,
 731         DBG_BLOCK_ID_MCD4_BY4                            = 0x39,
 732 } DebugBlockId_BY4;
 733 typedef enum DebugBlockId_BY8 {
 734         DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
 735         DBG_BLOCK_ID_CSC_BY8                             = 0x1,
 736         DBG_BLOCK_ID_DMA0_BY8                            = 0x2,
 737         DBG_BLOCK_ID_CP0_BY8                             = 0x3,
 738         DBG_BLOCK_ID_VGT0_BY8                            = 0x4,
 739         DBG_BLOCK_ID_TCAA_BY8                            = 0x5,
 740         DBG_BLOCK_ID_SX0_BY8                             = 0x6,
 741         DBG_BLOCK_ID_PC0_BY8                             = 0x7,
 742         DBG_BLOCK_ID_SCB0_BY8                            = 0x8,
 743         DBG_BLOCK_ID_BCI0_BY8                            = 0x9,
 744         DBG_BLOCK_ID_CB00_BY8                            = 0xa,
 745         DBG_BLOCK_ID_CB10_BY8                            = 0xb,
 746         DBG_BLOCK_ID_TCP0_BY8                            = 0xc,
 747         DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
 748         DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
 749         DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
 750         DBG_BLOCK_ID_DB00_BY8                            = 0x10,
 751         DBG_BLOCK_ID_DB10_BY8                            = 0x11,
 752         DBG_BLOCK_ID_TCC0_BY8                            = 0x12,
 753         DBG_BLOCK_ID_SPS00_BY8                           = 0x13,
 754         DBG_BLOCK_ID_TA00_BY8                            = 0x14,
 755         DBG_BLOCK_ID_TA08_BY8                            = 0x15,
 756         DBG_BLOCK_ID_TA10_BY8                            = 0x16,
 757         DBG_BLOCK_ID_TA18_BY8                            = 0x17,
 758         DBG_BLOCK_ID_TD00_BY8                            = 0x18,
 759         DBG_BLOCK_ID_TD08_BY8                            = 0x19,
 760         DBG_BLOCK_ID_TD10_BY8                            = 0x1a,
 761         DBG_BLOCK_ID_TD18_BY8                            = 0x1b,
 762         DBG_BLOCK_ID_MCD0_BY8                            = 0x1c,
 763 } DebugBlockId_BY8;
 764 typedef enum DebugBlockId_BY16 {
 765         DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
 766         DBG_BLOCK_ID_DMA0_BY16                           = 0x1,
 767         DBG_BLOCK_ID_VGT0_BY16                           = 0x2,
 768         DBG_BLOCK_ID_SX0_BY16                            = 0x3,
 769         DBG_BLOCK_ID_SCB0_BY16                           = 0x4,
 770         DBG_BLOCK_ID_CB00_BY16                           = 0x5,
 771         DBG_BLOCK_ID_TCP0_BY16                           = 0x6,
 772         DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
 773         DBG_BLOCK_ID_DB00_BY16                           = 0x8,
 774         DBG_BLOCK_ID_TCC0_BY16                           = 0x9,
 775         DBG_BLOCK_ID_TA00_BY16                           = 0xa,
 776         DBG_BLOCK_ID_TA10_BY16                           = 0xb,
 777         DBG_BLOCK_ID_TD00_BY16                           = 0xc,
 778         DBG_BLOCK_ID_TD10_BY16                           = 0xd,
 779         DBG_BLOCK_ID_MCD0_BY16                           = 0xe,
 780 } DebugBlockId_BY16;
 781 typedef enum ColorTransform {
 782         DCC_CT_AUTO                                      = 0x0,
 783         DCC_CT_NONE                                      = 0x1,
 784         ABGR_TO_A_BG_G_RB                                = 0x2,
 785         BGRA_TO_BG_G_RB_A                                = 0x3,
 786 } ColorTransform;
 787 typedef enum CompareRef {
 788         REF_NEVER                                        = 0x0,
 789         REF_LESS                                         = 0x1,
 790         REF_EQUAL                                        = 0x2,
 791         REF_LEQUAL                                       = 0x3,
 792         REF_GREATER                                      = 0x4,
 793         REF_NOTEQUAL                                     = 0x5,
 794         REF_GEQUAL                                       = 0x6,
 795         REF_ALWAYS                                       = 0x7,
 796 } CompareRef;
 797 typedef enum ReadSize {
 798         READ_256_BITS                                    = 0x0,
 799         READ_512_BITS                                    = 0x1,
 800 } ReadSize;
 801 typedef enum DepthFormat {
 802         DEPTH_INVALID                                    = 0x0,
 803         DEPTH_16                                         = 0x1,
 804         DEPTH_X8_24                                      = 0x2,
 805         DEPTH_8_24                                       = 0x3,
 806         DEPTH_X8_24_FLOAT                                = 0x4,
 807         DEPTH_8_24_FLOAT                                 = 0x5,
 808         DEPTH_32_FLOAT                                   = 0x6,
 809         DEPTH_X24_8_32_FLOAT                             = 0x7,
 810 } DepthFormat;
 811 typedef enum ZFormat {
 812         Z_INVALID                                        = 0x0,
 813         Z_16                                             = 0x1,
 814         Z_24                                             = 0x2,
 815         Z_32_FLOAT                                       = 0x3,
 816 } ZFormat;
 817 typedef enum StencilFormat {
 818         STENCIL_INVALID                                  = 0x0,
 819         STENCIL_8                                        = 0x1,
 820 } StencilFormat;
 821 typedef enum CmaskMode {
 822         CMASK_CLEAR_NONE                                 = 0x0,
 823         CMASK_CLEAR_ONE                                  = 0x1,
 824         CMASK_CLEAR_ALL                                  = 0x2,
 825         CMASK_ANY_EXPANDED                               = 0x3,
 826         CMASK_ALPHA0_FRAG1                               = 0x4,
 827         CMASK_ALPHA0_FRAG2                               = 0x5,
 828         CMASK_ALPHA0_FRAG4                               = 0x6,
 829         CMASK_ALPHA0_FRAGS                               = 0x7,
 830         CMASK_ALPHA1_FRAG1                               = 0x8,
 831         CMASK_ALPHA1_FRAG2                               = 0x9,
 832         CMASK_ALPHA1_FRAG4                               = 0xa,
 833         CMASK_ALPHA1_FRAGS                               = 0xb,
 834         CMASK_ALPHAX_FRAG1                               = 0xc,
 835         CMASK_ALPHAX_FRAG2                               = 0xd,
 836         CMASK_ALPHAX_FRAG4                               = 0xe,
 837         CMASK_ALPHAX_FRAGS                               = 0xf,
 838 } CmaskMode;
 839 typedef enum QuadExportFormat {
 840         EXPORT_UNUSED                                    = 0x0,
 841         EXPORT_32_R                                      = 0x1,
 842         EXPORT_32_GR                                     = 0x2,
 843         EXPORT_32_AR                                     = 0x3,
 844         EXPORT_FP16_ABGR                                 = 0x4,
 845         EXPORT_UNSIGNED16_ABGR                           = 0x5,
 846         EXPORT_SIGNED16_ABGR                             = 0x6,
 847         EXPORT_32_ABGR                                   = 0x7,
 848 } QuadExportFormat;
 849 typedef enum QuadExportFormatOld {
 850         EXPORT_4P_32BPC_ABGR                             = 0x0,
 851         EXPORT_4P_16BPC_ABGR                             = 0x1,
 852         EXPORT_4P_32BPC_GR                               = 0x2,
 853         EXPORT_4P_32BPC_AR                               = 0x3,
 854         EXPORT_2P_32BPC_ABGR                             = 0x4,
 855         EXPORT_8P_32BPC_R                                = 0x5,
 856 } QuadExportFormatOld;
 857 typedef enum ColorFormat {
 858         COLOR_INVALID                                    = 0x0,
 859         COLOR_8                                          = 0x1,
 860         COLOR_16                                         = 0x2,
 861         COLOR_8_8                                        = 0x3,
 862         COLOR_32                                         = 0x4,
 863         COLOR_16_16                                      = 0x5,
 864         COLOR_10_11_11                                   = 0x6,
 865         COLOR_11_11_10                                   = 0x7,
 866         COLOR_10_10_10_2                                 = 0x8,
 867         COLOR_2_10_10_10                                 = 0x9,
 868         COLOR_8_8_8_8                                    = 0xa,
 869         COLOR_32_32                                      = 0xb,
 870         COLOR_16_16_16_16                                = 0xc,
 871         COLOR_RESERVED_13                                = 0xd,
 872         COLOR_32_32_32_32                                = 0xe,
 873         COLOR_RESERVED_15                                = 0xf,
 874         COLOR_5_6_5                                      = 0x10,
 875         COLOR_1_5_5_5                                    = 0x11,
 876         COLOR_5_5_5_1                                    = 0x12,
 877         COLOR_4_4_4_4                                    = 0x13,
 878         COLOR_8_24                                       = 0x14,
 879         COLOR_24_8                                       = 0x15,
 880         COLOR_X24_8_32_FLOAT                             = 0x16,
 881         COLOR_RESERVED_23                                = 0x17,
 882 } ColorFormat;
 883 typedef enum SurfaceFormat {
 884         FMT_INVALID                                      = 0x0,
 885         FMT_8                                            = 0x1,
 886         FMT_16                                           = 0x2,
 887         FMT_8_8                                          = 0x3,
 888         FMT_32                                           = 0x4,
 889         FMT_16_16                                        = 0x5,
 890         FMT_10_11_11                                     = 0x6,
 891         FMT_11_11_10                                     = 0x7,
 892         FMT_10_10_10_2                                   = 0x8,
 893         FMT_2_10_10_10                                   = 0x9,
 894         FMT_8_8_8_8                                      = 0xa,
 895         FMT_32_32                                        = 0xb,
 896         FMT_16_16_16_16                                  = 0xc,
 897         FMT_32_32_32                                     = 0xd,
 898         FMT_32_32_32_32                                  = 0xe,
 899         FMT_RESERVED_4                                   = 0xf,
 900         FMT_5_6_5                                        = 0x10,
 901         FMT_1_5_5_5                                      = 0x11,
 902         FMT_5_5_5_1                                      = 0x12,
 903         FMT_4_4_4_4                                      = 0x13,
 904         FMT_8_24                                         = 0x14,
 905         FMT_24_8                                         = 0x15,
 906         FMT_X24_8_32_FLOAT                               = 0x16,
 907         FMT_RESERVED_33                                  = 0x17,
 908         FMT_11_11_10_FLOAT                               = 0x18,
 909         FMT_16_FLOAT                                     = 0x19,
 910         FMT_32_FLOAT                                     = 0x1a,
 911         FMT_16_16_FLOAT                                  = 0x1b,
 912         FMT_8_24_FLOAT                                   = 0x1c,
 913         FMT_24_8_FLOAT                                   = 0x1d,
 914         FMT_32_32_FLOAT                                  = 0x1e,
 915         FMT_10_11_11_FLOAT                               = 0x1f,
 916         FMT_16_16_16_16_FLOAT                            = 0x20,
 917         FMT_3_3_2                                        = 0x21,
 918         FMT_6_5_5                                        = 0x22,
 919         FMT_32_32_32_32_FLOAT                            = 0x23,
 920         FMT_RESERVED_36                                  = 0x24,
 921         FMT_1                                            = 0x25,
 922         FMT_1_REVERSED                                   = 0x26,
 923         FMT_GB_GR                                        = 0x27,
 924         FMT_BG_RG                                        = 0x28,
 925         FMT_32_AS_8                                      = 0x29,
 926         FMT_32_AS_8_8                                    = 0x2a,
 927         FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
 928         FMT_8_8_8                                        = 0x2c,
 929         FMT_16_16_16                                     = 0x2d,
 930         FMT_16_16_16_FLOAT                               = 0x2e,
 931         FMT_4_4                                          = 0x2f,
 932         FMT_32_32_32_FLOAT                               = 0x30,
 933         FMT_BC1                                          = 0x31,
 934         FMT_BC2                                          = 0x32,
 935         FMT_BC3                                          = 0x33,
 936         FMT_BC4                                          = 0x34,
 937         FMT_BC5                                          = 0x35,
 938         FMT_BC6                                          = 0x36,
 939         FMT_BC7                                          = 0x37,
 940         FMT_32_AS_32_32_32_32                            = 0x38,
 941         FMT_APC3                                         = 0x39,
 942         FMT_APC4                                         = 0x3a,
 943         FMT_APC5                                         = 0x3b,
 944         FMT_APC6                                         = 0x3c,
 945         FMT_APC7                                         = 0x3d,
 946         FMT_CTX1                                         = 0x3e,
 947         FMT_RESERVED_63                                  = 0x3f,
 948 } SurfaceFormat;
 949 typedef enum BUF_DATA_FORMAT {
 950         BUF_DATA_FORMAT_INVALID                          = 0x0,
 951         BUF_DATA_FORMAT_8                                = 0x1,
 952         BUF_DATA_FORMAT_16                               = 0x2,
 953         BUF_DATA_FORMAT_8_8                              = 0x3,
 954         BUF_DATA_FORMAT_32                               = 0x4,
 955         BUF_DATA_FORMAT_16_16                            = 0x5,
 956         BUF_DATA_FORMAT_10_11_11                         = 0x6,
 957         BUF_DATA_FORMAT_11_11_10                         = 0x7,
 958         BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
 959         BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
 960         BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
 961         BUF_DATA_FORMAT_32_32                            = 0xb,
 962         BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
 963         BUF_DATA_FORMAT_32_32_32                         = 0xd,
 964         BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
 965         BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
 966 } BUF_DATA_FORMAT;
 967 typedef enum IMG_DATA_FORMAT {
 968         IMG_DATA_FORMAT_INVALID                          = 0x0,
 969         IMG_DATA_FORMAT_8                                = 0x1,
 970         IMG_DATA_FORMAT_16                               = 0x2,
 971         IMG_DATA_FORMAT_8_8                              = 0x3,
 972         IMG_DATA_FORMAT_32                               = 0x4,
 973         IMG_DATA_FORMAT_16_16                            = 0x5,
 974         IMG_DATA_FORMAT_10_11_11                         = 0x6,
 975         IMG_DATA_FORMAT_11_11_10                         = 0x7,
 976         IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
 977         IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
 978         IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
 979         IMG_DATA_FORMAT_32_32                            = 0xb,
 980         IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
 981         IMG_DATA_FORMAT_32_32_32                         = 0xd,
 982         IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
 983         IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
 984         IMG_DATA_FORMAT_5_6_5                            = 0x10,
 985         IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
 986         IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
 987         IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
 988         IMG_DATA_FORMAT_8_24                             = 0x14,
 989         IMG_DATA_FORMAT_24_8                             = 0x15,
 990         IMG_DATA_FORMAT_X24_8_32                         = 0x16,
 991         IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
 992         IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
 993         IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
 994         IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
 995         IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
 996         IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
 997         IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
 998         IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
 999         IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
1000         IMG_DATA_FORMAT_GB_GR                            = 0x20,
1001         IMG_DATA_FORMAT_BG_RG                            = 0x21,
1002         IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
1003         IMG_DATA_FORMAT_BC1                              = 0x23,
1004         IMG_DATA_FORMAT_BC2                              = 0x24,
1005         IMG_DATA_FORMAT_BC3                              = 0x25,
1006         IMG_DATA_FORMAT_BC4                              = 0x26,
1007         IMG_DATA_FORMAT_BC5                              = 0x27,
1008         IMG_DATA_FORMAT_BC6                              = 0x28,
1009         IMG_DATA_FORMAT_BC7                              = 0x29,
1010         IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
1011         IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
1012         IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
1013         IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
1014         IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
1015         IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
1016         IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
1017         IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
1018         IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
1019         IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
1020         IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
1021         IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
1022         IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
1023         IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
1024         IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
1025         IMG_DATA_FORMAT_4_4                              = 0x39,
1026         IMG_DATA_FORMAT_6_5_5                            = 0x3a,
1027         IMG_DATA_FORMAT_1                                = 0x3b,
1028         IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
1029         IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
1030         IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
1031         IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
1032 } IMG_DATA_FORMAT;
1033 typedef enum BUF_NUM_FORMAT {
1034         BUF_NUM_FORMAT_UNORM                             = 0x0,
1035         BUF_NUM_FORMAT_SNORM                             = 0x1,
1036         BUF_NUM_FORMAT_USCALED                           = 0x2,
1037         BUF_NUM_FORMAT_SSCALED                           = 0x3,
1038         BUF_NUM_FORMAT_UINT                              = 0x4,
1039         BUF_NUM_FORMAT_SINT                              = 0x5,
1040         BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
1041         BUF_NUM_FORMAT_FLOAT                             = 0x7,
1042 } BUF_NUM_FORMAT;
1043 typedef enum IMG_NUM_FORMAT {
1044         IMG_NUM_FORMAT_UNORM                             = 0x0,
1045         IMG_NUM_FORMAT_SNORM                             = 0x1,
1046         IMG_NUM_FORMAT_USCALED                           = 0x2,
1047         IMG_NUM_FORMAT_SSCALED                           = 0x3,
1048         IMG_NUM_FORMAT_UINT                              = 0x4,
1049         IMG_NUM_FORMAT_SINT                              = 0x5,
1050         IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
1051         IMG_NUM_FORMAT_FLOAT                             = 0x7,
1052         IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
1053         IMG_NUM_FORMAT_SRGB                              = 0x9,
1054         IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
1055         IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
1056         IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
1057         IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
1058         IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
1059         IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
1060 } IMG_NUM_FORMAT;
1061 typedef enum TileType {
1062         ARRAY_COLOR_TILE                                 = 0x0,
1063         ARRAY_DEPTH_TILE                                 = 0x1,
1064 } TileType;
1065 typedef enum NonDispTilingOrder {
1066         ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
1067         ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
1068 } NonDispTilingOrder;
1069 typedef enum MicroTileMode {
1070         ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
1071         ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
1072         ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
1073         ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
1074         ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
1075 } MicroTileMode;
1076 typedef enum TileSplit {
1077         ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
1078         ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
1079         ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
1080         ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
1081         ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
1082         ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
1083         ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
1084 } TileSplit;
1085 typedef enum SampleSplit {
1086         ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
1087         ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
1088         ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
1089         ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
1090 } SampleSplit;
1091 typedef enum PipeConfig {
1092         ADDR_SURF_P2                                     = 0x0,
1093         ADDR_SURF_P2_RESERVED0                           = 0x1,
1094         ADDR_SURF_P2_RESERVED1                           = 0x2,
1095         ADDR_SURF_P2_RESERVED2                           = 0x3,
1096         ADDR_SURF_P4_8x16                                = 0x4,
1097         ADDR_SURF_P4_16x16                               = 0x5,
1098         ADDR_SURF_P4_16x32                               = 0x6,
1099         ADDR_SURF_P4_32x32                               = 0x7,
1100         ADDR_SURF_P8_16x16_8x16                          = 0x8,
1101         ADDR_SURF_P8_16x32_8x16                          = 0x9,
1102         ADDR_SURF_P8_32x32_8x16                          = 0xa,
1103         ADDR_SURF_P8_16x32_16x16                         = 0xb,
1104         ADDR_SURF_P8_32x32_16x16                         = 0xc,
1105         ADDR_SURF_P8_32x32_16x32                         = 0xd,
1106         ADDR_SURF_P8_32x64_32x32                         = 0xe,
1107         ADDR_SURF_P8_RESERVED0                           = 0xf,
1108         ADDR_SURF_P16_32x32_8x16                         = 0x10,
1109         ADDR_SURF_P16_32x32_16x16                        = 0x11,
1110 } PipeConfig;
1111 typedef enum NumBanks {
1112         ADDR_SURF_2_BANK                                 = 0x0,
1113         ADDR_SURF_4_BANK                                 = 0x1,
1114         ADDR_SURF_8_BANK                                 = 0x2,
1115         ADDR_SURF_16_BANK                                = 0x3,
1116 } NumBanks;
1117 typedef enum BankWidth {
1118         ADDR_SURF_BANK_WIDTH_1                           = 0x0,
1119         ADDR_SURF_BANK_WIDTH_2                           = 0x1,
1120         ADDR_SURF_BANK_WIDTH_4                           = 0x2,
1121         ADDR_SURF_BANK_WIDTH_8                           = 0x3,
1122 } BankWidth;
1123 typedef enum BankHeight {
1124         ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
1125         ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
1126         ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
1127         ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
1128 } BankHeight;
1129 typedef enum BankWidthHeight {
1130         ADDR_SURF_BANK_WH_1                              = 0x0,
1131         ADDR_SURF_BANK_WH_2                              = 0x1,
1132         ADDR_SURF_BANK_WH_4                              = 0x2,
1133         ADDR_SURF_BANK_WH_8                              = 0x3,
1134 } BankWidthHeight;
1135 typedef enum MacroTileAspect {
1136         ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
1137         ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
1138         ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
1139         ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
1140 } MacroTileAspect;
1141 typedef enum GATCL1RequestType {
1142         GATCL1_TYPE_NORMAL                               = 0x0,
1143         GATCL1_TYPE_SHOOTDOWN                            = 0x1,
1144         GATCL1_TYPE_BYPASS                               = 0x2,
1145 } GATCL1RequestType;
1146 typedef enum TCC_CACHE_POLICIES {
1147         TCC_CACHE_POLICY_LRU                             = 0x0,
1148         TCC_CACHE_POLICY_STREAM                          = 0x1,
1149 } TCC_CACHE_POLICIES;
1150 typedef enum MTYPE {
1151         MTYPE_NC_NV                                      = 0x0,
1152         MTYPE_NC                                         = 0x1,
1153         MTYPE_CC                                         = 0x2,
1154         MTYPE_UC                                         = 0x3,
1155 } MTYPE;
1156 typedef enum PERFMON_COUNTER_MODE {
1157         PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
1158         PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
1159         PERFMON_COUNTER_MODE_MAX                         = 0x2,
1160         PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
1161         PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
1162         PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
1163         PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
1164         PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
1165         PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
1166         PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
1167         PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
1168 } PERFMON_COUNTER_MODE;
1169 typedef enum PERFMON_SPM_MODE {
1170         PERFMON_SPM_MODE_OFF                             = 0x0,
1171         PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
1172         PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
1173         PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
1174         PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
1175         PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
1176         PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
1177         PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
1178         PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
1179         PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
1180         PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
1181 } PERFMON_SPM_MODE;
1182 typedef enum SurfaceTiling {
1183         ARRAY_LINEAR                                     = 0x0,
1184         ARRAY_TILED                                      = 0x1,
1185 } SurfaceTiling;
1186 typedef enum SurfaceArray {
1187         ARRAY_1D                                         = 0x0,
1188         ARRAY_2D                                         = 0x1,
1189         ARRAY_3D                                         = 0x2,
1190         ARRAY_3D_SLICE                                   = 0x3,
1191 } SurfaceArray;
1192 typedef enum ColorArray {
1193         ARRAY_2D_ALT_COLOR                               = 0x0,
1194         ARRAY_2D_COLOR                                   = 0x1,
1195         ARRAY_3D_SLICE_COLOR                             = 0x3,
1196 } ColorArray;
1197 typedef enum DepthArray {
1198         ARRAY_2D_ALT_DEPTH                               = 0x0,
1199         ARRAY_2D_DEPTH                                   = 0x1,
1200 } DepthArray;
1201 typedef enum ENUM_NUM_SIMD_PER_CU {
1202         NUM_SIMD_PER_CU                                  = 0x4,
1203 } ENUM_NUM_SIMD_PER_CU;
1204
1205 #endif /* SMU_7_1_1_ENUM_H */