sys/dev/drm/amd/include/asic_reg/uvd/uvd_6_0_enum.h

   1 /*
   2  * UVD_6_0 Register documentation
   3  *
   4  * Copyright (C) 2014  Advanced Micro Devices, Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included
  14  * in all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #ifndef UVD_6_0_ENUM_H
  25 #define UVD_6_0_ENUM_H
  26
  27 typedef enum UVDFirmwareCommand {
  28         UVDFC_FENCE                                      = 0x0,
  29         UVDFC_TRAP                                       = 0x1,
  30         UVDFC_DECODED_ADDR                               = 0x2,
  31         UVDFC_MBLOCK_ADDR                                = 0x3,
  32         UVDFC_ITBUF_ADDR                                 = 0x4,
  33         UVDFC_DISPLAY_ADDR                               = 0x5,
  34         UVDFC_EOD                                        = 0x6,
  35         UVDFC_DISPLAY_PITCH                              = 0x7,
  36         UVDFC_DISPLAY_TILING                             = 0x8,
  37         UVDFC_BITSTREAM_ADDR                             = 0x9,
  38         UVDFC_BITSTREAM_SIZE                             = 0xa,
  39 } UVDFirmwareCommand;
  40 typedef enum DebugBlockId {
  41         DBG_BLOCK_ID_RESERVED                            = 0x0,
  42         DBG_BLOCK_ID_DBG                                 = 0x1,
  43         DBG_BLOCK_ID_VMC                                 = 0x2,
  44         DBG_BLOCK_ID_PDMA                                = 0x3,
  45         DBG_BLOCK_ID_CG                                  = 0x4,
  46         DBG_BLOCK_ID_SRBM                                = 0x5,
  47         DBG_BLOCK_ID_GRBM                                = 0x6,
  48         DBG_BLOCK_ID_RLC                                 = 0x7,
  49         DBG_BLOCK_ID_CSC                                 = 0x8,
  50         DBG_BLOCK_ID_SEM                                 = 0x9,
  51         DBG_BLOCK_ID_IH                                  = 0xa,
  52         DBG_BLOCK_ID_SC                                  = 0xb,
  53         DBG_BLOCK_ID_SQ                                  = 0xc,
  54         DBG_BLOCK_ID_UVDU                                = 0xd,
  55         DBG_BLOCK_ID_SQA                                 = 0xe,
  56         DBG_BLOCK_ID_SDMA0                               = 0xf,
  57         DBG_BLOCK_ID_SDMA1                               = 0x10,
  58         DBG_BLOCK_ID_SPIM                                = 0x11,
  59         DBG_BLOCK_ID_GDS                                 = 0x12,
  60         DBG_BLOCK_ID_VC0                                 = 0x13,
  61         DBG_BLOCK_ID_VC1                                 = 0x14,
  62         DBG_BLOCK_ID_PA0                                 = 0x15,
  63         DBG_BLOCK_ID_PA1                                 = 0x16,
  64         DBG_BLOCK_ID_CP0                                 = 0x17,
  65         DBG_BLOCK_ID_CP1                                 = 0x18,
  66         DBG_BLOCK_ID_CP2                                 = 0x19,
  67         DBG_BLOCK_ID_XBR                                 = 0x1a,
  68         DBG_BLOCK_ID_UVDM                                = 0x1b,
  69         DBG_BLOCK_ID_VGT0                                = 0x1c,
  70         DBG_BLOCK_ID_VGT1                                = 0x1d,
  71         DBG_BLOCK_ID_IA                                  = 0x1e,
  72         DBG_BLOCK_ID_SXM0                                = 0x1f,
  73         DBG_BLOCK_ID_SXM1                                = 0x20,
  74         DBG_BLOCK_ID_SCT0                                = 0x21,
  75         DBG_BLOCK_ID_SCT1                                = 0x22,
  76         DBG_BLOCK_ID_SPM0                                = 0x23,
  77         DBG_BLOCK_ID_SPM1                                = 0x24,
  78         DBG_BLOCK_ID_UNUSED0                             = 0x25,
  79         DBG_BLOCK_ID_UNUSED1                             = 0x26,
  80         DBG_BLOCK_ID_TCAA                                = 0x27,
  81         DBG_BLOCK_ID_TCAB                                = 0x28,
  82         DBG_BLOCK_ID_TCCA                                = 0x29,
  83         DBG_BLOCK_ID_TCCB                                = 0x2a,
  84         DBG_BLOCK_ID_MCC0                                = 0x2b,
  85         DBG_BLOCK_ID_MCC1                                = 0x2c,
  86         DBG_BLOCK_ID_MCC2                                = 0x2d,
  87         DBG_BLOCK_ID_MCC3                                = 0x2e,
  88         DBG_BLOCK_ID_SXS0                                = 0x2f,
  89         DBG_BLOCK_ID_SXS1                                = 0x30,
  90         DBG_BLOCK_ID_SXS2                                = 0x31,
  91         DBG_BLOCK_ID_SXS3                                = 0x32,
  92         DBG_BLOCK_ID_SXS4                                = 0x33,
  93         DBG_BLOCK_ID_SXS5                                = 0x34,
  94         DBG_BLOCK_ID_SXS6                                = 0x35,
  95         DBG_BLOCK_ID_SXS7                                = 0x36,
  96         DBG_BLOCK_ID_SXS8                                = 0x37,
  97         DBG_BLOCK_ID_SXS9                                = 0x38,
  98         DBG_BLOCK_ID_BCI0                                = 0x39,
  99         DBG_BLOCK_ID_BCI1                                = 0x3a,
 100         DBG_BLOCK_ID_BCI2                                = 0x3b,
 101         DBG_BLOCK_ID_BCI3                                = 0x3c,
 102         DBG_BLOCK_ID_MCB                                 = 0x3d,
 103         DBG_BLOCK_ID_UNUSED6                             = 0x3e,
 104         DBG_BLOCK_ID_SQA00                               = 0x3f,
 105         DBG_BLOCK_ID_SQA01                               = 0x40,
 106         DBG_BLOCK_ID_SQA02                               = 0x41,
 107         DBG_BLOCK_ID_SQA10                               = 0x42,
 108         DBG_BLOCK_ID_SQA11                               = 0x43,
 109         DBG_BLOCK_ID_SQA12                               = 0x44,
 110         DBG_BLOCK_ID_UNUSED7                             = 0x45,
 111         DBG_BLOCK_ID_UNUSED8                             = 0x46,
 112         DBG_BLOCK_ID_SQB00                               = 0x47,
 113         DBG_BLOCK_ID_SQB01                               = 0x48,
 114         DBG_BLOCK_ID_SQB10                               = 0x49,
 115         DBG_BLOCK_ID_SQB11                               = 0x4a,
 116         DBG_BLOCK_ID_SQ00                                = 0x4b,
 117         DBG_BLOCK_ID_SQ01                                = 0x4c,
 118         DBG_BLOCK_ID_SQ10                                = 0x4d,
 119         DBG_BLOCK_ID_SQ11                                = 0x4e,
 120         DBG_BLOCK_ID_CB00                                = 0x4f,
 121         DBG_BLOCK_ID_CB01                                = 0x50,
 122         DBG_BLOCK_ID_CB02                                = 0x51,
 123         DBG_BLOCK_ID_CB03                                = 0x52,
 124         DBG_BLOCK_ID_CB04                                = 0x53,
 125         DBG_BLOCK_ID_UNUSED9                             = 0x54,
 126         DBG_BLOCK_ID_UNUSED10                            = 0x55,
 127         DBG_BLOCK_ID_UNUSED11                            = 0x56,
 128         DBG_BLOCK_ID_CB10                                = 0x57,
 129         DBG_BLOCK_ID_CB11                                = 0x58,
 130         DBG_BLOCK_ID_CB12                                = 0x59,
 131         DBG_BLOCK_ID_CB13                                = 0x5a,
 132         DBG_BLOCK_ID_CB14                                = 0x5b,
 133         DBG_BLOCK_ID_UNUSED12                            = 0x5c,
 134         DBG_BLOCK_ID_UNUSED13                            = 0x5d,
 135         DBG_BLOCK_ID_UNUSED14                            = 0x5e,
 136         DBG_BLOCK_ID_TCP0                                = 0x5f,
 137         DBG_BLOCK_ID_TCP1                                = 0x60,
 138         DBG_BLOCK_ID_TCP2                                = 0x61,
 139         DBG_BLOCK_ID_TCP3                                = 0x62,
 140         DBG_BLOCK_ID_TCP4                                = 0x63,
 141         DBG_BLOCK_ID_TCP5                                = 0x64,
 142         DBG_BLOCK_ID_TCP6                                = 0x65,
 143         DBG_BLOCK_ID_TCP7                                = 0x66,
 144         DBG_BLOCK_ID_TCP8                                = 0x67,
 145         DBG_BLOCK_ID_TCP9                                = 0x68,
 146         DBG_BLOCK_ID_TCP10                               = 0x69,
 147         DBG_BLOCK_ID_TCP11                               = 0x6a,
 148         DBG_BLOCK_ID_TCP12                               = 0x6b,
 149         DBG_BLOCK_ID_TCP13                               = 0x6c,
 150         DBG_BLOCK_ID_TCP14                               = 0x6d,
 151         DBG_BLOCK_ID_TCP15                               = 0x6e,
 152         DBG_BLOCK_ID_TCP16                               = 0x6f,
 153         DBG_BLOCK_ID_TCP17                               = 0x70,
 154         DBG_BLOCK_ID_TCP18                               = 0x71,
 155         DBG_BLOCK_ID_TCP19                               = 0x72,
 156         DBG_BLOCK_ID_TCP20                               = 0x73,
 157         DBG_BLOCK_ID_TCP21                               = 0x74,
 158         DBG_BLOCK_ID_TCP22                               = 0x75,
 159         DBG_BLOCK_ID_TCP23                               = 0x76,
 160         DBG_BLOCK_ID_TCP_RESERVED0                       = 0x77,
 161         DBG_BLOCK_ID_TCP_RESERVED1                       = 0x78,
 162         DBG_BLOCK_ID_TCP_RESERVED2                       = 0x79,
 163         DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7a,
 164         DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7b,
 165         DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7c,
 166         DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7d,
 167         DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7e,
 168         DBG_BLOCK_ID_DB00                                = 0x7f,
 169         DBG_BLOCK_ID_DB01                                = 0x80,
 170         DBG_BLOCK_ID_DB02                                = 0x81,
 171         DBG_BLOCK_ID_DB03                                = 0x82,
 172         DBG_BLOCK_ID_DB04                                = 0x83,
 173         DBG_BLOCK_ID_UNUSED15                            = 0x84,
 174         DBG_BLOCK_ID_UNUSED16                            = 0x85,
 175         DBG_BLOCK_ID_UNUSED17                            = 0x86,
 176         DBG_BLOCK_ID_DB10                                = 0x87,
 177         DBG_BLOCK_ID_DB11                                = 0x88,
 178         DBG_BLOCK_ID_DB12                                = 0x89,
 179         DBG_BLOCK_ID_DB13                                = 0x8a,
 180         DBG_BLOCK_ID_DB14                                = 0x8b,
 181         DBG_BLOCK_ID_UNUSED18                            = 0x8c,
 182         DBG_BLOCK_ID_UNUSED19                            = 0x8d,
 183         DBG_BLOCK_ID_UNUSED20                            = 0x8e,
 184         DBG_BLOCK_ID_TCC0                                = 0x8f,
 185         DBG_BLOCK_ID_TCC1                                = 0x90,
 186         DBG_BLOCK_ID_TCC2                                = 0x91,
 187         DBG_BLOCK_ID_TCC3                                = 0x92,
 188         DBG_BLOCK_ID_TCC4                                = 0x93,
 189         DBG_BLOCK_ID_TCC5                                = 0x94,
 190         DBG_BLOCK_ID_TCC6                                = 0x95,
 191         DBG_BLOCK_ID_TCC7                                = 0x96,
 192         DBG_BLOCK_ID_SPS00                               = 0x97,
 193         DBG_BLOCK_ID_SPS01                               = 0x98,
 194         DBG_BLOCK_ID_SPS02                               = 0x99,
 195         DBG_BLOCK_ID_SPS10                               = 0x9a,
 196         DBG_BLOCK_ID_SPS11                               = 0x9b,
 197         DBG_BLOCK_ID_SPS12                               = 0x9c,
 198         DBG_BLOCK_ID_UNUSED21                            = 0x9d,
 199         DBG_BLOCK_ID_UNUSED22                            = 0x9e,
 200         DBG_BLOCK_ID_TA00                                = 0x9f,
 201         DBG_BLOCK_ID_TA01                                = 0xa0,
 202         DBG_BLOCK_ID_TA02                                = 0xa1,
 203         DBG_BLOCK_ID_TA03                                = 0xa2,
 204         DBG_BLOCK_ID_TA04                                = 0xa3,
 205         DBG_BLOCK_ID_TA05                                = 0xa4,
 206         DBG_BLOCK_ID_TA06                                = 0xa5,
 207         DBG_BLOCK_ID_TA07                                = 0xa6,
 208         DBG_BLOCK_ID_TA08                                = 0xa7,
 209         DBG_BLOCK_ID_TA09                                = 0xa8,
 210         DBG_BLOCK_ID_TA0A                                = 0xa9,
 211         DBG_BLOCK_ID_TA0B                                = 0xaa,
 212         DBG_BLOCK_ID_UNUSED23                            = 0xab,
 213         DBG_BLOCK_ID_UNUSED24                            = 0xac,
 214         DBG_BLOCK_ID_UNUSED25                            = 0xad,
 215         DBG_BLOCK_ID_UNUSED26                            = 0xae,
 216         DBG_BLOCK_ID_TA10                                = 0xaf,
 217         DBG_BLOCK_ID_TA11                                = 0xb0,
 218         DBG_BLOCK_ID_TA12                                = 0xb1,
 219         DBG_BLOCK_ID_TA13                                = 0xb2,
 220         DBG_BLOCK_ID_TA14                                = 0xb3,
 221         DBG_BLOCK_ID_TA15                                = 0xb4,
 222         DBG_BLOCK_ID_TA16                                = 0xb5,
 223         DBG_BLOCK_ID_TA17                                = 0xb6,
 224         DBG_BLOCK_ID_TA18                                = 0xb7,
 225         DBG_BLOCK_ID_TA19                                = 0xb8,
 226         DBG_BLOCK_ID_TA1A                                = 0xb9,
 227         DBG_BLOCK_ID_TA1B                                = 0xba,
 228         DBG_BLOCK_ID_UNUSED27                            = 0xbb,
 229         DBG_BLOCK_ID_UNUSED28                            = 0xbc,
 230         DBG_BLOCK_ID_UNUSED29                            = 0xbd,
 231         DBG_BLOCK_ID_UNUSED30                            = 0xbe,
 232         DBG_BLOCK_ID_TD00                                = 0xbf,
 233         DBG_BLOCK_ID_TD01                                = 0xc0,
 234         DBG_BLOCK_ID_TD02                                = 0xc1,
 235         DBG_BLOCK_ID_TD03                                = 0xc2,
 236         DBG_BLOCK_ID_TD04                                = 0xc3,
 237         DBG_BLOCK_ID_TD05                                = 0xc4,
 238         DBG_BLOCK_ID_TD06                                = 0xc5,
 239         DBG_BLOCK_ID_TD07                                = 0xc6,
 240         DBG_BLOCK_ID_TD08                                = 0xc7,
 241         DBG_BLOCK_ID_TD09                                = 0xc8,
 242         DBG_BLOCK_ID_TD0A                                = 0xc9,
 243         DBG_BLOCK_ID_TD0B                                = 0xca,
 244         DBG_BLOCK_ID_UNUSED31                            = 0xcb,
 245         DBG_BLOCK_ID_UNUSED32                            = 0xcc,
 246         DBG_BLOCK_ID_UNUSED33                            = 0xcd,
 247         DBG_BLOCK_ID_UNUSED34                            = 0xce,
 248         DBG_BLOCK_ID_TD10                                = 0xcf,
 249         DBG_BLOCK_ID_TD11                                = 0xd0,
 250         DBG_BLOCK_ID_TD12                                = 0xd1,
 251         DBG_BLOCK_ID_TD13                                = 0xd2,
 252         DBG_BLOCK_ID_TD14                                = 0xd3,
 253         DBG_BLOCK_ID_TD15                                = 0xd4,
 254         DBG_BLOCK_ID_TD16                                = 0xd5,
 255         DBG_BLOCK_ID_TD17                                = 0xd6,
 256         DBG_BLOCK_ID_TD18                                = 0xd7,
 257         DBG_BLOCK_ID_TD19                                = 0xd8,
 258         DBG_BLOCK_ID_TD1A                                = 0xd9,
 259         DBG_BLOCK_ID_TD1B                                = 0xda,
 260         DBG_BLOCK_ID_UNUSED35                            = 0xdb,
 261         DBG_BLOCK_ID_UNUSED36                            = 0xdc,
 262         DBG_BLOCK_ID_UNUSED37                            = 0xdd,
 263         DBG_BLOCK_ID_UNUSED38                            = 0xde,
 264         DBG_BLOCK_ID_LDS00                               = 0xdf,
 265         DBG_BLOCK_ID_LDS01                               = 0xe0,
 266         DBG_BLOCK_ID_LDS02                               = 0xe1,
 267         DBG_BLOCK_ID_LDS03                               = 0xe2,
 268         DBG_BLOCK_ID_LDS04                               = 0xe3,
 269         DBG_BLOCK_ID_LDS05                               = 0xe4,
 270         DBG_BLOCK_ID_LDS06                               = 0xe5,
 271         DBG_BLOCK_ID_LDS07                               = 0xe6,
 272         DBG_BLOCK_ID_LDS08                               = 0xe7,
 273         DBG_BLOCK_ID_LDS09                               = 0xe8,
 274         DBG_BLOCK_ID_LDS0A                               = 0xe9,
 275         DBG_BLOCK_ID_LDS0B                               = 0xea,
 276         DBG_BLOCK_ID_UNUSED39                            = 0xeb,
 277         DBG_BLOCK_ID_UNUSED40                            = 0xec,
 278         DBG_BLOCK_ID_UNUSED41                            = 0xed,
 279         DBG_BLOCK_ID_UNUSED42                            = 0xee,
 280         DBG_BLOCK_ID_LDS10                               = 0xef,
 281         DBG_BLOCK_ID_LDS11                               = 0xf0,
 282         DBG_BLOCK_ID_LDS12                               = 0xf1,
 283         DBG_BLOCK_ID_LDS13                               = 0xf2,
 284         DBG_BLOCK_ID_LDS14                               = 0xf3,
 285         DBG_BLOCK_ID_LDS15                               = 0xf4,
 286         DBG_BLOCK_ID_LDS16                               = 0xf5,
 287         DBG_BLOCK_ID_LDS17                               = 0xf6,
 288         DBG_BLOCK_ID_LDS18                               = 0xf7,
 289         DBG_BLOCK_ID_LDS19                               = 0xf8,
 290         DBG_BLOCK_ID_LDS1A                               = 0xf9,
 291         DBG_BLOCK_ID_LDS1B                               = 0xfa,
 292         DBG_BLOCK_ID_UNUSED43                            = 0xfb,
 293         DBG_BLOCK_ID_UNUSED44                            = 0xfc,
 294         DBG_BLOCK_ID_UNUSED45                            = 0xfd,
 295         DBG_BLOCK_ID_UNUSED46                            = 0xfe,
 296 } DebugBlockId;
 297 typedef enum DebugBlockId_BY2 {
 298         DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
 299         DBG_BLOCK_ID_VMC_BY2                             = 0x1,
 300         DBG_BLOCK_ID_UNUSED0_BY2                         = 0x2,
 301         DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
 302         DBG_BLOCK_ID_CSC_BY2                             = 0x4,
 303         DBG_BLOCK_ID_IH_BY2                              = 0x5,
 304         DBG_BLOCK_ID_SQ_BY2                              = 0x6,
 305         DBG_BLOCK_ID_UVD_BY2                             = 0x7,
 306         DBG_BLOCK_ID_SDMA0_BY2                           = 0x8,
 307         DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
 308         DBG_BLOCK_ID_VC0_BY2                             = 0xa,
 309         DBG_BLOCK_ID_PA_BY2                              = 0xb,
 310         DBG_BLOCK_ID_CP0_BY2                             = 0xc,
 311         DBG_BLOCK_ID_CP2_BY2                             = 0xd,
 312         DBG_BLOCK_ID_PC0_BY2                             = 0xe,
 313         DBG_BLOCK_ID_BCI0_BY2                            = 0xf,
 314         DBG_BLOCK_ID_SXM0_BY2                            = 0x10,
 315         DBG_BLOCK_ID_SCT0_BY2                            = 0x11,
 316         DBG_BLOCK_ID_SPM0_BY2                            = 0x12,
 317         DBG_BLOCK_ID_BCI2_BY2                            = 0x13,
 318         DBG_BLOCK_ID_TCA_BY2                             = 0x14,
 319         DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
 320         DBG_BLOCK_ID_MCC_BY2                             = 0x16,
 321         DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
 322         DBG_BLOCK_ID_MCD_BY2                             = 0x18,
 323         DBG_BLOCK_ID_MCD2_BY2                            = 0x19,
 324         DBG_BLOCK_ID_MCD4_BY2                            = 0x1a,
 325         DBG_BLOCK_ID_MCB_BY2                             = 0x1b,
 326         DBG_BLOCK_ID_SQA_BY2                             = 0x1c,
 327         DBG_BLOCK_ID_SQA02_BY2                           = 0x1d,
 328         DBG_BLOCK_ID_SQA11_BY2                           = 0x1e,
 329         DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1f,
 330         DBG_BLOCK_ID_SQB_BY2                             = 0x20,
 331         DBG_BLOCK_ID_SQB10_BY2                           = 0x21,
 332         DBG_BLOCK_ID_UNUSED10_BY2                        = 0x22,
 333         DBG_BLOCK_ID_UNUSED12_BY2                        = 0x23,
 334         DBG_BLOCK_ID_CB_BY2                              = 0x24,
 335         DBG_BLOCK_ID_CB02_BY2                            = 0x25,
 336         DBG_BLOCK_ID_CB10_BY2                            = 0x26,
 337         DBG_BLOCK_ID_CB12_BY2                            = 0x27,
 338         DBG_BLOCK_ID_SXS_BY2                             = 0x28,
 339         DBG_BLOCK_ID_SXS2_BY2                            = 0x29,
 340         DBG_BLOCK_ID_SXS4_BY2                            = 0x2a,
 341         DBG_BLOCK_ID_SXS6_BY2                            = 0x2b,
 342         DBG_BLOCK_ID_DB_BY2                              = 0x2c,
 343         DBG_BLOCK_ID_DB02_BY2                            = 0x2d,
 344         DBG_BLOCK_ID_DB10_BY2                            = 0x2e,
 345         DBG_BLOCK_ID_DB12_BY2                            = 0x2f,
 346         DBG_BLOCK_ID_TCP_BY2                             = 0x30,
 347         DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
 348         DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
 349         DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
 350         DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
 351         DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
 352         DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
 353         DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
 354         DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
 355         DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
 356         DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
 357         DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
 358         DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
 359         DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
 360         DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
 361         DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
 362         DBG_BLOCK_ID_TCC_BY2                             = 0x40,
 363         DBG_BLOCK_ID_TCC2_BY2                            = 0x41,
 364         DBG_BLOCK_ID_TCC4_BY2                            = 0x42,
 365         DBG_BLOCK_ID_TCC6_BY2                            = 0x43,
 366         DBG_BLOCK_ID_SPS_BY2                             = 0x44,
 367         DBG_BLOCK_ID_SPS02_BY2                           = 0x45,
 368         DBG_BLOCK_ID_SPS11_BY2                           = 0x46,
 369         DBG_BLOCK_ID_UNUSED14_BY2                        = 0x47,
 370         DBG_BLOCK_ID_TA_BY2                              = 0x48,
 371         DBG_BLOCK_ID_TA02_BY2                            = 0x49,
 372         DBG_BLOCK_ID_TA04_BY2                            = 0x4a,
 373         DBG_BLOCK_ID_TA06_BY2                            = 0x4b,
 374         DBG_BLOCK_ID_TA08_BY2                            = 0x4c,
 375         DBG_BLOCK_ID_TA0A_BY2                            = 0x4d,
 376         DBG_BLOCK_ID_UNUSED20_BY2                        = 0x4e,
 377         DBG_BLOCK_ID_UNUSED22_BY2                        = 0x4f,
 378         DBG_BLOCK_ID_TA10_BY2                            = 0x50,
 379         DBG_BLOCK_ID_TA12_BY2                            = 0x51,
 380         DBG_BLOCK_ID_TA14_BY2                            = 0x52,
 381         DBG_BLOCK_ID_TA16_BY2                            = 0x53,
 382         DBG_BLOCK_ID_TA18_BY2                            = 0x54,
 383         DBG_BLOCK_ID_TA1A_BY2                            = 0x55,
 384         DBG_BLOCK_ID_UNUSED24_BY2                        = 0x56,
 385         DBG_BLOCK_ID_UNUSED26_BY2                        = 0x57,
 386         DBG_BLOCK_ID_TD_BY2                              = 0x58,
 387         DBG_BLOCK_ID_TD02_BY2                            = 0x59,
 388         DBG_BLOCK_ID_TD04_BY2                            = 0x5a,
 389         DBG_BLOCK_ID_TD06_BY2                            = 0x5b,
 390         DBG_BLOCK_ID_TD08_BY2                            = 0x5c,
 391         DBG_BLOCK_ID_TD0A_BY2                            = 0x5d,
 392         DBG_BLOCK_ID_UNUSED28_BY2                        = 0x5e,
 393         DBG_BLOCK_ID_UNUSED30_BY2                        = 0x5f,
 394         DBG_BLOCK_ID_TD10_BY2                            = 0x60,
 395         DBG_BLOCK_ID_TD12_BY2                            = 0x61,
 396         DBG_BLOCK_ID_TD14_BY2                            = 0x62,
 397         DBG_BLOCK_ID_TD16_BY2                            = 0x63,
 398         DBG_BLOCK_ID_TD18_BY2                            = 0x64,
 399         DBG_BLOCK_ID_TD1A_BY2                            = 0x65,
 400         DBG_BLOCK_ID_UNUSED32_BY2                        = 0x66,
 401         DBG_BLOCK_ID_UNUSED34_BY2                        = 0x67,
 402         DBG_BLOCK_ID_LDS_BY2                             = 0x68,
 403         DBG_BLOCK_ID_LDS02_BY2                           = 0x69,
 404         DBG_BLOCK_ID_LDS04_BY2                           = 0x6a,
 405         DBG_BLOCK_ID_LDS06_BY2                           = 0x6b,
 406         DBG_BLOCK_ID_LDS08_BY2                           = 0x6c,
 407         DBG_BLOCK_ID_LDS0A_BY2                           = 0x6d,
 408         DBG_BLOCK_ID_UNUSED36_BY2                        = 0x6e,
 409         DBG_BLOCK_ID_UNUSED38_BY2                        = 0x6f,
 410         DBG_BLOCK_ID_LDS10_BY2                           = 0x70,
 411         DBG_BLOCK_ID_LDS12_BY2                           = 0x71,
 412         DBG_BLOCK_ID_LDS14_BY2                           = 0x72,
 413         DBG_BLOCK_ID_LDS16_BY2                           = 0x73,
 414         DBG_BLOCK_ID_LDS18_BY2                           = 0x74,
 415         DBG_BLOCK_ID_LDS1A_BY2                           = 0x75,
 416         DBG_BLOCK_ID_UNUSED40_BY2                        = 0x76,
 417         DBG_BLOCK_ID_UNUSED42_BY2                        = 0x77,
 418 } DebugBlockId_BY2;
 419 typedef enum DebugBlockId_BY4 {
 420         DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
 421         DBG_BLOCK_ID_UNUSED0_BY4                         = 0x1,
 422         DBG_BLOCK_ID_CSC_BY4                             = 0x2,
 423         DBG_BLOCK_ID_SQ_BY4                              = 0x3,
 424         DBG_BLOCK_ID_SDMA0_BY4                           = 0x4,
 425         DBG_BLOCK_ID_VC0_BY4                             = 0x5,
 426         DBG_BLOCK_ID_CP0_BY4                             = 0x6,
 427         DBG_BLOCK_ID_UNUSED1_BY4                         = 0x7,
 428         DBG_BLOCK_ID_SXM0_BY4                            = 0x8,
 429         DBG_BLOCK_ID_SPM0_BY4                            = 0x9,
 430         DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
 431         DBG_BLOCK_ID_MCC_BY4                             = 0xb,
 432         DBG_BLOCK_ID_MCD_BY4                             = 0xc,
 433         DBG_BLOCK_ID_MCD4_BY4                            = 0xd,
 434         DBG_BLOCK_ID_SQA_BY4                             = 0xe,
 435         DBG_BLOCK_ID_SQA11_BY4                           = 0xf,
 436         DBG_BLOCK_ID_SQB_BY4                             = 0x10,
 437         DBG_BLOCK_ID_UNUSED10_BY4                        = 0x11,
 438         DBG_BLOCK_ID_CB_BY4                              = 0x12,
 439         DBG_BLOCK_ID_CB10_BY4                            = 0x13,
 440         DBG_BLOCK_ID_SXS_BY4                             = 0x14,
 441         DBG_BLOCK_ID_SXS4_BY4                            = 0x15,
 442         DBG_BLOCK_ID_DB_BY4                              = 0x16,
 443         DBG_BLOCK_ID_DB10_BY4                            = 0x17,
 444         DBG_BLOCK_ID_TCP_BY4                             = 0x18,
 445         DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
 446         DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
 447         DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
 448         DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
 449         DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
 450         DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
 451         DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
 452         DBG_BLOCK_ID_TCC_BY4                             = 0x20,
 453         DBG_BLOCK_ID_TCC4_BY4                            = 0x21,
 454         DBG_BLOCK_ID_SPS_BY4                             = 0x22,
 455         DBG_BLOCK_ID_SPS11_BY4                           = 0x23,
 456         DBG_BLOCK_ID_TA_BY4                              = 0x24,
 457         DBG_BLOCK_ID_TA04_BY4                            = 0x25,
 458         DBG_BLOCK_ID_TA08_BY4                            = 0x26,
 459         DBG_BLOCK_ID_UNUSED20_BY4                        = 0x27,
 460         DBG_BLOCK_ID_TA10_BY4                            = 0x28,
 461         DBG_BLOCK_ID_TA14_BY4                            = 0x29,
 462         DBG_BLOCK_ID_TA18_BY4                            = 0x2a,
 463         DBG_BLOCK_ID_UNUSED24_BY4                        = 0x2b,
 464         DBG_BLOCK_ID_TD_BY4                              = 0x2c,
 465         DBG_BLOCK_ID_TD04_BY4                            = 0x2d,
 466         DBG_BLOCK_ID_TD08_BY4                            = 0x2e,
 467         DBG_BLOCK_ID_UNUSED28_BY4                        = 0x2f,
 468         DBG_BLOCK_ID_TD10_BY4                            = 0x30,
 469         DBG_BLOCK_ID_TD14_BY4                            = 0x31,
 470         DBG_BLOCK_ID_TD18_BY4                            = 0x32,
 471         DBG_BLOCK_ID_UNUSED32_BY4                        = 0x33,
 472         DBG_BLOCK_ID_LDS_BY4                             = 0x34,
 473         DBG_BLOCK_ID_LDS04_BY4                           = 0x35,
 474         DBG_BLOCK_ID_LDS08_BY4                           = 0x36,
 475         DBG_BLOCK_ID_UNUSED36_BY4                        = 0x37,
 476         DBG_BLOCK_ID_LDS10_BY4                           = 0x38,
 477         DBG_BLOCK_ID_LDS14_BY4                           = 0x39,
 478         DBG_BLOCK_ID_LDS18_BY4                           = 0x3a,
 479         DBG_BLOCK_ID_UNUSED40_BY4                        = 0x3b,
 480 } DebugBlockId_BY4;
 481 typedef enum DebugBlockId_BY8 {
 482         DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
 483         DBG_BLOCK_ID_CSC_BY8                             = 0x1,
 484         DBG_BLOCK_ID_SDMA0_BY8                           = 0x2,
 485         DBG_BLOCK_ID_CP0_BY8                             = 0x3,
 486         DBG_BLOCK_ID_SXM0_BY8                            = 0x4,
 487         DBG_BLOCK_ID_TCA_BY8                             = 0x5,
 488         DBG_BLOCK_ID_MCD_BY8                             = 0x6,
 489         DBG_BLOCK_ID_SQA_BY8                             = 0x7,
 490         DBG_BLOCK_ID_SQB_BY8                             = 0x8,
 491         DBG_BLOCK_ID_CB_BY8                              = 0x9,
 492         DBG_BLOCK_ID_SXS_BY8                             = 0xa,
 493         DBG_BLOCK_ID_DB_BY8                              = 0xb,
 494         DBG_BLOCK_ID_TCP_BY8                             = 0xc,
 495         DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
 496         DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
 497         DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
 498         DBG_BLOCK_ID_TCC_BY8                             = 0x10,
 499         DBG_BLOCK_ID_SPS_BY8                             = 0x11,
 500         DBG_BLOCK_ID_TA_BY8                              = 0x12,
 501         DBG_BLOCK_ID_TA08_BY8                            = 0x13,
 502         DBG_BLOCK_ID_TA10_BY8                            = 0x14,
 503         DBG_BLOCK_ID_TA18_BY8                            = 0x15,
 504         DBG_BLOCK_ID_TD_BY8                              = 0x16,
 505         DBG_BLOCK_ID_TD08_BY8                            = 0x17,
 506         DBG_BLOCK_ID_TD10_BY8                            = 0x18,
 507         DBG_BLOCK_ID_TD18_BY8                            = 0x19,
 508         DBG_BLOCK_ID_LDS_BY8                             = 0x1a,
 509         DBG_BLOCK_ID_LDS08_BY8                           = 0x1b,
 510         DBG_BLOCK_ID_LDS10_BY8                           = 0x1c,
 511         DBG_BLOCK_ID_LDS18_BY8                           = 0x1d,
 512 } DebugBlockId_BY8;
 513 typedef enum DebugBlockId_BY16 {
 514         DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
 515         DBG_BLOCK_ID_SDMA0_BY16                          = 0x1,
 516         DBG_BLOCK_ID_SXM_BY16                            = 0x2,
 517         DBG_BLOCK_ID_MCD_BY16                            = 0x3,
 518         DBG_BLOCK_ID_SQB_BY16                            = 0x4,
 519         DBG_BLOCK_ID_SXS_BY16                            = 0x5,
 520         DBG_BLOCK_ID_TCP_BY16                            = 0x6,
 521         DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
 522         DBG_BLOCK_ID_TCC_BY16                            = 0x8,
 523         DBG_BLOCK_ID_TA_BY16                             = 0x9,
 524         DBG_BLOCK_ID_TA10_BY16                           = 0xa,
 525         DBG_BLOCK_ID_TD_BY16                             = 0xb,
 526         DBG_BLOCK_ID_TD10_BY16                           = 0xc,
 527         DBG_BLOCK_ID_LDS_BY16                            = 0xd,
 528         DBG_BLOCK_ID_LDS10_BY16                          = 0xe,
 529 } DebugBlockId_BY16;
 530 typedef enum SurfaceEndian {
 531         ENDIAN_NONE                                      = 0x0,
 532         ENDIAN_8IN16                                     = 0x1,
 533         ENDIAN_8IN32                                     = 0x2,
 534         ENDIAN_8IN64                                     = 0x3,
 535 } SurfaceEndian;
 536 typedef enum ArrayMode {
 537         ARRAY_LINEAR_GENERAL                             = 0x0,
 538         ARRAY_LINEAR_ALIGNED                             = 0x1,
 539         ARRAY_1D_TILED_THIN1                             = 0x2,
 540         ARRAY_1D_TILED_THICK                             = 0x3,
 541         ARRAY_2D_TILED_THIN1                             = 0x4,
 542         ARRAY_PRT_TILED_THIN1                            = 0x5,
 543         ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
 544         ARRAY_2D_TILED_THICK                             = 0x7,
 545         ARRAY_2D_TILED_XTHICK                            = 0x8,
 546         ARRAY_PRT_TILED_THICK                            = 0x9,
 547         ARRAY_PRT_2D_TILED_THICK                         = 0xa,
 548         ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
 549         ARRAY_3D_TILED_THIN1                             = 0xc,
 550         ARRAY_3D_TILED_THICK                             = 0xd,
 551         ARRAY_3D_TILED_XTHICK                            = 0xe,
 552         ARRAY_PRT_3D_TILED_THICK                         = 0xf,
 553 } ArrayMode;
 554 typedef enum PipeTiling {
 555         CONFIG_1_PIPE                                    = 0x0,
 556         CONFIG_2_PIPE                                    = 0x1,
 557         CONFIG_4_PIPE                                    = 0x2,
 558         CONFIG_8_PIPE                                    = 0x3,
 559 } PipeTiling;
 560 typedef enum BankTiling {
 561         CONFIG_4_BANK                                    = 0x0,
 562         CONFIG_8_BANK                                    = 0x1,
 563 } BankTiling;
 564 typedef enum GroupInterleave {
 565         CONFIG_256B_GROUP                                = 0x0,
 566         CONFIG_512B_GROUP                                = 0x1,
 567 } GroupInterleave;
 568 typedef enum RowTiling {
 569         CONFIG_1KB_ROW                                   = 0x0,
 570         CONFIG_2KB_ROW                                   = 0x1,
 571         CONFIG_4KB_ROW                                   = 0x2,
 572         CONFIG_8KB_ROW                                   = 0x3,
 573         CONFIG_1KB_ROW_OPT                               = 0x4,
 574         CONFIG_2KB_ROW_OPT                               = 0x5,
 575         CONFIG_4KB_ROW_OPT                               = 0x6,
 576         CONFIG_8KB_ROW_OPT                               = 0x7,
 577 } RowTiling;
 578 typedef enum BankSwapBytes {
 579         CONFIG_128B_SWAPS                                = 0x0,
 580         CONFIG_256B_SWAPS                                = 0x1,
 581         CONFIG_512B_SWAPS                                = 0x2,
 582         CONFIG_1KB_SWAPS                                 = 0x3,
 583 } BankSwapBytes;
 584 typedef enum SampleSplitBytes {
 585         CONFIG_1KB_SPLIT                                 = 0x0,
 586         CONFIG_2KB_SPLIT                                 = 0x1,
 587         CONFIG_4KB_SPLIT                                 = 0x2,
 588         CONFIG_8KB_SPLIT                                 = 0x3,
 589 } SampleSplitBytes;
 590 typedef enum NumPipes {
 591         ADDR_CONFIG_1_PIPE                               = 0x0,
 592         ADDR_CONFIG_2_PIPE                               = 0x1,
 593         ADDR_CONFIG_4_PIPE                               = 0x2,
 594         ADDR_CONFIG_8_PIPE                               = 0x3,
 595 } NumPipes;
 596 typedef enum PipeInterleaveSize {
 597         ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
 598         ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
 599 } PipeInterleaveSize;
 600 typedef enum BankInterleaveSize {
 601         ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
 602         ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
 603         ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
 604         ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
 605 } BankInterleaveSize;
 606 typedef enum NumShaderEngines {
 607         ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
 608         ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
 609 } NumShaderEngines;
 610 typedef enum ShaderEngineTileSize {
 611         ADDR_CONFIG_SE_TILE_16                           = 0x0,
 612         ADDR_CONFIG_SE_TILE_32                           = 0x1,
 613 } ShaderEngineTileSize;
 614 typedef enum NumGPUs {
 615         ADDR_CONFIG_1_GPU                                = 0x0,
 616         ADDR_CONFIG_2_GPU                                = 0x1,
 617         ADDR_CONFIG_4_GPU                                = 0x2,
 618 } NumGPUs;
 619 typedef enum MultiGPUTileSize {
 620         ADDR_CONFIG_GPU_TILE_16                          = 0x0,
 621         ADDR_CONFIG_GPU_TILE_32                          = 0x1,
 622         ADDR_CONFIG_GPU_TILE_64                          = 0x2,
 623         ADDR_CONFIG_GPU_TILE_128                         = 0x3,
 624 } MultiGPUTileSize;
 625 typedef enum RowSize {
 626         ADDR_CONFIG_1KB_ROW                              = 0x0,
 627         ADDR_CONFIG_2KB_ROW                              = 0x1,
 628         ADDR_CONFIG_4KB_ROW                              = 0x2,
 629 } RowSize;
 630 typedef enum NumLowerPipes {
 631         ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
 632         ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
 633 } NumLowerPipes;
 634 typedef enum ColorTransform {
 635         DCC_CT_AUTO                                      = 0x0,
 636         DCC_CT_NONE                                      = 0x1,
 637         ABGR_TO_A_BG_G_RB                                = 0x2,
 638         BGRA_TO_BG_G_RB_A                                = 0x3,
 639 } ColorTransform;
 640 typedef enum CompareRef {
 641         REF_NEVER                                        = 0x0,
 642         REF_LESS                                         = 0x1,
 643         REF_EQUAL                                        = 0x2,
 644         REF_LEQUAL                                       = 0x3,
 645         REF_GREATER                                      = 0x4,
 646         REF_NOTEQUAL                                     = 0x5,
 647         REF_GEQUAL                                       = 0x6,
 648         REF_ALWAYS                                       = 0x7,
 649 } CompareRef;
 650 typedef enum ReadSize {
 651         READ_256_BITS                                    = 0x0,
 652         READ_512_BITS                                    = 0x1,
 653 } ReadSize;
 654 typedef enum DepthFormat {
 655         DEPTH_INVALID                                    = 0x0,
 656         DEPTH_16                                         = 0x1,
 657         DEPTH_X8_24                                      = 0x2,
 658         DEPTH_8_24                                       = 0x3,
 659         DEPTH_X8_24_FLOAT                                = 0x4,
 660         DEPTH_8_24_FLOAT                                 = 0x5,
 661         DEPTH_32_FLOAT                                   = 0x6,
 662         DEPTH_X24_8_32_FLOAT                             = 0x7,
 663 } DepthFormat;
 664 typedef enum ZFormat {
 665         Z_INVALID                                        = 0x0,
 666         Z_16                                             = 0x1,
 667         Z_24                                             = 0x2,
 668         Z_32_FLOAT                                       = 0x3,
 669 } ZFormat;
 670 typedef enum StencilFormat {
 671         STENCIL_INVALID                                  = 0x0,
 672         STENCIL_8                                        = 0x1,
 673 } StencilFormat;
 674 typedef enum CmaskMode {
 675         CMASK_CLEAR_NONE                                 = 0x0,
 676         CMASK_CLEAR_ONE                                  = 0x1,
 677         CMASK_CLEAR_ALL                                  = 0x2,
 678         CMASK_ANY_EXPANDED                               = 0x3,
 679         CMASK_ALPHA0_FRAG1                               = 0x4,
 680         CMASK_ALPHA0_FRAG2                               = 0x5,
 681         CMASK_ALPHA0_FRAG4                               = 0x6,
 682         CMASK_ALPHA0_FRAGS                               = 0x7,
 683         CMASK_ALPHA1_FRAG1                               = 0x8,
 684         CMASK_ALPHA1_FRAG2                               = 0x9,
 685         CMASK_ALPHA1_FRAG4                               = 0xa,
 686         CMASK_ALPHA1_FRAGS                               = 0xb,
 687         CMASK_ALPHAX_FRAG1                               = 0xc,
 688         CMASK_ALPHAX_FRAG2                               = 0xd,
 689         CMASK_ALPHAX_FRAG4                               = 0xe,
 690         CMASK_ALPHAX_FRAGS                               = 0xf,
 691 } CmaskMode;
 692 typedef enum QuadExportFormat {
 693         EXPORT_UNUSED                                    = 0x0,
 694         EXPORT_32_R                                      = 0x1,
 695         EXPORT_32_GR                                     = 0x2,
 696         EXPORT_32_AR                                     = 0x3,
 697         EXPORT_FP16_ABGR                                 = 0x4,
 698         EXPORT_UNSIGNED16_ABGR                           = 0x5,
 699         EXPORT_SIGNED16_ABGR                             = 0x6,
 700         EXPORT_32_ABGR                                   = 0x7,
 701 } QuadExportFormat;
 702 typedef enum QuadExportFormatOld {
 703         EXPORT_4P_32BPC_ABGR                             = 0x0,
 704         EXPORT_4P_16BPC_ABGR                             = 0x1,
 705         EXPORT_4P_32BPC_GR                               = 0x2,
 706         EXPORT_4P_32BPC_AR                               = 0x3,
 707         EXPORT_2P_32BPC_ABGR                             = 0x4,
 708         EXPORT_8P_32BPC_R                                = 0x5,
 709 } QuadExportFormatOld;
 710 typedef enum ColorFormat {
 711         COLOR_INVALID                                    = 0x0,
 712         COLOR_8                                          = 0x1,
 713         COLOR_16                                         = 0x2,
 714         COLOR_8_8                                        = 0x3,
 715         COLOR_32                                         = 0x4,
 716         COLOR_16_16                                      = 0x5,
 717         COLOR_10_11_11                                   = 0x6,
 718         COLOR_11_11_10                                   = 0x7,
 719         COLOR_10_10_10_2                                 = 0x8,
 720         COLOR_2_10_10_10                                 = 0x9,
 721         COLOR_8_8_8_8                                    = 0xa,
 722         COLOR_32_32                                      = 0xb,
 723         COLOR_16_16_16_16                                = 0xc,
 724         COLOR_RESERVED_13                                = 0xd,
 725         COLOR_32_32_32_32                                = 0xe,
 726         COLOR_RESERVED_15                                = 0xf,
 727         COLOR_5_6_5                                      = 0x10,
 728         COLOR_1_5_5_5                                    = 0x11,
 729         COLOR_5_5_5_1                                    = 0x12,
 730         COLOR_4_4_4_4                                    = 0x13,
 731         COLOR_8_24                                       = 0x14,
 732         COLOR_24_8                                       = 0x15,
 733         COLOR_X24_8_32_FLOAT                             = 0x16,
 734         COLOR_RESERVED_23                                = 0x17,
 735 } ColorFormat;
 736 typedef enum SurfaceFormat {
 737         FMT_INVALID                                      = 0x0,
 738         FMT_8                                            = 0x1,
 739         FMT_16                                           = 0x2,
 740         FMT_8_8                                          = 0x3,
 741         FMT_32                                           = 0x4,
 742         FMT_16_16                                        = 0x5,
 743         FMT_10_11_11                                     = 0x6,
 744         FMT_11_11_10                                     = 0x7,
 745         FMT_10_10_10_2                                   = 0x8,
 746         FMT_2_10_10_10                                   = 0x9,
 747         FMT_8_8_8_8                                      = 0xa,
 748         FMT_32_32                                        = 0xb,
 749         FMT_16_16_16_16                                  = 0xc,
 750         FMT_32_32_32                                     = 0xd,
 751         FMT_32_32_32_32                                  = 0xe,
 752         FMT_RESERVED_4                                   = 0xf,
 753         FMT_5_6_5                                        = 0x10,
 754         FMT_1_5_5_5                                      = 0x11,
 755         FMT_5_5_5_1                                      = 0x12,
 756         FMT_4_4_4_4                                      = 0x13,
 757         FMT_8_24                                         = 0x14,
 758         FMT_24_8                                         = 0x15,
 759         FMT_X24_8_32_FLOAT                               = 0x16,
 760         FMT_RESERVED_33                                  = 0x17,
 761         FMT_11_11_10_FLOAT                               = 0x18,
 762         FMT_16_FLOAT                                     = 0x19,
 763         FMT_32_FLOAT                                     = 0x1a,
 764         FMT_16_16_FLOAT                                  = 0x1b,
 765         FMT_8_24_FLOAT                                   = 0x1c,
 766         FMT_24_8_FLOAT                                   = 0x1d,
 767         FMT_32_32_FLOAT                                  = 0x1e,
 768         FMT_10_11_11_FLOAT                               = 0x1f,
 769         FMT_16_16_16_16_FLOAT                            = 0x20,
 770         FMT_3_3_2                                        = 0x21,
 771         FMT_6_5_5                                        = 0x22,
 772         FMT_32_32_32_32_FLOAT                            = 0x23,
 773         FMT_RESERVED_36                                  = 0x24,
 774         FMT_1                                            = 0x25,
 775         FMT_1_REVERSED                                   = 0x26,
 776         FMT_GB_GR                                        = 0x27,
 777         FMT_BG_RG                                        = 0x28,
 778         FMT_32_AS_8                                      = 0x29,
 779         FMT_32_AS_8_8                                    = 0x2a,
 780         FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
 781         FMT_8_8_8                                        = 0x2c,
 782         FMT_16_16_16                                     = 0x2d,
 783         FMT_16_16_16_FLOAT                               = 0x2e,
 784         FMT_4_4                                          = 0x2f,
 785         FMT_32_32_32_FLOAT                               = 0x30,
 786         FMT_BC1                                          = 0x31,
 787         FMT_BC2                                          = 0x32,
 788         FMT_BC3                                          = 0x33,
 789         FMT_BC4                                          = 0x34,
 790         FMT_BC5                                          = 0x35,
 791         FMT_BC6                                          = 0x36,
 792         FMT_BC7                                          = 0x37,
 793         FMT_32_AS_32_32_32_32                            = 0x38,
 794         FMT_APC3                                         = 0x39,
 795         FMT_APC4                                         = 0x3a,
 796         FMT_APC5                                         = 0x3b,
 797         FMT_APC6                                         = 0x3c,
 798         FMT_APC7                                         = 0x3d,
 799         FMT_CTX1                                         = 0x3e,
 800         FMT_RESERVED_63                                  = 0x3f,
 801 } SurfaceFormat;
 802 typedef enum BUF_DATA_FORMAT {
 803         BUF_DATA_FORMAT_INVALID                          = 0x0,
 804         BUF_DATA_FORMAT_8                                = 0x1,
 805         BUF_DATA_FORMAT_16                               = 0x2,
 806         BUF_DATA_FORMAT_8_8                              = 0x3,
 807         BUF_DATA_FORMAT_32                               = 0x4,
 808         BUF_DATA_FORMAT_16_16                            = 0x5,
 809         BUF_DATA_FORMAT_10_11_11                         = 0x6,
 810         BUF_DATA_FORMAT_11_11_10                         = 0x7,
 811         BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
 812         BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
 813         BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
 814         BUF_DATA_FORMAT_32_32                            = 0xb,
 815         BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
 816         BUF_DATA_FORMAT_32_32_32                         = 0xd,
 817         BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
 818         BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
 819 } BUF_DATA_FORMAT;
 820 typedef enum IMG_DATA_FORMAT {
 821         IMG_DATA_FORMAT_INVALID                          = 0x0,
 822         IMG_DATA_FORMAT_8                                = 0x1,
 823         IMG_DATA_FORMAT_16                               = 0x2,
 824         IMG_DATA_FORMAT_8_8                              = 0x3,
 825         IMG_DATA_FORMAT_32                               = 0x4,
 826         IMG_DATA_FORMAT_16_16                            = 0x5,
 827         IMG_DATA_FORMAT_10_11_11                         = 0x6,
 828         IMG_DATA_FORMAT_11_11_10                         = 0x7,
 829         IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
 830         IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
 831         IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
 832         IMG_DATA_FORMAT_32_32                            = 0xb,
 833         IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
 834         IMG_DATA_FORMAT_32_32_32                         = 0xd,
 835         IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
 836         IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
 837         IMG_DATA_FORMAT_5_6_5                            = 0x10,
 838         IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
 839         IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
 840         IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
 841         IMG_DATA_FORMAT_8_24                             = 0x14,
 842         IMG_DATA_FORMAT_24_8                             = 0x15,
 843         IMG_DATA_FORMAT_X24_8_32                         = 0x16,
 844         IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
 845         IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
 846         IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
 847         IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
 848         IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
 849         IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
 850         IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
 851         IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
 852         IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
 853         IMG_DATA_FORMAT_GB_GR                            = 0x20,
 854         IMG_DATA_FORMAT_BG_RG                            = 0x21,
 855         IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
 856         IMG_DATA_FORMAT_BC1                              = 0x23,
 857         IMG_DATA_FORMAT_BC2                              = 0x24,
 858         IMG_DATA_FORMAT_BC3                              = 0x25,
 859         IMG_DATA_FORMAT_BC4                              = 0x26,
 860         IMG_DATA_FORMAT_BC5                              = 0x27,
 861         IMG_DATA_FORMAT_BC6                              = 0x28,
 862         IMG_DATA_FORMAT_BC7                              = 0x29,
 863         IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
 864         IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
 865         IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
 866         IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
 867         IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
 868         IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
 869         IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
 870         IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
 871         IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
 872         IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
 873         IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
 874         IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
 875         IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
 876         IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
 877         IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
 878         IMG_DATA_FORMAT_4_4                              = 0x39,
 879         IMG_DATA_FORMAT_6_5_5                            = 0x3a,
 880         IMG_DATA_FORMAT_1                                = 0x3b,
 881         IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
 882         IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
 883         IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
 884         IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
 885 } IMG_DATA_FORMAT;
 886 typedef enum BUF_NUM_FORMAT {
 887         BUF_NUM_FORMAT_UNORM                             = 0x0,
 888         BUF_NUM_FORMAT_SNORM                             = 0x1,
 889         BUF_NUM_FORMAT_USCALED                           = 0x2,
 890         BUF_NUM_FORMAT_SSCALED                           = 0x3,
 891         BUF_NUM_FORMAT_UINT                              = 0x4,
 892         BUF_NUM_FORMAT_SINT                              = 0x5,
 893         BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
 894         BUF_NUM_FORMAT_FLOAT                             = 0x7,
 895 } BUF_NUM_FORMAT;
 896 typedef enum IMG_NUM_FORMAT {
 897         IMG_NUM_FORMAT_UNORM                             = 0x0,
 898         IMG_NUM_FORMAT_SNORM                             = 0x1,
 899         IMG_NUM_FORMAT_USCALED                           = 0x2,
 900         IMG_NUM_FORMAT_SSCALED                           = 0x3,
 901         IMG_NUM_FORMAT_UINT                              = 0x4,
 902         IMG_NUM_FORMAT_SINT                              = 0x5,
 903         IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
 904         IMG_NUM_FORMAT_FLOAT                             = 0x7,
 905         IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
 906         IMG_NUM_FORMAT_SRGB                              = 0x9,
 907         IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
 908         IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
 909         IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
 910         IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
 911         IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
 912         IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
 913 } IMG_NUM_FORMAT;
 914 typedef enum TileType {
 915         ARRAY_COLOR_TILE                                 = 0x0,
 916         ARRAY_DEPTH_TILE                                 = 0x1,
 917 } TileType;
 918 typedef enum NonDispTilingOrder {
 919         ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
 920         ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
 921 } NonDispTilingOrder;
 922 typedef enum MicroTileMode {
 923         ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
 924         ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
 925         ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
 926         ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
 927         ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
 928 } MicroTileMode;
 929 typedef enum TileSplit {
 930         ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
 931         ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
 932         ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
 933         ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
 934         ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
 935         ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
 936         ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
 937 } TileSplit;
 938 typedef enum SampleSplit {
 939         ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
 940         ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
 941         ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
 942         ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
 943 } SampleSplit;
 944 typedef enum PipeConfig {
 945         ADDR_SURF_P2                                     = 0x0,
 946         ADDR_SURF_P2_RESERVED0                           = 0x1,
 947         ADDR_SURF_P2_RESERVED1                           = 0x2,
 948         ADDR_SURF_P2_RESERVED2                           = 0x3,
 949         ADDR_SURF_P4_8x16                                = 0x4,
 950         ADDR_SURF_P4_16x16                               = 0x5,
 951         ADDR_SURF_P4_16x32                               = 0x6,
 952         ADDR_SURF_P4_32x32                               = 0x7,
 953         ADDR_SURF_P8_16x16_8x16                          = 0x8,
 954         ADDR_SURF_P8_16x32_8x16                          = 0x9,
 955         ADDR_SURF_P8_32x32_8x16                          = 0xa,
 956         ADDR_SURF_P8_16x32_16x16                         = 0xb,
 957         ADDR_SURF_P8_32x32_16x16                         = 0xc,
 958         ADDR_SURF_P8_32x32_16x32                         = 0xd,
 959         ADDR_SURF_P8_32x64_32x32                         = 0xe,
 960         ADDR_SURF_P8_RESERVED0                           = 0xf,
 961         ADDR_SURF_P16_32x32_8x16                         = 0x10,
 962         ADDR_SURF_P16_32x32_16x16                        = 0x11,
 963 } PipeConfig;
 964 typedef enum NumBanks {
 965         ADDR_SURF_2_BANK                                 = 0x0,
 966         ADDR_SURF_4_BANK                                 = 0x1,
 967         ADDR_SURF_8_BANK                                 = 0x2,
 968         ADDR_SURF_16_BANK                                = 0x3,
 969 } NumBanks;
 970 typedef enum BankWidth {
 971         ADDR_SURF_BANK_WIDTH_1                           = 0x0,
 972         ADDR_SURF_BANK_WIDTH_2                           = 0x1,
 973         ADDR_SURF_BANK_WIDTH_4                           = 0x2,
 974         ADDR_SURF_BANK_WIDTH_8                           = 0x3,
 975 } BankWidth;
 976 typedef enum BankHeight {
 977         ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
 978         ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
 979         ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
 980         ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
 981 } BankHeight;
 982 typedef enum BankWidthHeight {
 983         ADDR_SURF_BANK_WH_1                              = 0x0,
 984         ADDR_SURF_BANK_WH_2                              = 0x1,
 985         ADDR_SURF_BANK_WH_4                              = 0x2,
 986         ADDR_SURF_BANK_WH_8                              = 0x3,
 987 } BankWidthHeight;
 988 typedef enum MacroTileAspect {
 989         ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
 990         ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
 991         ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
 992         ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
 993 } MacroTileAspect;
 994 typedef enum GATCL1RequestType {
 995         GATCL1_TYPE_NORMAL                               = 0x0,
 996         GATCL1_TYPE_SHOOTDOWN                            = 0x1,
 997         GATCL1_TYPE_BYPASS                               = 0x2,
 998 } GATCL1RequestType;
 999 typedef enum TCC_CACHE_POLICIES {
1000         TCC_CACHE_POLICY_LRU                             = 0x0,
1001         TCC_CACHE_POLICY_STREAM                          = 0x1,
1002 } TCC_CACHE_POLICIES;
1003 typedef enum MTYPE {
1004         MTYPE_NC_NV                                      = 0x0,
1005         MTYPE_NC                                         = 0x1,
1006         MTYPE_CC                                         = 0x2,
1007         MTYPE_UC                                         = 0x3,
1008 } MTYPE;
1009 typedef enum PERFMON_COUNTER_MODE {
1010         PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
1011         PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
1012         PERFMON_COUNTER_MODE_MAX                         = 0x2,
1013         PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
1014         PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
1015         PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
1016         PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
1017         PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
1018         PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
1019         PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
1020         PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
1021 } PERFMON_COUNTER_MODE;
1022 typedef enum PERFMON_SPM_MODE {
1023         PERFMON_SPM_MODE_OFF                             = 0x0,
1024         PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
1025         PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
1026         PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
1027         PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
1028         PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
1029         PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
1030         PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
1031         PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
1032         PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
1033         PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
1034 } PERFMON_SPM_MODE;
1035 typedef enum SurfaceTiling {
1036         ARRAY_LINEAR                                     = 0x0,
1037         ARRAY_TILED                                      = 0x1,
1038 } SurfaceTiling;
1039 typedef enum SurfaceArray {
1040         ARRAY_1D                                         = 0x0,
1041         ARRAY_2D                                         = 0x1,
1042         ARRAY_3D                                         = 0x2,
1043         ARRAY_3D_SLICE                                   = 0x3,
1044 } SurfaceArray;
1045 typedef enum ColorArray {
1046         ARRAY_2D_ALT_COLOR                               = 0x0,
1047         ARRAY_2D_COLOR                                   = 0x1,
1048         ARRAY_3D_SLICE_COLOR                             = 0x3,
1049 } ColorArray;
1050 typedef enum DepthArray {
1051         ARRAY_2D_ALT_DEPTH                               = 0x0,
1052         ARRAY_2D_DEPTH                                   = 0x1,
1053 } DepthArray;
1054 typedef enum ENUM_NUM_SIMD_PER_CU {
1055         NUM_SIMD_PER_CU                                  = 0x4,
1056 } ENUM_NUM_SIMD_PER_CU;
1057 typedef enum MEM_PWR_FORCE_CTRL {
1058         NO_FORCE_REQUEST                                 = 0x0,
1059         FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
1060         FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
1061         FORCE_SHUT_DOWN_REQUEST                          = 0x3,
1062 } MEM_PWR_FORCE_CTRL;
1063 typedef enum MEM_PWR_FORCE_CTRL2 {
1064         NO_FORCE_REQ                                     = 0x0,
1065         FORCE_LIGHT_SLEEP_REQ                            = 0x1,
1066 } MEM_PWR_FORCE_CTRL2;
1067 typedef enum MEM_PWR_DIS_CTRL {
1068         ENABLE_MEM_PWR_CTRL                              = 0x0,
1069         DISABLE_MEM_PWR_CTRL                             = 0x1,
1070 } MEM_PWR_DIS_CTRL;
1071 typedef enum MEM_PWR_SEL_CTRL {
1072         DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
1073         DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
1074         DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
1075 } MEM_PWR_SEL_CTRL;
1076 typedef enum MEM_PWR_SEL_CTRL2 {
1077         DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
1078         DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
1079 } MEM_PWR_SEL_CTRL2;
1080
1081 #endif /* UVD_6_0_ENUM_H */