sys/dev/drm/amd/include/atombios.h

   1 /*
   2  * Copyright 2006-2007 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23
  24 /****************************************************************************/
  25 /*Portion I: Definitions  shared between VBIOS and Driver                   */
  26 /****************************************************************************/
  27
  28 #ifndef _ATOMBIOS_H
  29 #define _ATOMBIOS_H
  30
  31 #define ATOM_VERSION_MAJOR                   0x00020000
  32 #define ATOM_VERSION_MINOR                   0x00000002
  33
  34 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
  35
  36 /* Endianness should be specified before inclusion,
  37  * default to little endian
  38  */
  39 #ifndef ATOM_BIG_ENDIAN
  40 #error Endian not specified
  41 #endif
  42
  43 #ifdef _H2INC
  44   #ifndef ULONG
  45     typedef unsigned long ULONG;
  46   #endif
  47
  48   #ifndef UCHAR
  49     typedef unsigned char UCHAR;
  50   #endif
  51
  52   #ifndef USHORT
  53     typedef unsigned short USHORT;
  54   #endif
  55 #endif
  56
  57 #define ATOM_DAC_A            0
  58 #define ATOM_DAC_B            1
  59 #define ATOM_EXT_DAC          2
  60
  61 #define ATOM_CRTC1            0
  62 #define ATOM_CRTC2            1
  63 #define ATOM_CRTC3            2
  64 #define ATOM_CRTC4            3
  65 #define ATOM_CRTC5            4
  66 #define ATOM_CRTC6            5
  67
  68 #define ATOM_UNDERLAY_PIPE0   16
  69 #define ATOM_UNDERLAY_PIPE1   17
  70
  71 #define ATOM_CRTC_INVALID     0xFF
  72
  73 #define ATOM_DIGA             0
  74 #define ATOM_DIGB             1
  75
  76 #define ATOM_PPLL1            0
  77 #define ATOM_PPLL2            1
  78 #define ATOM_DCPLL            2
  79 #define ATOM_PPLL0            2
  80 #define ATOM_PPLL3            3
  81
  82 #define ATOM_EXT_PLL1         8
  83 #define ATOM_EXT_PLL2         9
  84 #define ATOM_EXT_CLOCK        10
  85 #define ATOM_PPLL_INVALID     0xFF
  86
  87 #define ENCODER_REFCLK_SRC_P1PLL       0
  88 #define ENCODER_REFCLK_SRC_P2PLL       1
  89 #define ENCODER_REFCLK_SRC_DCPLL       2
  90 #define ENCODER_REFCLK_SRC_EXTCLK      3
  91 #define ENCODER_REFCLK_SRC_INVALID     0xFF
  92
  93 #define ATOM_SCALER_DISABLE   0   //For Fudo, it's bypass and auto-cengter & no replication
  94 #define ATOM_SCALER_CENTER    1   //For Fudo, it's bypass and auto-center & auto replication
  95 #define ATOM_SCALER_EXPANSION 2   //For Fudo, it's 2 Tap alpha blending mode
  96 #define ATOM_SCALER_MULTI_EX  3   //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios
  97
  98 #define ATOM_DISABLE          0
  99 #define ATOM_ENABLE           1
 100 #define ATOM_LCD_BLOFF                          (ATOM_DISABLE+2)
 101 #define ATOM_LCD_BLON                           (ATOM_ENABLE+2)
 102 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL          (ATOM_ENABLE+3)
 103 #define ATOM_LCD_SELFTEST_START                 (ATOM_DISABLE+5)
 104 #define ATOM_LCD_SELFTEST_STOP                  (ATOM_ENABLE+5)
 105 #define ATOM_ENCODER_INIT                       (ATOM_DISABLE+7)
 106 #define ATOM_INIT                               (ATOM_DISABLE+7)
 107 #define ATOM_GET_STATUS                         (ATOM_DISABLE+8)
 108
 109 #define ATOM_BLANKING         1
 110 #define ATOM_BLANKING_OFF     0
 111
 112
 113 #define ATOM_CRT1             0
 114 #define ATOM_CRT2             1
 115
 116 #define ATOM_TV_NTSC          1
 117 #define ATOM_TV_NTSCJ         2
 118 #define ATOM_TV_PAL           3
 119 #define ATOM_TV_PALM          4
 120 #define ATOM_TV_PALCN         5
 121 #define ATOM_TV_PALN          6
 122 #define ATOM_TV_PAL60         7
 123 #define ATOM_TV_SECAM         8
 124 #define ATOM_TV_CV            16
 125
 126 #define ATOM_DAC1_PS2         1
 127 #define ATOM_DAC1_CV          2
 128 #define ATOM_DAC1_NTSC        3
 129 #define ATOM_DAC1_PAL         4
 130
 131 #define ATOM_DAC2_PS2         ATOM_DAC1_PS2
 132 #define ATOM_DAC2_CV          ATOM_DAC1_CV
 133 #define ATOM_DAC2_NTSC        ATOM_DAC1_NTSC
 134 #define ATOM_DAC2_PAL         ATOM_DAC1_PAL
 135
 136 #define ATOM_PM_ON            0
 137 #define ATOM_PM_STANDBY       1
 138 #define ATOM_PM_SUSPEND       2
 139 #define ATOM_PM_OFF           3
 140
 141 // For ATOM_LVDS_INFO_V12
 142 // Bit0:{=0:single, =1:dual},
 143 // Bit1 {=0:666RGB, =1:888RGB},
 144 // Bit2:3:{Grey level}
 145 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
 146 #define ATOM_PANEL_MISC_DUAL               0x00000001
 147 #define ATOM_PANEL_MISC_888RGB             0x00000002
 148 #define ATOM_PANEL_MISC_GREY_LEVEL         0x0000000C
 149 #define ATOM_PANEL_MISC_FPDI               0x00000010
 150 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT   2
 151 #define ATOM_PANEL_MISC_SPATIAL            0x00000020
 152 #define ATOM_PANEL_MISC_TEMPORAL           0x00000040
 153 #define ATOM_PANEL_MISC_API_ENABLED        0x00000080
 154
 155 #define MEMTYPE_DDR1                       "DDR1"
 156 #define MEMTYPE_DDR2                       "DDR2"
 157 #define MEMTYPE_DDR3                       "DDR3"
 158 #define MEMTYPE_DDR4                       "DDR4"
 159
 160 #define ASIC_BUS_TYPE_PCI                  "PCI"
 161 #define ASIC_BUS_TYPE_AGP                  "AGP"
 162 #define ASIC_BUS_TYPE_PCIE                 "PCI_EXPRESS"
 163
 164 //Maximum size of that FireGL flag string
 165 #define ATOM_FIREGL_FLAG_STRING            "FGL"      //Flag used to enable FireGL Support
 166 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING     3     //sizeof( ATOM_FIREGL_FLAG_STRING )
 167
 168 #define ATOM_FAKE_DESKTOP_STRING           "DSK"      //Flag used to enable mobile ASIC on Desktop
 169 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING    ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
 170
 171 #define ATOM_M54T_FLAG_STRING              "M54T"     //Flag used to enable M54T Support
 172 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING  4          //sizeof( ATOM_M54T_FLAG_STRING )
 173
 174 #define HW_ASSISTED_I2C_STATUS_FAILURE     2
 175 #define HW_ASSISTED_I2C_STATUS_SUCCESS     1
 176
 177 #pragma pack(1)                                       // BIOS data must use byte aligment
 178
 179 // Define offset to location of ROM header.
 180 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER         0x00000048L
 181 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE                0x00000002L
 182
 183 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE         0x94
 184 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE        20    //including the terminator 0x0!
 185 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER      0x002f
 186 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START       0x006e
 187
 188 /****************************************************************************/
 189 // Common header for all tables (Data table, Command table).
 190 // Every table pointed  _ATOM_MASTER_DATA_TABLE has this common header.
 191 // And the pointer actually points to this header.
 192 /****************************************************************************/
 193
 194 typedef struct _ATOM_COMMON_TABLE_HEADER
 195 {
 196   USHORT usStructureSize;
 197   UCHAR  ucTableFormatRevision;   //Change it when the Parser is not backward compatible
 198   UCHAR  ucTableContentRevision;  //Change it only when the table needs to change but the firmware
 199                                   //Image can't be updated, while Driver needs to carry the new table!
 200 }ATOM_COMMON_TABLE_HEADER;
 201
 202 /****************************************************************************/
 203 // Structure stores the ROM header.
 204 /****************************************************************************/
 205 typedef struct _ATOM_ROM_HEADER
 206 {
 207   ATOM_COMMON_TABLE_HEADER      sHeader;
 208   UCHAR  uaFirmWareSignature[4];    //Signature to distinguish between Atombios and non-atombios,
 209                                     //atombios should init it as "ATOM", don't change the position
 210   USHORT usBiosRuntimeSegmentAddress;
 211   USHORT usProtectedModeInfoOffset;
 212   USHORT usConfigFilenameOffset;
 213   USHORT usCRC_BlockOffset;
 214   USHORT usBIOS_BootupMessageOffset;
 215   USHORT usInt10Offset;
 216   USHORT usPciBusDevInitCode;
 217   USHORT usIoBaseAddress;
 218   USHORT usSubsystemVendorID;
 219   USHORT usSubsystemID;
 220   USHORT usPCI_InfoOffset;
 221   USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
 222   USHORT usMasterDataTableOffset;   //Offest for SW to get all data table offsets, Don't change the position
 223   UCHAR  ucExtendedFunctionCode;
 224   UCHAR  ucReserved;
 225 }ATOM_ROM_HEADER;
 226
 227 //==============================Command Table Portion====================================
 228
 229
 230 /****************************************************************************/
 231 // Structures used in Command.mtb
 232 /****************************************************************************/
 233 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
 234   USHORT ASIC_Init;                              //Function Table, used by various SW components,latest version 1.1
 235   USHORT GetDisplaySurfaceSize;                  //Atomic Table,  Used by Bios when enabling HW ICON
 236   USHORT ASIC_RegistersInit;                     //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 237   USHORT VRAM_BlockVenderDetection;              //Atomic Table,  used only by Bios
 238   USHORT DIGxEncoderControl;                     //Only used by Bios
 239   USHORT MemoryControllerInit;                   //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 240   USHORT EnableCRTCMemReq;                       //Function Table,directly used by various SW components,latest version 2.1
 241   USHORT MemoryParamAdjust;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock if needed
 242   USHORT DVOEncoderControl;                      //Function Table,directly used by various SW components,latest version 1.2
 243   USHORT GPIOPinControl;                         //Atomic Table,  only used by Bios
 244   USHORT SetEngineClock;                         //Function Table,directly used by various SW components,latest version 1.1
 245   USHORT SetMemoryClock;                         //Function Table,directly used by various SW components,latest version 1.1
 246   USHORT SetPixelClock;                          //Function Table,directly used by various SW components,latest version 1.2
 247   USHORT EnableDispPowerGating;                  //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 248   USHORT ResetMemoryDLL;                         //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 249   USHORT ResetMemoryDevice;                      //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 250   USHORT MemoryPLLInit;                          //Atomic Table,  used only by Bios
 251   USHORT AdjustDisplayPll;                       //Atomic Table,  used by various SW componentes.
 252   USHORT AdjustMemoryController;                 //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 253   USHORT EnableASIC_StaticPwrMgt;                //Atomic Table,  only used by Bios
 254   USHORT SetUniphyInstance;                      //Atomic Table,  only used by Bios
 255   USHORT DAC_LoadDetection;                      //Atomic Table,  directly used by various SW components,latest version 1.2
 256   USHORT LVTMAEncoderControl;                    //Atomic Table,directly used by various SW components,latest version 1.3
 257   USHORT HW_Misc_Operation;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 258   USHORT DAC1EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 259   USHORT DAC2EncoderControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 260   USHORT DVOOutputControl;                       //Atomic Table,  directly used by various SW components,latest version 1.1
 261   USHORT CV1OutputControl;                       //Atomic Table,  Atomic Table,  Obsolete from Ry6xx, use DAC2 Output instead
 262   USHORT GetConditionalGoldenSetting;            //Only used by Bios
 263   USHORT SMC_Init;                               //Function Table,directly used by various SW components,latest version 1.1
 264   USHORT PatchMCSetting;                         //only used by BIOS
 265   USHORT MC_SEQ_Control;                         //only used by BIOS
 266   USHORT Gfx_Harvesting;                         //Atomic Table,  Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting
 267   USHORT EnableScaler;                           //Atomic Table,  used only by Bios
 268   USHORT BlankCRTC;                              //Atomic Table,  directly used by various SW components,latest version 1.1
 269   USHORT EnableCRTC;                             //Atomic Table,  directly used by various SW components,latest version 1.1
 270   USHORT GetPixelClock;                          //Atomic Table,  directly used by various SW components,latest version 1.1
 271   USHORT EnableVGA_Render;                       //Function Table,directly used by various SW components,latest version 1.1
 272   USHORT GetSCLKOverMCLKRatio;                   //Atomic Table,  only used by Bios
 273   USHORT SetCRTC_Timing;                         //Atomic Table,  directly used by various SW components,latest version 1.1
 274   USHORT SetCRTC_OverScan;                       //Atomic Table,  used by various SW components,latest version 1.1
 275   USHORT SetCRTC_Replication;                    //Atomic Table,  used only by Bios
 276   USHORT SelectCRTC_Source;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 277   USHORT EnableGraphSurfaces;                    //Atomic Table,  used only by Bios
 278   USHORT UpdateCRTC_DoubleBufferRegisters;       //Atomic Table,  used only by Bios
 279   USHORT LUT_AutoFill;                           //Atomic Table,  only used by Bios
 280   USHORT EnableHW_IconCursor;                    //Atomic Table,  only used by Bios
 281   USHORT GetMemoryClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
 282   USHORT GetEngineClock;                         //Atomic Table,  directly used by various SW components,latest version 1.1
 283   USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
 284   USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
 285   USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 286   USHORT VRAM_BlockDetectionByStrap;             //Atomic Table,  used only by Bios
 287   USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios
 288   USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
 289   USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components
 290   USHORT ReadHWAssistedI2CStatus;                //Atomic Table,  indirectly used by various SW components
 291   USHORT SpeedFanControl;                        //Function Table,indirectly used by various SW components,called from ASIC_Init
 292   USHORT PowerConnectorDetection;                //Atomic Table,  directly used by various SW components,latest version 1.1
 293   USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 294   USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
 295   USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
 296   USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
 297   USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 298   USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
 299   USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
 300   USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
 301   USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
 302   USHORT DAC1OutputControl;                      //Atomic Table,  directly used by various SW components,latest version 1.1
 303   USHORT ReadEfuseValue;                         //Atomic Table,  directly used by various SW components,latest version 1.1
 304   USHORT ComputeMemoryClockParam;                //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
 305   USHORT ClockSource;                            //Atomic Table,  indirectly used by various SW components,called from ASIC_Init
 306   USHORT MemoryDeviceInit;                       //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
 307   USHORT GetDispObjectInfo;                      //Atomic Table,  indirectly used by various SW components,called from EnableVGARender
 308   USHORT DIG1EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
 309   USHORT DIG2EncoderControl;                     //Atomic Table,directly used by various SW components,latest version 1.1
 310   USHORT DIG1TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
 311   USHORT DIG2TransmitterControl;                 //Atomic Table,directly used by various SW components,latest version 1.1
 312   USHORT ProcessAuxChannelTransaction;           //Function Table,only used by Bios
 313   USHORT DPEncoderService;                       //Function Table,only used by Bios
 314   USHORT GetVoltageInfo;                         //Function Table,only used by Bios since SI
 315 }ATOM_MASTER_LIST_OF_COMMAND_TABLES;
 316
 317 // For backward compatible
 318 #define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
 319 #define DPTranslatorControl                      DIG2EncoderControl
 320 #define UNIPHYTransmitterControl                 DIG1TransmitterControl
 321 #define LVTMATransmitterControl                  DIG2TransmitterControl
 322 #define SetCRTC_DPM_State                        GetConditionalGoldenSetting
 323 #define ASIC_StaticPwrMgtStatusChange            SetUniphyInstance
 324 #define HPDInterruptService                      ReadHWAssistedI2CStatus
 325 #define EnableVGA_Access                         GetSCLKOverMCLKRatio
 326 #define EnableYUV                                GetDispObjectInfo
 327 #define DynamicClockGating                       EnableDispPowerGating
 328 #define SetupHWAssistedI2CStatus                 ComputeMemoryClockParam
 329 #define DAC2OutputControl                        ReadEfuseValue
 330
 331 #define TMDSAEncoderControl                      PatchMCSetting
 332 #define LVDSEncoderControl                       MC_SEQ_Control
 333 #define LCD1OutputControl                        HW_Misc_Operation
 334 #define TV1OutputControl                         Gfx_Harvesting
 335 #define TVEncoderControl                         SMC_Init
 336
 337 typedef struct _ATOM_MASTER_COMMAND_TABLE
 338 {
 339   ATOM_COMMON_TABLE_HEADER           sHeader;
 340   ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
 341 }ATOM_MASTER_COMMAND_TABLE;
 342
 343 /****************************************************************************/
 344 // Structures used in every command table
 345 /****************************************************************************/
 346 typedef struct _ATOM_TABLE_ATTRIBUTE
 347 {
 348 #if ATOM_BIG_ENDIAN
 349   USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
 350   USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword),
 351   USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword),
 352 #else
 353   USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword),
 354   USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword),
 355   USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
 356 #endif
 357 }ATOM_TABLE_ATTRIBUTE;
 358
 359 /****************************************************************************/
 360 // Common header for all command tables.
 361 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
 362 // And the pointer actually points to this header.
 363 /****************************************************************************/
 364 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
 365 {
 366   ATOM_COMMON_TABLE_HEADER CommonHeader;
 367   ATOM_TABLE_ATTRIBUTE     TableAttribute;
 368 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
 369
 370 /****************************************************************************/
 371 // Structures used by ComputeMemoryEnginePLLTable
 372 /****************************************************************************/
 373
 374 #define COMPUTE_MEMORY_PLL_PARAM        1
 375 #define COMPUTE_ENGINE_PLL_PARAM        2
 376 #define ADJUST_MC_SETTING_PARAM         3
 377
 378 /****************************************************************************/
 379 // Structures used by AdjustMemoryControllerTable
 380 /****************************************************************************/
 381 typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
 382 {
 383 #if ATOM_BIG_ENDIAN
 384   ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
 385   ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
 386   ULONG ulClockFreq:24;
 387 #else
 388   ULONG ulClockFreq:24;
 389   ULONG ulMemoryModuleNumber:7;     // BYTE_3[6:0]
 390   ULONG ulPointerReturnFlag:1;      // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
 391 #endif
 392 }ATOM_ADJUST_MEMORY_CLOCK_FREQ;
 393 #define POINTER_RETURN_FLAG             0x80
 394
 395 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
 396 {
 397   ULONG   ulClock;        //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
 398   UCHAR   ucAction;       //0:reserved //1:Memory //2:Engine
 399   UCHAR   ucReserved;     //may expand to return larger Fbdiv later
 400   UCHAR   ucFbDiv;        //return value
 401   UCHAR   ucPostDiv;      //return value
 402 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
 403
 404 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
 405 {
 406   ULONG   ulClock;        //When return, [23:0] return real clock
 407   UCHAR   ucAction;       //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
 408   USHORT  usFbDiv;          //return Feedback value to be written to register
 409   UCHAR   ucPostDiv;      //return post div to be written to register
 410 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
 411
 412 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
 413
 414 #define SET_CLOCK_FREQ_MASK                       0x00FFFFFF  //Clock change tables only take bit [23:0] as the requested clock value
 415 #define USE_NON_BUS_CLOCK_MASK                    0x01000000  //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
 416 #define USE_MEMORY_SELF_REFRESH_MASK              0x02000000   //Only applicable to memory clock change, when set, using memory self refresh during clock transition
 417 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE     0x04000000  //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
 418 #define FIRST_TIME_CHANGE_CLOCK                   0x08000000   //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
 419 #define SKIP_SW_PROGRAM_PLL                       0x10000000   //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
 420 #define USE_SS_ENABLED_PIXEL_CLOCK                USE_NON_BUS_CLOCK_MASK
 421
 422 #define b3USE_NON_BUS_CLOCK_MASK                  0x01       //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
 423 #define b3USE_MEMORY_SELF_REFRESH                 0x02        //Only applicable to memory clock change, when set, using memory self refresh during clock transition
 424 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE   0x04       //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
 425 #define b3FIRST_TIME_CHANGE_CLOCK                 0x08       //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
 426 #define b3SKIP_SW_PROGRAM_PLL                     0x10       //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
 427 #define b3DRAM_SELF_REFRESH_EXIT                  0x20       //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path
 428
 429 typedef struct _ATOM_COMPUTE_CLOCK_FREQ
 430 {
 431 #if ATOM_BIG_ENDIAN
 432   ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
 433   ULONG ulClockFreq:24;                       // in unit of 10kHz
 434 #else
 435   ULONG ulClockFreq:24;                       // in unit of 10kHz
 436   ULONG ulComputeClockFlag:8;                 // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
 437 #endif
 438 }ATOM_COMPUTE_CLOCK_FREQ;
 439
 440 typedef struct _ATOM_S_MPLL_FB_DIVIDER
 441 {
 442   USHORT usFbDivFrac;
 443   USHORT usFbDiv;
 444 }ATOM_S_MPLL_FB_DIVIDER;
 445
 446 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
 447 {
 448   union
 449   {
 450     ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
 451     ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
 452   };
 453   UCHAR   ucRefDiv;                           //Output Parameter
 454   UCHAR   ucPostDiv;                          //Output Parameter
 455   UCHAR   ucCntlFlag;                         //Output Parameter
 456   UCHAR   ucReserved;
 457 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
 458
 459 // ucCntlFlag
 460 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN          1
 461 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE            2
 462 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE         4
 463 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9                  8
 464
 465
 466 // V4 are only used for APU which PLL outside GPU
 467 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
 468 {
 469 #if ATOM_BIG_ENDIAN
 470   ULONG  ucPostDiv:8;        //return parameter: post divider which is used to program to register directly
 471   ULONG  ulClock:24;         //Input= target clock, output = actual clock
 472 #else
 473   ULONG  ulClock:24;         //Input= target clock, output = actual clock
 474   ULONG  ucPostDiv:8;        //return parameter: post divider which is used to program to register directly
 475 #endif
 476 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
 477
 478 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
 479 {
 480   union
 481   {
 482     ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
 483     ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter
 484   };
 485   UCHAR   ucRefDiv;                           //Output Parameter
 486   UCHAR   ucPostDiv;                          //Output Parameter
 487   union
 488   {
 489     UCHAR   ucCntlFlag;                       //Output Flags
 490     UCHAR   ucInputFlag;                      //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
 491   };
 492   UCHAR   ucReserved;
 493 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
 494
 495
 496 typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6
 497 {
 498   ATOM_COMPUTE_CLOCK_FREQ  ulClock;         //Input Parameter
 499   ULONG   ulReserved[2];
 500 }COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6;
 501
 502 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
 503 #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK            0x0f
 504 #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK           0x00
 505 #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK                     0x01
 506
 507
 508 typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6
 509 {
 510   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4  ulClock;         //Output Parameter: ucPostDiv=DFS divider
 511   ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output Parameter: PLL FB divider
 512   UCHAR   ucPllRefDiv;                      //Output Parameter: PLL ref divider
 513   UCHAR   ucPllPostDiv;                     //Output Parameter: PLL post divider
 514   UCHAR   ucPllCntlFlag;                    //Output Flags: control flag
 515   UCHAR   ucReserved;
 516 }COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6;
 517
 518 //ucPllCntlFlag
 519 #define SPLL_CNTL_FLAG_VCO_MODE_MASK            0x03
 520
 521
 522 // ucInputFlag
 523 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN  1   // 1-StrobeMode, 0-PerformanceMode
 524
 525 // use for ComputeMemoryClockParamTable
 526 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
 527 {
 528   union
 529   {
 530     ULONG  ulClock;
 531     ATOM_S_MPLL_FB_DIVIDER   ulFbDiv;         //Output:UPPER_WORD=FB_DIV_INTEGER,  LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
 532   };
 533   UCHAR   ucDllSpeed;                         //Output
 534   UCHAR   ucPostDiv;                          //Output
 535   union{
 536     UCHAR   ucInputFlag;                      //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
 537     UCHAR   ucPllCntlFlag;                    //Output:
 538   };
 539   UCHAR   ucBWCntl;
 540 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
 541
 542 // definition of ucInputFlag
 543 #define MPLL_INPUT_FLAG_STROBE_MODE_EN          0x01
 544 // definition of ucPllCntlFlag
 545 #define MPLL_CNTL_FLAG_VCO_MODE_MASK            0x03
 546 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL            0x04
 547 #define MPLL_CNTL_FLAG_QDR_ENABLE               0x08
 548 #define MPLL_CNTL_FLAG_AD_HALF_RATE             0x10
 549
 550 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
 551 #define MPLL_CNTL_FLAG_BYPASS_AD_PLL            0x04
 552
 553 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
 554 {
 555   ATOM_COMPUTE_CLOCK_FREQ ulClock;
 556   ULONG ulReserved[2];
 557 }DYNAMICE_MEMORY_SETTINGS_PARAMETER;
 558
 559 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
 560 {
 561   ATOM_COMPUTE_CLOCK_FREQ ulClock;
 562   ULONG ulMemoryClock;
 563   ULONG ulReserved;
 564 }DYNAMICE_ENGINE_SETTINGS_PARAMETER;
 565
 566 /****************************************************************************/
 567 // Structures used by SetEngineClockTable
 568 /****************************************************************************/
 569 typedef struct _SET_ENGINE_CLOCK_PARAMETERS
 570 {
 571   ULONG ulTargetEngineClock;          //In 10Khz unit
 572 }SET_ENGINE_CLOCK_PARAMETERS;
 573
 574 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
 575 {
 576   ULONG ulTargetEngineClock;          //In 10Khz unit
 577   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
 578 }SET_ENGINE_CLOCK_PS_ALLOCATION;
 579
 580 /****************************************************************************/
 581 // Structures used by SetMemoryClockTable
 582 /****************************************************************************/
 583 typedef struct _SET_MEMORY_CLOCK_PARAMETERS
 584 {
 585   ULONG ulTargetMemoryClock;          //In 10Khz unit
 586 }SET_MEMORY_CLOCK_PARAMETERS;
 587
 588 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
 589 {
 590   ULONG ulTargetMemoryClock;          //In 10Khz unit
 591   COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
 592 }SET_MEMORY_CLOCK_PS_ALLOCATION;
 593
 594 /****************************************************************************/
 595 // Structures used by ASIC_Init.ctb
 596 /****************************************************************************/
 597 typedef struct _ASIC_INIT_PARAMETERS
 598 {
 599   ULONG ulDefaultEngineClock;         //In 10Khz unit
 600   ULONG ulDefaultMemoryClock;         //In 10Khz unit
 601 }ASIC_INIT_PARAMETERS;
 602
 603 typedef struct _ASIC_INIT_PS_ALLOCATION
 604 {
 605   ASIC_INIT_PARAMETERS sASICInitClocks;
 606   SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
 607 }ASIC_INIT_PS_ALLOCATION;
 608
 609 typedef struct _ASIC_INIT_CLOCK_PARAMETERS
 610 {
 611   ULONG ulClkFreqIn10Khz:24;
 612   ULONG ucClkFlag:8;
 613 }ASIC_INIT_CLOCK_PARAMETERS;
 614
 615 typedef struct _ASIC_INIT_PARAMETERS_V1_2
 616 {
 617   ASIC_INIT_CLOCK_PARAMETERS asSclkClock;         //In 10Khz unit
 618   ASIC_INIT_CLOCK_PARAMETERS asMemClock;          //In 10Khz unit
 619 }ASIC_INIT_PARAMETERS_V1_2;
 620
 621 typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2
 622 {
 623   ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks;
 624   ULONG ulReserved[8];
 625 }ASIC_INIT_PS_ALLOCATION_V1_2;
 626
 627 /****************************************************************************/
 628 // Structure used by DynamicClockGatingTable.ctb
 629 /****************************************************************************/
 630 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
 631 {
 632   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
 633   UCHAR ucPadding[3];
 634 }DYNAMIC_CLOCK_GATING_PARAMETERS;
 635 #define  DYNAMIC_CLOCK_GATING_PS_ALLOCATION  DYNAMIC_CLOCK_GATING_PARAMETERS
 636
 637 /****************************************************************************/
 638 // Structure used by EnableDispPowerGatingTable.ctb
 639 /****************************************************************************/
 640 typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
 641 {
 642   UCHAR ucDispPipeId;                 // ATOM_CRTC1, ATOM_CRTC2, ...
 643   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
 644   UCHAR ucPadding[2];
 645 }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
 646
 647 typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION
 648 {
 649   UCHAR ucDispPipeId;                 // ATOM_CRTC1, ATOM_CRTC2, ...
 650   UCHAR ucEnable;                     // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT
 651   UCHAR ucPadding[2];
 652   ULONG ulReserved[4];
 653 }ENABLE_DISP_POWER_GATING_PS_ALLOCATION;
 654
 655 /****************************************************************************/
 656 // Structure used by EnableASIC_StaticPwrMgtTable.ctb
 657 /****************************************************************************/
 658 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
 659 {
 660   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
 661   UCHAR ucPadding[3];
 662 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
 663 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION  ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
 664
 665 /****************************************************************************/
 666 // Structures used by DAC_LoadDetectionTable.ctb
 667 /****************************************************************************/
 668 typedef struct _DAC_LOAD_DETECTION_PARAMETERS
 669 {
 670   USHORT usDeviceID;                  //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
 671   UCHAR  ucDacType;                   //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
 672   UCHAR  ucMisc;                                 //Valid only when table revision =1.3 and above
 673 }DAC_LOAD_DETECTION_PARAMETERS;
 674
 675 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc
 676 #define DAC_LOAD_MISC_YPrPb                  0x01
 677
 678 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
 679 {
 680   DAC_LOAD_DETECTION_PARAMETERS            sDacload;
 681   ULONG                                    Reserved[2];// Don't set this one, allocation for EXT DAC
 682 }DAC_LOAD_DETECTION_PS_ALLOCATION;
 683
 684 /****************************************************************************/
 685 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
 686 /****************************************************************************/
 687 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
 688 {
 689   USHORT usPixelClock;                // in 10KHz; for bios convenient
 690   UCHAR  ucDacStandard;               // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
 691   UCHAR  ucAction;                    // 0: turn off encoder
 692                                       // 1: setup and turn on encoder
 693                                       // 7: ATOM_ENCODER_INIT Initialize DAC
 694 }DAC_ENCODER_CONTROL_PARAMETERS;
 695
 696 #define DAC_ENCODER_CONTROL_PS_ALLOCATION  DAC_ENCODER_CONTROL_PARAMETERS
 697
 698 /****************************************************************************/
 699 // Structures used by DIG1EncoderControlTable
 700 //                    DIG2EncoderControlTable
 701 //                    ExternalEncoderControlTable
 702 /****************************************************************************/
 703 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
 704 {
 705   USHORT usPixelClock;      // in 10KHz; for bios convenient
 706   UCHAR  ucConfig;
 707                             // [2] Link Select:
 708                             // =0: PHY linkA if bfLane<3
 709                             // =1: PHY linkB if bfLanes<3
 710                             // =0: PHY linkA+B if bfLanes=3
 711                             // [3] Transmitter Sel
 712                             // =0: UNIPHY or PCIEPHY
 713                             // =1: LVTMA
 714   UCHAR ucAction;           // =0: turn off encoder
 715                             // =1: turn on encoder
 716   UCHAR ucEncoderMode;
 717                             // =0: DP   encoder
 718                             // =1: LVDS encoder
 719                             // =2: DVI  encoder
 720                             // =3: HDMI encoder
 721                             // =4: SDVO encoder
 722   UCHAR ucLaneNum;          // how many lanes to enable
 723   UCHAR ucReserved[2];
 724 }DIG_ENCODER_CONTROL_PARAMETERS;
 725 #define DIG_ENCODER_CONTROL_PS_ALLOCATION             DIG_ENCODER_CONTROL_PARAMETERS
 726 #define EXTERNAL_ENCODER_CONTROL_PARAMETER            DIG_ENCODER_CONTROL_PARAMETERS
 727
 728 //ucConfig
 729 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK           0x01
 730 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ        0x00
 731 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ        0x01
 732 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ        0x02
 733 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK             0x04
 734 #define ATOM_ENCODER_CONFIG_LINKA                     0x00
 735 #define ATOM_ENCODER_CONFIG_LINKB                     0x04
 736 #define ATOM_ENCODER_CONFIG_LINKA_B                   ATOM_TRANSMITTER_CONFIG_LINKA
 737 #define ATOM_ENCODER_CONFIG_LINKB_A                   ATOM_ENCODER_CONFIG_LINKB
 738 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK      0x08
 739 #define ATOM_ENCODER_CONFIG_UNIPHY                    0x00
 740 #define ATOM_ENCODER_CONFIG_LVTMA                     0x08
 741 #define ATOM_ENCODER_CONFIG_TRANSMITTER1              0x00
 742 #define ATOM_ENCODER_CONFIG_TRANSMITTER2              0x08
 743 #define ATOM_ENCODER_CONFIG_DIGB                      0x80         // VBIOS Internal use, outside SW should set this bit=0
 744 // ucAction
 745 // ATOM_ENABLE:  Enable Encoder
 746 // ATOM_DISABLE: Disable Encoder
 747
 748 //ucEncoderMode
 749 #define ATOM_ENCODER_MODE_DP                          0
 750 #define ATOM_ENCODER_MODE_LVDS                        1
 751 #define ATOM_ENCODER_MODE_DVI                         2
 752 #define ATOM_ENCODER_MODE_HDMI                        3
 753 #define ATOM_ENCODER_MODE_SDVO                        4
 754 #define ATOM_ENCODER_MODE_DP_AUDIO                    5
 755 #define ATOM_ENCODER_MODE_TV                          13
 756 #define ATOM_ENCODER_MODE_CV                          14
 757 #define ATOM_ENCODER_MODE_CRT                         15
 758 #define ATOM_ENCODER_MODE_DVO                         16
 759 #define ATOM_ENCODER_MODE_DP_SST                      ATOM_ENCODER_MODE_DP    // For DP1.2
 760 #define ATOM_ENCODER_MODE_DP_MST                      5                       // For DP1.2
 761
 762
 763 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
 764 {
 765 #if ATOM_BIG_ENDIAN
 766     UCHAR ucReserved1:2;
 767     UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
 768     UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
 769     UCHAR ucReserved:1;
 770     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 771 #else
 772     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 773     UCHAR ucReserved:1;
 774     UCHAR ucLinkSel:1;            // =0: linkA/C/E =1: linkB/D/F
 775     UCHAR ucTransmitterSel:2;     // =0: UniphyAB, =1: UniphyCD  =2: UniphyEF
 776     UCHAR ucReserved1:2;
 777 #endif
 778 }ATOM_DIG_ENCODER_CONFIG_V2;
 779
 780
 781 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
 782 {
 783   USHORT usPixelClock;      // in 10KHz; for bios convenient
 784   ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
 785   UCHAR ucAction;
 786   UCHAR ucEncoderMode;
 787                             // =0: DP   encoder
 788                             // =1: LVDS encoder
 789                             // =2: DVI  encoder
 790                             // =3: HDMI encoder
 791                             // =4: SDVO encoder
 792   UCHAR ucLaneNum;          // how many lanes to enable
 793   UCHAR ucStatus;           // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
 794   UCHAR ucReserved;
 795 }DIG_ENCODER_CONTROL_PARAMETERS_V2;
 796
 797 //ucConfig
 798 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK            0x01
 799 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ        0x00
 800 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ        0x01
 801 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK              0x04
 802 #define ATOM_ENCODER_CONFIG_V2_LINKA                          0x00
 803 #define ATOM_ENCODER_CONFIG_V2_LINKB                          0x04
 804 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK     0x18
 805 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1                0x00
 806 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2                0x08
 807 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3                0x10
 808
 809 // ucAction:
 810 // ATOM_DISABLE
 811 // ATOM_ENABLE
 812 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START       0x08
 813 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1    0x09
 814 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2    0x0a
 815 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3    0x13
 816 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE    0x0b
 817 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF                 0x0c
 818 #define ATOM_ENCODER_CMD_DP_VIDEO_ON                  0x0d
 819 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS    0x0e
 820 #define ATOM_ENCODER_CMD_SETUP                        0x0f
 821 #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE            0x10
 822
 823 // ucStatus
 824 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE    0x10
 825 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE  0x00
 826
 827 //ucTableFormatRevision=1
 828 //ucTableContentRevision=3
 829 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
 830 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
 831 {
 832 #if ATOM_BIG_ENDIAN
 833     UCHAR ucReserved1:1;
 834     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 835     UCHAR ucReserved:3;
 836     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 837 #else
 838     UCHAR ucDPLinkRate:1;         // =0: 1.62Ghz, =1: 2.7Ghz
 839     UCHAR ucReserved:3;
 840     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 841     UCHAR ucReserved1:1;
 842 #endif
 843 }ATOM_DIG_ENCODER_CONFIG_V3;
 844
 845 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK            0x03
 846 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ        0x00
 847 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ        0x01
 848 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL                 0x70
 849 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER                 0x00
 850 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER                 0x10
 851 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER                 0x20
 852 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER                 0x30
 853 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER                 0x40
 854 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER                 0x50
 855
 856 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
 857 {
 858   USHORT usPixelClock;      // in 10KHz; for bios convenient
 859   ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
 860   UCHAR ucAction;
 861   union{
 862     UCHAR ucEncoderMode;
 863                             // =0: DP   encoder
 864                             // =1: LVDS encoder
 865                             // =2: DVI  encoder
 866                             // =3: HDMI encoder
 867                             // =4: SDVO encoder
 868                             // =5: DP audio
 869     UCHAR ucPanelMode;        // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
 870                             // =0:     external DP
 871                             // =0x1:   internal DP2
 872                             // =0x11:  internal DP1 for NutMeg/Travis DP translator
 873   };
 874   UCHAR ucLaneNum;          // how many lanes to enable
 875   UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
 876   UCHAR ucReserved;
 877 }DIG_ENCODER_CONTROL_PARAMETERS_V3;
 878
 879 //ucTableFormatRevision=1
 880 //ucTableContentRevision=4
 881 // start from NI
 882 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
 883 typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
 884 {
 885 #if ATOM_BIG_ENDIAN
 886     UCHAR ucReserved1:1;
 887     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 888     UCHAR ucReserved:2;
 889     UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
 890 #else
 891     UCHAR ucDPLinkRate:2;         // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz    <= Changed comparing to previous version
 892     UCHAR ucReserved:2;
 893     UCHAR ucDigSel:3;             // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
 894     UCHAR ucReserved1:1;
 895 #endif
 896 }ATOM_DIG_ENCODER_CONFIG_V4;
 897
 898 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK            0x03
 899 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ        0x00
 900 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ        0x01
 901 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ        0x02
 902 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ        0x03
 903 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL                 0x70
 904 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER                 0x00
 905 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER                 0x10
 906 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER                 0x20
 907 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER                 0x30
 908 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER                 0x40
 909 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER                 0x50
 910 #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER                 0x60
 911
 912 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
 913 {
 914   USHORT usPixelClock;      // in 10KHz; for bios convenient
 915   union{
 916   ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
 917   UCHAR ucConfig;
 918   };
 919   UCHAR ucAction;
 920   union{
 921     UCHAR ucEncoderMode;
 922                             // =0: DP   encoder
 923                             // =1: LVDS encoder
 924                             // =2: DVI  encoder
 925                             // =3: HDMI encoder
 926                             // =4: SDVO encoder
 927                             // =5: DP audio
 928     UCHAR ucPanelMode;      // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
 929                             // =0:     external DP
 930                             // =0x1:   internal DP2
 931                             // =0x11:  internal DP1 for NutMeg/Travis DP translator
 932   };
 933   UCHAR ucLaneNum;          // how many lanes to enable
 934   UCHAR ucBitPerColor;      // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
 935   UCHAR ucHPD_ID;           // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
 936 }DIG_ENCODER_CONTROL_PARAMETERS_V4;
 937
 938 // define ucBitPerColor:
 939 #define PANEL_BPC_UNDEFINE                               0x00
 940 #define PANEL_6BIT_PER_COLOR                             0x01
 941 #define PANEL_8BIT_PER_COLOR                             0x02
 942 #define PANEL_10BIT_PER_COLOR                            0x03
 943 #define PANEL_12BIT_PER_COLOR                            0x04
 944 #define PANEL_16BIT_PER_COLOR                            0x05
 945
 946 //define ucPanelMode
 947 #define DP_PANEL_MODE_EXTERNAL_DP_MODE                   0x00
 948 #define DP_PANEL_MODE_INTERNAL_DP2_MODE                  0x01
 949 #define DP_PANEL_MODE_INTERNAL_DP1_MODE                  0x11
 950
 951 /****************************************************************************/
 952 // Structures used by UNIPHYTransmitterControlTable
 953 //                    LVTMATransmitterControlTable
 954 //                    DVOOutputControlTable
 955 /****************************************************************************/
 956 typedef struct _ATOM_DP_VS_MODE
 957 {
 958   UCHAR ucLaneSel;
 959   UCHAR ucLaneSet;
 960 }ATOM_DP_VS_MODE;
 961
 962 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
 963 {
 964    union
 965    {
 966   USHORT usPixelClock;      // in 10KHz; for bios convenient
 967    USHORT usInitInfo;         // when init uniphy,lower 8bit is used for connector type defined in objectid.h
 968   ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
 969    };
 970   UCHAR ucConfig;
 971                                        // [0]=0: 4 lane Link,
 972                                        //    =1: 8 lane Link ( Dual Links TMDS )
 973                           // [1]=0: InCoherent mode
 974                                        //    =1: Coherent Mode
 975                                        // [2] Link Select:
 976                                       // =0: PHY linkA   if bfLane<3
 977                                        // =1: PHY linkB   if bfLanes<3
 978                                       // =0: PHY linkA+B if bfLanes=3
 979                           // [5:4]PCIE lane Sel
 980                           // =0: lane 0~3 or 0~7
 981                           // =1: lane 4~7
 982                           // =2: lane 8~11 or 8~15
 983                           // =3: lane 12~15
 984    UCHAR ucAction;              // =0: turn off encoder
 985                            // =1: turn on encoder
 986   UCHAR ucReserved[4];
 987 }DIG_TRANSMITTER_CONTROL_PARAMETERS;
 988
 989 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION      DIG_TRANSMITTER_CONTROL_PARAMETERS
 990
 991 //ucInitInfo
 992 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK   0x00ff
 993
 994 //ucConfig
 995 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK         0x01
 996 #define ATOM_TRANSMITTER_CONFIG_COHERENT            0x02
 997 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK      0x04
 998 #define ATOM_TRANSMITTER_CONFIG_LINKA                  0x00
 999 #define ATOM_TRANSMITTER_CONFIG_LINKB                  0x04
1000 #define ATOM_TRANSMITTER_CONFIG_LINKA_B               0x00
1001 #define ATOM_TRANSMITTER_CONFIG_LINKB_A               0x04
1002
1003 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK   0x08         // only used when ATOM_TRANSMITTER_ACTION_ENABLE
1004 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER      0x00            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
1005 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER      0x08            // only used when ATOM_TRANSMITTER_ACTION_ENABLE
1006
1007 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK         0x30
1008 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL         0x00
1009 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE         0x20
1010 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN      0x30
1011 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK      0xc0
1012 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3            0x00
1013 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7            0x00
1014 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7            0x40
1015 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11            0x80
1016 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15            0x80
1017 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15         0xc0
1018
1019 //ucAction
1020 #define ATOM_TRANSMITTER_ACTION_DISABLE                      0
1021 #define ATOM_TRANSMITTER_ACTION_ENABLE                      1
1022 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF                   2
1023 #define ATOM_TRANSMITTER_ACTION_LCD_BLON                   3
1024 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL  4
1025 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START       5
1026 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP          6
1027 #define ATOM_TRANSMITTER_ACTION_INIT                         7
1028 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT          8
1029 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT             9
1030 #define ATOM_TRANSMITTER_ACTION_SETUP                         10
1031 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH           11
1032 #define ATOM_TRANSMITTER_ACTION_POWER_ON               12
1033 #define ATOM_TRANSMITTER_ACTION_POWER_OFF              13
1034
1035 // Following are used for DigTransmitterControlTable ver1.2
1036 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
1037 {
1038 #if ATOM_BIG_ENDIAN
1039   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1040                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1041                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1042   UCHAR ucReserved:1;
1043   UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
1044   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1045   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1046                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1047
1048   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1049   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1050 #else
1051   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1052   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1053   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1054                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1055   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1056   UCHAR fDPConnector:1;             //bit4=0: DP connector  =1: None DP connector
1057   UCHAR ucReserved:1;
1058   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1059                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1060                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1061 #endif
1062 }ATOM_DIG_TRANSMITTER_CONFIG_V2;
1063
1064 //ucConfig
1065 //Bit0
1066 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR         0x01
1067
1068 //Bit1
1069 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT                      0x02
1070
1071 //Bit2
1072 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK              0x04
1073 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA                       0x00
1074 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB                        0x04
1075
1076 // Bit3
1077 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK           0x08
1078 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER                0x00            // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1079 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER                0x08            // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
1080
1081 // Bit4
1082 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR                 0x10
1083
1084 // Bit7:6
1085 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK     0xC0
1086 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1              0x00   //AB
1087 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2              0x40   //CD
1088 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3              0x80   //EF
1089
1090 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
1091 {
1092    union
1093    {
1094   USHORT usPixelClock;      // in 10KHz; for bios convenient
1095    USHORT usInitInfo;         // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1096   ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1097    };
1098   ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
1099    UCHAR ucAction;              // define as ATOM_TRANSMITER_ACTION_XXX
1100   UCHAR ucReserved[4];
1101 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
1102
1103 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
1104 {
1105 #if ATOM_BIG_ENDIAN
1106   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1107                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1108                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1109   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1110   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1111   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1112                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1113   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1114   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1115 #else
1116   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1117   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1118   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1119                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1120   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1121   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1122   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1123                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1124                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1125 #endif
1126 }ATOM_DIG_TRANSMITTER_CONFIG_V3;
1127
1128
1129 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
1130 {
1131    union
1132    {
1133     USHORT usPixelClock;      // in 10KHz; for bios convenient
1134      USHORT usInitInfo;         // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1135     ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
1136    };
1137   ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
1138    UCHAR ucAction;                // define as ATOM_TRANSMITER_ACTION_XXX
1139   UCHAR ucLaneNum;
1140   UCHAR ucReserved[3];
1141 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
1142
1143 //ucConfig
1144 //Bit0
1145 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR         0x01
1146
1147 //Bit1
1148 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT                      0x02
1149
1150 //Bit2
1151 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK              0x04
1152 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA                       0x00
1153 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB                        0x04
1154
1155 // Bit3
1156 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK           0x08
1157 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER                0x00
1158 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER                0x08
1159
1160 // Bit5:4
1161 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK            0x30
1162 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL                        0x00
1163 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL                        0x10
1164 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT            0x20
1165
1166 // Bit7:6
1167 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK     0xC0
1168 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1              0x00   //AB
1169 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2              0x40   //CD
1170 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3              0x80   //EF
1171
1172
1173 /****************************************************************************/
1174 // Structures used by UNIPHYTransmitterControlTable V1.4
1175 // ASIC Families: NI
1176 // ucTableFormatRevision=1
1177 // ucTableContentRevision=4
1178 /****************************************************************************/
1179 typedef struct _ATOM_DP_VS_MODE_V4
1180 {
1181   UCHAR ucLaneSel;
1182         union
1183         {
1184           UCHAR ucLaneSet;
1185           struct {
1186 #if ATOM_BIG_ENDIAN
1187                   UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
1188                   UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
1189                   UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
1190 #else
1191                   UCHAR ucVOLTAGE_SWING:3;        //Bit[2:0] Voltage Swing Level
1192                   UCHAR ucPRE_EMPHASIS:3;         //Bit[5:3] Pre-emphasis Level
1193                   UCHAR ucPOST_CURSOR2:2;         //Bit[7:6] Post Cursor2 Level      <= New in V4
1194 #endif
1195                 };
1196         };
1197 }ATOM_DP_VS_MODE_V4;
1198
1199 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
1200 {
1201 #if ATOM_BIG_ENDIAN
1202   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1203                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1204                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1205   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
1206   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1207   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1208                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1209   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1210   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1211 #else
1212   UCHAR fDualLinkConnector:1;       //bit0=1: Dual Link DVI connector
1213   UCHAR fCoherentMode:1;            //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1214   UCHAR ucLinkSel:1;                //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1215                                     //    =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
1216   UCHAR ucEncoderSel:1;             //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1217   UCHAR ucRefClkSource:2;           //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3   <= New
1218   UCHAR ucTransmitterSel:2;         //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1219                                     //        =1 Dig Transmitter 2 ( Uniphy CD )
1220                                     //        =2 Dig Transmitter 3 ( Uniphy EF )
1221 #endif
1222 }ATOM_DIG_TRANSMITTER_CONFIG_V4;
1223
1224 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
1225 {
1226   union
1227   {
1228     USHORT usPixelClock;      // in 10KHz; for bios convenient
1229     USHORT usInitInfo;         // when init uniphy,lower 8bit is used for connector type defined in objectid.h
1230     ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode     Redefined comparing to previous version
1231   };
1232   union
1233   {
1234   ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
1235   UCHAR ucConfig;
1236   };
1237   UCHAR ucAction;                // define as ATOM_TRANSMITER_ACTION_XXX
1238   UCHAR ucLaneNum;
1239   UCHAR ucReserved[3];
1240 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
1241
1242 //ucConfig
1243 //Bit0
1244 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR         0x01
1245 //Bit1
1246 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT                      0x02
1247 //Bit2
1248 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK              0x04
1249 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA                       0x00
1250 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB                        0x04
1251 // Bit3
1252 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK           0x08
1253 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER                0x00
1254 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER                0x08
1255 // Bit5:4
1256 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK            0x30
1257 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL                       0x00
1258 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL                      0x10
1259 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL                      0x20   // New in _V4
1260 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT           0x30   // Changed comparing to V3
1261 // Bit7:6
1262 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK     0xC0
1263 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1              0x00   //AB
1264 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2              0x40   //CD
1265 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3              0x80   //EF
1266
1267
1268 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
1269 {
1270 #if ATOM_BIG_ENDIAN
1271   UCHAR ucReservd1:1;
1272   UCHAR ucHPDSel:3;
1273   UCHAR ucPhyClkSrcId:2;
1274   UCHAR ucCoherentMode:1;
1275   UCHAR ucReserved:1;
1276 #else
1277   UCHAR ucReserved:1;
1278   UCHAR ucCoherentMode:1;
1279   UCHAR ucPhyClkSrcId:2;
1280   UCHAR ucHPDSel:3;
1281   UCHAR ucReservd1:1;
1282 #endif
1283 }ATOM_DIG_TRANSMITTER_CONFIG_V5;
1284
1285 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1286 {
1287   USHORT usSymClock;              // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock,  (HDMI deep color), =pixel clock * deep_color_ratio
1288   UCHAR  ucPhyId;                   // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1289   UCHAR  ucAction;                // define as ATOM_TRANSMITER_ACTION_xxx
1290   UCHAR  ucLaneNum;                 // indicate lane number 1-8
1291   UCHAR  ucConnObjId;               // Connector Object Id defined in ObjectId.h
1292   UCHAR  ucDigMode;                 // indicate DIG mode
1293   union{
1294   ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1295   UCHAR ucConfig;
1296   };
1297   UCHAR  ucDigEncoderSel;           // indicate DIG front end encoder
1298   UCHAR  ucDPLaneSet;
1299   UCHAR  ucReserved;
1300   UCHAR  ucReserved1;
1301 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
1302
1303 //ucPhyId
1304 #define ATOM_PHY_ID_UNIPHYA                                 0
1305 #define ATOM_PHY_ID_UNIPHYB                                 1
1306 #define ATOM_PHY_ID_UNIPHYC                                 2
1307 #define ATOM_PHY_ID_UNIPHYD                                 3
1308 #define ATOM_PHY_ID_UNIPHYE                                 4
1309 #define ATOM_PHY_ID_UNIPHYF                                 5
1310 #define ATOM_PHY_ID_UNIPHYG                                 6
1311
1312 // ucDigEncoderSel
1313 #define ATOM_TRANMSITTER_V5__DIGA_SEL                       0x01
1314 #define ATOM_TRANMSITTER_V5__DIGB_SEL                       0x02
1315 #define ATOM_TRANMSITTER_V5__DIGC_SEL                       0x04
1316 #define ATOM_TRANMSITTER_V5__DIGD_SEL                       0x08
1317 #define ATOM_TRANMSITTER_V5__DIGE_SEL                       0x10
1318 #define ATOM_TRANMSITTER_V5__DIGF_SEL                       0x20
1319 #define ATOM_TRANMSITTER_V5__DIGG_SEL                       0x40
1320
1321 // ucDigMode
1322 #define ATOM_TRANSMITTER_DIGMODE_V5_DP                      0
1323 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS                    1
1324 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI                     2
1325 #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI                    3
1326 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO                    4
1327 #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST                  5
1328
1329 // ucDPLaneSet
1330 #define DP_LANE_SET__0DB_0_4V                               0x00
1331 #define DP_LANE_SET__0DB_0_6V                               0x01
1332 #define DP_LANE_SET__0DB_0_8V                               0x02
1333 #define DP_LANE_SET__0DB_1_2V                               0x03
1334 #define DP_LANE_SET__3_5DB_0_4V                             0x08
1335 #define DP_LANE_SET__3_5DB_0_6V                             0x09
1336 #define DP_LANE_SET__3_5DB_0_8V                             0x0a
1337 #define DP_LANE_SET__6DB_0_4V                               0x10
1338 #define DP_LANE_SET__6DB_0_6V                               0x11
1339 #define DP_LANE_SET__9_5DB_0_4V                             0x18
1340
1341 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
1342 // Bit1
1343 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT                      0x02
1344
1345 // Bit3:2
1346 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK            0x0c
1347 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT          0x02
1348
1349 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL                       0x00
1350 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL                      0x04
1351 #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL                      0x08
1352 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT           0x0c
1353 // Bit6:4
1354 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK                0x70
1355 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT            0x04
1356
1357 #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL                    0x00
1358 #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL                      0x10
1359 #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL                      0x20
1360 #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL                      0x30
1361 #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL                      0x40
1362 #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL                      0x50
1363 #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL                      0x60
1364
1365 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5            DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
1366
1367
1368 /****************************************************************************/
1369 // Structures used by ExternalEncoderControlTable V1.3
1370 // ASIC Families: Evergreen, Llano, NI
1371 // ucTableFormatRevision=1
1372 // ucTableContentRevision=3
1373 /****************************************************************************/
1374
1375 typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
1376 {
1377   union{
1378   USHORT usPixelClock;      // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
1379   USHORT usConnectorId;     // connector id, valid when ucAction = INIT
1380   };
1381   UCHAR  ucConfig;          // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1382   UCHAR  ucAction;          //
1383   UCHAR  ucEncoderMode;     // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1384   UCHAR  ucLaneNum;         // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1385   UCHAR  ucBitPerColor;     // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1386   UCHAR  ucReserved;
1387 }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
1388
1389 // ucAction
1390 #define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT         0x00
1391 #define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT          0x01
1392 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT           0x07
1393 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP          0x0f
1394 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF   0x10
1395 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING       0x11
1396 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION      0x12
1397 #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP              0x14
1398
1399 // ucConfig
1400 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK            0x03
1401 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ        0x00
1402 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ        0x01
1403 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ        0x02
1404 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS          0x70
1405 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1                  0x00
1406 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2                  0x10
1407 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3                  0x20
1408
1409 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
1410 {
1411   EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
1412   ULONG ulReserved[2];
1413 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
1414
1415
1416 /****************************************************************************/
1417 // Structures used by DAC1OuputControlTable
1418 //                    DAC2OuputControlTable
1419 //                    LVTMAOutputControlTable  (Before DEC30)
1420 //                    TMDSAOutputControlTable  (Before DEC30)
1421 /****************************************************************************/
1422 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1423 {
1424   UCHAR  ucAction;                    // Possible input:ATOM_ENABLE||ATOMDISABLE
1425                                       // When the display is LCD, in addition to above:
1426                                       // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
1427                                       // ATOM_LCD_SELFTEST_STOP
1428
1429   UCHAR  aucPadding[3];               // padding to DWORD aligned
1430 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
1431
1432 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1433
1434
1435 #define CRT1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1436 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1437
1438 #define CRT2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1439 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1440
1441 #define CV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1442 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1443
1444 #define TV1_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1445 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION   DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1446
1447 #define DFP1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1448 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1449
1450 #define DFP2_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1451 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1452
1453 #define LCD1_OUTPUT_CONTROL_PARAMETERS     DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1454 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION  DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
1455
1456 #define DVO_OUTPUT_CONTROL_PARAMETERS      DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
1457 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION   DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
1458 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3   DIG_TRANSMITTER_CONTROL_PARAMETERS
1459
1460
1461 typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2
1462 {
1463   // Possible value of ucAction
1464   // ATOM_TRANSMITTER_ACTION_LCD_BLON
1465   // ATOM_TRANSMITTER_ACTION_LCD_BLOFF
1466   // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
1467   // ATOM_TRANSMITTER_ACTION_POWER_ON
1468   // ATOM_TRANSMITTER_ACTION_POWER_OFF
1469   UCHAR  ucAction;
1470   UCHAR  ucBriLevel;
1471   USHORT usPwmFreq;                  // in unit of Hz, 200 means 200Hz
1472 }LVTMA_OUTPUT_CONTROL_PARAMETERS_V2;
1473
1474
1475
1476 /****************************************************************************/
1477 // Structures used by BlankCRTCTable
1478 /****************************************************************************/
1479 typedef struct _BLANK_CRTC_PARAMETERS
1480 {
1481   UCHAR  ucCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
1482   UCHAR  ucBlanking;                  // ATOM_BLANKING or ATOM_BLANKINGOFF
1483   USHORT usBlackColorRCr;
1484   USHORT usBlackColorGY;
1485   USHORT usBlackColorBCb;
1486 }BLANK_CRTC_PARAMETERS;
1487 #define BLANK_CRTC_PS_ALLOCATION    BLANK_CRTC_PARAMETERS
1488
1489 /****************************************************************************/
1490 // Structures used by EnableCRTCTable
1491 //                    EnableCRTCMemReqTable
1492 //                    UpdateCRTC_DoubleBufferRegistersTable
1493 /****************************************************************************/
1494 typedef struct _ENABLE_CRTC_PARAMETERS
1495 {
1496   UCHAR ucCRTC;                         // ATOM_CRTC1 or ATOM_CRTC2
1497   UCHAR ucEnable;                     // ATOM_ENABLE or ATOM_DISABLE
1498   UCHAR ucPadding[2];
1499 }ENABLE_CRTC_PARAMETERS;
1500 #define ENABLE_CRTC_PS_ALLOCATION   ENABLE_CRTC_PARAMETERS
1501
1502 /****************************************************************************/
1503 // Structures used by SetCRTC_OverScanTable
1504 /****************************************************************************/
1505 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
1506 {
1507   USHORT usOverscanRight;             // right
1508   USHORT usOverscanLeft;              // left
1509   USHORT usOverscanBottom;            // bottom
1510   USHORT usOverscanTop;               // top
1511   UCHAR  ucCRTC;                      // ATOM_CRTC1 or ATOM_CRTC2
1512   UCHAR  ucPadding[3];
1513 }SET_CRTC_OVERSCAN_PARAMETERS;
1514 #define SET_CRTC_OVERSCAN_PS_ALLOCATION  SET_CRTC_OVERSCAN_PARAMETERS
1515
1516 /****************************************************************************/
1517 // Structures used by SetCRTC_ReplicationTable
1518 /****************************************************************************/
1519 typedef struct _SET_CRTC_REPLICATION_PARAMETERS
1520 {
1521   UCHAR ucH_Replication;              // horizontal replication
1522   UCHAR ucV_Replication;              // vertical replication
1523   UCHAR usCRTC;                       // ATOM_CRTC1 or ATOM_CRTC2
1524   UCHAR ucPadding;
1525 }SET_CRTC_REPLICATION_PARAMETERS;
1526 #define SET_CRTC_REPLICATION_PS_ALLOCATION  SET_CRTC_REPLICATION_PARAMETERS
1527
1528 /****************************************************************************/
1529 // Structures used by SelectCRTC_SourceTable
1530 /****************************************************************************/
1531 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
1532 {
1533   UCHAR ucCRTC;                         // ATOM_CRTC1 or ATOM_CRTC2
1534   UCHAR ucDevice;                     // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1535   UCHAR ucPadding[2];
1536 }SELECT_CRTC_SOURCE_PARAMETERS;
1537 #define SELECT_CRTC_SOURCE_PS_ALLOCATION  SELECT_CRTC_SOURCE_PARAMETERS
1538
1539 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
1540 {
1541   UCHAR ucCRTC;                         // ATOM_CRTC1 or ATOM_CRTC2
1542   UCHAR ucEncoderID;                  // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1543   UCHAR ucEncodeMode;                           // Encoding mode, only valid when using DIG1/DIG2/DVO
1544   UCHAR ucPadding;
1545 }SELECT_CRTC_SOURCE_PARAMETERS_V2;
1546
1547 //ucEncoderID
1548 //#define ASIC_INT_DAC1_ENCODER_ID                      0x00
1549 //#define ASIC_INT_TV_ENCODER_ID                           0x02
1550 //#define ASIC_INT_DIG1_ENCODER_ID                        0x03
1551 //#define ASIC_INT_DAC2_ENCODER_ID                        0x04
1552 //#define ASIC_EXT_TV_ENCODER_ID                           0x06
1553 //#define ASIC_INT_DVO_ENCODER_ID                           0x07
1554 //#define ASIC_INT_DIG2_ENCODER_ID                        0x09
1555 //#define ASIC_EXT_DIG_ENCODER_ID                           0x05
1556
1557 //ucEncodeMode
1558 //#define ATOM_ENCODER_MODE_DP                              0
1559 //#define ATOM_ENCODER_MODE_LVDS                           1
1560 //#define ATOM_ENCODER_MODE_DVI                              2
1561 //#define ATOM_ENCODER_MODE_HDMI                           3
1562 //#define ATOM_ENCODER_MODE_SDVO                           4
1563 //#define ATOM_ENCODER_MODE_TV                              13
1564 //#define ATOM_ENCODER_MODE_CV                              14
1565 //#define ATOM_ENCODER_MODE_CRT                              15
1566
1567
1568 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3
1569 {
1570   UCHAR ucCRTC;                         // ATOM_CRTC1 or ATOM_CRTC2
1571   UCHAR ucEncoderID;                    // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1572   UCHAR ucEncodeMode;                   // Encoding mode, only valid when using DIG1/DIG2/DVO
1573   UCHAR ucDstBpc;                       // PANEL_6/8/10/12BIT_PER_COLOR
1574 }SELECT_CRTC_SOURCE_PARAMETERS_V3;
1575
1576
1577 /****************************************************************************/
1578 // Structures used by SetPixelClockTable
1579 //                    GetPixelClockTable
1580 /****************************************************************************/
1581 //Major revision=1., Minor revision=1
1582 typedef struct _PIXEL_CLOCK_PARAMETERS
1583 {
1584   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1585                                       // 0 means disable PPLL
1586   USHORT usRefDiv;                    // Reference divider
1587   USHORT usFbDiv;                     // feedback divider
1588   UCHAR  ucPostDiv;                   // post divider
1589   UCHAR  ucFracFbDiv;                 // fractional feedback divider
1590   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
1591   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
1592   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
1593   UCHAR  ucPadding;
1594 }PIXEL_CLOCK_PARAMETERS;
1595
1596 //Major revision=1., Minor revision=2, add ucMiscIfno
1597 //ucMiscInfo:
1598 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
1599 #define MISC_DEVICE_INDEX_MASK        0xF0
1600 #define MISC_DEVICE_INDEX_SHIFT       4
1601
1602 typedef struct _PIXEL_CLOCK_PARAMETERS_V2
1603 {
1604   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1605                                       // 0 means disable PPLL
1606   USHORT usRefDiv;                    // Reference divider
1607   USHORT usFbDiv;                     // feedback divider
1608   UCHAR  ucPostDiv;                   // post divider
1609   UCHAR  ucFracFbDiv;                 // fractional feedback divider
1610   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
1611   UCHAR  ucRefDivSrc;                 // ATOM_PJITTER or ATO_NONPJITTER
1612   UCHAR  ucCRTC;                      // Which CRTC uses this Ppll
1613   UCHAR  ucMiscInfo;                  // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1614 }PIXEL_CLOCK_PARAMETERS_V2;
1615
1616 //Major revision=1., Minor revision=3, structure/definition change
1617 //ucEncoderMode:
1618 //ATOM_ENCODER_MODE_DP
1619 //ATOM_ENOCDER_MODE_LVDS
1620 //ATOM_ENOCDER_MODE_DVI
1621 //ATOM_ENOCDER_MODE_HDMI
1622 //ATOM_ENOCDER_MODE_SDVO
1623 //ATOM_ENCODER_MODE_TV                                          13
1624 //ATOM_ENCODER_MODE_CV                                          14
1625 //ATOM_ENCODER_MODE_CRT                                          15
1626
1627 //ucDVOConfig
1628 //#define DVO_ENCODER_CONFIG_RATE_SEL                     0x01
1629 //#define DVO_ENCODER_CONFIG_DDR_SPEED                  0x00
1630 //#define DVO_ENCODER_CONFIG_SDR_SPEED                  0x01
1631 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL                  0x0c
1632 //#define DVO_ENCODER_CONFIG_LOW12BIT                     0x00
1633 //#define DVO_ENCODER_CONFIG_UPPER12BIT                  0x04
1634 //#define DVO_ENCODER_CONFIG_24BIT                        0x08
1635
1636 //ucMiscInfo: also changed, see below
1637 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL                  0x01
1638 #define PIXEL_CLOCK_MISC_VGA_MODE                              0x02
1639 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK                     0x04
1640 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1                     0x00
1641 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2                     0x04
1642 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK         0x08
1643 #define PIXEL_CLOCK_MISC_REF_DIV_SRC                    0x10
1644 // V1.4 for RoadRunner
1645 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE               0x10
1646 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE           0x20
1647
1648
1649 typedef struct _PIXEL_CLOCK_PARAMETERS_V3
1650 {
1651   USHORT usPixelClock;                // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
1652                                       // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
1653   USHORT usRefDiv;                    // Reference divider
1654   USHORT usFbDiv;                     // feedback divider
1655   UCHAR  ucPostDiv;                   // post divider
1656   UCHAR  ucFracFbDiv;                 // fractional feedback divider
1657   UCHAR  ucPpll;                      // ATOM_PPLL1 or ATOM_PPL2
1658   UCHAR  ucTransmitterId;             // graphic encoder id defined in objectId.h
1659    union
1660    {
1661   UCHAR  ucEncoderMode;               // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1662    UCHAR  ucDVOConfig;                           // when use DVO, need to know SDR/DDR, 12bit or 24bit
1663    };
1664   UCHAR  ucMiscInfo;                  // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1665                                       // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
1666                                       // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
1667 }PIXEL_CLOCK_PARAMETERS_V3;
1668
1669 #define PIXEL_CLOCK_PARAMETERS_LAST                     PIXEL_CLOCK_PARAMETERS_V2
1670 #define GET_PIXEL_CLOCK_PS_ALLOCATION                  PIXEL_CLOCK_PARAMETERS_LAST
1671
1672
1673 typedef struct _PIXEL_CLOCK_PARAMETERS_V5
1674 {
1675   UCHAR  ucCRTC;             // ATOM_CRTC1~6, indicate the CRTC controller to
1676                              // drive the pixel clock. not used for DCPLL case.
1677   union{
1678   UCHAR  ucReserved;
1679   UCHAR  ucFracFbDiv;        // [gphan] temporary to prevent build problem.  remove it after driver code is changed.
1680   };
1681   USHORT usPixelClock;       // target the pixel clock to drive the CRTC timing
1682                              // 0 means disable PPLL/DCPLL.
1683   USHORT usFbDiv;            // feedback divider integer part.
1684   UCHAR  ucPostDiv;          // post divider.
1685   UCHAR  ucRefDiv;           // Reference divider
1686   UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1687   UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h,
1688                              // indicate which graphic encoder will be used.
1689   UCHAR  ucEncoderMode;      // Encoder mode:
1690   UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL
1691                              // bit[1]= when VGA timing is used.
1692                              // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1693                              // bit[4]= RefClock source for PPLL.
1694                              // =0: XTLAIN( default mode )
1695                               // =1: other external clock source, which is pre-defined
1696                              //     by VBIOS depend on the feature required.
1697                              // bit[7:5]: reserved.
1698   ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1699
1700 }PIXEL_CLOCK_PARAMETERS_V5;
1701
1702 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL               0x01
1703 #define PIXEL_CLOCK_V5_MISC_VGA_MODE                        0x02
1704 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK           0x0c
1705 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP              0x00
1706 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP              0x04
1707 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP              0x08
1708 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC             0x10
1709
1710 typedef struct _CRTC_PIXEL_CLOCK_FREQ
1711 {
1712 #if ATOM_BIG_ENDIAN
1713   ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to
1714                               // drive the pixel clock. not used for DCPLL case.
1715   ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing.
1716                               // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1717 #else
1718   ULONG  ulPixelClock:24;     // target the pixel clock to drive the CRTC timing.
1719                               // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
1720   ULONG  ucCRTC:8;            // ATOM_CRTC1~6, indicate the CRTC controller to
1721                               // drive the pixel clock. not used for DCPLL case.
1722 #endif
1723 }CRTC_PIXEL_CLOCK_FREQ;
1724
1725 typedef struct _PIXEL_CLOCK_PARAMETERS_V6
1726 {
1727   union{
1728     CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;    // pixel clock and CRTC id frequency
1729     ULONG ulDispEngClkFreq;                  // dispclk frequency
1730   };
1731   USHORT usFbDiv;            // feedback divider integer part.
1732   UCHAR  ucPostDiv;          // post divider.
1733   UCHAR  ucRefDiv;           // Reference divider
1734   UCHAR  ucPpll;             // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1735   UCHAR  ucTransmitterID;    // ASIC encoder id defined in objectId.h,
1736                              // indicate which graphic encoder will be used.
1737   UCHAR  ucEncoderMode;      // Encoder mode:
1738   UCHAR  ucMiscInfo;         // bit[0]= Force program PPLL
1739                              // bit[1]= when VGA timing is used.
1740                              // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
1741                              // bit[4]= RefClock source for PPLL.
1742                              // =0: XTLAIN( default mode )
1743                               // =1: other external clock source, which is pre-defined
1744                              //     by VBIOS depend on the feature required.
1745                              // bit[7:5]: reserved.
1746   ULONG  ulFbDivDecFrac;     // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
1747
1748 }PIXEL_CLOCK_PARAMETERS_V6;
1749
1750 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL               0x01
1751 #define PIXEL_CLOCK_V6_MISC_VGA_MODE                        0x02
1752 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK           0x0c
1753 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP              0x00
1754 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP              0x04
1755 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6           0x08    //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
1756 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP              0x08
1757 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6           0x04    //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
1758 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP              0x0c
1759 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC             0x10
1760 #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK            0x40
1761 #define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS         0x40
1762
1763 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
1764 {
1765   PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
1766 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
1767
1768 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
1769 {
1770   UCHAR  ucStatus;
1771   UCHAR  ucRefDivSrc;                 // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
1772   UCHAR  ucReserved[2];
1773 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
1774
1775 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
1776 {
1777   PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
1778 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
1779
1780
1781 /****************************************************************************/
1782 // Structures used by AdjustDisplayPllTable
1783 /****************************************************************************/
1784 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
1785 {
1786    USHORT usPixelClock;
1787    UCHAR ucTransmitterID;
1788    UCHAR ucEncodeMode;
1789    union
1790    {
1791       UCHAR ucDVOConfig;                           //if DVO, need passing link rate and output 12bitlow or 24bit
1792       UCHAR ucConfig;                                 //if none DVO, not defined yet
1793    };
1794    UCHAR ucReserved[3];
1795 }ADJUST_DISPLAY_PLL_PARAMETERS;
1796
1797 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE            0x10
1798 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION              ADJUST_DISPLAY_PLL_PARAMETERS
1799
1800 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
1801 {
1802    USHORT usPixelClock;                    // target pixel clock
1803    UCHAR ucTransmitterID;                  // GPU transmitter id defined in objectid.h
1804    UCHAR ucEncodeMode;                     // encoder mode: CRT, LVDS, DP, TMDS or HDMI
1805   UCHAR ucDispPllConfig;                 // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
1806   UCHAR ucExtTransmitterID;               // external encoder id.
1807    UCHAR ucReserved[2];
1808 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
1809
1810 // usDispPllConfig v1.2 for RoadRunner
1811 #define DISPPLL_CONFIG_DVO_RATE_SEL                0x0001     // need only when ucTransmitterID = DVO
1812 #define DISPPLL_CONFIG_DVO_DDR_SPEED               0x0000     // need only when ucTransmitterID = DVO
1813 #define DISPPLL_CONFIG_DVO_SDR_SPEED               0x0001     // need only when ucTransmitterID = DVO
1814 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL              0x000c     // need only when ucTransmitterID = DVO
1815 #define DISPPLL_CONFIG_DVO_LOW12BIT                0x0000     // need only when ucTransmitterID = DVO
1816 #define DISPPLL_CONFIG_DVO_UPPER12BIT              0x0004     // need only when ucTransmitterID = DVO
1817 #define DISPPLL_CONFIG_DVO_24BIT                   0x0008     // need only when ucTransmitterID = DVO
1818 #define DISPPLL_CONFIG_SS_ENABLE                   0x0010     // Only used when ucEncoderMode = DP or LVDS
1819 #define DISPPLL_CONFIG_COHERENT_MODE               0x0020     // Only used when ucEncoderMode = TMDS or HDMI
1820 #define DISPPLL_CONFIG_DUAL_LINK                   0x0040     // Only used when ucEncoderMode = TMDS or LVDS
1821
1822
1823 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
1824 {
1825   ULONG ulDispPllFreq;                 // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
1826   UCHAR ucRefDiv;                      // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
1827   UCHAR ucPostDiv;                     // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
1828   UCHAR ucReserved[2];
1829 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
1830
1831 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
1832 {
1833   union
1834   {
1835     ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3  sInput;
1836     ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
1837   };
1838 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
1839
1840 /****************************************************************************/
1841 // Structures used by EnableYUVTable
1842 /****************************************************************************/
1843 typedef struct _ENABLE_YUV_PARAMETERS
1844 {
1845   UCHAR ucEnable;                     // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
1846   UCHAR ucCRTC;                       // Which CRTC needs this YUV or RGB format
1847   UCHAR ucPadding[2];
1848 }ENABLE_YUV_PARAMETERS;
1849 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
1850
1851 /****************************************************************************/
1852 // Structures used by GetMemoryClockTable
1853 /****************************************************************************/
1854 typedef struct _GET_MEMORY_CLOCK_PARAMETERS
1855 {
1856   ULONG ulReturnMemoryClock;          // current memory speed in 10KHz unit
1857 } GET_MEMORY_CLOCK_PARAMETERS;
1858 #define GET_MEMORY_CLOCK_PS_ALLOCATION  GET_MEMORY_CLOCK_PARAMETERS
1859
1860 /****************************************************************************/
1861 // Structures used by GetEngineClockTable
1862 /****************************************************************************/
1863 typedef struct _GET_ENGINE_CLOCK_PARAMETERS
1864 {
1865   ULONG ulReturnEngineClock;          // current engine speed in 10KHz unit
1866 } GET_ENGINE_CLOCK_PARAMETERS;
1867 #define GET_ENGINE_CLOCK_PS_ALLOCATION  GET_ENGINE_CLOCK_PARAMETERS
1868
1869 /****************************************************************************/
1870 // Following Structures and constant may be obsolete
1871 /****************************************************************************/
1872 //Maxium 8 bytes,the data read in will be placed in the parameter space.
1873 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
1874 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1875 {
1876   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
1877   USHORT    usVRAMAddress;      //Adress in Frame Buffer where to pace raw EDID
1878   USHORT    usStatus;           //When use output: lower byte EDID checksum, high byte hardware status
1879                                 //WHen use input:  lower byte as 'byte to read':currently limited to 128byte or 1byte
1880   UCHAR     ucSlaveAddr;        //Read from which slave
1881   UCHAR     ucLineNumber;       //Read from which HW assisted line
1882 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
1883 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION  READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
1884
1885
1886 #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE                  0
1887 #define  ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES              1
1888 #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK       2
1889 #define  ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK  3
1890 #define  ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK       4
1891
1892 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1893 {
1894   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
1895   USHORT    usByteOffset;       //Write to which byte
1896                                 //Upper portion of usByteOffset is Format of data
1897                                 //1bytePS+offsetPS
1898                                 //2bytesPS+offsetPS
1899                                 //blockID+offsetPS
1900                                 //blockID+offsetID
1901                                 //blockID+counterID+offsetID
1902   UCHAR     ucData;             //PS data1
1903   UCHAR     ucStatus;           //Status byte 1=success, 2=failure, Also is used as PS data2
1904   UCHAR     ucSlaveAddr;        //Write to which slave
1905   UCHAR     ucLineNumber;       //Write from which HW assisted line
1906 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
1907
1908 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION  WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1909
1910 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
1911 {
1912   USHORT    usPrescale;         //Ratio between Engine clock and I2C clock
1913   UCHAR     ucSlaveAddr;        //Write to which slave
1914   UCHAR     ucLineNumber;       //Write from which HW assisted line
1915 }SET_UP_HW_I2C_DATA_PARAMETERS;
1916
1917 /**************************************************************************/
1918 #define SPEED_FAN_CONTROL_PS_ALLOCATION   WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
1919
1920
1921 /****************************************************************************/
1922 // Structures used by PowerConnectorDetectionTable
1923 /****************************************************************************/
1924 typedef struct   _POWER_CONNECTOR_DETECTION_PARAMETERS
1925 {
1926   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
1927    UCHAR   ucPwrBehaviorId;
1928    USHORT   usPwrBudget;                         //how much power currently boot to in unit of watt
1929 }POWER_CONNECTOR_DETECTION_PARAMETERS;
1930
1931 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
1932 {
1933   UCHAR   ucPowerConnectorStatus;      //Used for return value 0: detected, 1:not detected
1934    UCHAR   ucReserved;
1935    USHORT   usPwrBudget;                         //how much power currently boot to in unit of watt
1936   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved;
1937 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
1938
1939
1940 /****************************LVDS SS Command Table Definitions**********************/
1941
1942 /****************************************************************************/
1943 // Structures used by EnableSpreadSpectrumOnPPLLTable
1944 /****************************************************************************/
1945 typedef struct   _ENABLE_LVDS_SS_PARAMETERS
1946 {
1947   USHORT  usSpreadSpectrumPercentage;
1948   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1949   UCHAR   ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
1950   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
1951   UCHAR   ucPadding[3];
1952 }ENABLE_LVDS_SS_PARAMETERS;
1953
1954 //ucTableFormatRevision=1,ucTableContentRevision=2
1955 typedef struct   _ENABLE_LVDS_SS_PARAMETERS_V2
1956 {
1957   USHORT  usSpreadSpectrumPercentage;
1958   UCHAR   ucSpreadSpectrumType;           //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1959   UCHAR   ucSpreadSpectrumStep;           //
1960   UCHAR   ucEnable;                       //ATOM_ENABLE or ATOM_DISABLE
1961   UCHAR   ucSpreadSpectrumDelay;
1962   UCHAR   ucSpreadSpectrumRange;
1963   UCHAR   ucPadding;
1964 }ENABLE_LVDS_SS_PARAMETERS_V2;
1965
1966 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
1967 typedef struct   _ENABLE_SPREAD_SPECTRUM_ON_PPLL
1968 {
1969   USHORT  usSpreadSpectrumPercentage;
1970   UCHAR   ucSpreadSpectrumType;           // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
1971   UCHAR   ucSpreadSpectrumStep;           //
1972   UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
1973   UCHAR   ucSpreadSpectrumDelay;
1974   UCHAR   ucSpreadSpectrumRange;
1975   UCHAR   ucPpll;                                      // ATOM_PPLL1/ATOM_PPLL2
1976 }ENABLE_SPREAD_SPECTRUM_ON_PPLL;
1977
1978  typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
1979 {
1980   USHORT  usSpreadSpectrumPercentage;
1981   UCHAR   ucSpreadSpectrumType;           // Bit[0]: 0-Down Spread,1-Center Spread.
1982                                         // Bit[1]: 1-Ext. 0-Int.
1983                                         // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
1984                                         // Bits[7:4] reserved
1985   UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
1986   USHORT  usSpreadSpectrumAmount;         // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
1987   USHORT  usSpreadSpectrumStep;           // SS_STEP_SIZE_DSFRAC
1988 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
1989
1990 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD      0x00
1991 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD    0x01
1992 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD       0x02
1993 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK    0x0c
1994 #define ATOM_PPLL_SS_TYPE_V2_P1PLL            0x00
1995 #define ATOM_PPLL_SS_TYPE_V2_P2PLL            0x04
1996 #define ATOM_PPLL_SS_TYPE_V2_DCPLL            0x08
1997 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK     0x00FF
1998 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT    0
1999 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK     0x0F00
2000 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT    8
2001
2002 // Used by DCE5.0
2003  typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
2004 {
2005   USHORT  usSpreadSpectrumAmountFrac;   // SS_AMOUNT_DSFRAC New in DCE5.0
2006   UCHAR   ucSpreadSpectrumType;           // Bit[0]: 0-Down Spread,1-Center Spread.
2007                                         // Bit[1]: 1-Ext. 0-Int.
2008                                         // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
2009                                         // Bits[7:4] reserved
2010   UCHAR   ucEnable;                       // ATOM_ENABLE or ATOM_DISABLE
2011   USHORT  usSpreadSpectrumAmount;         // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
2012   USHORT  usSpreadSpectrumStep;           // SS_STEP_SIZE_DSFRAC
2013 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
2014
2015
2016 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD      0x00
2017 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD    0x01
2018 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD       0x02
2019 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK    0x0c
2020 #define ATOM_PPLL_SS_TYPE_V3_P1PLL            0x00
2021 #define ATOM_PPLL_SS_TYPE_V3_P2PLL            0x04
2022 #define ATOM_PPLL_SS_TYPE_V3_DCPLL            0x08
2023 #define ATOM_PPLL_SS_TYPE_V3_P0PLL            ATOM_PPLL_SS_TYPE_V3_DCPLL
2024 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK     0x00FF
2025 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT    0
2026 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK     0x0F00
2027 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT    8
2028
2029 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION  ENABLE_SPREAD_SPECTRUM_ON_PPLL
2030
2031 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
2032 {
2033   PIXEL_CLOCK_PARAMETERS sPCLKInput;
2034   ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
2035 }SET_PIXEL_CLOCK_PS_ALLOCATION;
2036
2037
2038
2039 #define ENABLE_VGA_RENDER_PS_ALLOCATION   SET_PIXEL_CLOCK_PS_ALLOCATION
2040
2041 /****************************************************************************/
2042 // Structures used by ###
2043 /****************************************************************************/
2044 typedef struct   _MEMORY_TRAINING_PARAMETERS
2045 {
2046   ULONG ulTargetMemoryClock;          //In 10Khz unit
2047 }MEMORY_TRAINING_PARAMETERS;
2048 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
2049
2050
2051 typedef struct   _MEMORY_TRAINING_PARAMETERS_V1_2
2052 {
2053   USHORT usMemTrainingMode;
2054   USHORT usReserved;
2055 }MEMORY_TRAINING_PARAMETERS_V1_2;
2056
2057 //usMemTrainingMode
2058 #define NORMAL_MEMORY_TRAINING_MODE       0
2059 #define ENTER_DRAM_SELFREFRESH_MODE       1
2060 #define EXIT_DRAM_SELFRESH_MODE           2
2061
2062 /****************************LVDS and other encoder command table definitions **********************/
2063
2064
2065 /****************************************************************************/
2066 // Structures used by LVDSEncoderControlTable   (Before DEC30)
2067 //                    LVTMAEncoderControlTable  (Before DEC30)
2068 //                    TMDSAEncoderControlTable  (Before DEC30)
2069 /****************************************************************************/
2070 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
2071 {
2072   USHORT usPixelClock;  // in 10KHz; for bios convenient
2073   UCHAR  ucMisc;        // bit0=0: Enable single link
2074                         //     =1: Enable dual link
2075                         // Bit1=0: 666RGB
2076                         //     =1: 888RGB
2077   UCHAR  ucAction;      // 0: turn off encoder
2078                         // 1: setup and turn on encoder
2079 }LVDS_ENCODER_CONTROL_PARAMETERS;
2080
2081 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION  LVDS_ENCODER_CONTROL_PARAMETERS
2082
2083 #define TMDS1_ENCODER_CONTROL_PARAMETERS    LVDS_ENCODER_CONTROL_PARAMETERS
2084 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
2085
2086 #define TMDS2_ENCODER_CONTROL_PARAMETERS    TMDS1_ENCODER_CONTROL_PARAMETERS
2087 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
2088
2089 //ucTableFormatRevision=1,ucTableContentRevision=2
2090 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
2091 {
2092   USHORT usPixelClock;  // in 10KHz; for bios convenient
2093   UCHAR  ucMisc;        // see PANEL_ENCODER_MISC_xx defintions below
2094   UCHAR  ucAction;      // 0: turn off encoder
2095                         // 1: setup and turn on encoder
2096   UCHAR  ucTruncate;    // bit0=0: Disable truncate
2097                         //     =1: Enable truncate
2098                         // bit4=0: 666RGB
2099                         //     =1: 888RGB
2100   UCHAR  ucSpatial;     // bit0=0: Disable spatial dithering
2101                         //     =1: Enable spatial dithering
2102                         // bit4=0: 666RGB
2103                         //     =1: 888RGB
2104   UCHAR  ucTemporal;    // bit0=0: Disable temporal dithering
2105                         //     =1: Enable temporal dithering
2106                         // bit4=0: 666RGB
2107                         //     =1: 888RGB
2108                         // bit5=0: Gray level 2
2109                         //     =1: Gray level 4
2110   UCHAR  ucFRC;         // bit4=0: 25FRC_SEL pattern E
2111                         //     =1: 25FRC_SEL pattern F
2112                         // bit6:5=0: 50FRC_SEL pattern A
2113                         //       =1: 50FRC_SEL pattern B
2114                         //       =2: 50FRC_SEL pattern C
2115                         //       =3: 50FRC_SEL pattern D
2116                         // bit7=0: 75FRC_SEL pattern E
2117                         //     =1: 75FRC_SEL pattern F
2118 }LVDS_ENCODER_CONTROL_PARAMETERS_V2;
2119
2120 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
2121
2122 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2    LVDS_ENCODER_CONTROL_PARAMETERS_V2
2123 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2124
2125 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2    TMDS1_ENCODER_CONTROL_PARAMETERS_V2
2126 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
2127
2128
2129 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3     LVDS_ENCODER_CONTROL_PARAMETERS_V2
2130 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3  LVDS_ENCODER_CONTROL_PARAMETERS_V3
2131
2132 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
2133 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
2134
2135 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3    LVDS_ENCODER_CONTROL_PARAMETERS_V3
2136 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
2137
2138 /****************************************************************************/
2139 // Structures used by ###
2140 /****************************************************************************/
2141 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
2142 {
2143   UCHAR    ucEnable;            // Enable or Disable External TMDS encoder
2144   UCHAR    ucMisc;              // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
2145   UCHAR    ucPadding[2];
2146 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
2147
2148 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
2149 {
2150   ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS    sXTmdsEncoder;
2151   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION   sReserved;     //Caller doesn't need to init this portion
2152 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
2153
2154 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2  LVDS_ENCODER_CONTROL_PARAMETERS_V2
2155 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
2156 {
2157   ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2    sXTmdsEncoder;
2158   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
2159 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
2160
2161 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
2162 {
2163   DIG_ENCODER_CONTROL_PARAMETERS            sDigEncoder;
2164   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2165 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
2166
2167 /****************************************************************************/
2168 // Structures used by DVOEncoderControlTable
2169 /****************************************************************************/
2170 //ucTableFormatRevision=1,ucTableContentRevision=3
2171 //ucDVOConfig:
2172 #define DVO_ENCODER_CONFIG_RATE_SEL                     0x01
2173 #define DVO_ENCODER_CONFIG_DDR_SPEED                  0x00
2174 #define DVO_ENCODER_CONFIG_SDR_SPEED                  0x01
2175 #define DVO_ENCODER_CONFIG_OUTPUT_SEL                  0x0c
2176 #define DVO_ENCODER_CONFIG_LOW12BIT                     0x00
2177 #define DVO_ENCODER_CONFIG_UPPER12BIT                  0x04
2178 #define DVO_ENCODER_CONFIG_24BIT                        0x08
2179
2180 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
2181 {
2182   USHORT usPixelClock;
2183   UCHAR  ucDVOConfig;
2184   UCHAR  ucAction;                                          //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2185   UCHAR  ucReseved[4];
2186 }DVO_ENCODER_CONTROL_PARAMETERS_V3;
2187 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3   DVO_ENCODER_CONTROL_PARAMETERS_V3
2188
2189 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4
2190 {
2191   USHORT usPixelClock;
2192   UCHAR  ucDVOConfig;
2193   UCHAR  ucAction;                                          //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2194   UCHAR  ucBitPerColor;                       //please refer to definition of PANEL_xBIT_PER_COLOR
2195   UCHAR  ucReseved[3];
2196 }DVO_ENCODER_CONTROL_PARAMETERS_V1_4;
2197 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4   DVO_ENCODER_CONTROL_PARAMETERS_V1_4
2198
2199
2200 //ucTableFormatRevision=1
2201 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
2202 // bit1=0: non-coherent mode
2203 //     =1: coherent mode
2204
2205 //==========================================================================================
2206 //Only change is here next time when changing encoder parameter definitions again!
2207 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST     LVDS_ENCODER_CONTROL_PARAMETERS_V3
2208 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST  LVDS_ENCODER_CONTROL_PARAMETERS_LAST
2209
2210 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
2211 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
2212
2213 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST    LVDS_ENCODER_CONTROL_PARAMETERS_V3
2214 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
2215
2216 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST      DVO_ENCODER_CONTROL_PARAMETERS
2217 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST   DVO_ENCODER_CONTROL_PS_ALLOCATION
2218
2219 //==========================================================================================
2220 #define PANEL_ENCODER_MISC_DUAL                0x01
2221 #define PANEL_ENCODER_MISC_COHERENT            0x02
2222 #define   PANEL_ENCODER_MISC_TMDS_LINKB                0x04
2223 #define   PANEL_ENCODER_MISC_HDMI_TYPE                0x08
2224
2225 #define PANEL_ENCODER_ACTION_DISABLE           ATOM_DISABLE
2226 #define PANEL_ENCODER_ACTION_ENABLE            ATOM_ENABLE
2227 #define PANEL_ENCODER_ACTION_COHERENTSEQ       (ATOM_ENABLE+1)
2228
2229 #define PANEL_ENCODER_TRUNCATE_EN              0x01
2230 #define PANEL_ENCODER_TRUNCATE_DEPTH           0x10
2231 #define PANEL_ENCODER_SPATIAL_DITHER_EN        0x01
2232 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH     0x10
2233 #define PANEL_ENCODER_TEMPORAL_DITHER_EN       0x01
2234 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH    0x10
2235 #define PANEL_ENCODER_TEMPORAL_LEVEL_4         0x20
2236 #define PANEL_ENCODER_25FRC_MASK               0x10
2237 #define PANEL_ENCODER_25FRC_E                  0x00
2238 #define PANEL_ENCODER_25FRC_F                  0x10
2239 #define PANEL_ENCODER_50FRC_MASK               0x60
2240 #define PANEL_ENCODER_50FRC_A                  0x00
2241 #define PANEL_ENCODER_50FRC_B                  0x20
2242 #define PANEL_ENCODER_50FRC_C                  0x40
2243 #define PANEL_ENCODER_50FRC_D                  0x60
2244 #define PANEL_ENCODER_75FRC_MASK               0x80
2245 #define PANEL_ENCODER_75FRC_E                  0x00
2246 #define PANEL_ENCODER_75FRC_F                  0x80
2247
2248 /****************************************************************************/
2249 // Structures used by SetVoltageTable
2250 /****************************************************************************/
2251 #define SET_VOLTAGE_TYPE_ASIC_VDDC             1
2252 #define SET_VOLTAGE_TYPE_ASIC_MVDDC            2
2253 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ            3
2254 #define SET_VOLTAGE_TYPE_ASIC_VDDCI            4
2255 #define SET_VOLTAGE_INIT_MODE                  5
2256 #define SET_VOLTAGE_GET_MAX_VOLTAGE            6               //Gets the Max. voltage for the soldered Asic
2257
2258 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE       0x1
2259 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A         0x2
2260 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B         0x4
2261
2262 #define   SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE      0x0
2263 #define   SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL      0x1
2264 #define   SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK     0x2
2265
2266 typedef struct   _SET_VOLTAGE_PARAMETERS
2267 {
2268   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2269   UCHAR    ucVoltageMode;               // To set all, to set source A or source B or ...
2270   UCHAR    ucVoltageIndex;              // An index to tell which voltage level
2271   UCHAR    ucReserved;
2272 }SET_VOLTAGE_PARAMETERS;
2273
2274 typedef struct   _SET_VOLTAGE_PARAMETERS_V2
2275 {
2276   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2277   UCHAR    ucVoltageMode;               // Not used, maybe use for state machine for differen power mode
2278   USHORT   usVoltageLevel;              // real voltage level
2279 }SET_VOLTAGE_PARAMETERS_V2;
2280
2281 // used by both SetVoltageTable v1.3 and v1.4
2282 typedef struct   _SET_VOLTAGE_PARAMETERS_V1_3
2283 {
2284   UCHAR    ucVoltageType;               // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2285   UCHAR    ucVoltageMode;               // Indicate action: Set voltage level
2286   USHORT   usVoltageLevel;              // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
2287 }SET_VOLTAGE_PARAMETERS_V1_3;
2288
2289 //ucVoltageType
2290 #define VOLTAGE_TYPE_VDDC                    1
2291 #define VOLTAGE_TYPE_MVDDC                   2
2292 #define VOLTAGE_TYPE_MVDDQ                   3
2293 #define VOLTAGE_TYPE_VDDCI                   4
2294 #define VOLTAGE_TYPE_VDDGFX                  5
2295 #define VOLTAGE_TYPE_PCC                     6
2296
2297 #define VOLTAGE_TYPE_GENERIC_I2C_1           0x11
2298 #define VOLTAGE_TYPE_GENERIC_I2C_2           0x12
2299 #define VOLTAGE_TYPE_GENERIC_I2C_3           0x13
2300 #define VOLTAGE_TYPE_GENERIC_I2C_4           0x14
2301 #define VOLTAGE_TYPE_GENERIC_I2C_5           0x15
2302 #define VOLTAGE_TYPE_GENERIC_I2C_6           0x16
2303 #define VOLTAGE_TYPE_GENERIC_I2C_7           0x17
2304 #define VOLTAGE_TYPE_GENERIC_I2C_8           0x18
2305 #define VOLTAGE_TYPE_GENERIC_I2C_9           0x19
2306 #define VOLTAGE_TYPE_GENERIC_I2C_10          0x1A
2307
2308 //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
2309 #define ATOM_SET_VOLTAGE                     0        //Set voltage Level
2310 #define ATOM_INIT_VOLTAGE_REGULATOR          3        //Init Regulator
2311 #define ATOM_SET_VOLTAGE_PHASE               4        //Set Vregulator Phase, only for SVID/PVID regulator
2312 #define ATOM_GET_MAX_VOLTAGE                 6        //Get Max Voltage, not used from SetVoltageTable v1.3
2313 #define ATOM_GET_VOLTAGE_LEVEL               6        //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4
2314 #define ATOM_GET_LEAKAGE_ID                  8        //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4
2315
2316 // define vitual voltage id in usVoltageLevel
2317 #define ATOM_VIRTUAL_VOLTAGE_ID0             0xff01
2318 #define ATOM_VIRTUAL_VOLTAGE_ID1             0xff02
2319 #define ATOM_VIRTUAL_VOLTAGE_ID2             0xff03
2320 #define ATOM_VIRTUAL_VOLTAGE_ID3             0xff04
2321 #define ATOM_VIRTUAL_VOLTAGE_ID4             0xff05
2322 #define ATOM_VIRTUAL_VOLTAGE_ID5             0xff06
2323 #define ATOM_VIRTUAL_VOLTAGE_ID6             0xff07
2324 #define ATOM_VIRTUAL_VOLTAGE_ID7             0xff08
2325
2326 typedef struct _SET_VOLTAGE_PS_ALLOCATION
2327 {
2328   SET_VOLTAGE_PARAMETERS sASICSetVoltage;
2329   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
2330 }SET_VOLTAGE_PS_ALLOCATION;
2331
2332 // New Added from SI for GetVoltageInfoTable, input parameter structure
2333 typedef struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
2334 {
2335   UCHAR    ucVoltageType;               // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2336   UCHAR    ucVoltageMode;               // Input: Indicate action: Get voltage info
2337   USHORT   usVoltageLevel;              // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2338   ULONG    ulReserved;
2339 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
2340
2341 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
2342 typedef struct  _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2343 {
2344   ULONG    ulVotlageGpioState;
2345   ULONG    ulVoltageGPioMask;
2346 }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2347
2348 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
2349 typedef struct  _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
2350 {
2351   USHORT   usVoltageLevel;
2352   USHORT   usVoltageId;                                  // Voltage Id programmed in Voltage Regulator
2353   ULONG    ulReseved;
2354 }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
2355
2356 // GetVoltageInfo v1.1 ucVoltageMode
2357 #define ATOM_GET_VOLTAGE_VID                0x00
2358 #define ATOM_GET_VOTLAGE_INIT_SEQ           0x03
2359 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID   0x04
2360 #define ATOM_GET_VOLTAGE_SVID2              0x07        //Get SVI2 Regulator Info
2361
2362 // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
2363 #define   ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
2364 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
2365 #define   ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
2366
2367 #define   ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
2368 #define   ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
2369
2370
2371 // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
2372 typedef struct  _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
2373 {
2374   UCHAR    ucVoltageType;               // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2375   UCHAR    ucVoltageMode;               // Input: Indicate action: Get voltage info
2376   USHORT   usVoltageLevel;              // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
2377   ULONG    ulSCLKFreq;                  // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
2378 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;
2379
2380 // New in GetVoltageInfo v1.2 ucVoltageMode
2381 #define ATOM_GET_VOLTAGE_EVV_VOLTAGE        0x09
2382
2383 // New Added from CI Hawaii for EVV feature
2384 typedef struct  _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
2385 {
2386   USHORT   usVoltageLevel;                               // real voltage level in unit of mv
2387   USHORT   usVoltageId;                                  // Voltage Id programmed in Voltage Regulator
2388   USHORT   usTDP_Current;                                // TDP_Current in unit of  0.01A
2389   USHORT   usTDP_Power;                                  // TDP_Current in unit  of 0.1W
2390 }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;
2391
2392 /****************************************************************************/
2393 // Structures used by TVEncoderControlTable
2394 /****************************************************************************/
2395 typedef struct _TV_ENCODER_CONTROL_PARAMETERS
2396 {
2397   USHORT usPixelClock;                // in 10KHz; for bios convenient
2398   UCHAR  ucTvStandard;                // See definition "ATOM_TV_NTSC ..."
2399   UCHAR  ucAction;                    // 0: turn off encoder
2400                                       // 1: setup and turn on encoder
2401 }TV_ENCODER_CONTROL_PARAMETERS;
2402
2403 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
2404 {
2405   TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
2406   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION    sReserved; // Don't set this one
2407 }TV_ENCODER_CONTROL_PS_ALLOCATION;
2408
2409 //==============================Data Table Portion====================================
2410
2411
2412 /****************************************************************************/
2413 // Structure used in Data.mtb
2414 /****************************************************************************/
2415 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
2416 {
2417   USHORT        UtilityPipeLine;          // Offest for the utility to get parser info,Don't change this position!
2418   USHORT        MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
2419   USHORT        MultimediaConfigInfo;     // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
2420   USHORT        StandardVESA_Timing;      // Only used by Bios
2421   USHORT        FirmwareInfo;             // Shared by various SW components,latest version 1.4
2422   USHORT        PaletteData;              // Only used by BIOS
2423   USHORT        LCD_Info;                 // Shared by various SW components,latest version 1.3, was called LVDS_Info
2424   USHORT        DIGTransmitterInfo;       // Internal used by VBIOS only version 3.1
2425   USHORT        AnalogTV_Info;            // Shared by various SW components,latest version 1.1
2426   USHORT        SupportedDevicesInfo;     // Will be obsolete from R600
2427   USHORT        GPIO_I2C_Info;            // Shared by various SW components,latest version 1.2 will be used from R600
2428   USHORT        VRAM_UsageByFirmware;     // Shared by various SW components,latest version 1.3 will be used from R600
2429   USHORT        GPIO_Pin_LUT;             // Shared by various SW components,latest version 1.1
2430   USHORT        VESA_ToInternalModeLUT;   // Only used by Bios
2431   USHORT        ComponentVideoInfo;       // Shared by various SW components,latest version 2.1 will be used from R600
2432   USHORT        PowerPlayInfo;            // Shared by various SW components,latest version 2.1,new design from R600
2433   USHORT        GPUVirtualizationInfo;    // Will be obsolete from R600
2434   USHORT        SaveRestoreInfo;          // Only used by Bios
2435   USHORT        PPLL_SS_Info;             // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
2436   USHORT        OemInfo;                  // Defined and used by external SW, should be obsolete soon
2437   USHORT        XTMDS_Info;               // Will be obsolete from R600
2438   USHORT        MclkSS_Info;              // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
2439   USHORT        Object_Header;            // Shared by various SW components,latest version 1.1
2440   USHORT        IndirectIOAccess;         // Only used by Bios,this table position can't change at all!!
2441   USHORT        MC_InitParameter;         // Only used by command table
2442   USHORT        ASIC_VDDC_Info;           // Will be obsolete from R600
2443   USHORT        ASIC_InternalSS_Info;     // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
2444   USHORT        TV_VideoMode;             // Only used by command table
2445   USHORT        VRAM_Info;                // Only used by command table, latest version 1.3
2446   USHORT        MemoryTrainingInfo;       // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
2447   USHORT        IntegratedSystemInfo;     // Shared by various SW components
2448   USHORT        ASIC_ProfilingInfo;       // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
2449   USHORT        VoltageObjectInfo;        // Shared by various SW components, latest version 1.1
2450   USHORT        PowerSourceInfo;          // Shared by various SW components, latest versoin 1.1
2451   USHORT              ServiceInfo;
2452 }ATOM_MASTER_LIST_OF_DATA_TABLES;
2453
2454 typedef struct _ATOM_MASTER_DATA_TABLE
2455 {
2456   ATOM_COMMON_TABLE_HEADER sHeader;
2457   ATOM_MASTER_LIST_OF_DATA_TABLES   ListOfDataTables;
2458 }ATOM_MASTER_DATA_TABLE;
2459
2460 // For backward compatible
2461 #define LVDS_Info                LCD_Info
2462 #define DAC_Info                 PaletteData
2463 #define TMDS_Info                DIGTransmitterInfo
2464 #define CompassionateData        GPUVirtualizationInfo
2465
2466 /****************************************************************************/
2467 // Structure used in MultimediaCapabilityInfoTable
2468 /****************************************************************************/
2469 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
2470 {
2471   ATOM_COMMON_TABLE_HEADER sHeader;
2472   ULONG                    ulSignature;      // HW info table signature string "$ATI"
2473   UCHAR                    ucI2C_Type;       // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
2474   UCHAR                    ucTV_OutInfo;     // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2475   UCHAR                    ucVideoPortInfo;  // Provides the video port capabilities
2476   UCHAR                    ucHostPortInfo;   // Provides host port configuration information
2477 }ATOM_MULTIMEDIA_CAPABILITY_INFO;
2478
2479
2480 /****************************************************************************/
2481 // Structure used in MultimediaConfigInfoTable
2482 /****************************************************************************/
2483 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
2484 {
2485   ATOM_COMMON_TABLE_HEADER sHeader;
2486   ULONG                    ulSignature;      // MM info table signature sting "$MMT"
2487   UCHAR                    ucTunerInfo;      // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2488   UCHAR                    ucAudioChipInfo;  // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2489   UCHAR                    ucProductID;      // Defines as OEM ID or ATI board ID dependent on product type setting
2490   UCHAR                    ucMiscInfo1;      // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2491   UCHAR                    ucMiscInfo2;      // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2492   UCHAR                    ucMiscInfo3;      // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2493   UCHAR                    ucMiscInfo4;      // Video Decoder Host Config (2:0) reserved (7:3)
2494   UCHAR                    ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2495   UCHAR                    ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2496   UCHAR                    ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2497   UCHAR                    ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2498   UCHAR                    ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2499 }ATOM_MULTIMEDIA_CONFIG_INFO;
2500
2501
2502 /****************************************************************************/
2503 // Structures used in FirmwareInfoTable
2504 /****************************************************************************/
2505
2506 // usBIOSCapability Defintion:
2507 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
2508 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
2509 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
2510 // Others: Reserved
2511 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED         0x0001
2512 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT            0x0002
2513 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT     0x0004
2514 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT      0x0008      // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
2515 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT      0x0010      // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
2516 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU         0x0020
2517 #define ATOM_BIOS_INFO_WMI_SUPPORT                  0x0040
2518 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM   0x0080
2519 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT          0x0100
2520 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK        0x1E00
2521 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
2522 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE  0x4000
2523 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT  0x0008      // (valid from v2.1 ): =1: memclk ss enable with external ss chip
2524 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT  0x0010      // (valid from v2.1 ): =1: engclk ss enable with external ss chip
2525
2526
2527 #ifndef _H2INC
2528
2529 //Please don't add or expand this bitfield structure below, this one will retire soon.!
2530 typedef struct _ATOM_FIRMWARE_CAPABILITY
2531 {
2532 #if ATOM_BIG_ENDIAN
2533   USHORT Reserved:1;
2534   USHORT SCL2Redefined:1;
2535   USHORT PostWithoutModeSet:1;
2536   USHORT HyperMemory_Size:4;
2537   USHORT HyperMemory_Support:1;
2538   USHORT PPMode_Assigned:1;
2539   USHORT WMI_SUPPORT:1;
2540   USHORT GPUControlsBL:1;
2541   USHORT EngineClockSS_Support:1;
2542   USHORT MemoryClockSS_Support:1;
2543   USHORT ExtendedDesktopSupport:1;
2544   USHORT DualCRTC_Support:1;
2545   USHORT FirmwarePosted:1;
2546 #else
2547   USHORT FirmwarePosted:1;
2548   USHORT DualCRTC_Support:1;
2549   USHORT ExtendedDesktopSupport:1;
2550   USHORT MemoryClockSS_Support:1;
2551   USHORT EngineClockSS_Support:1;
2552   USHORT GPUControlsBL:1;
2553   USHORT WMI_SUPPORT:1;
2554   USHORT PPMode_Assigned:1;
2555   USHORT HyperMemory_Support:1;
2556   USHORT HyperMemory_Size:4;
2557   USHORT PostWithoutModeSet:1;
2558   USHORT SCL2Redefined:1;
2559   USHORT Reserved:1;
2560 #endif
2561 }ATOM_FIRMWARE_CAPABILITY;
2562
2563 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2564 {
2565   ATOM_FIRMWARE_CAPABILITY sbfAccess;
2566   USHORT                   susAccess;
2567 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
2568
2569 #else
2570
2571 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
2572 {
2573   USHORT                   susAccess;
2574 }ATOM_FIRMWARE_CAPABILITY_ACCESS;
2575
2576 #endif
2577
2578 typedef struct _ATOM_FIRMWARE_INFO
2579 {
2580   ATOM_COMMON_TABLE_HEADER        sHeader;
2581   ULONG                           ulFirmwareRevision;
2582   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2583   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2584   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
2585   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
2586   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
2587   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
2588   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2589   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
2590   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
2591   UCHAR                           ucASICMaxTemperature;
2592   UCHAR                           ucPadding[3];               //Don't use them
2593   ULONG                           aulReservedForBIOS[3];      //Don't use them
2594   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
2595   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
2596   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
2597   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
2598   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
2599   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
2600   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
2601   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2602   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2603   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit, the definitions above can't change!!!
2604   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2605   USHORT                          usReferenceClock;           //In 10Khz unit
2606   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
2607   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
2608   UCHAR                           ucDesign_ID;                //Indicate what is the board design
2609   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2610 }ATOM_FIRMWARE_INFO;
2611
2612 typedef struct _ATOM_FIRMWARE_INFO_V1_2
2613 {
2614   ATOM_COMMON_TABLE_HEADER        sHeader;
2615   ULONG                           ulFirmwareRevision;
2616   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2617   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2618   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
2619   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
2620   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
2621   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
2622   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2623   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
2624   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
2625   UCHAR                           ucASICMaxTemperature;
2626   UCHAR                           ucMinAllowedBL_Level;
2627   UCHAR                           ucPadding[2];               //Don't use them
2628   ULONG                           aulReservedForBIOS[2];      //Don't use them
2629   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
2630   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
2631   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
2632   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
2633   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
2634   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
2635   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
2636   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
2637   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2638   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2639   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2640   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2641   USHORT                          usReferenceClock;           //In 10Khz unit
2642   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
2643   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
2644   UCHAR                           ucDesign_ID;                //Indicate what is the board design
2645   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2646 }ATOM_FIRMWARE_INFO_V1_2;
2647
2648 typedef struct _ATOM_FIRMWARE_INFO_V1_3
2649 {
2650   ATOM_COMMON_TABLE_HEADER        sHeader;
2651   ULONG                           ulFirmwareRevision;
2652   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2653   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2654   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
2655   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
2656   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
2657   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
2658   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2659   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
2660   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
2661   UCHAR                           ucASICMaxTemperature;
2662   UCHAR                           ucMinAllowedBL_Level;
2663   UCHAR                           ucPadding[2];               //Don't use them
2664   ULONG                           aulReservedForBIOS;         //Don't use them
2665   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
2666   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
2667   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
2668   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
2669   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
2670   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
2671   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
2672   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
2673   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
2674   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2675   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2676   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2677   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2678   USHORT                          usReferenceClock;           //In 10Khz unit
2679   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
2680   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
2681   UCHAR                           ucDesign_ID;                //Indicate what is the board design
2682   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2683 }ATOM_FIRMWARE_INFO_V1_3;
2684
2685 typedef struct _ATOM_FIRMWARE_INFO_V1_4
2686 {
2687   ATOM_COMMON_TABLE_HEADER        sHeader;
2688   ULONG                           ulFirmwareRevision;
2689   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2690   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2691   ULONG                           ulDriverTargetEngineClock;  //In 10Khz unit
2692   ULONG                           ulDriverTargetMemoryClock;  //In 10Khz unit
2693   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
2694   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
2695   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2696   ULONG                           ulASICMaxEngineClock;       //In 10Khz unit
2697   ULONG                           ulASICMaxMemoryClock;       //In 10Khz unit
2698   UCHAR                           ucASICMaxTemperature;
2699   UCHAR                           ucMinAllowedBL_Level;
2700   USHORT                          usBootUpVDDCVoltage;        //In MV unit
2701   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
2702   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
2703   ULONG                           ul3DAccelerationEngineClock;//In 10Khz unit
2704   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
2705   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
2706   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
2707   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
2708   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
2709   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
2710   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
2711   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
2712   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2713   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2714   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2715   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2716   USHORT                          usReferenceClock;           //In 10Khz unit
2717   USHORT                          usPM_RTS_Location;          //RTS PM4 starting location in ROM in 1Kb unit
2718   UCHAR                           ucPM_RTS_StreamSize;        //RTS PM4 packets in Kb unit
2719   UCHAR                           ucDesign_ID;                //Indicate what is the board design
2720   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2721 }ATOM_FIRMWARE_INFO_V1_4;
2722
2723 //the structure below to be used from Cypress
2724 typedef struct _ATOM_FIRMWARE_INFO_V2_1
2725 {
2726   ATOM_COMMON_TABLE_HEADER        sHeader;
2727   ULONG                           ulFirmwareRevision;
2728   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2729   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2730   ULONG                           ulReserved1;
2731   ULONG                           ulReserved2;
2732   ULONG                           ulMaxEngineClockPLL_Output; //In 10Khz unit
2733   ULONG                           ulMaxMemoryClockPLL_Output; //In 10Khz unit
2734   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2735   ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock
2736   ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit
2737   UCHAR                           ucReserved1;                //Was ucASICMaxTemperature;
2738   UCHAR                           ucMinAllowedBL_Level;
2739   USHORT                          usBootUpVDDCVoltage;        //In MV unit
2740   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
2741   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
2742   ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
2743   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
2744   USHORT                          usMinEngineClockPLL_Input;  //In 10Khz unit
2745   USHORT                          usMaxEngineClockPLL_Input;  //In 10Khz unit
2746   USHORT                          usMinEngineClockPLL_Output; //In 10Khz unit
2747   USHORT                          usMinMemoryClockPLL_Input;  //In 10Khz unit
2748   USHORT                          usMaxMemoryClockPLL_Input;  //In 10Khz unit
2749   USHORT                          usMinMemoryClockPLL_Output; //In 10Khz unit
2750   USHORT                          usMaxPixelClock;            //In 10Khz unit, Max.  Pclk
2751   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2752   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2753   USHORT                          usMinPixelClockPLL_Output;  //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
2754   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2755   USHORT                          usCoreReferenceClock;       //In 10Khz unit
2756   USHORT                          usMemoryReferenceClock;     //In 10Khz unit
2757   USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2758   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2759   UCHAR                           ucReserved4[3];
2760
2761 }ATOM_FIRMWARE_INFO_V2_1;
2762
2763 //the structure below to be used from NI
2764 //ucTableFormatRevision=2
2765 //ucTableContentRevision=2
2766
2767 typedef struct _PRODUCT_BRANDING
2768 {
2769     UCHAR     ucEMBEDDED_CAP:2;          // Bit[1:0] Embedded feature level
2770     UCHAR     ucReserved:2;              // Bit[3:2] Reserved
2771     UCHAR     ucBRANDING_ID:4;           // Bit[7:4] Branding ID
2772 }PRODUCT_BRANDING;
2773
2774 typedef struct _ATOM_FIRMWARE_INFO_V2_2
2775 {
2776   ATOM_COMMON_TABLE_HEADER        sHeader;
2777   ULONG                           ulFirmwareRevision;
2778   ULONG                           ulDefaultEngineClock;       //In 10Khz unit
2779   ULONG                           ulDefaultMemoryClock;       //In 10Khz unit
2780   ULONG                           ulSPLL_OutputFreq;          //In 10Khz unit
2781   ULONG                           ulGPUPLL_OutputFreq;        //In 10Khz unit
2782   ULONG                           ulReserved1;                //Was ulMaxEngineClockPLL_Output; //In 10Khz unit*
2783   ULONG                           ulReserved2;                //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit*
2784   ULONG                           ulMaxPixelClockPLL_Output;  //In 10Khz unit
2785   ULONG                           ulBinaryAlteredInfo;        //Was ulASICMaxEngineClock  ?
2786   ULONG                           ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage.
2787   UCHAR                           ucReserved3;                //Was ucASICMaxTemperature;
2788   UCHAR                           ucMinAllowedBL_Level;
2789   USHORT                          usBootUpVDDCVoltage;        //In MV unit
2790   USHORT                          usLcdMinPixelClockPLL_Output; // In MHz unit
2791   USHORT                          usLcdMaxPixelClockPLL_Output; // In MHz unit
2792   ULONG                           ulReserved4;                //Was ulAsicMaximumVoltage
2793   ULONG                           ulMinPixelClockPLL_Output;  //In 10Khz unit
2794   UCHAR                           ucRemoteDisplayConfig;
2795   UCHAR                           ucReserved5[3];             //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
2796   ULONG                           ulReserved6;                //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input
2797   ULONG                           ulReserved7;                //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output
2798   USHORT                          usReserved11;               //Was usMaxPixelClock;  //In 10Khz unit, Max.  Pclk used only for DAC
2799   USHORT                          usMinPixelClockPLL_Input;   //In 10Khz unit
2800   USHORT                          usMaxPixelClockPLL_Input;   //In 10Khz unit
2801   USHORT                          usBootUpVDDCIVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
2802   ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
2803   USHORT                          usCoreReferenceClock;       //In 10Khz unit
2804   USHORT                          usMemoryReferenceClock;     //In 10Khz unit
2805   USHORT                          usUniphyDPModeExtClkFreq;   //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock
2806   UCHAR                           ucMemoryModule_ID;          //Indicate what is the board design
2807   UCHAR                           ucCoolingSolution_ID;       //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION]
2808   PRODUCT_BRANDING                ucProductBranding;          // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level.
2809   UCHAR                           ucReserved9;
2810   USHORT                          usBootUpMVDDCVoltage;       //In unit of mv; Was usMinPixelClockPLL_Output;
2811   USHORT                          usBootUpVDDGFXVoltage;      //In unit of mv;
2812   ULONG                           ulReserved10[3];            // New added comparing to previous version
2813 }ATOM_FIRMWARE_INFO_V2_2;
2814
2815 #define ATOM_FIRMWARE_INFO_LAST  ATOM_FIRMWARE_INFO_V2_2
2816
2817
2818 // definition of ucRemoteDisplayConfig
2819 #define REMOTE_DISPLAY_DISABLE                   0x00
2820 #define REMOTE_DISPLAY_ENABLE                    0x01
2821
2822 /****************************************************************************/
2823 // Structures used in IntegratedSystemInfoTable
2824 /****************************************************************************/
2825 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN      0x2
2826 #define IGP_CAP_FLAG_AC_CARD               0x4
2827 #define IGP_CAP_FLAG_SDVO_CARD             0x8
2828 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE     0x10
2829
2830 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO
2831 {
2832   ATOM_COMMON_TABLE_HEADER        sHeader;
2833   ULONG                           ulBootUpEngineClock;          //in 10kHz unit
2834   ULONG                           ulBootUpMemoryClock;          //in 10kHz unit
2835   ULONG                           ulMaxSystemMemoryClock;       //in 10kHz unit
2836   ULONG                           ulMinSystemMemoryClock;       //in 10kHz unit
2837   UCHAR                           ucNumberOfCyclesInPeriodHi;
2838   UCHAR                           ucLCDTimingSel;             //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
2839   USHORT                          usReserved1;
2840   USHORT                          usInterNBVoltageLow;        //An intermidiate PMW value to set the voltage
2841   USHORT                          usInterNBVoltageHigh;       //Another intermidiate PMW value to set the voltage
2842   ULONG                           ulReserved[2];
2843
2844   USHORT                          usFSBClock;                     //In MHz unit
2845   USHORT                          usCapabilityFlag;              //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable
2846                                                                               //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card
2847                                                               //Bit[4]==1: P/2 mode, ==0: P/1 mode
2848   USHORT                          usPCIENBCfgReg7;                //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal
2849   USHORT                          usK8MemoryClock;            //in MHz unit
2850   USHORT                          usK8SyncStartDelay;         //in 0.01 us unit
2851   USHORT                          usK8DataReturnTime;         //in 0.01 us unit
2852   UCHAR                           ucMaxNBVoltage;
2853   UCHAR                           ucMinNBVoltage;
2854   UCHAR                           ucMemoryType;                     //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
2855   UCHAR                           ucNumberOfCyclesInPeriod;      //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
2856   UCHAR                           ucStartingPWM_HighTime;     //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
2857   UCHAR                           ucHTLinkWidth;              //16 bit vs. 8 bit
2858   UCHAR                           ucMaxNBVoltageHigh;
2859   UCHAR                           ucMinNBVoltageHigh;
2860 }ATOM_INTEGRATED_SYSTEM_INFO;
2861
2862 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO
2863 ulBootUpMemoryClock:    For Intel IGP,it's the UMA system memory clock
2864                         For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock
2865 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2866                         For AMD IGP,for now this can be 0
2867 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0
2868                         For AMD IGP,for now this can be 0
2869
2870 usFSBClock:             For Intel IGP,it's FSB Freq
2871                         For AMD IGP,it's HT Link Speed
2872
2873 usK8MemoryClock:        For AMD IGP only. For RevF CPU, set it to 200
2874 usK8SyncStartDelay:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
2875 usK8DataReturnTime:     For AMD IGP only. Memory access latency in K8, required for watermark calculation
2876
2877 VC:Voltage Control
2878 ucMaxNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2879 ucMinNBVoltage:         Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2880
2881 ucNumberOfCyclesInPeriod:   Indicate how many cycles when PWM duty is 100%. low 8 bits of the value.
2882 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0
2883
2884 ucMaxNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of  the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all.
2885 ucMinNBVoltageHigh:     Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all.
2886
2887
2888 usInterNBVoltageLow:    Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all.
2889 usInterNBVoltageHigh:   Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all.
2890 */
2891
2892
2893 /*
2894 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST;
2895 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need.
2896 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries.
2897
2898 SW components can access the IGP system infor structure in the same way as before
2899 */
2900
2901
2902 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
2903 {
2904   ATOM_COMMON_TABLE_HEADER   sHeader;
2905   ULONG                      ulBootUpEngineClock;       //in 10kHz unit
2906   ULONG                      ulReserved1[2];            //must be 0x0 for the reserved
2907   ULONG                      ulBootUpUMAClock;          //in 10kHz unit
2908   ULONG                      ulBootUpSidePortClock;     //in 10kHz unit
2909   ULONG                      ulMinSidePortClock;        //in 10kHz unit
2910   ULONG                      ulReserved2[6];            //must be 0x0 for the reserved
2911   ULONG                      ulSystemConfig;            //see explanation below
2912   ULONG                      ulBootUpReqDisplayVector;
2913   ULONG                      ulOtherDisplayMisc;
2914   ULONG                      ulDDISlot1Config;
2915   ULONG                      ulDDISlot2Config;
2916   UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
2917   UCHAR                      ucUMAChannelNumber;
2918   UCHAR                      ucDockingPinBit;
2919   UCHAR                      ucDockingPinPolarity;
2920   ULONG                      ulDockingPinCFGInfo;
2921   ULONG                      ulCPUCapInfo;
2922   USHORT                     usNumberOfCyclesInPeriod;
2923   USHORT                     usMaxNBVoltage;
2924   USHORT                     usMinNBVoltage;
2925   USHORT                     usBootUpNBVoltage;
2926   ULONG                      ulHTLinkFreq;              //in 10Khz
2927   USHORT                     usMinHTLinkWidth;
2928   USHORT                     usMaxHTLinkWidth;
2929   USHORT                     usUMASyncStartDelay;
2930   USHORT                     usUMADataReturnTime;
2931   USHORT                     usLinkStatusZeroTime;
2932   USHORT                     usDACEfuse;            //for storing badgap value (for RS880 only)
2933   ULONG                      ulHighVoltageHTLinkFreq;     // in 10Khz
2934   ULONG                      ulLowVoltageHTLinkFreq;      // in 10Khz
2935   USHORT                     usMaxUpStreamHTLinkWidth;
2936   USHORT                     usMaxDownStreamHTLinkWidth;
2937   USHORT                     usMinUpStreamHTLinkWidth;
2938   USHORT                     usMinDownStreamHTLinkWidth;
2939   USHORT                     usFirmwareVersion;         //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW.
2940   USHORT                     usFullT0Time;             // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us.
2941   ULONG                      ulReserved3[96];          //must be 0x0
2942 }ATOM_INTEGRATED_SYSTEM_INFO_V2;
2943
2944 /*
2945 ulBootUpEngineClock:   Boot-up Engine Clock in 10Khz;
2946 ulBootUpUMAClock:      Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present
2947 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock
2948
2949 ulSystemConfig:
2950 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode;
2951 Bit[1]=1: system boots up at AMD overdrived state or user customized  mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state
2952       =0: system boots up at driver control state. Power state depends on PowerPlay table.
2953 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used.
2954 Bit[3]=1: Only one power state(Performance) will be supported.
2955       =0: Multiple power states supported from PowerPlay table.
2956 Bit[4]=1: CLMC is supported and enabled on current system.
2957       =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface.
2958 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement.
2959       =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied.
2960 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored.
2961       =0: Voltage settings is determined by powerplay table.
2962 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue.
2963       =0: Enable CLMC as regular mode, CDLD and CILR will be enabled.
2964 Bit[8]=1: CDLF is supported and enabled on current system.
2965       =0: CDLF is not supported or enabled on current system.
2966 Bit[9]=1: DLL Shut Down feature is enabled on current system.
2967       =0: DLL Shut Down feature is not enabled or supported on current system.
2968
2969 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions.
2970
2971 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion;
2972                        [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition;
2973
2974 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design).
2975       [3:0]  - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12)
2976          [7:4]  - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12)
2977       When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time.
2978       in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example:
2979       one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2.
2980
2981          [15:8] - Lane configuration attribute;
2982       [23:16]- Connector type, possible value:
2983                CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
2984                CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
2985                CONNECTOR_OBJECT_ID_HDMI_TYPE_A
2986                CONNECTOR_OBJECT_ID_DISPLAYPORT
2987                CONNECTOR_OBJECT_ID_eDP
2988          [31:24]- Reserved
2989
2990 ulDDISlot2Config: Same as Slot1.
2991 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC.
2992 For IGP, Hypermemory is the only memory type showed in CCC.
2993
2994 ucUMAChannelNumber:  how many channels for the UMA;
2995
2996 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin
2997 ucDockingPinBit:     which bit in this register to read the pin status;
2998 ucDockingPinPolarity:Polarity of the pin when docked;
2999
3000 ulCPUCapInfo:        [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0
3001
3002 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%.
3003
3004 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode.
3005 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode.
3006                     GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0
3007                     PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1
3008                     GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE
3009
3010 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value.
3011
3012
3013 ulHTLinkFreq:       Bootup HT link Frequency in 10Khz.
3014 usMinHTLinkWidth:   Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth.
3015                     If CDLW enabled, both upstream and downstream width should be the same during bootup.
3016 usMaxHTLinkWidth:   Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth.
3017                     If CDLW enabled, both upstream and downstream width should be the same during bootup.
3018
3019 usUMASyncStartDelay: Memory access latency, required for watermark calculation
3020 usUMADataReturnTime: Memory access latency, required for watermark calculation
3021 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us
3022 for Griffin or Greyhound. SBIOS needs to convert to actual time by:
3023                      if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us)
3024                      if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us)
3025                      if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us)
3026                      if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us)
3027
3028 ulHighVoltageHTLinkFreq:     HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0.
3029                              This must be less than or equal to ulHTLinkFreq(bootup frequency).
3030 ulLowVoltageHTLinkFreq:      HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0.
3031                              This must be less than or equal to ulHighVoltageHTLinkFreq.
3032
3033 usMaxUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now.
3034 usMaxDownStreamHTLinkWidth:  same as above.
3035 usMinUpStreamHTLinkWidth:    Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now.
3036 usMinDownStreamHTLinkWidth:  same as above.
3037 */
3038
3039 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo  - CPU type definition
3040 #define    INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU             0
3041 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN        1
3042 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND      2
3043 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__K8             3
3044 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH        4
3045 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI         5
3046
3047 #define    INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE       INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI    // this deff reflects max defined CPU code
3048
3049 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE                 0x00000001
3050 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE             0x00000002
3051 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE                  0x00000004
3052 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY         0x00000008
3053 #define SYSTEM_CONFIG_CLMC_ENABLED                        0x00000010
3054 #define SYSTEM_CONFIG_CDLW_ENABLED                        0x00000020
3055 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED              0x00000040
3056 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED            0x00000080
3057 #define SYSTEM_CONFIG_CDLF_ENABLED                        0x00000100
3058 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED                0x00000200
3059
3060 #define IGP_DDI_SLOT_LANE_CONFIG_MASK                     0x000000FF
3061
3062 #define b0IGP_DDI_SLOT_LANE_MAP_MASK                      0x0F
3063 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK              0xF0
3064 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3                    0x01
3065 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7                    0x02
3066 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11                   0x04
3067 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15                  0x08
3068
3069 #define IGP_DDI_SLOT_ATTRIBUTE_MASK                       0x0000FF00
3070 #define IGP_DDI_SLOT_CONFIG_REVERSED                      0x00000100
3071 #define b1IGP_DDI_SLOT_CONFIG_REVERSED                    0x01
3072
3073 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK                  0x00FF0000
3074
3075 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR
3076 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5
3077 {
3078   ATOM_COMMON_TABLE_HEADER   sHeader;
3079   ULONG                        ulBootUpEngineClock;       //in 10kHz unit
3080   ULONG                      ulDentistVCOFreq;          //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK.
3081   ULONG                      ulLClockFreq;              //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge
3082   ULONG                        ulBootUpUMAClock;          //in 10kHz unit
3083   ULONG                      ulReserved1[8];            //must be 0x0 for the reserved
3084   ULONG                      ulBootUpReqDisplayVector;
3085   ULONG                      ulOtherDisplayMisc;
3086   ULONG                      ulReserved2[4];            //must be 0x0 for the reserved
3087   ULONG                      ulSystemConfig;            //TBD
3088   ULONG                      ulCPUCapInfo;              //TBD
3089   USHORT                     usMaxNBVoltage;            //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
3090   USHORT                     usMinNBVoltage;            //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse;
3091   USHORT                     usBootUpNBVoltage;         //boot up NB voltage
3092   UCHAR                      ucHtcTmpLmt;               //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
3093   UCHAR                      ucTjOffset;                //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
3094   ULONG                      ulReserved3[4];            //must be 0x0 for the reserved
3095   ULONG                      ulDDISlot1Config;          //see above ulDDISlot1Config definition
3096   ULONG                      ulDDISlot2Config;
3097   ULONG                      ulDDISlot3Config;
3098   ULONG                      ulDDISlot4Config;
3099   ULONG                      ulReserved4[4];            //must be 0x0 for the reserved
3100   UCHAR                      ucMemoryType;              //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
3101   UCHAR                      ucUMAChannelNumber;
3102   USHORT                     usReserved;
3103   ULONG                      ulReserved5[4];            //must be 0x0 for the reserved
3104   ULONG                      ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
3105   ULONG                      ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
3106   ULONG                      ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
3107   ULONG                      ulReserved6[61];           //must be 0x0
3108 }ATOM_INTEGRATED_SYSTEM_INFO_V5;
3109
3110
3111
3112 /****************************************************************************/
3113 // Structure used in GPUVirtualizationInfoTable
3114 /****************************************************************************/
3115 typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_1
3116 {
3117   ATOM_COMMON_TABLE_HEADER   sHeader;
3118   ULONG ulMCUcodeRomStartAddr;
3119   ULONG ulMCUcodeLength;
3120   ULONG ulSMCUcodeRomStartAddr;
3121   ULONG ulSMCUcodeLength;
3122   ULONG ulRLCVUcodeRomStartAddr;
3123   ULONG ulRLCVUcodeLength;
3124   ULONG ulTOCUcodeStartAddr;
3125   ULONG ulTOCUcodeLength;
3126   ULONG ulSMCPatchTableStartAddr;
3127   ULONG ulSmcPatchTableLength;
3128   ULONG ulSystemFlag;
3129 }ATOM_GPU_VIRTUALIZATION_INFO_V2_1;
3130
3131
3132 #define ATOM_CRT_INT_ENCODER1_INDEX                       0x00000000
3133 #define ATOM_LCD_INT_ENCODER1_INDEX                       0x00000001
3134 #define ATOM_TV_INT_ENCODER1_INDEX                        0x00000002
3135 #define ATOM_DFP_INT_ENCODER1_INDEX                       0x00000003
3136 #define ATOM_CRT_INT_ENCODER2_INDEX                       0x00000004
3137 #define ATOM_LCD_EXT_ENCODER1_INDEX                       0x00000005
3138 #define ATOM_TV_EXT_ENCODER1_INDEX                        0x00000006
3139 #define ATOM_DFP_EXT_ENCODER1_INDEX                       0x00000007
3140 #define ATOM_CV_INT_ENCODER1_INDEX                        0x00000008
3141 #define ATOM_DFP_INT_ENCODER2_INDEX                       0x00000009
3142 #define ATOM_CRT_EXT_ENCODER1_INDEX                       0x0000000A
3143 #define ATOM_CV_EXT_ENCODER1_INDEX                        0x0000000B
3144 #define ATOM_DFP_INT_ENCODER3_INDEX                       0x0000000C
3145 #define ATOM_DFP_INT_ENCODER4_INDEX                       0x0000000D
3146
3147 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable
3148 #define ASIC_INT_DAC1_ENCODER_ID                                     0x00
3149 #define ASIC_INT_TV_ENCODER_ID                                       0x02
3150 #define ASIC_INT_DIG1_ENCODER_ID                                     0x03
3151 #define ASIC_INT_DAC2_ENCODER_ID                                     0x04
3152 #define ASIC_EXT_TV_ENCODER_ID                                       0x06
3153 #define ASIC_INT_DVO_ENCODER_ID                                      0x07
3154 #define ASIC_INT_DIG2_ENCODER_ID                                     0x09
3155 #define ASIC_EXT_DIG_ENCODER_ID                                      0x05
3156 #define ASIC_EXT_DIG2_ENCODER_ID                                     0x08
3157 #define ASIC_INT_DIG3_ENCODER_ID                                     0x0a
3158 #define ASIC_INT_DIG4_ENCODER_ID                                     0x0b
3159 #define ASIC_INT_DIG5_ENCODER_ID                                     0x0c
3160 #define ASIC_INT_DIG6_ENCODER_ID                                     0x0d
3161 #define ASIC_INT_DIG7_ENCODER_ID                                     0x0e
3162
3163 //define Encoder attribute
3164 #define ATOM_ANALOG_ENCODER                                                0
3165 #define ATOM_DIGITAL_ENCODER                                             1
3166 #define ATOM_DP_ENCODER                                                   2
3167
3168 #define ATOM_ENCODER_ENUM_MASK                            0x70
3169 #define ATOM_ENCODER_ENUM_ID1                             0x00
3170 #define ATOM_ENCODER_ENUM_ID2                             0x10
3171 #define ATOM_ENCODER_ENUM_ID3                             0x20
3172 #define ATOM_ENCODER_ENUM_ID4                             0x30
3173 #define ATOM_ENCODER_ENUM_ID5                             0x40
3174 #define ATOM_ENCODER_ENUM_ID6                             0x50
3175
3176 #define ATOM_DEVICE_CRT1_INDEX                            0x00000000
3177 #define ATOM_DEVICE_LCD1_INDEX                            0x00000001
3178 #define ATOM_DEVICE_TV1_INDEX                             0x00000002
3179 #define ATOM_DEVICE_DFP1_INDEX                            0x00000003
3180 #define ATOM_DEVICE_CRT2_INDEX                            0x00000004
3181 #define ATOM_DEVICE_LCD2_INDEX                            0x00000005
3182 #define ATOM_DEVICE_DFP6_INDEX                            0x00000006
3183 #define ATOM_DEVICE_DFP2_INDEX                            0x00000007
3184 #define ATOM_DEVICE_CV_INDEX                              0x00000008
3185 #define ATOM_DEVICE_DFP3_INDEX                            0x00000009
3186 #define ATOM_DEVICE_DFP4_INDEX                            0x0000000A
3187 #define ATOM_DEVICE_DFP5_INDEX                            0x0000000B
3188
3189 #define ATOM_DEVICE_RESERVEDC_INDEX                       0x0000000C
3190 #define ATOM_DEVICE_RESERVEDD_INDEX                       0x0000000D
3191 #define ATOM_DEVICE_RESERVEDE_INDEX                       0x0000000E
3192 #define ATOM_DEVICE_RESERVEDF_INDEX                       0x0000000F
3193 #define ATOM_MAX_SUPPORTED_DEVICE_INFO                    (ATOM_DEVICE_DFP3_INDEX+1)
3194 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2                  ATOM_MAX_SUPPORTED_DEVICE_INFO
3195 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3                  (ATOM_DEVICE_DFP5_INDEX + 1 )
3196
3197 #define ATOM_MAX_SUPPORTED_DEVICE                         (ATOM_DEVICE_RESERVEDF_INDEX+1)
3198
3199 #define ATOM_DEVICE_CRT1_SUPPORT                          (0x1L << ATOM_DEVICE_CRT1_INDEX )
3200 #define ATOM_DEVICE_LCD1_SUPPORT                          (0x1L << ATOM_DEVICE_LCD1_INDEX )
3201 #define ATOM_DEVICE_TV1_SUPPORT                           (0x1L << ATOM_DEVICE_TV1_INDEX  )
3202 #define ATOM_DEVICE_DFP1_SUPPORT                          (0x1L << ATOM_DEVICE_DFP1_INDEX )
3203 #define ATOM_DEVICE_CRT2_SUPPORT                          (0x1L << ATOM_DEVICE_CRT2_INDEX )
3204 #define ATOM_DEVICE_LCD2_SUPPORT                          (0x1L << ATOM_DEVICE_LCD2_INDEX )
3205 #define ATOM_DEVICE_DFP6_SUPPORT                          (0x1L << ATOM_DEVICE_DFP6_INDEX )
3206 #define ATOM_DEVICE_DFP2_SUPPORT                          (0x1L << ATOM_DEVICE_DFP2_INDEX )
3207 #define ATOM_DEVICE_CV_SUPPORT                            (0x1L << ATOM_DEVICE_CV_INDEX   )
3208 #define ATOM_DEVICE_DFP3_SUPPORT                          (0x1L << ATOM_DEVICE_DFP3_INDEX )
3209 #define ATOM_DEVICE_DFP4_SUPPORT                          (0x1L << ATOM_DEVICE_DFP4_INDEX )
3210 #define ATOM_DEVICE_DFP5_SUPPORT                          (0x1L << ATOM_DEVICE_DFP5_INDEX )
3211
3212
3213 #define ATOM_DEVICE_CRT_SUPPORT                           (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT)
3214 #define ATOM_DEVICE_DFP_SUPPORT                           (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT |  ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT)
3215 #define ATOM_DEVICE_TV_SUPPORT                            ATOM_DEVICE_TV1_SUPPORT
3216 #define ATOM_DEVICE_LCD_SUPPORT                           (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT)
3217
3218 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK                   0x000000F0
3219 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT                  0x00000004
3220 #define ATOM_DEVICE_CONNECTOR_VGA                         0x00000001
3221 #define ATOM_DEVICE_CONNECTOR_DVI_I                       0x00000002
3222 #define ATOM_DEVICE_CONNECTOR_DVI_D                       0x00000003
3223 #define ATOM_DEVICE_CONNECTOR_DVI_A                       0x00000004
3224 #define ATOM_DEVICE_CONNECTOR_SVIDEO                      0x00000005
3225 #define ATOM_DEVICE_CONNECTOR_COMPOSITE                   0x00000006
3226 #define ATOM_DEVICE_CONNECTOR_LVDS                        0x00000007
3227 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK                   0x00000008
3228 #define ATOM_DEVICE_CONNECTOR_SCART                       0x00000009
3229 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A                 0x0000000A
3230 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B                 0x0000000B
3231 #define ATOM_DEVICE_CONNECTOR_CASE_1                      0x0000000E
3232 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT                 0x0000000F
3233
3234
3235 #define ATOM_DEVICE_DAC_INFO_MASK                         0x0000000F
3236 #define ATOM_DEVICE_DAC_INFO_SHIFT                        0x00000000
3237 #define ATOM_DEVICE_DAC_INFO_NODAC                        0x00000000
3238 #define ATOM_DEVICE_DAC_INFO_DACA                         0x00000001
3239 #define ATOM_DEVICE_DAC_INFO_DACB                         0x00000002
3240 #define ATOM_DEVICE_DAC_INFO_EXDAC                        0x00000003
3241
3242 #define ATOM_DEVICE_I2C_ID_NOI2C                          0x00000000
3243
3244 #define ATOM_DEVICE_I2C_LINEMUX_MASK                      0x0000000F
3245 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT                     0x00000000
3246
3247 #define ATOM_DEVICE_I2C_ID_MASK                           0x00000070
3248 #define ATOM_DEVICE_I2C_ID_SHIFT                          0x00000004
3249 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE              0x00000001
3250 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE                  0x00000002
3251 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE                0x00000003    //For IGP RS600
3252 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL                 0x00000004    //For IGP RS690
3253
3254 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK                 0x00000080
3255 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT                0x00000007
3256 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C            0x00000000
3257 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C            0x00000001
3258
3259 //  usDeviceSupport:
3260 //  Bits0   = 0 - no CRT1 support= 1- CRT1 is supported
3261 //  Bit 1   = 0 - no LCD1 support= 1- LCD1 is supported
3262 //  Bit 2   = 0 - no TV1  support= 1- TV1  is supported
3263 //  Bit 3   = 0 - no DFP1 support= 1- DFP1 is supported
3264 //  Bit 4   = 0 - no CRT2 support= 1- CRT2 is supported
3265 //  Bit 5   = 0 - no LCD2 support= 1- LCD2 is supported
3266 //  Bit 6   = 0 - no DFP6 support= 1- DFP6 is supported
3267 //  Bit 7   = 0 - no DFP2 support= 1- DFP2 is supported
3268 //  Bit 8   = 0 - no CV   support= 1- CV   is supported
3269 //  Bit 9   = 0 - no DFP3 support= 1- DFP3 is supported
3270 //  Bit 10= 0 - no DFP4 support= 1- DFP4 is supported
3271 //  Bit 11= 0 - no DFP5 support= 1- DFP5 is supported
3272 //
3273 //
3274
3275 /****************************************************************************/
3276 // Structure used in MclkSS_InfoTable
3277 /****************************************************************************/
3278 //      ucI2C_ConfigID
3279 //    [7:0] - I2C LINE Associate ID
3280 //          = 0   - no I2C
3281 //    [7]      -   HW_Cap        =   1,  [6:0]=HW assisted I2C ID(HW line selection)
3282 //                          =   0,  [6:0]=SW assisted I2C ID
3283 //    [6-4]   - HW_ENGINE_ID  =   1,  HW engine for NON multimedia use
3284 //                          =   2,   HW engine for Multimedia use
3285 //                          =   3-7   Reserved for future I2C engines
3286 //      [3-0] - I2C_LINE_MUX  = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C
3287
3288 typedef struct _ATOM_I2C_ID_CONFIG
3289 {
3290 #if ATOM_BIG_ENDIAN
3291   UCHAR   bfHW_Capable:1;
3292   UCHAR   bfHW_EngineID:3;
3293   UCHAR   bfI2C_LineMux:4;
3294 #else
3295   UCHAR   bfI2C_LineMux:4;
3296   UCHAR   bfHW_EngineID:3;
3297   UCHAR   bfHW_Capable:1;
3298 #endif
3299 }ATOM_I2C_ID_CONFIG;
3300
3301 typedef union _ATOM_I2C_ID_CONFIG_ACCESS
3302 {
3303   ATOM_I2C_ID_CONFIG sbfAccess;
3304   UCHAR              ucAccess;
3305 }ATOM_I2C_ID_CONFIG_ACCESS;
3306
3307
3308 /****************************************************************************/
3309 // Structure used in GPIO_I2C_InfoTable
3310 /****************************************************************************/
3311 typedef struct _ATOM_GPIO_I2C_ASSIGMENT
3312 {
3313   USHORT                    usClkMaskRegisterIndex;
3314   USHORT                    usClkEnRegisterIndex;
3315   USHORT                    usClkY_RegisterIndex;
3316   USHORT                    usClkA_RegisterIndex;
3317   USHORT                    usDataMaskRegisterIndex;
3318   USHORT                    usDataEnRegisterIndex;
3319   USHORT                    usDataY_RegisterIndex;
3320   USHORT                    usDataA_RegisterIndex;
3321   ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
3322   UCHAR                     ucClkMaskShift;
3323   UCHAR                     ucClkEnShift;
3324   UCHAR                     ucClkY_Shift;
3325   UCHAR                     ucClkA_Shift;
3326   UCHAR                     ucDataMaskShift;
3327   UCHAR                     ucDataEnShift;
3328   UCHAR                     ucDataY_Shift;
3329   UCHAR                     ucDataA_Shift;
3330   UCHAR                     ucReserved1;
3331   UCHAR                     ucReserved2;
3332 }ATOM_GPIO_I2C_ASSIGMENT;
3333
3334 typedef struct _ATOM_GPIO_I2C_INFO
3335 {
3336   ATOM_COMMON_TABLE_HEADER   sHeader;
3337   ATOM_GPIO_I2C_ASSIGMENT   asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE];
3338 }ATOM_GPIO_I2C_INFO;
3339
3340 /****************************************************************************/
3341 // Common Structure used in other structures
3342 /****************************************************************************/
3343
3344 #ifndef _H2INC
3345
3346 //Please don't add or expand this bitfield structure below, this one will retire soon.!
3347 typedef struct _ATOM_MODE_MISC_INFO
3348 {
3349 #if ATOM_BIG_ENDIAN
3350   USHORT Reserved:6;
3351   USHORT RGB888:1;
3352   USHORT DoubleClock:1;
3353   USHORT Interlace:1;
3354   USHORT CompositeSync:1;
3355   USHORT V_ReplicationBy2:1;
3356   USHORT H_ReplicationBy2:1;
3357   USHORT VerticalCutOff:1;
3358   USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
3359   USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
3360   USHORT HorizontalCutOff:1;
3361 #else
3362   USHORT HorizontalCutOff:1;
3363   USHORT HSyncPolarity:1;      //0=Active High, 1=Active Low
3364   USHORT VSyncPolarity:1;      //0=Active High, 1=Active Low
3365   USHORT VerticalCutOff:1;
3366   USHORT H_ReplicationBy2:1;
3367   USHORT V_ReplicationBy2:1;
3368   USHORT CompositeSync:1;
3369   USHORT Interlace:1;
3370   USHORT DoubleClock:1;
3371   USHORT RGB888:1;
3372   USHORT Reserved:6;
3373 #endif
3374 }ATOM_MODE_MISC_INFO;
3375
3376 typedef union _ATOM_MODE_MISC_INFO_ACCESS
3377 {
3378   ATOM_MODE_MISC_INFO sbfAccess;
3379   USHORT              usAccess;
3380 }ATOM_MODE_MISC_INFO_ACCESS;
3381
3382 #else
3383
3384 typedef union _ATOM_MODE_MISC_INFO_ACCESS
3385 {
3386   USHORT              usAccess;
3387 }ATOM_MODE_MISC_INFO_ACCESS;
3388
3389 #endif
3390
3391 // usModeMiscInfo-
3392 #define ATOM_H_CUTOFF           0x01
3393 #define ATOM_HSYNC_POLARITY     0x02             //0=Active High, 1=Active Low
3394 #define ATOM_VSYNC_POLARITY     0x04             //0=Active High, 1=Active Low
3395 #define ATOM_V_CUTOFF           0x08
3396 #define ATOM_H_REPLICATIONBY2   0x10
3397 #define ATOM_V_REPLICATIONBY2   0x20
3398 #define ATOM_COMPOSITESYNC      0x40
3399 #define ATOM_INTERLACE          0x80
3400 #define ATOM_DOUBLE_CLOCK_MODE  0x100
3401 #define ATOM_RGB888_MODE        0x200
3402
3403 //usRefreshRate-
3404 #define ATOM_REFRESH_43         43
3405 #define ATOM_REFRESH_47         47
3406 #define ATOM_REFRESH_56         56
3407 #define ATOM_REFRESH_60         60
3408 #define ATOM_REFRESH_65         65
3409 #define ATOM_REFRESH_70         70
3410 #define ATOM_REFRESH_72         72
3411 #define ATOM_REFRESH_75         75
3412 #define ATOM_REFRESH_85         85
3413
3414 // ATOM_MODE_TIMING data are exactly the same as VESA timing data.
3415 // Translation from EDID to ATOM_MODE_TIMING, use the following formula.
3416 //
3417 //   VESA_HTOTAL         =   VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK
3418 //                  =   EDID_HA + EDID_HBL
3419 //   VESA_HDISP         =   VESA_ACTIVE   =   EDID_HA
3420 //   VESA_HSYNC_START   =   VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH
3421 //                  =   EDID_HA + EDID_HSO
3422 //   VESA_HSYNC_WIDTH   =   VESA_HSYNC_TIME   =   EDID_HSPW
3423 //   VESA_BORDER         =   EDID_BORDER
3424
3425
3426 /****************************************************************************/
3427 // Structure used in SetCRTC_UsingDTDTimingTable
3428 /****************************************************************************/
3429 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS
3430 {
3431   USHORT  usH_Size;
3432   USHORT  usH_Blanking_Time;
3433   USHORT  usV_Size;
3434   USHORT  usV_Blanking_Time;
3435   USHORT  usH_SyncOffset;
3436   USHORT  usH_SyncWidth;
3437   USHORT  usV_SyncOffset;
3438   USHORT  usV_SyncWidth;
3439   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
3440   UCHAR   ucH_Border;         // From DFP EDID
3441   UCHAR   ucV_Border;
3442   UCHAR   ucCRTC;             // ATOM_CRTC1 or ATOM_CRTC2
3443   UCHAR   ucPadding[3];
3444 }SET_CRTC_USING_DTD_TIMING_PARAMETERS;
3445
3446 /****************************************************************************/
3447 // Structure used in SetCRTC_TimingTable
3448 /****************************************************************************/
3449 typedef struct _SET_CRTC_TIMING_PARAMETERS
3450 {
3451   USHORT                      usH_Total;        // horizontal total
3452   USHORT                      usH_Disp;         // horizontal display
3453   USHORT                      usH_SyncStart;    // horozontal Sync start
3454   USHORT                      usH_SyncWidth;    // horizontal Sync width
3455   USHORT                      usV_Total;        // vertical total
3456   USHORT                      usV_Disp;         // vertical display
3457   USHORT                      usV_SyncStart;    // vertical Sync start
3458   USHORT                      usV_SyncWidth;    // vertical Sync width
3459   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
3460   UCHAR                       ucCRTC;           // ATOM_CRTC1 or ATOM_CRTC2
3461   UCHAR                       ucOverscanRight;  // right
3462   UCHAR                       ucOverscanLeft;   // left
3463   UCHAR                       ucOverscanBottom; // bottom
3464   UCHAR                       ucOverscanTop;    // top
3465   UCHAR                       ucReserved;
3466 }SET_CRTC_TIMING_PARAMETERS;
3467 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS
3468
3469
3470 /****************************************************************************/
3471 // Structure used in StandardVESA_TimingTable
3472 //                   AnalogTV_InfoTable
3473 //                   ComponentVideoInfoTable
3474 /****************************************************************************/
3475 typedef struct _ATOM_MODE_TIMING
3476 {
3477   USHORT  usCRTC_H_Total;
3478   USHORT  usCRTC_H_Disp;
3479   USHORT  usCRTC_H_SyncStart;
3480   USHORT  usCRTC_H_SyncWidth;
3481   USHORT  usCRTC_V_Total;
3482   USHORT  usCRTC_V_Disp;
3483   USHORT  usCRTC_V_SyncStart;
3484   USHORT  usCRTC_V_SyncWidth;
3485   USHORT  usPixelClock;                                //in 10Khz unit
3486   ATOM_MODE_MISC_INFO_ACCESS  susModeMiscInfo;
3487   USHORT  usCRTC_OverscanRight;
3488   USHORT  usCRTC_OverscanLeft;
3489   USHORT  usCRTC_OverscanBottom;
3490   USHORT  usCRTC_OverscanTop;
3491   USHORT  usReserve;
3492   UCHAR   ucInternalModeNumber;
3493   UCHAR   ucRefreshRate;
3494 }ATOM_MODE_TIMING;
3495
3496 typedef struct _ATOM_DTD_FORMAT
3497 {
3498   USHORT  usPixClk;
3499   USHORT  usHActive;
3500   USHORT  usHBlanking_Time;
3501   USHORT  usVActive;
3502   USHORT  usVBlanking_Time;
3503   USHORT  usHSyncOffset;
3504   USHORT  usHSyncWidth;
3505   USHORT  usVSyncOffset;
3506   USHORT  usVSyncWidth;
3507   USHORT  usImageHSize;
3508   USHORT  usImageVSize;
3509   UCHAR   ucHBorder;
3510   UCHAR   ucVBorder;
3511   ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo;
3512   UCHAR   ucInternalModeNumber;
3513   UCHAR   ucRefreshRate;
3514 }ATOM_DTD_FORMAT;
3515
3516 /****************************************************************************/
3517 // Structure used in LVDS_InfoTable
3518 //  * Need a document to describe this table
3519 /****************************************************************************/
3520 #define SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
3521 #define SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
3522 #define SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
3523 #define SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
3524 #define SUPPORTED_LCD_REFRESHRATE_48Hz          0x0040
3525
3526 //ucTableFormatRevision=1
3527 //ucTableContentRevision=1
3528 typedef struct _ATOM_LVDS_INFO
3529 {
3530   ATOM_COMMON_TABLE_HEADER sHeader;
3531   ATOM_DTD_FORMAT     sLCDTiming;
3532   USHORT              usModePatchTableOffset;
3533   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
3534   USHORT              usOffDelayInMs;
3535   UCHAR               ucPowerSequenceDigOntoDEin10Ms;
3536   UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
3537   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3538                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3539                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3540                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3541   UCHAR               ucPanelDefaultRefreshRate;
3542   UCHAR               ucPanelIdentification;
3543   UCHAR               ucSS_Id;
3544 }ATOM_LVDS_INFO;
3545
3546 //ucTableFormatRevision=1
3547 //ucTableContentRevision=2
3548 typedef struct _ATOM_LVDS_INFO_V12
3549 {
3550   ATOM_COMMON_TABLE_HEADER sHeader;
3551   ATOM_DTD_FORMAT     sLCDTiming;
3552   USHORT              usExtInfoTableOffset;
3553   USHORT              usSupportedRefreshRate;     //Refer to panel info table in ATOMBIOS extension Spec.
3554   USHORT              usOffDelayInMs;
3555   UCHAR               ucPowerSequenceDigOntoDEin10Ms;
3556   UCHAR               ucPowerSequenceDEtoBLOnin10Ms;
3557   UCHAR               ucLVDS_Misc;               // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3558                                                  // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
3559                                                  // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled}
3560                                                  // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled}
3561   UCHAR               ucPanelDefaultRefreshRate;
3562   UCHAR               ucPanelIdentification;
3563   UCHAR               ucSS_Id;
3564   USHORT              usLCDVenderID;
3565   USHORT              usLCDProductID;
3566   UCHAR               ucLCDPanel_SpecialHandlingCap;
3567    UCHAR                        ucPanelInfoSize;               //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3568   UCHAR               ucReserved[2];
3569 }ATOM_LVDS_INFO_V12;
3570
3571 //Definitions for ucLCDPanel_SpecialHandlingCap:
3572
3573 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3574 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3575 #define   LCDPANEL_CAP_READ_EDID                  0x1
3576
3577 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3578 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3579 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3580 #define   LCDPANEL_CAP_DRR_SUPPORTED              0x2
3581
3582 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3583 #define   LCDPANEL_CAP_eDP                        0x4
3584
3585
3586 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3587 //Bit 6  5  4
3588                               //      0  0  0  -  Color bit depth is undefined
3589                               //      0  0  1  -  6 Bits per Primary Color
3590                               //      0  1  0  -  8 Bits per Primary Color
3591                               //      0  1  1  - 10 Bits per Primary Color
3592                               //      1  0  0  - 12 Bits per Primary Color
3593                               //      1  0  1  - 14 Bits per Primary Color
3594                               //      1  1  0  - 16 Bits per Primary Color
3595                               //      1  1  1  - Reserved
3596
3597 #define PANEL_COLOR_BIT_DEPTH_MASK    0x70
3598
3599 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled}
3600 #define PANEL_RANDOM_DITHER   0x80
3601 #define PANEL_RANDOM_DITHER_MASK   0x80
3602
3603 #define ATOM_LVDS_INFO_LAST  ATOM_LVDS_INFO_V12   // no need to change this
3604
3605
3606 typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT
3607 {
3608     UCHAR ucSupportedRefreshRate;
3609     UCHAR ucMinRefreshRateForDRR;
3610 }ATOM_LCD_REFRESH_RATE_SUPPORT;
3611
3612 /****************************************************************************/
3613 // Structures used by LCD_InfoTable V1.3    Note: previous version was called ATOM_LVDS_INFO_V12
3614 // ASIC Families:  NI
3615 // ucTableFormatRevision=1
3616 // ucTableContentRevision=3
3617 /****************************************************************************/
3618 typedef struct _ATOM_LCD_INFO_V13
3619 {
3620   ATOM_COMMON_TABLE_HEADER sHeader;
3621   ATOM_DTD_FORMAT     sLCDTiming;
3622   USHORT              usExtInfoTableOffset;
3623   union
3624   {
3625     USHORT            usSupportedRefreshRate;
3626     ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport;
3627   };
3628   ULONG               ulReserved0;
3629   UCHAR               ucLCD_Misc;                // Reorganized in V13
3630                                                  // Bit0: {=0:single, =1:dual},
3631                                                  // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888}  // was {=0:666RGB, =1:888RGB},
3632                                                  // Bit3:2: {Grey level}
3633                                                  // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h)
3634                                                  // Bit7   Reserved.  was for ATOM_PANEL_MISC_API_ENABLED, still need it?
3635   UCHAR               ucPanelDefaultRefreshRate;
3636   UCHAR               ucPanelIdentification;
3637   UCHAR               ucSS_Id;
3638   USHORT              usLCDVenderID;
3639   USHORT              usLCDProductID;
3640   UCHAR               ucLCDPanel_SpecialHandlingCap;  // Reorganized in V13
3641                                                  // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own
3642                                                  // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED
3643                                                  // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1)
3644                                                  // Bit7-3: Reserved
3645   UCHAR               ucPanelInfoSize;                //  start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3646   USHORT              usBacklightPWM;            //  Backlight PWM in Hz. New in _V13
3647
3648   UCHAR               ucPowerSequenceDIGONtoDE_in4Ms;
3649   UCHAR               ucPowerSequenceDEtoVARY_BL_in4Ms;
3650   UCHAR               ucPowerSequenceVARY_BLtoDE_in4Ms;
3651   UCHAR               ucPowerSequenceDEtoDIGON_in4Ms;
3652
3653   UCHAR               ucOffDelay_in4Ms;
3654   UCHAR               ucPowerSequenceVARY_BLtoBLON_in4Ms;
3655   UCHAR               ucPowerSequenceBLONtoVARY_BL_in4Ms;
3656   UCHAR               ucReserved1;
3657
3658   UCHAR               ucDPCD_eDP_CONFIGURATION_CAP;     // dpcd 0dh
3659   UCHAR               ucDPCD_MAX_LINK_RATE;             // dpcd 01h
3660   UCHAR               ucDPCD_MAX_LANE_COUNT;            // dpcd 02h
3661   UCHAR               ucDPCD_MAX_DOWNSPREAD;            // dpcd 03h
3662
3663   USHORT              usMaxPclkFreqInSingleLink;        // Max PixelClock frequency in single link mode.
3664   UCHAR               uceDPToLVDSRxId;
3665   UCHAR               ucLcdReservd;
3666   ULONG               ulReserved[2];
3667 }ATOM_LCD_INFO_V13;
3668
3669 #define ATOM_LCD_INFO_LAST  ATOM_LCD_INFO_V13
3670
3671 //Definitions for ucLCD_Misc
3672 #define ATOM_PANEL_MISC_V13_DUAL                   0x00000001
3673 #define ATOM_PANEL_MISC_V13_FPDI                   0x00000002
3674 #define ATOM_PANEL_MISC_V13_GREY_LEVEL             0x0000000C
3675 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT       2
3676 #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK   0x70
3677 #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR         0x10
3678 #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR         0x20
3679
3680 //Color Bit Depth definition in EDID V1.4 @BYTE 14h
3681 //Bit 6  5  4
3682                               //      0  0  0  -  Color bit depth is undefined
3683                               //      0  0  1  -  6 Bits per Primary Color
3684                               //      0  1  0  -  8 Bits per Primary Color
3685                               //      0  1  1  - 10 Bits per Primary Color
3686                               //      1  0  0  - 12 Bits per Primary Color
3687                               //      1  0  1  - 14 Bits per Primary Color
3688                               //      1  1  0  - 16 Bits per Primary Color
3689                               //      1  1  1  - Reserved
3690
3691 //Definitions for ucLCDPanel_SpecialHandlingCap:
3692
3693 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12.
3694 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL
3695 #define   LCDPANEL_CAP_V13_READ_EDID              0x1        // = LCDPANEL_CAP_READ_EDID no change comparing to previous version
3696
3697 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together
3698 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static
3699 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12
3700 #define   LCDPANEL_CAP_V13_DRR_SUPPORTED          0x2        // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version
3701
3702 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP.
3703 #define   LCDPANEL_CAP_V13_eDP                    0x4        // = LCDPANEL_CAP_eDP no change comparing to previous version
3704
3705 //uceDPToLVDSRxId
3706 #define eDP_TO_LVDS_RX_DISABLE                  0x00       // no eDP->LVDS translator chip
3707 #define eDP_TO_LVDS_COMMON_ID                   0x01       // common eDP->LVDS translator chip without AMD SW init
3708 #define eDP_TO_LVDS_RT_ID                       0x02       // RT tansaltor which require AMD SW init
3709
3710 typedef struct  _ATOM_PATCH_RECORD_MODE
3711 {
3712   UCHAR     ucRecordType;
3713   USHORT    usHDisp;
3714   USHORT    usVDisp;
3715 }ATOM_PATCH_RECORD_MODE;
3716
3717 typedef struct  _ATOM_LCD_RTS_RECORD
3718 {
3719   UCHAR     ucRecordType;
3720   UCHAR     ucRTSValue;
3721 }ATOM_LCD_RTS_RECORD;
3722
3723 //!! If the record below exits, it shoud always be the first record for easy use in command table!!!
3724 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead.
3725 typedef struct  _ATOM_LCD_MODE_CONTROL_CAP
3726 {
3727   UCHAR     ucRecordType;
3728   USHORT    usLCDCap;
3729 }ATOM_LCD_MODE_CONTROL_CAP;
3730
3731 #define LCD_MODE_CAP_BL_OFF                   1
3732 #define LCD_MODE_CAP_CRTC_OFF                 2
3733 #define LCD_MODE_CAP_PANEL_OFF                4
3734
3735
3736 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD
3737 {
3738   UCHAR ucRecordType;
3739   UCHAR ucFakeEDIDLength;       // = 128 means EDID lenght is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128
3740   UCHAR ucFakeEDIDString[1];    // This actually has ucFakeEdidLength elements.
3741 } ATOM_FAKE_EDID_PATCH_RECORD;
3742
3743 typedef struct  _ATOM_PANEL_RESOLUTION_PATCH_RECORD
3744 {
3745    UCHAR    ucRecordType;
3746    USHORT      usHSize;
3747    USHORT      usVSize;
3748 }ATOM_PANEL_RESOLUTION_PATCH_RECORD;
3749
3750 #define LCD_MODE_PATCH_RECORD_MODE_TYPE       1
3751 #define LCD_RTS_RECORD_TYPE                   2
3752 #define LCD_CAP_RECORD_TYPE                   3
3753 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE       4
3754 #define LCD_PANEL_RESOLUTION_RECORD_TYPE      5
3755 #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE     6
3756 #define ATOM_RECORD_END_TYPE                  0xFF
3757
3758 /****************************Spread Spectrum Info Table Definitions **********************/
3759
3760 //ucTableFormatRevision=1
3761 //ucTableContentRevision=2
3762 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT
3763 {
3764   USHORT              usSpreadSpectrumPercentage;
3765   UCHAR               ucSpreadSpectrumType;       //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS  Others:TBD
3766   UCHAR               ucSS_Step;
3767   UCHAR               ucSS_Delay;
3768   UCHAR               ucSS_Id;
3769   UCHAR               ucRecommendedRef_Div;
3770   UCHAR               ucSS_Range;               //it was reserved for V11
3771 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
3772
3773 #define ATOM_MAX_SS_ENTRY                      16
3774 #define ATOM_DP_SS_ID1                                     0x0f1         // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well.
3775 #define ATOM_DP_SS_ID2                                     0x0f2         // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable.
3776 #define ATOM_LVLINK_2700MHz_SS_ID              0x0f3      // SS ID for LV link translator chip at 2.7Ghz
3777 #define ATOM_LVLINK_1620MHz_SS_ID              0x0f4      // SS ID for LV link translator chip at 1.62Ghz
3778
3779
3780
3781 #define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
3782 #define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
3783 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
3784 #define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
3785 #define ATOM_INTERNAL_SS_MASK                  0x00000000
3786 #define ATOM_EXTERNAL_SS_MASK                  0x00000002
3787 #define EXEC_SS_STEP_SIZE_SHIFT                2
3788 #define EXEC_SS_DELAY_SHIFT                    4
3789 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT         4
3790
3791 typedef struct _ATOM_SPREAD_SPECTRUM_INFO
3792 {
3793   ATOM_COMMON_TABLE_HEADER   sHeader;
3794   ATOM_SPREAD_SPECTRUM_ASSIGNMENT   asSS_Info[ATOM_MAX_SS_ENTRY];
3795 }ATOM_SPREAD_SPECTRUM_INFO;
3796
3797
3798 /****************************************************************************/
3799 // Structure used in AnalogTV_InfoTable (Top level)
3800 /****************************************************************************/
3801 //ucTVBootUpDefaultStd definiton:
3802
3803 //ATOM_TV_NTSC                1
3804 //ATOM_TV_NTSCJ               2
3805 //ATOM_TV_PAL                 3
3806 //ATOM_TV_PALM                4
3807 //ATOM_TV_PALCN               5
3808 //ATOM_TV_PALN                6
3809 //ATOM_TV_PAL60               7
3810 //ATOM_TV_SECAM               8
3811
3812 //ucTVSuppportedStd definition:
3813 #define NTSC_SUPPORT          0x1
3814 #define NTSCJ_SUPPORT         0x2
3815
3816 #define PAL_SUPPORT           0x4
3817 #define PALM_SUPPORT          0x8
3818 #define PALCN_SUPPORT         0x10
3819 #define PALN_SUPPORT          0x20
3820 #define PAL60_SUPPORT         0x40
3821 #define SECAM_SUPPORT         0x80
3822
3823 #define MAX_SUPPORTED_TV_TIMING    2
3824
3825 typedef struct _ATOM_ANALOG_TV_INFO
3826 {
3827   ATOM_COMMON_TABLE_HEADER sHeader;
3828   UCHAR                    ucTV_SuppportedStandard;
3829   UCHAR                    ucTV_BootUpDefaultStandard;
3830   UCHAR                    ucExt_TV_ASIC_ID;
3831   UCHAR                    ucExt_TV_ASIC_SlaveAddr;
3832   ATOM_DTD_FORMAT          aModeTimings[MAX_SUPPORTED_TV_TIMING];
3833 }ATOM_ANALOG_TV_INFO;
3834
3835 typedef struct _ATOM_DPCD_INFO
3836 {
3837   UCHAR   ucRevisionNumber;        //10h : Revision 1.0; 11h : Revision 1.1
3838   UCHAR   ucMaxLinkRate;           //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
3839   UCHAR   ucMaxLane;               //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
3840   UCHAR   ucMaxDownSpread;         //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
3841 }ATOM_DPCD_INFO;
3842
3843 #define ATOM_DPCD_MAX_LANE_MASK    0x1F
3844
3845 /**************************************************************************/
3846 // VRAM usage and their defintions
3847
3848 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data.
3849 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below.
3850 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned!
3851 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR
3852 // To Bios:  ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX
3853
3854 // Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU).
3855 //#ifndef VESA_MEMORY_IN_64K_BLOCK
3856 //#define VESA_MEMORY_IN_64K_BLOCK        0x100       //256*64K=16Mb (Max. VESA memory is 16Mb!)
3857 //#endif
3858
3859 #define ATOM_EDID_RAW_DATASIZE          256         //In Bytes
3860 #define ATOM_HWICON_SURFACE_SIZE        4096        //In Bytes
3861 #define ATOM_HWICON_INFOTABLE_SIZE      32
3862 #define MAX_DTD_MODE_IN_VRAM            6
3863 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE  (MAX_DTD_MODE_IN_VRAM*28)    //28= (SIZEOF ATOM_DTD_FORMAT)
3864 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE  32*8                         //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT)
3865 //20 bytes for Encoder Type and DPCD in STD EDID area
3866 #define DFP_ENCODER_TYPE_OFFSET         (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20)
3867 #define ATOM_DP_DPCD_OFFSET             (DFP_ENCODER_TYPE_OFFSET + 4 )
3868
3869 #define ATOM_HWICON1_SURFACE_ADDR       0
3870 #define ATOM_HWICON2_SURFACE_ADDR       (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
3871 #define ATOM_HWICON_INFOTABLE_ADDR      (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE)
3872 #define ATOM_CRT1_EDID_ADDR             (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE)
3873 #define ATOM_CRT1_DTD_MODE_TBL_ADDR     (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3874 #define ATOM_CRT1_STD_MODE_TBL_ADDR       (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3875
3876 #define ATOM_LCD1_EDID_ADDR             (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3877 #define ATOM_LCD1_DTD_MODE_TBL_ADDR     (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3878 #define ATOM_LCD1_STD_MODE_TBL_ADDR      (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3879
3880 #define ATOM_TV1_DTD_MODE_TBL_ADDR      (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3881
3882 #define ATOM_DFP1_EDID_ADDR             (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3883 #define ATOM_DFP1_DTD_MODE_TBL_ADDR     (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3884 #define ATOM_DFP1_STD_MODE_TBL_ADDR       (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3885
3886 #define ATOM_CRT2_EDID_ADDR             (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3887 #define ATOM_CRT2_DTD_MODE_TBL_ADDR     (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3888 #define ATOM_CRT2_STD_MODE_TBL_ADDR       (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3889
3890 #define ATOM_LCD2_EDID_ADDR             (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3891 #define ATOM_LCD2_DTD_MODE_TBL_ADDR     (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3892 #define ATOM_LCD2_STD_MODE_TBL_ADDR      (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3893
3894 #define ATOM_DFP6_EDID_ADDR             (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3895 #define ATOM_DFP6_DTD_MODE_TBL_ADDR     (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3896 #define ATOM_DFP6_STD_MODE_TBL_ADDR     (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3897
3898 #define ATOM_DFP2_EDID_ADDR             (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3899 #define ATOM_DFP2_DTD_MODE_TBL_ADDR     (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3900 #define ATOM_DFP2_STD_MODE_TBL_ADDR     (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3901
3902 #define ATOM_CV_EDID_ADDR               (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3903 #define ATOM_CV_DTD_MODE_TBL_ADDR       (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3904 #define ATOM_CV_STD_MODE_TBL_ADDR       (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3905
3906 #define ATOM_DFP3_EDID_ADDR             (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3907 #define ATOM_DFP3_DTD_MODE_TBL_ADDR     (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3908 #define ATOM_DFP3_STD_MODE_TBL_ADDR     (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3909
3910 #define ATOM_DFP4_EDID_ADDR             (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3911 #define ATOM_DFP4_DTD_MODE_TBL_ADDR     (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3912 #define ATOM_DFP4_STD_MODE_TBL_ADDR     (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3913
3914 #define ATOM_DFP5_EDID_ADDR             (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3915 #define ATOM_DFP5_DTD_MODE_TBL_ADDR     (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE)
3916 #define ATOM_DFP5_STD_MODE_TBL_ADDR     (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE)
3917
3918 #define ATOM_DP_TRAINING_TBL_ADDR       (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE)
3919
3920 #define ATOM_STACK_STORAGE_START        (ATOM_DP_TRAINING_TBL_ADDR + 1024)
3921 #define ATOM_STACK_STORAGE_END          ATOM_STACK_STORAGE_START + 512
3922
3923 //The size below is in Kb!
3924 #define ATOM_VRAM_RESERVE_SIZE         ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC)
3925
3926 #define ATOM_VRAM_RESERVE_V2_SIZE      32
3927
3928 #define   ATOM_VRAM_OPERATION_FLAGS_MASK         0xC0000000L
3929 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT        30
3930 #define   ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION   0x1
3931 #define   ATOM_VRAM_BLOCK_NEEDS_RESERVATION      0x0
3932
3933 /***********************************************************************************/
3934 // Structure used in VRAM_UsageByFirmwareTable
3935 // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm
3936 //        at running time.
3937 // note2: From RV770, the memory is more than 32bit addressable, so we will change
3938 //        ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains
3939 //        exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware
3940 //        (in offset to start of memory address) is KB aligned instead of byte aligend.
3941 // Note3:
3942 /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged
3943 constant across VGA or non VGA adapter,
3944 for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can  have:
3945
3946 If (ulStartAddrUsedByFirmware!=0)
3947 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB;
3948 Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose
3949 else   //Non VGA case
3950  if (FB_Size<=2Gb)
3951     FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB;
3952  else
3953      FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB
3954
3955 CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/
3956
3957 /***********************************************************************************/
3958 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO         1
3959
3960 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO
3961 {
3962   ULONG   ulStartAddrUsedByFirmware;
3963   USHORT  usFirmwareUseInKb;
3964   USHORT  usReserved;
3965 }ATOM_FIRMWARE_VRAM_RESERVE_INFO;
3966
3967 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE
3968 {
3969   ATOM_COMMON_TABLE_HEADER sHeader;
3970   ATOM_FIRMWARE_VRAM_RESERVE_INFO   asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
3971 }ATOM_VRAM_USAGE_BY_FIRMWARE;
3972
3973 // change verion to 1.5, when allow driver to allocate the vram area for command table access.
3974 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5
3975 {
3976   ULONG   ulStartAddrUsedByFirmware;
3977   USHORT  usFirmwareUseInKb;
3978   USHORT  usFBUsedByDrvInKb;
3979 }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5;
3980
3981 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5
3982 {
3983   ATOM_COMMON_TABLE_HEADER sHeader;
3984   ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5   asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO];
3985 }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5;
3986
3987 /****************************************************************************/
3988 // Structure used in GPIO_Pin_LUTTable
3989 /****************************************************************************/
3990 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT
3991 {
3992   USHORT                   usGpioPin_AIndex;
3993   UCHAR                    ucGpioPinBitShift;
3994   UCHAR                    ucGPIO_ID;
3995 }ATOM_GPIO_PIN_ASSIGNMENT;
3996
3997 //ucGPIO_ID pre-define id for multiple usage
3998 // GPIO use to control PCIE_VDDC in certain SLT board
3999 #define PCIE_VDDC_CONTROL_GPIO_PINID        56
4000
4001 //from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC swithing feature is enable
4002 #define PP_AC_DC_SWITCH_GPIO_PINID          60
4003 //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable
4004 #define VDDC_VRHOT_GPIO_PINID               61
4005 //if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled
4006 #define VDDC_PCC_GPIO_PINID                 62
4007 // Only used on certain SLT/PA board to allow utility to cut Efuse.
4008 #define EFUSE_CUT_ENABLE_GPIO_PINID         63
4009 // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses  for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO=
4010 #define DRAM_SELF_REFRESH_GPIO_PINID        64
4011 // Thermal interrupt output->system thermal chip GPIO pin
4012 #define THERMAL_INT_OUTPUT_GPIO_PINID       65
4013
4014
4015 typedef struct _ATOM_GPIO_PIN_LUT
4016 {
4017   ATOM_COMMON_TABLE_HEADER  sHeader;
4018   ATOM_GPIO_PIN_ASSIGNMENT   asGPIO_Pin[1];
4019 }ATOM_GPIO_PIN_LUT;
4020
4021 /****************************************************************************/
4022 // Structure used in ComponentVideoInfoTable
4023 /****************************************************************************/
4024 #define GPIO_PIN_ACTIVE_HIGH          0x1
4025 #define MAX_SUPPORTED_CV_STANDARDS    5
4026
4027 // definitions for ATOM_D_INFO.ucSettings
4028 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK  0x1F    // [4:0]
4029 #define ATOM_GPIO_SETTINGS_RESERVED_MASK  0x60    // [6:5] = must be zeroed out
4030 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK    0x80    // [7]
4031
4032 typedef struct _ATOM_GPIO_INFO
4033 {
4034   USHORT  usAOffset;
4035   UCHAR   ucSettings;
4036   UCHAR   ucReserved;
4037 }ATOM_GPIO_INFO;
4038
4039 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector)
4040 #define ATOM_CV_RESTRICT_FORMAT_SELECTION           0x2
4041
4042 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i
4043 #define ATOM_GPIO_DEFAULT_MODE_EN                   0x80 //[7];
4044 #define ATOM_GPIO_SETTING_PERMODE_MASK              0x7F //[6:0]
4045
4046 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode
4047 //Line 3 out put 5V.
4048 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A       0x01     //represent gpio 3 state for 16:9
4049 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B       0x02     //represent gpio 4 state for 16:9
4050 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT   0x0
4051
4052 //Line 3 out put 2.2V
4053 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04     //represent gpio 3 state for 4:3 Letter box
4054 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08     //represent gpio 4 state for 4:3 Letter box
4055 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2
4056
4057 //Line 3 out put 0V
4058 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A        0x10     //represent gpio 3 state for 4:3
4059 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B        0x20     //represent gpio 4 state for 4:3
4060 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT    0x4
4061
4062 #define ATOM_CV_LINE3_ASPECTRATIO_MASK              0x3F     // bit [5:0]
4063
4064 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST             0x80     //bit 7
4065
4066 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks.
4067 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A   3   //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
4068 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B   4   //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode.
4069
4070
4071 typedef struct _ATOM_COMPONENT_VIDEO_INFO
4072 {
4073   ATOM_COMMON_TABLE_HEADER sHeader;
4074   USHORT             usMask_PinRegisterIndex;
4075   USHORT             usEN_PinRegisterIndex;
4076   USHORT             usY_PinRegisterIndex;
4077   USHORT             usA_PinRegisterIndex;
4078   UCHAR              ucBitShift;
4079   UCHAR              ucPinActiveState;  //ucPinActiveState: Bit0=1 active high, =0 active low
4080   ATOM_DTD_FORMAT    sReserved;         // must be zeroed out
4081   UCHAR              ucMiscInfo;
4082   UCHAR              uc480i;
4083   UCHAR              uc480p;
4084   UCHAR              uc720p;
4085   UCHAR              uc1080i;
4086   UCHAR              ucLetterBoxMode;
4087   UCHAR              ucReserved[3];
4088   UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
4089   ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
4090   ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
4091 }ATOM_COMPONENT_VIDEO_INFO;
4092
4093 //ucTableFormatRevision=2
4094 //ucTableContentRevision=1
4095 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21
4096 {
4097   ATOM_COMMON_TABLE_HEADER sHeader;
4098   UCHAR              ucMiscInfo;
4099   UCHAR              uc480i;
4100   UCHAR              uc480p;
4101   UCHAR              uc720p;
4102   UCHAR              uc1080i;
4103   UCHAR              ucReserved;
4104   UCHAR              ucLetterBoxMode;
4105   UCHAR              ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
4106   ATOM_GPIO_INFO     aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS];
4107   ATOM_DTD_FORMAT    aModeTimings[MAX_SUPPORTED_CV_STANDARDS];
4108 }ATOM_COMPONENT_VIDEO_INFO_V21;
4109
4110 #define ATOM_COMPONENT_VIDEO_INFO_LAST  ATOM_COMPONENT_VIDEO_INFO_V21
4111
4112 /****************************************************************************/
4113 // Structure used in object_InfoTable
4114 /****************************************************************************/
4115 typedef struct _ATOM_OBJECT_HEADER
4116 {
4117   ATOM_COMMON_TABLE_HEADER   sHeader;
4118   USHORT                    usDeviceSupport;
4119   USHORT                    usConnectorObjectTableOffset;
4120   USHORT                    usRouterObjectTableOffset;
4121   USHORT                    usEncoderObjectTableOffset;
4122   USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
4123   USHORT                    usDisplayPathTableOffset;
4124 }ATOM_OBJECT_HEADER;
4125
4126 typedef struct _ATOM_OBJECT_HEADER_V3
4127 {
4128   ATOM_COMMON_TABLE_HEADER   sHeader;
4129   USHORT                    usDeviceSupport;
4130   USHORT                    usConnectorObjectTableOffset;
4131   USHORT                    usRouterObjectTableOffset;
4132   USHORT                    usEncoderObjectTableOffset;
4133   USHORT                    usProtectionObjectTableOffset; //only available when Protection block is independent.
4134   USHORT                    usDisplayPathTableOffset;
4135   USHORT                    usMiscObjectTableOffset;
4136 }ATOM_OBJECT_HEADER_V3;
4137
4138
4139 typedef struct  _ATOM_DISPLAY_OBJECT_PATH
4140 {
4141   USHORT    usDeviceTag;                                   //supported device
4142   USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
4143   USHORT    usConnObjectId;                                //Connector Object ID
4144   USHORT    usGPUObjectId;                                 //GPU ID
4145   USHORT    usGraphicObjIds[1];                            //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector.
4146 }ATOM_DISPLAY_OBJECT_PATH;
4147
4148 typedef struct  _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH
4149 {
4150   USHORT    usDeviceTag;                                   //supported device
4151   USHORT    usSize;                                        //the size of ATOM_DISPLAY_OBJECT_PATH
4152   USHORT    usConnObjectId;                                //Connector Object ID
4153   USHORT    usGPUObjectId;                                 //GPU ID
4154   USHORT    usGraphicObjIds[2];                            //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder
4155 }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH;
4156
4157 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE
4158 {
4159   UCHAR                           ucNumOfDispPath;
4160   UCHAR                           ucVersion;
4161   UCHAR                           ucPadding[2];
4162   ATOM_DISPLAY_OBJECT_PATH        asDispPath[1];
4163 }ATOM_DISPLAY_OBJECT_PATH_TABLE;
4164
4165 typedef struct _ATOM_OBJECT                                //each object has this structure
4166 {
4167   USHORT              usObjectID;
4168   USHORT              usSrcDstTableOffset;
4169   USHORT              usRecordOffset;                     //this pointing to a bunch of records defined below
4170   USHORT              usReserved;
4171 }ATOM_OBJECT;
4172
4173 typedef struct _ATOM_OBJECT_TABLE                         //Above 4 object table offset pointing to a bunch of objects all have this structure
4174 {
4175   UCHAR               ucNumberOfObjects;
4176   UCHAR               ucPadding[3];
4177   ATOM_OBJECT         asObjects[1];
4178 }ATOM_OBJECT_TABLE;
4179
4180 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT         //usSrcDstTableOffset pointing to this structure
4181 {
4182   UCHAR               ucNumberOfSrc;
4183   USHORT              usSrcObjectID[1];
4184   UCHAR               ucNumberOfDst;
4185   USHORT              usDstObjectID[1];
4186 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT;
4187
4188
4189 //Two definitions below are for OPM on MXM module designs
4190
4191 #define EXT_HPDPIN_LUTINDEX_0                   0
4192 #define EXT_HPDPIN_LUTINDEX_1                   1
4193 #define EXT_HPDPIN_LUTINDEX_2                   2
4194 #define EXT_HPDPIN_LUTINDEX_3                   3
4195 #define EXT_HPDPIN_LUTINDEX_4                   4
4196 #define EXT_HPDPIN_LUTINDEX_5                   5
4197 #define EXT_HPDPIN_LUTINDEX_6                   6
4198 #define EXT_HPDPIN_LUTINDEX_7                   7
4199 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES   (EXT_HPDPIN_LUTINDEX_7+1)
4200
4201 #define EXT_AUXDDC_LUTINDEX_0                   0
4202 #define EXT_AUXDDC_LUTINDEX_1                   1
4203 #define EXT_AUXDDC_LUTINDEX_2                   2
4204 #define EXT_AUXDDC_LUTINDEX_3                   3
4205 #define EXT_AUXDDC_LUTINDEX_4                   4
4206 #define EXT_AUXDDC_LUTINDEX_5                   5
4207 #define EXT_AUXDDC_LUTINDEX_6                   6
4208 #define EXT_AUXDDC_LUTINDEX_7                   7
4209 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES   (EXT_AUXDDC_LUTINDEX_7+1)
4210
4211 //ucChannelMapping are defined as following
4212 //for DP connector, eDP, DP to VGA/LVDS
4213 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4214 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4215 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4216 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4217 typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING
4218 {
4219 #if ATOM_BIG_ENDIAN
4220   UCHAR ucDP_Lane3_Source:2;
4221   UCHAR ucDP_Lane2_Source:2;
4222   UCHAR ucDP_Lane1_Source:2;
4223   UCHAR ucDP_Lane0_Source:2;
4224 #else
4225   UCHAR ucDP_Lane0_Source:2;
4226   UCHAR ucDP_Lane1_Source:2;
4227   UCHAR ucDP_Lane2_Source:2;
4228   UCHAR ucDP_Lane3_Source:2;
4229 #endif
4230 }ATOM_DP_CONN_CHANNEL_MAPPING;
4231
4232 //for DVI/HDMI, in dual link case, both links have to have same mapping.
4233 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4234 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4235 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4236 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3
4237 typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING
4238 {
4239 #if ATOM_BIG_ENDIAN
4240   UCHAR ucDVI_CLK_Source:2;
4241   UCHAR ucDVI_DATA0_Source:2;
4242   UCHAR ucDVI_DATA1_Source:2;
4243   UCHAR ucDVI_DATA2_Source:2;
4244 #else
4245   UCHAR ucDVI_DATA2_Source:2;
4246   UCHAR ucDVI_DATA1_Source:2;
4247   UCHAR ucDVI_DATA0_Source:2;
4248   UCHAR ucDVI_CLK_Source:2;
4249 #endif
4250 }ATOM_DVI_CONN_CHANNEL_MAPPING;
4251
4252 typedef struct _EXT_DISPLAY_PATH
4253 {
4254   USHORT  usDeviceTag;                    //A bit vector to show what devices are supported
4255   USHORT  usDeviceACPIEnum;               //16bit device ACPI id.
4256   USHORT  usDeviceConnector;              //A physical connector for displays to plug in, using object connector definitions
4257   UCHAR   ucExtAUXDDCLutIndex;            //An index into external AUX/DDC channel LUT
4258   UCHAR   ucExtHPDPINLutIndex;            //An index into external HPD pin LUT
4259   USHORT  usExtEncoderObjId;              //external encoder object id
4260   union{
4261     UCHAR   ucChannelMapping;                  // if ucChannelMapping=0, using default one to one mapping
4262     ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping;
4263     ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping;
4264   };
4265   UCHAR   ucChPNInvert;                   // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
4266   USHORT  usCaps;
4267   USHORT  usReserved;
4268 }EXT_DISPLAY_PATH;
4269
4270 #define NUMBER_OF_UCHAR_FOR_GUID          16
4271 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH    7
4272
4273 //usCaps
4274 #define  EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE               0x01
4275 #define  EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN             0x02
4276 #define  EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204          0x04
4277 #define  EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT     0x08
4278
4279 typedef  struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO
4280 {
4281   ATOM_COMMON_TABLE_HEADER sHeader;
4282   UCHAR                    ucGuid [NUMBER_OF_UCHAR_FOR_GUID];     // a GUID is a 16 byte long string
4283   EXT_DISPLAY_PATH         sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries.
4284   UCHAR                    ucChecksum;                            // a simple Checksum of the sum of whole structure equal to 0x0.
4285   UCHAR                    uc3DStereoPinId;                       // use for eDP panel
4286   UCHAR                    ucRemoteDisplayConfig;
4287   UCHAR                    uceDPToLVDSRxId;
4288   UCHAR                    ucFixDPVoltageSwing;                   // usCaps[1]=1, this indicate DP_LANE_SET value
4289   UCHAR                    Reserved[3];                           // for potential expansion
4290 }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO;
4291
4292 //Related definitions, all records are differnt but they have a commond header
4293 typedef struct _ATOM_COMMON_RECORD_HEADER
4294 {
4295   UCHAR               ucRecordType;                      //An emun to indicate the record type
4296   UCHAR               ucRecordSize;                      //The size of the whole record in byte
4297 }ATOM_COMMON_RECORD_HEADER;
4298
4299
4300 #define ATOM_I2C_RECORD_TYPE                           1
4301 #define ATOM_HPD_INT_RECORD_TYPE                       2
4302 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE             3
4303 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE          4
4304 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE       5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4305 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE          6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4306 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE      7
4307 #define ATOM_JTAG_RECORD_TYPE                          8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE
4308 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE              9
4309 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE                10
4310 #define ATOM_CONNECTOR_CF_RECORD_TYPE                  11
4311 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE        12
4312 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE   13
4313 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE        14
4314 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15
4315 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE          16 //This is for the case when connectors are not known to object table
4316 #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE          17 //This is for the case when connectors are not known to object table
4317 #define ATOM_OBJECT_LINK_RECORD_TYPE                   18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record
4318 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE          19
4319 #define ATOM_ENCODER_CAP_RECORD_TYPE                   20
4320 #define ATOM_BRACKET_LAYOUT_RECORD_TYPE                21
4321
4322
4323 //Must be updated when new record type is added,equal to that record definition!
4324 #define ATOM_MAX_OBJECT_RECORD_NUMBER             ATOM_ENCODER_CAP_RECORD_TYPE
4325
4326 typedef struct  _ATOM_I2C_RECORD
4327 {
4328   ATOM_COMMON_RECORD_HEADER   sheader;
4329   ATOM_I2C_ID_CONFIG          sucI2cId;
4330   UCHAR                       ucI2CAddr;              //The slave address, it's 0 when the record is attached to connector for DDC
4331 }ATOM_I2C_RECORD;
4332
4333 typedef struct  _ATOM_HPD_INT_RECORD
4334 {
4335   ATOM_COMMON_RECORD_HEADER   sheader;
4336   UCHAR                       ucHPDIntGPIOID;         //Corresponding block in GPIO_PIN_INFO table gives the pin info
4337   UCHAR                       ucPlugged_PinState;
4338 }ATOM_HPD_INT_RECORD;
4339
4340
4341 typedef struct  _ATOM_OUTPUT_PROTECTION_RECORD
4342 {
4343   ATOM_COMMON_RECORD_HEADER   sheader;
4344   UCHAR                       ucProtectionFlag;
4345   UCHAR                       ucReserved;
4346 }ATOM_OUTPUT_PROTECTION_RECORD;
4347
4348 typedef struct  _ATOM_CONNECTOR_DEVICE_TAG
4349 {
4350   ULONG                       ulACPIDeviceEnum;       //Reserved for now
4351   USHORT                      usDeviceID;             //This Id is same as "ATOM_DEVICE_XXX_SUPPORT"
4352   USHORT                      usPadding;
4353 }ATOM_CONNECTOR_DEVICE_TAG;
4354
4355 typedef struct  _ATOM_CONNECTOR_DEVICE_TAG_RECORD
4356 {
4357   ATOM_COMMON_RECORD_HEADER   sheader;
4358   UCHAR                       ucNumberOfDevice;
4359   UCHAR                       ucReserved;
4360   ATOM_CONNECTOR_DEVICE_TAG   asDeviceTag[1];         //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation
4361 }ATOM_CONNECTOR_DEVICE_TAG_RECORD;
4362
4363
4364 typedef struct  _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD
4365 {
4366   ATOM_COMMON_RECORD_HEADER   sheader;
4367   UCHAR                              ucConfigGPIOID;
4368   UCHAR                              ucConfigGPIOState;       //Set to 1 when it's active high to enable external flow in
4369   UCHAR                       ucFlowinGPIPID;
4370   UCHAR                       ucExtInGPIPID;
4371 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD;
4372
4373 typedef struct  _ATOM_ENCODER_FPGA_CONTROL_RECORD
4374 {
4375   ATOM_COMMON_RECORD_HEADER   sheader;
4376   UCHAR                       ucCTL1GPIO_ID;
4377   UCHAR                       ucCTL1GPIOState;        //Set to 1 when it's active high
4378   UCHAR                       ucCTL2GPIO_ID;
4379   UCHAR                       ucCTL2GPIOState;        //Set to 1 when it's active high
4380   UCHAR                       ucCTL3GPIO_ID;
4381   UCHAR                       ucCTL3GPIOState;        //Set to 1 when it's active high
4382   UCHAR                       ucCTLFPGA_IN_ID;
4383   UCHAR                       ucPadding[3];
4384 }ATOM_ENCODER_FPGA_CONTROL_RECORD;
4385
4386 typedef struct  _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD
4387 {
4388   ATOM_COMMON_RECORD_HEADER   sheader;
4389   UCHAR                       ucGPIOID;               //Corresponding block in GPIO_PIN_INFO table gives the pin info
4390   UCHAR                       ucTVActiveState;        //Indicating when the pin==0 or 1 when TV is connected
4391 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD;
4392
4393 typedef struct  _ATOM_JTAG_RECORD
4394 {
4395   ATOM_COMMON_RECORD_HEADER   sheader;
4396   UCHAR                       ucTMSGPIO_ID;
4397   UCHAR                       ucTMSGPIOState;         //Set to 1 when it's active high
4398   UCHAR                       ucTCKGPIO_ID;
4399   UCHAR                       ucTCKGPIOState;         //Set to 1 when it's active high
4400   UCHAR                       ucTDOGPIO_ID;
4401   UCHAR                       ucTDOGPIOState;         //Set to 1 when it's active high
4402   UCHAR                       ucTDIGPIO_ID;
4403   UCHAR                       ucTDIGPIOState;         //Set to 1 when it's active high
4404   UCHAR                       ucPadding[2];
4405 }ATOM_JTAG_RECORD;
4406
4407
4408 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
4409 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR
4410 {
4411   UCHAR                       ucGPIOID;               // GPIO_ID, find the corresponding ID in GPIO_LUT table
4412   UCHAR                       ucGPIO_PinState;        // Pin state showing how to set-up the pin
4413 }ATOM_GPIO_PIN_CONTROL_PAIR;
4414
4415 typedef struct  _ATOM_OBJECT_GPIO_CNTL_RECORD
4416 {
4417   ATOM_COMMON_RECORD_HEADER   sheader;
4418   UCHAR                       ucFlags;                // Future expnadibility
4419   UCHAR                       ucNumberOfPins;         // Number of GPIO pins used to control the object
4420   ATOM_GPIO_PIN_CONTROL_PAIR  asGpio[1];              // the real gpio pin pair determined by number of pins ucNumberOfPins
4421 }ATOM_OBJECT_GPIO_CNTL_RECORD;
4422
4423 //Definitions for GPIO pin state
4424 #define GPIO_PIN_TYPE_INPUT             0x00
4425 #define GPIO_PIN_TYPE_OUTPUT            0x10
4426 #define GPIO_PIN_TYPE_HW_CONTROL        0x20
4427
4428 //For GPIO_PIN_TYPE_OUTPUT the following is defined
4429 #define GPIO_PIN_OUTPUT_STATE_MASK      0x01
4430 #define GPIO_PIN_OUTPUT_STATE_SHIFT     0
4431 #define GPIO_PIN_STATE_ACTIVE_LOW       0x0
4432 #define GPIO_PIN_STATE_ACTIVE_HIGH      0x1
4433
4434 // Indexes to GPIO array in GLSync record
4435 // GLSync record is for Frame Lock/Gen Lock feature.
4436 #define ATOM_GPIO_INDEX_GLSYNC_REFCLK    0
4437 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC     1
4438 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC     2
4439 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ  3
4440 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT  4
4441 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5
4442 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET   6
4443 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7
4444 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL  8
4445 #define ATOM_GPIO_INDEX_GLSYNC_MAX       9
4446
4447 typedef struct  _ATOM_ENCODER_DVO_CF_RECORD
4448 {
4449   ATOM_COMMON_RECORD_HEADER   sheader;
4450   ULONG                       ulStrengthControl;      // DVOA strength control for CF
4451   UCHAR                       ucPadding[2];
4452 }ATOM_ENCODER_DVO_CF_RECORD;
4453
4454 // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap
4455 #define ATOM_ENCODER_CAP_RECORD_HBR2                  0x01         // DP1.2 HBR2 is supported by HW encoder
4456 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN               0x02         // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
4457 #define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN          0x04         // HDMI2.0 6Gbps enable or not.
4458
4459 typedef struct  _ATOM_ENCODER_CAP_RECORD
4460 {
4461   ATOM_COMMON_RECORD_HEADER   sheader;
4462   union {
4463     USHORT                    usEncoderCap;
4464     struct {
4465 #if ATOM_BIG_ENDIAN
4466       USHORT                  usReserved:14;        // Bit1-15 may be defined for other capability in future
4467       USHORT                  usHBR2En:1;           // Bit1 is for DP1.2 HBR2 enable
4468       USHORT                  usHBR2Cap:1;          // Bit0 is for DP1.2 HBR2 capability.
4469 #else
4470       USHORT                  usHBR2Cap:1;          // Bit0 is for DP1.2 HBR2 capability.
4471       USHORT                  usHBR2En:1;           // Bit1 is for DP1.2 HBR2 enable
4472       USHORT                  usReserved:14;        // Bit1-15 may be defined for other capability in future
4473 #endif
4474     };
4475   };
4476 }ATOM_ENCODER_CAP_RECORD;
4477
4478 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle
4479 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA   1
4480 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB   2
4481
4482 typedef struct  _ATOM_CONNECTOR_CF_RECORD
4483 {
4484   ATOM_COMMON_RECORD_HEADER   sheader;
4485   USHORT                      usMaxPixClk;
4486   UCHAR                       ucFlowCntlGpioId;
4487   UCHAR                       ucSwapCntlGpioId;
4488   UCHAR                       ucConnectedDvoBundle;
4489   UCHAR                       ucPadding;
4490 }ATOM_CONNECTOR_CF_RECORD;
4491
4492 typedef struct  _ATOM_CONNECTOR_HARDCODE_DTD_RECORD
4493 {
4494   ATOM_COMMON_RECORD_HEADER   sheader;
4495    ATOM_DTD_FORMAT                     asTiming;
4496 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD;
4497
4498 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD
4499 {
4500   ATOM_COMMON_RECORD_HEADER   sheader;                //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE
4501   UCHAR                       ucSubConnectorType;     //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
4502   UCHAR                       ucReserved;
4503 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD;
4504
4505
4506 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD
4507 {
4508    ATOM_COMMON_RECORD_HEADER   sheader;
4509    UCHAR                                    ucMuxType;                     //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
4510    UCHAR                                    ucMuxControlPin;
4511    UCHAR                                    ucMuxState[2];               //for alligment purpose
4512 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD;
4513
4514 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
4515 {
4516    ATOM_COMMON_RECORD_HEADER   sheader;
4517    UCHAR                                    ucMuxType;
4518    UCHAR                                    ucMuxControlPin;
4519    UCHAR                                    ucMuxState[2];               //for alligment purpose
4520 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD;
4521
4522 // define ucMuxType
4523 #define ATOM_ROUTER_MUX_PIN_STATE_MASK                        0x0f
4524 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT      0x01
4525
4526 typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD     //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
4527 {
4528   ATOM_COMMON_RECORD_HEADER   sheader;
4529   UCHAR                       ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES];  //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
4530 }ATOM_CONNECTOR_HPDPIN_LUT_RECORD;
4531
4532 typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD  //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
4533 {
4534   ATOM_COMMON_RECORD_HEADER   sheader;
4535   ATOM_I2C_ID_CONFIG          ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES];  //An fixed size array which maps external pins to internal DDC ID
4536 }ATOM_CONNECTOR_AUXDDC_LUT_RECORD;
4537
4538 typedef struct _ATOM_OBJECT_LINK_RECORD
4539 {
4540   ATOM_COMMON_RECORD_HEADER   sheader;
4541   USHORT                      usObjectID;         //could be connector, encorder or other object in object.h
4542 }ATOM_OBJECT_LINK_RECORD;
4543
4544 typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD
4545 {
4546   ATOM_COMMON_RECORD_HEADER   sheader;
4547   USHORT                      usReserved;
4548 }ATOM_CONNECTOR_REMOTE_CAP_RECORD;
4549
4550 typedef struct  _ATOM_CONNECTOR_LAYOUT_INFO
4551 {
4552    USHORT usConnectorObjectId;
4553    UCHAR  ucConnectorType;
4554    UCHAR  ucPosition;
4555 }ATOM_CONNECTOR_LAYOUT_INFO;
4556
4557 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
4558 #define CONNECTOR_TYPE_DVI_D                 1
4559 #define CONNECTOR_TYPE_DVI_I                 2
4560 #define CONNECTOR_TYPE_VGA                   3
4561 #define CONNECTOR_TYPE_HDMI                  4
4562 #define CONNECTOR_TYPE_DISPLAY_PORT          5
4563 #define CONNECTOR_TYPE_MINI_DISPLAY_PORT     6
4564
4565 typedef struct  _ATOM_BRACKET_LAYOUT_RECORD
4566 {
4567   ATOM_COMMON_RECORD_HEADER   sheader;
4568   UCHAR                       ucLength;
4569   UCHAR                       ucWidth;
4570   UCHAR                       ucConnNum;
4571   UCHAR                       ucReserved;
4572   ATOM_CONNECTOR_LAYOUT_INFO  asConnInfo[1];
4573 }ATOM_BRACKET_LAYOUT_RECORD;
4574
4575
4576 /****************************************************************************/
4577 // Structure used in XXXX
4578 /****************************************************************************/
4579 typedef struct  _ATOM_VOLTAGE_INFO_HEADER
4580 {
4581    USHORT   usVDDCBaseLevel;                //In number of 50mv unit
4582    USHORT   usReserved;                     //For possible extension table offset
4583    UCHAR    ucNumOfVoltageEntries;
4584    UCHAR    ucBytesPerVoltageEntry;
4585    UCHAR    ucVoltageStep;                  //Indicating in how many mv increament is one step, 0.5mv unit
4586    UCHAR    ucDefaultVoltageEntry;
4587    UCHAR    ucVoltageControlI2cLine;
4588    UCHAR    ucVoltageControlAddress;
4589    UCHAR    ucVoltageControlOffset;
4590 }ATOM_VOLTAGE_INFO_HEADER;
4591
4592 typedef struct  _ATOM_VOLTAGE_INFO
4593 {
4594    ATOM_COMMON_TABLE_HEADER   sHeader;
4595    ATOM_VOLTAGE_INFO_HEADER viHeader;
4596    UCHAR    ucVoltageEntries[64];            //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
4597 }ATOM_VOLTAGE_INFO;
4598
4599
4600 typedef struct  _ATOM_VOLTAGE_FORMULA
4601 {
4602    USHORT   usVoltageBaseLevel;             // In number of 1mv unit
4603    USHORT   usVoltageStep;                  // Indicating in how many mv increament is one step, 1mv unit
4604    UCHAR    ucNumOfVoltageEntries;          // Number of Voltage Entry, which indicate max Voltage
4605    UCHAR    ucFlag;                         // bit0=0 :step is 1mv =1 0.5mv
4606    UCHAR    ucBaseVID;                      // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
4607    UCHAR    ucReserved;
4608    UCHAR    ucVIDAdjustEntries[32];         // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
4609 }ATOM_VOLTAGE_FORMULA;
4610
4611 typedef struct  _VOLTAGE_LUT_ENTRY
4612 {
4613     USHORT     usVoltageCode;               // The Voltage ID, either GPIO or I2C code
4614     USHORT     usVoltageValue;              // The corresponding Voltage Value, in mV
4615 }VOLTAGE_LUT_ENTRY;
4616
4617 typedef struct  _ATOM_VOLTAGE_FORMULA_V2
4618 {
4619     UCHAR      ucNumOfVoltageEntries;               // Number of Voltage Entry, which indicate max Voltage
4620     UCHAR      ucReserved[3];
4621     VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries
4622 }ATOM_VOLTAGE_FORMULA_V2;
4623
4624 typedef struct _ATOM_VOLTAGE_CONTROL
4625 {
4626   UCHAR    ucVoltageControlId;                     //Indicate it is controlled by I2C or GPIO or HW state machine
4627   UCHAR    ucVoltageControlI2cLine;
4628   UCHAR    ucVoltageControlAddress;
4629   UCHAR    ucVoltageControlOffset;
4630   USHORT   usGpioPin_AIndex;                       //GPIO_PAD register index
4631   UCHAR    ucGpioPinBitShift[9];                   //at most 8 pin support 255 VIDs, termintate with 0xff
4632   UCHAR    ucReserved;
4633 }ATOM_VOLTAGE_CONTROL;
4634
4635 // Define ucVoltageControlId
4636 #define VOLTAGE_CONTROLLED_BY_HW              0x00
4637 #define VOLTAGE_CONTROLLED_BY_I2C_MASK        0x7F
4638 #define VOLTAGE_CONTROLLED_BY_GPIO            0x80
4639 #define VOLTAGE_CONTROL_ID_LM64               0x01                           //I2C control, used for R5xx Core Voltage
4640 #define VOLTAGE_CONTROL_ID_DAC                0x02                           //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI
4641 #define VOLTAGE_CONTROL_ID_VT116xM            0x03                           //I2C control, used for R6xx Core Voltage
4642 #define VOLTAGE_CONTROL_ID_DS4402             0x04
4643 #define VOLTAGE_CONTROL_ID_UP6266             0x05
4644 #define VOLTAGE_CONTROL_ID_SCORPIO            0x06
4645 #define VOLTAGE_CONTROL_ID_VT1556M            0x07
4646 #define VOLTAGE_CONTROL_ID_CHL822x            0x08
4647 #define VOLTAGE_CONTROL_ID_VT1586M            0x09
4648 #define VOLTAGE_CONTROL_ID_UP1637             0x0A
4649 #define VOLTAGE_CONTROL_ID_CHL8214            0x0B
4650 #define VOLTAGE_CONTROL_ID_UP1801             0x0C
4651 #define VOLTAGE_CONTROL_ID_ST6788A            0x0D
4652 #define VOLTAGE_CONTROL_ID_CHLIR3564SVI2      0x0E
4653 #define VOLTAGE_CONTROL_ID_AD527x             0x0F
4654 #define VOLTAGE_CONTROL_ID_NCP81022           0x10
4655 #define VOLTAGE_CONTROL_ID_LTC2635                        0x11
4656 #define VOLTAGE_CONTROL_ID_NCP4208                0x12
4657 #define VOLTAGE_CONTROL_ID_IR35xx             0x13
4658 #define VOLTAGE_CONTROL_ID_RT9403                 0x14
4659
4660 #define VOLTAGE_CONTROL_ID_GENERIC_I2C        0x40
4661
4662 typedef struct  _ATOM_VOLTAGE_OBJECT
4663 {
4664    UCHAR      ucVoltageType;                           //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4665    UCHAR      ucSize;                                       //Size of Object
4666    ATOM_VOLTAGE_CONTROL         asControl;         //describ how to control
4667    ATOM_VOLTAGE_FORMULA         asFormula;         //Indicate How to convert real Voltage to VID
4668 }ATOM_VOLTAGE_OBJECT;
4669
4670 typedef struct  _ATOM_VOLTAGE_OBJECT_V2
4671 {
4672     UCHAR ucVoltageType;                      //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4673     UCHAR ucSize;                             //Size of Object
4674     ATOM_VOLTAGE_CONTROL    asControl;        //describ how to control
4675     ATOM_VOLTAGE_FORMULA_V2 asFormula;        //Indicate How to convert real Voltage to VID
4676 }ATOM_VOLTAGE_OBJECT_V2;
4677
4678 typedef struct  _ATOM_VOLTAGE_OBJECT_INFO
4679 {
4680    ATOM_COMMON_TABLE_HEADER   sHeader;
4681    ATOM_VOLTAGE_OBJECT        asVoltageObj[3];   //Info for Voltage control
4682 }ATOM_VOLTAGE_OBJECT_INFO;
4683
4684 typedef struct  _ATOM_VOLTAGE_OBJECT_INFO_V2
4685 {
4686    ATOM_COMMON_TABLE_HEADER   sHeader;
4687     ATOM_VOLTAGE_OBJECT_V2    asVoltageObj[3];   //Info for Voltage control
4688 }ATOM_VOLTAGE_OBJECT_INFO_V2;
4689
4690 typedef struct  _ATOM_LEAKID_VOLTAGE
4691 {
4692    UCHAR    ucLeakageId;
4693    UCHAR    ucReserved;
4694    USHORT   usVoltage;
4695 }ATOM_LEAKID_VOLTAGE;
4696
4697 typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{
4698    UCHAR    ucVoltageType;                            //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
4699    UCHAR    ucVoltageMode;                            //Indicate voltage control mode: Init/Set/Leakage/Set phase
4700    USHORT   usSize;                                   //Size of Object
4701 }ATOM_VOLTAGE_OBJECT_HEADER_V3;
4702
4703 // ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode
4704 #define VOLTAGE_OBJ_GPIO_LUT                 0        //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
4705 #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ          3        //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3
4706 #define VOLTAGE_OBJ_PHASE_LUT                4        //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3
4707 #define VOLTAGE_OBJ_SVID2                    7        //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3
4708 #define VOLTAGE_OBJ_EVV                      8
4709 #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT     0x10     //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
4710 #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT   0x11     //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
4711 #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT  0x12     //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
4712
4713 typedef struct  _VOLTAGE_LUT_ENTRY_V2
4714 {
4715   ULONG   ulVoltageId;                       // The Voltage ID which is used to program GPIO register
4716   USHORT  usVoltageValue;                    // The corresponding Voltage Value, in mV
4717 }VOLTAGE_LUT_ENTRY_V2;
4718
4719 typedef struct  _LEAKAGE_VOLTAGE_LUT_ENTRY_V2
4720 {
4721   USHORT  usVoltageLevel;                    // The Voltage ID which is used to program GPIO register
4722   USHORT  usVoltageId;
4723   USHORT  usLeakageId;                       // The corresponding Voltage Value, in mV
4724 }LEAKAGE_VOLTAGE_LUT_ENTRY_V2;
4725
4726
4727 typedef struct  _ATOM_I2C_VOLTAGE_OBJECT_V3
4728 {
4729    ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
4730    UCHAR  ucVoltageRegulatorId;              //Indicate Voltage Regulator Id
4731    UCHAR  ucVoltageControlI2cLine;
4732    UCHAR  ucVoltageControlAddress;
4733    UCHAR  ucVoltageControlOffset;
4734    UCHAR  ucVoltageControlFlag;              // Bit0: 0 - One byte data; 1 - Two byte data
4735    UCHAR  ulReserved[3];
4736    VOLTAGE_LUT_ENTRY asVolI2cLut[1];         // end with 0xff
4737 }ATOM_I2C_VOLTAGE_OBJECT_V3;
4738
4739 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
4740 #define VOLTAGE_DATA_ONE_BYTE                0
4741 #define VOLTAGE_DATA_TWO_BYTE                1
4742
4743 typedef struct  _ATOM_GPIO_VOLTAGE_OBJECT_V3
4744 {
4745    ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
4746    UCHAR  ucVoltageGpioCntlId;               // default is 0 which indicate control through CG VID mode
4747    UCHAR  ucGpioEntryNum;                    // indiate the entry numbers of Votlage/Gpio value Look up table
4748    UCHAR  ucPhaseDelay;                      // phase delay in unit of micro second
4749    UCHAR  ucReserved;
4750    ULONG  ulGpioMaskVal;                     // GPIO Mask value
4751    VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1];
4752 }ATOM_GPIO_VOLTAGE_OBJECT_V3;
4753
4754 typedef struct  _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3
4755 {
4756    ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = 0x10/0x11/0x12
4757    UCHAR    ucLeakageCntlId;                 // default is 0
4758    UCHAR    ucLeakageEntryNum;               // indicate the entry number of LeakageId/Voltage Lut table
4759    UCHAR    ucReserved[2];
4760    ULONG    ulMaxVoltageLevel;
4761    LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1];
4762 }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3;
4763
4764
4765 typedef struct  _ATOM_SVID2_VOLTAGE_OBJECT_V3
4766 {
4767    ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader;    // voltage mode = VOLTAGE_OBJ_SVID2
4768 // 14:7 � PSI0_VID
4769 // 6 � PSI0_EN
4770 // 5 � PSI1
4771 // 4:2 � load line slope trim.
4772 // 1:0 � offset trim,
4773    USHORT   usLoadLine_PSI;
4774 // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31
4775    UCHAR    ucSVDGpioId;     //0~31 indicate GPIO0~31
4776    UCHAR    ucSVCGpioId;     //0~31 indicate GPIO0~31
4777    ULONG    ulReserved;
4778 }ATOM_SVID2_VOLTAGE_OBJECT_V3;
4779
4780 typedef union _ATOM_VOLTAGE_OBJECT_V3{
4781   ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj;
4782   ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj;
4783   ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj;
4784   ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj;
4785 }ATOM_VOLTAGE_OBJECT_V3;
4786
4787 typedef struct  _ATOM_VOLTAGE_OBJECT_INFO_V3_1
4788 {
4789   ATOM_COMMON_TABLE_HEADER   sHeader;
4790   ATOM_VOLTAGE_OBJECT_V3     asVoltageObj[3];   //Info for Voltage control
4791 }ATOM_VOLTAGE_OBJECT_INFO_V3_1;
4792
4793
4794 typedef struct  _ATOM_ASIC_PROFILE_VOLTAGE
4795 {
4796    UCHAR    ucProfileId;
4797    UCHAR    ucReserved;
4798    USHORT   usSize;
4799    USHORT   usEfuseSpareStartAddr;
4800    USHORT   usFuseIndex[8];                                    //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id,
4801    ATOM_LEAKID_VOLTAGE               asLeakVol[2];         //Leakid and relatd voltage
4802 }ATOM_ASIC_PROFILE_VOLTAGE;
4803
4804 //ucProfileId
4805 #define   ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE                     1
4806 #define   ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE         1
4807 #define   ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE             2
4808
4809 typedef struct  _ATOM_ASIC_PROFILING_INFO
4810 {
4811   ATOM_COMMON_TABLE_HEADER         asHeader;
4812   ATOM_ASIC_PROFILE_VOLTAGE        asVoltage;
4813 }ATOM_ASIC_PROFILING_INFO;
4814
4815 typedef struct  _ATOM_ASIC_PROFILING_INFO_V2_1
4816 {
4817   ATOM_COMMON_TABLE_HEADER         asHeader;
4818   UCHAR  ucLeakageBinNum;                // indicate the entry number of LeakageId/Voltage Lut table
4819   USHORT usLeakageBinArrayOffset;        // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher)
4820
4821   UCHAR  ucElbVDDC_Num;
4822   USHORT usElbVDDC_IdArrayOffset;        // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 )
4823   USHORT usElbVDDC_LevelArrayOffset;     // offset of 2 dimension voltage level USHORT array
4824
4825   UCHAR  ucElbVDDCI_Num;
4826   USHORT usElbVDDCI_IdArrayOffset;       // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 )
4827   USHORT usElbVDDCI_LevelArrayOffset;    // offset of 2 dimension voltage level USHORT array
4828 }ATOM_ASIC_PROFILING_INFO_V2_1;
4829
4830
4831 //Here is parameter to convert Efuse value to Measure value
4832 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2
4833 typedef struct _EFUSE_LOGISTIC_FUNC_PARAM
4834 {
4835   USHORT usEfuseIndex;                  // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
4836   UCHAR  ucEfuseBitLSB;                 // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
4837   UCHAR  ucEfuseLength;                 // Efuse bits length,
4838   ULONG  ulEfuseEncodeRange;            // Range = Max - Min, bit31 indicate the efuse is negative number
4839   ULONG  ulEfuseEncodeAverage;          // Average = ( Max + Min )/2
4840 }EFUSE_LOGISTIC_FUNC_PARAM;
4841
4842 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min )
4843 typedef struct _EFUSE_LINEAR_FUNC_PARAM
4844 {
4845   USHORT usEfuseIndex;                  // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112
4846   UCHAR  ucEfuseBitLSB;                 // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
4847   UCHAR  ucEfuseLength;                 // Efuse bits length,
4848   ULONG  ulEfuseEncodeRange;            // Range = Max - Min, bit31 indicate the efuse is negative number
4849   ULONG  ulEfuseMin;                    // Min
4850 }EFUSE_LINEAR_FUNC_PARAM;
4851
4852
4853 typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_1
4854 {
4855   ATOM_COMMON_TABLE_HEADER         asHeader;
4856   ULONG  ulEvvDerateTdp;
4857   ULONG  ulEvvDerateTdc;
4858   ULONG  ulBoardCoreTemp;
4859   ULONG  ulMaxVddc;
4860   ULONG  ulMinVddc;
4861   ULONG  ulLoadLineSlop;
4862   ULONG  ulLeakageTemp;
4863   ULONG  ulLeakageVoltage;
4864   EFUSE_LINEAR_FUNC_PARAM sCACm;
4865   EFUSE_LINEAR_FUNC_PARAM sCACb;
4866   EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
4867   EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
4868   EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
4869   USHORT usLkgEuseIndex;
4870   UCHAR  ucLkgEfuseBitLSB;
4871   UCHAR  ucLkgEfuseLength;
4872   ULONG  ulLkgEncodeLn_MaxDivMin;
4873   ULONG  ulLkgEncodeMax;
4874   ULONG  ulLkgEncodeMin;
4875   ULONG  ulEfuseLogisticAlpha;
4876   USHORT usPowerDpm0;
4877   USHORT usCurrentDpm0;
4878   USHORT usPowerDpm1;
4879   USHORT usCurrentDpm1;
4880   USHORT usPowerDpm2;
4881   USHORT usCurrentDpm2;
4882   USHORT usPowerDpm3;
4883   USHORT usCurrentDpm3;
4884   USHORT usPowerDpm4;
4885   USHORT usCurrentDpm4;
4886   USHORT usPowerDpm5;
4887   USHORT usCurrentDpm5;
4888   USHORT usPowerDpm6;
4889   USHORT usCurrentDpm6;
4890   USHORT usPowerDpm7;
4891   USHORT usCurrentDpm7;
4892 }ATOM_ASIC_PROFILING_INFO_V3_1;
4893
4894
4895 typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_2
4896 {
4897   ATOM_COMMON_TABLE_HEADER         asHeader;
4898   ULONG  ulEvvLkgFactor;
4899   ULONG  ulBoardCoreTemp;
4900   ULONG  ulMaxVddc;
4901   ULONG  ulMinVddc;
4902   ULONG  ulLoadLineSlop;
4903   ULONG  ulLeakageTemp;
4904   ULONG  ulLeakageVoltage;
4905   EFUSE_LINEAR_FUNC_PARAM sCACm;
4906   EFUSE_LINEAR_FUNC_PARAM sCACb;
4907   EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
4908   EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
4909   EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
4910   USHORT usLkgEuseIndex;
4911   UCHAR  ucLkgEfuseBitLSB;
4912   UCHAR  ucLkgEfuseLength;
4913   ULONG  ulLkgEncodeLn_MaxDivMin;
4914   ULONG  ulLkgEncodeMax;
4915   ULONG  ulLkgEncodeMin;
4916   ULONG  ulEfuseLogisticAlpha;
4917   USHORT usPowerDpm0;
4918   USHORT usPowerDpm1;
4919   USHORT usPowerDpm2;
4920   USHORT usPowerDpm3;
4921   USHORT usPowerDpm4;
4922   USHORT usPowerDpm5;
4923   USHORT usPowerDpm6;
4924   USHORT usPowerDpm7;
4925   ULONG  ulTdpDerateDPM0;
4926   ULONG  ulTdpDerateDPM1;
4927   ULONG  ulTdpDerateDPM2;
4928   ULONG  ulTdpDerateDPM3;
4929   ULONG  ulTdpDerateDPM4;
4930   ULONG  ulTdpDerateDPM5;
4931   ULONG  ulTdpDerateDPM6;
4932   ULONG  ulTdpDerateDPM7;
4933 }ATOM_ASIC_PROFILING_INFO_V3_2;
4934
4935
4936 // for Tonga/Fiji speed EVV algorithm
4937 typedef struct  _ATOM_ASIC_PROFILING_INFO_V3_3
4938 {
4939   ATOM_COMMON_TABLE_HEADER         asHeader;
4940   ULONG  ulEvvLkgFactor;
4941   ULONG  ulBoardCoreTemp;
4942   ULONG  ulMaxVddc;
4943   ULONG  ulMinVddc;
4944   ULONG  ulLoadLineSlop;
4945   ULONG  ulLeakageTemp;
4946   ULONG  ulLeakageVoltage;
4947   EFUSE_LINEAR_FUNC_PARAM sCACm;
4948   EFUSE_LINEAR_FUNC_PARAM sCACb;
4949   EFUSE_LOGISTIC_FUNC_PARAM sKt_b;
4950   EFUSE_LOGISTIC_FUNC_PARAM sKv_m;
4951   EFUSE_LOGISTIC_FUNC_PARAM sKv_b;
4952   USHORT usLkgEuseIndex;
4953   UCHAR  ucLkgEfuseBitLSB;
4954   UCHAR  ucLkgEfuseLength;
4955   ULONG  ulLkgEncodeLn_MaxDivMin;
4956   ULONG  ulLkgEncodeMax;
4957   ULONG  ulLkgEncodeMin;
4958   ULONG  ulEfuseLogisticAlpha;
4959   USHORT usPowerDpm0;
4960   USHORT usPowerDpm1;
4961   USHORT usPowerDpm2;
4962   USHORT usPowerDpm3;
4963   USHORT usPowerDpm4;
4964   USHORT usPowerDpm5;
4965   USHORT usPowerDpm6;
4966   USHORT usPowerDpm7;
4967   ULONG  ulTdpDerateDPM0;
4968   ULONG  ulTdpDerateDPM1;
4969   ULONG  ulTdpDerateDPM2;
4970   ULONG  ulTdpDerateDPM3;
4971   ULONG  ulTdpDerateDPM4;
4972   ULONG  ulTdpDerateDPM5;
4973   ULONG  ulTdpDerateDPM6;
4974   ULONG  ulTdpDerateDPM7;
4975   EFUSE_LINEAR_FUNC_PARAM sRoFuse;
4976   ULONG  ulRoAlpha;
4977   ULONG  ulRoBeta;
4978   ULONG  ulRoGamma;
4979   ULONG  ulRoEpsilon;
4980   ULONG  ulATermRo;
4981   ULONG  ulBTermRo;
4982   ULONG  ulCTermRo;
4983   ULONG  ulSclkMargin;
4984   ULONG  ulFmaxPercent;
4985   ULONG  ulCRPercent;
4986   ULONG  ulSFmaxPercent;
4987   ULONG  ulSCRPercent;
4988   ULONG  ulSDCMargine;
4989 }ATOM_ASIC_PROFILING_INFO_V3_3;
4990
4991 typedef struct _ATOM_POWER_SOURCE_OBJECT
4992 {
4993    UCHAR  ucPwrSrcId;                                   // Power source
4994    UCHAR  ucPwrSensorType;                              // GPIO, I2C or none
4995    UCHAR  ucPwrSensId;                                  // if GPIO detect, it is GPIO id,  if I2C detect, it is I2C id
4996    UCHAR  ucPwrSensSlaveAddr;                           // Slave address if I2C detect
4997    UCHAR  ucPwrSensRegIndex;                            // I2C register Index if I2C detect
4998    UCHAR  ucPwrSensRegBitMask;                          // detect which bit is used if I2C detect
4999    UCHAR  ucPwrSensActiveState;                         // high active or low active
5000    UCHAR  ucReserve[3];                                 // reserve
5001    USHORT usSensPwr;                                    // in unit of watt
5002 }ATOM_POWER_SOURCE_OBJECT;
5003
5004 typedef struct _ATOM_POWER_SOURCE_INFO
5005 {
5006       ATOM_COMMON_TABLE_HEADER      asHeader;
5007       UCHAR                                    asPwrbehave[16];
5008       ATOM_POWER_SOURCE_OBJECT      asPwrObj[1];
5009 }ATOM_POWER_SOURCE_INFO;
5010
5011
5012 //Define ucPwrSrcId
5013 #define POWERSOURCE_PCIE_ID1                  0x00
5014 #define POWERSOURCE_6PIN_CONNECTOR_ID1   0x01
5015 #define POWERSOURCE_8PIN_CONNECTOR_ID1   0x02
5016 #define POWERSOURCE_6PIN_CONNECTOR_ID2   0x04
5017 #define POWERSOURCE_8PIN_CONNECTOR_ID2   0x08
5018
5019 //define ucPwrSensorId
5020 #define POWER_SENSOR_ALWAYS                     0x00
5021 #define POWER_SENSOR_GPIO                        0x01
5022 #define POWER_SENSOR_I2C                        0x02
5023
5024 typedef struct _ATOM_CLK_VOLT_CAPABILITY
5025 {
5026   ULONG      ulVoltageIndex;                      // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table
5027   ULONG      ulMaximumSupportedCLK;               // Maximum clock supported with specified voltage index, unit in 10kHz
5028 }ATOM_CLK_VOLT_CAPABILITY;
5029
5030
5031 typedef struct _ATOM_CLK_VOLT_CAPABILITY_V2
5032 {
5033   USHORT     usVoltageLevel;                      // The real Voltage Level round up value in unit of mv,
5034   ULONG      ulMaximumSupportedCLK;               // Maximum clock supported with specified voltage index, unit in 10kHz
5035 }ATOM_CLK_VOLT_CAPABILITY_V2;
5036
5037 typedef struct _ATOM_AVAILABLE_SCLK_LIST
5038 {
5039   ULONG      ulSupportedSCLK;               // Maximum clock supported with specified voltage index,  unit in 10kHz
5040   USHORT     usVoltageIndex;                // The Voltage Index indicated by FUSE for specified SCLK
5041   USHORT     usVoltageID;                   // The Voltage ID indicated by FUSE for specified SCLK
5042 }ATOM_AVAILABLE_SCLK_LIST;
5043
5044 // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition
5045 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE             1       // refer to ulSystemConfig bit[0]
5046
5047 // this IntegrateSystemInfoTable is used for Liano/Ontario APU
5048 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
5049 {
5050   ATOM_COMMON_TABLE_HEADER   sHeader;
5051   ULONG  ulBootUpEngineClock;
5052   ULONG  ulDentistVCOFreq;
5053   ULONG  ulBootUpUMAClock;
5054   ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];
5055   ULONG  ulBootUpReqDisplayVector;
5056   ULONG  ulOtherDisplayMisc;
5057   ULONG  ulGPUCapInfo;
5058   ULONG  ulSB_MMIO_Base_Addr;
5059   USHORT usRequestedPWMFreqInHz;
5060   UCHAR  ucHtcTmpLmt;
5061   UCHAR  ucHtcHystLmt;
5062   ULONG  ulMinEngineClock;
5063   ULONG  ulSystemConfig;
5064   ULONG  ulCPUCapInfo;
5065   USHORT usNBP0Voltage;
5066   USHORT usNBP1Voltage;
5067   USHORT usBootUpNBVoltage;
5068   USHORT usExtDispConnInfoOffset;
5069   USHORT usPanelRefreshRateRange;
5070   UCHAR  ucMemoryType;
5071   UCHAR  ucUMAChannelNumber;
5072   ULONG  ulCSR_M3_ARB_CNTL_DEFAULT[10];
5073   ULONG  ulCSR_M3_ARB_CNTL_UVD[10];
5074   ULONG  ulCSR_M3_ARB_CNTL_FS3D[10];
5075   ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
5076   ULONG  ulGMCRestoreResetTime;
5077   ULONG  ulMinimumNClk;
5078   ULONG  ulIdleNClk;
5079   ULONG  ulDDR_DLL_PowerUpTime;
5080   ULONG  ulDDR_PLL_PowerUpTime;
5081   USHORT usPCIEClkSSPercentage;
5082   USHORT usPCIEClkSSType;
5083   USHORT usLvdsSSPercentage;
5084   USHORT usLvdsSSpreadRateIn10Hz;
5085   USHORT usHDMISSPercentage;
5086   USHORT usHDMISSpreadRateIn10Hz;
5087   USHORT usDVISSPercentage;
5088   USHORT usDVISSpreadRateIn10Hz;
5089   ULONG  SclkDpmBoostMargin;
5090   ULONG  SclkDpmThrottleMargin;
5091   USHORT SclkDpmTdpLimitPG;
5092   USHORT SclkDpmTdpLimitBoost;
5093   ULONG  ulBoostEngineCLock;
5094   UCHAR  ulBoostVid_2bit;
5095   UCHAR  EnableBoost;
5096   USHORT GnbTdpLimit;
5097   USHORT usMaxLVDSPclkFreqInSingleLink;
5098   UCHAR  ucLvdsMisc;
5099   UCHAR  ucLVDSReserved;
5100   ULONG  ulReserved3[15];
5101   ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
5102 }ATOM_INTEGRATED_SYSTEM_INFO_V6;
5103
5104 // ulGPUCapInfo
5105 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE       0x01
5106 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION          0x08
5107
5108 //ucLVDSMisc:
5109 #define SYS_INFO_LVDSMISC__888_FPDI_MODE                                             0x01
5110 #define SYS_INFO_LVDSMISC__DL_CH_SWAP                                                0x02
5111 #define SYS_INFO_LVDSMISC__888_BPC                                                   0x04
5112 #define SYS_INFO_LVDSMISC__OVERRIDE_EN                                               0x08
5113 #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW                                           0x10
5114 // new since Trinity
5115 #define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN                               0x20
5116
5117 // not used any more
5118 #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW                                          0x04
5119 #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW                                          0x08
5120
5121 /**********************************************************************************************************************
5122   ATOM_INTEGRATED_SYSTEM_INFO_V6 Description
5123 ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
5124 ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit.
5125 ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit.
5126 sDISPCLK_Voltage:                 Report Display clock voltage requirement.
5127
5128 ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects:
5129                                   ATOM_DEVICE_CRT1_SUPPORT                  0x0001
5130                                   ATOM_DEVICE_CRT2_SUPPORT                  0x0010
5131                                   ATOM_DEVICE_DFP1_SUPPORT                  0x0008
5132                                   ATOM_DEVICE_DFP6_SUPPORT                  0x0040
5133                                   ATOM_DEVICE_DFP2_SUPPORT                  0x0080
5134                                   ATOM_DEVICE_DFP3_SUPPORT                  0x0200
5135                                   ATOM_DEVICE_DFP4_SUPPORT                  0x0400
5136                                   ATOM_DEVICE_DFP5_SUPPORT                  0x0800
5137                                   ATOM_DEVICE_LCD1_SUPPORT                  0x0002
5138 ulOtherDisplayMisc:                 Other display related flags, not defined yet.
5139 ulGPUCapInfo:                     bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
5140                                         =1: TMDS/HDMI Coherent Mode use signel PLL mode.
5141                                   bit[3]=0: Enable HW AUX mode detection logic
5142                                         =1: Disable HW AUX mode dettion logic
5143 ulSB_MMIO_Base_Addr:              Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
5144
5145 usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5146                                   Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
5147
5148                                   When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
5149                                   1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5150                                   VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5151                                   Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5152                                   and enabling VariBri under the driver environment from PP table is optional.
5153
5154                                   2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
5155                                   that BL control from GPU is expected.
5156                                   VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5157                                   Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
5158                                   it's per platform
5159                                   and enabling VariBri under the driver environment from PP table is optional.
5160
5161 ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt.
5162                                   Threshold on value to enter HTC_active state.
5163 ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt.
5164                                   To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
5165 ulMinEngineClock:                 Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
5166 ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled
5167                                         =1: PCIE Power Gating Enabled
5168                                   Bit[1]=0: DDR-DLL shut-down feature disabled.
5169                                          1: DDR-DLL shut-down feature enabled.
5170                                   Bit[2]=0: DDR-PLL Power down feature disabled.
5171                                          1: DDR-PLL Power down feature enabled.
5172 ulCPUCapInfo:                     TBD
5173 usNBP0Voltage:                    VID for voltage on NB P0 State
5174 usNBP1Voltage:                    VID for voltage on NB P1 State
5175 usBootUpNBVoltage:                Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
5176 usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
5177 usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
5178                                   to indicate a range.
5179                                   SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
5180                                   SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
5181                                   SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
5182                                   SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
5183 ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5184 ucUMAChannelNumber:                 System memory channel numbers.
5185 ulCSR_M3_ARB_CNTL_DEFAULT[10]:    Arrays with values for CSR M3 arbiter for default
5186 ulCSR_M3_ARB_CNTL_UVD[10]:        Arrays with values for CSR M3 arbiter for UVD playback.
5187 ulCSR_M3_ARB_CNTL_FS3D[10]:       Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
5188 sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
5189 ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
5190 ulMinimumNClk:                    Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
5191 ulIdleNClk:                       NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5192 ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
5193 ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
5194 usPCIEClkSSPercentage:            PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%.
5195 usPCIEClkSSType:                  PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread.
5196 usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
5197 usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
5198 usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
5199 usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
5200 usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
5201 usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
5202 usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
5203 ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
5204                                   [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
5205                                   [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
5206                                   [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
5207                                   [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
5208 **********************************************************************************************************************/
5209
5210 // this Table is used for Liano/Ontario APU
5211 typedef struct _ATOM_FUSION_SYSTEM_INFO_V1
5212 {
5213   ATOM_INTEGRATED_SYSTEM_INFO_V6    sIntegratedSysInfo;
5214   ULONG  ulPowerplayTable[128];
5215 }ATOM_FUSION_SYSTEM_INFO_V1;
5216
5217
5218 typedef struct _ATOM_TDP_CONFIG_BITS
5219 {
5220 #if ATOM_BIG_ENDIAN
5221   ULONG   uReserved:2;
5222   ULONG   uTDP_Value:14;  // Original TDP value in tens of milli watts
5223   ULONG   uCTDP_Value:14; // Override value in tens of milli watts
5224   ULONG   uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5225 #else
5226   ULONG   uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value))
5227   ULONG   uCTDP_Value:14; // Override value in tens of milli watts
5228   ULONG   uTDP_Value:14;  // Original TDP value in tens of milli watts
5229   ULONG   uReserved:2;
5230 #endif
5231 }ATOM_TDP_CONFIG_BITS;
5232
5233 typedef union _ATOM_TDP_CONFIG
5234 {
5235   ATOM_TDP_CONFIG_BITS TDP_config;
5236   ULONG            TDP_config_all;
5237 }ATOM_TDP_CONFIG;
5238
5239 /**********************************************************************************************************************
5240   ATOM_FUSION_SYSTEM_INFO_V1 Description
5241 sIntegratedSysInfo:               refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition.
5242 ulPowerplayTable[128]:            This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0]
5243 **********************************************************************************************************************/
5244
5245 // this IntegrateSystemInfoTable is used for Trinity APU
5246 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7
5247 {
5248   ATOM_COMMON_TABLE_HEADER   sHeader;
5249   ULONG  ulBootUpEngineClock;
5250   ULONG  ulDentistVCOFreq;
5251   ULONG  ulBootUpUMAClock;
5252   ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];
5253   ULONG  ulBootUpReqDisplayVector;
5254   ULONG  ulOtherDisplayMisc;
5255   ULONG  ulGPUCapInfo;
5256   ULONG  ulSB_MMIO_Base_Addr;
5257   USHORT usRequestedPWMFreqInHz;
5258   UCHAR  ucHtcTmpLmt;
5259   UCHAR  ucHtcHystLmt;
5260   ULONG  ulMinEngineClock;
5261   ULONG  ulSystemConfig;
5262   ULONG  ulCPUCapInfo;
5263   USHORT usNBP0Voltage;
5264   USHORT usNBP1Voltage;
5265   USHORT usBootUpNBVoltage;
5266   USHORT usExtDispConnInfoOffset;
5267   USHORT usPanelRefreshRateRange;
5268   UCHAR  ucMemoryType;
5269   UCHAR  ucUMAChannelNumber;
5270   UCHAR  strVBIOSMsg[40];
5271   ATOM_TDP_CONFIG  asTdpConfig;
5272   ULONG  ulReserved[19];
5273   ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
5274   ULONG  ulGMCRestoreResetTime;
5275   ULONG  ulMinimumNClk;
5276   ULONG  ulIdleNClk;
5277   ULONG  ulDDR_DLL_PowerUpTime;
5278   ULONG  ulDDR_PLL_PowerUpTime;
5279   USHORT usPCIEClkSSPercentage;
5280   USHORT usPCIEClkSSType;
5281   USHORT usLvdsSSPercentage;
5282   USHORT usLvdsSSpreadRateIn10Hz;
5283   USHORT usHDMISSPercentage;
5284   USHORT usHDMISSpreadRateIn10Hz;
5285   USHORT usDVISSPercentage;
5286   USHORT usDVISSpreadRateIn10Hz;
5287   ULONG  SclkDpmBoostMargin;
5288   ULONG  SclkDpmThrottleMargin;
5289   USHORT SclkDpmTdpLimitPG;
5290   USHORT SclkDpmTdpLimitBoost;
5291   ULONG  ulBoostEngineCLock;
5292   UCHAR  ulBoostVid_2bit;
5293   UCHAR  EnableBoost;
5294   USHORT GnbTdpLimit;
5295   USHORT usMaxLVDSPclkFreqInSingleLink;
5296   UCHAR  ucLvdsMisc;
5297   UCHAR  ucTravisLVDSVolAdjust;
5298   UCHAR  ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5299   UCHAR  ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5300   UCHAR  ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5301   UCHAR  ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5302   UCHAR  ucLVDSOffToOnDelay_in4Ms;
5303   UCHAR  ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5304   UCHAR  ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5305   UCHAR  ucMinAllowedBL_Level;
5306   ULONG  ulLCDBitDepthControlVal;
5307   ULONG  ulNbpStateMemclkFreq[4];
5308   USHORT usNBP2Voltage;
5309   USHORT usNBP3Voltage;
5310   ULONG  ulNbpStateNClkFreq[4];
5311   UCHAR  ucNBDPMEnable;
5312   UCHAR  ucReserved[3];
5313   UCHAR  ucDPMState0VclkFid;
5314   UCHAR  ucDPMState0DclkFid;
5315   UCHAR  ucDPMState1VclkFid;
5316   UCHAR  ucDPMState1DclkFid;
5317   UCHAR  ucDPMState2VclkFid;
5318   UCHAR  ucDPMState2DclkFid;
5319   UCHAR  ucDPMState3VclkFid;
5320   UCHAR  ucDPMState3DclkFid;
5321   ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
5322 }ATOM_INTEGRATED_SYSTEM_INFO_V1_7;
5323
5324 // ulOtherDisplayMisc
5325 #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT            0x01
5326 #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT  0x02
5327 #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT       0x04
5328 #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT                         0x08
5329
5330 // ulGPUCapInfo
5331 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE                0x01
5332 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE                               0x02
5333 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT                         0x08
5334 #define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS                               0x10
5335 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML
5336 #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE                         0x00010000
5337
5338 //ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML
5339 #define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE                            0x00020000
5340
5341 /**********************************************************************************************************************
5342   ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description
5343 ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
5344 ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit.
5345 ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit.
5346 sDISPCLK_Voltage:                 Report Display clock voltage requirement.
5347
5348 ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Trinity projects:
5349                                   ATOM_DEVICE_CRT1_SUPPORT                  0x0001
5350                                   ATOM_DEVICE_DFP1_SUPPORT                  0x0008
5351                                   ATOM_DEVICE_DFP6_SUPPORT                  0x0040
5352                                   ATOM_DEVICE_DFP2_SUPPORT                  0x0080
5353                                   ATOM_DEVICE_DFP3_SUPPORT                  0x0200
5354                                   ATOM_DEVICE_DFP4_SUPPORT                  0x0400
5355                                   ATOM_DEVICE_DFP5_SUPPORT                  0x0800
5356                                   ATOM_DEVICE_LCD1_SUPPORT                  0x0002
5357 ulOtherDisplayMisc:                 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
5358                                         =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
5359                                   bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
5360                                         =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
5361                                   bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
5362                                         =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
5363                                   bit[3]=0: VBIOS fast boot is disable
5364                                         =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
5365 ulGPUCapInfo:                     bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode.
5366                                         =1: TMDS/HDMI Coherent Mode use signel PLL mode.
5367                                   bit[1]=0: DP mode use cascade PLL mode ( New for Trinity )
5368                                         =1: DP mode use single PLL mode
5369                                   bit[3]=0: Enable AUX HW mode detection logic
5370                                         =1: Disable AUX HW mode detection logic
5371
5372 ulSB_MMIO_Base_Addr:              Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage.
5373
5374 usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5375                                   Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
5376
5377                                   When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
5378                                   1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5379                                   VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5380                                   Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5381                                   and enabling VariBri under the driver environment from PP table is optional.
5382
5383                                   2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
5384                                   that BL control from GPU is expected.
5385                                   VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5386                                   Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
5387                                   it's per platform
5388                                   and enabling VariBri under the driver environment from PP table is optional.
5389
5390 ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt.
5391                                   Threshold on value to enter HTC_active state.
5392 ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt.
5393                                   To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
5394 ulMinEngineClock:                 Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings.
5395 ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled
5396                                         =1: PCIE Power Gating Enabled
5397                                   Bit[1]=0: DDR-DLL shut-down feature disabled.
5398                                          1: DDR-DLL shut-down feature enabled.
5399                                   Bit[2]=0: DDR-PLL Power down feature disabled.
5400                                          1: DDR-PLL Power down feature enabled.
5401 ulCPUCapInfo:                     TBD
5402 usNBP0Voltage:                    VID for voltage on NB P0 State
5403 usNBP1Voltage:                    VID for voltage on NB P1 State
5404 usNBP2Voltage:                    VID for voltage on NB P2 State
5405 usNBP3Voltage:                    VID for voltage on NB P3 State
5406 usBootUpNBVoltage:                Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement.
5407 usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
5408 usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
5409                                   to indicate a range.
5410                                   SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
5411                                   SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
5412                                   SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
5413                                   SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
5414 ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved.
5415 ucUMAChannelNumber:                 System memory channel numbers.
5416 ulCSR_M3_ARB_CNTL_DEFAULT[10]:    Arrays with values for CSR M3 arbiter for default
5417 ulCSR_M3_ARB_CNTL_UVD[10]:        Arrays with values for CSR M3 arbiter for UVD playback.
5418 ulCSR_M3_ARB_CNTL_FS3D[10]:       Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
5419 sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
5420 ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
5421 ulMinimumNClk:                    Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz.
5422 ulIdleNClk:                       NCLK speed while memory runs in self-refresh state. Unit in 10kHz.
5423 ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
5424 ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
5425 usPCIEClkSSPercentage:            PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
5426 usPCIEClkSSType:                  PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
5427 usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
5428 usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
5429 usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
5430 usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
5431 usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
5432 usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
5433 usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
5434 ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
5435                                   [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
5436                                   [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
5437                                   [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
5438                                   [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
5439                                   [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
5440 ucTravisLVDSVolAdjust             When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust
5441                                   value to program Travis register LVDS_CTRL_4
5442 ucLVDSPwrOnSeqDIGONtoDE_in4Ms:    LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
5443                                   =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5444                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5445 ucLVDSPwrOnDEtoVARY_BL_in4Ms:     LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
5446                                   =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5447                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5448
5449 ucLVDSPwrOffVARY_BLtoDE_in4Ms:    LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
5450                                   =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5451                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5452
5453 ucLVDSPwrOffDEtoDIGON_in4Ms:      LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
5454                                   =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5455                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5456
5457 ucLVDSOffToOnDelay_in4Ms:         LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
5458                                   =0 means to use VBIOS default delay which is 125 ( 500ms ).
5459                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5460
5461 ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
5462                                   LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
5463                                   =0 means to use VBIOS default delay which is 0 ( 0ms ).
5464                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5465
5466 ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:
5467                                   LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
5468                                   =0 means to use VBIOS default delay which is 0 ( 0ms ).
5469                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5470
5471 ucMinAllowedBL_Level:             Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
5472
5473 ulNbpStateMemclkFreq[4]:          system memory clock frequncey in unit of 10Khz in different NB pstate.
5474
5475 **********************************************************************************************************************/
5476
5477 // this IntegrateSystemInfoTable is used for Kaveri & Kabini APU
5478 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8
5479 {
5480   ATOM_COMMON_TABLE_HEADER   sHeader;
5481   ULONG  ulBootUpEngineClock;
5482   ULONG  ulDentistVCOFreq;
5483   ULONG  ulBootUpUMAClock;
5484   ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];
5485   ULONG  ulBootUpReqDisplayVector;
5486   ULONG  ulVBIOSMisc;
5487   ULONG  ulGPUCapInfo;
5488   ULONG  ulDISP_CLK2Freq;
5489   USHORT usRequestedPWMFreqInHz;
5490   UCHAR  ucHtcTmpLmt;
5491   UCHAR  ucHtcHystLmt;
5492   ULONG  ulReserved2;
5493   ULONG  ulSystemConfig;
5494   ULONG  ulCPUCapInfo;
5495   ULONG  ulReserved3;
5496   USHORT usGPUReservedSysMemSize;
5497   USHORT usExtDispConnInfoOffset;
5498   USHORT usPanelRefreshRateRange;
5499   UCHAR  ucMemoryType;
5500   UCHAR  ucUMAChannelNumber;
5501   UCHAR  strVBIOSMsg[40];
5502   ATOM_TDP_CONFIG  asTdpConfig;
5503   ULONG  ulReserved[19];
5504   ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];
5505   ULONG  ulGMCRestoreResetTime;
5506   ULONG  ulReserved4;
5507   ULONG  ulIdleNClk;
5508   ULONG  ulDDR_DLL_PowerUpTime;
5509   ULONG  ulDDR_PLL_PowerUpTime;
5510   USHORT usPCIEClkSSPercentage;
5511   USHORT usPCIEClkSSType;
5512   USHORT usLvdsSSPercentage;
5513   USHORT usLvdsSSpreadRateIn10Hz;
5514   USHORT usHDMISSPercentage;
5515   USHORT usHDMISSpreadRateIn10Hz;
5516   USHORT usDVISSPercentage;
5517   USHORT usDVISSpreadRateIn10Hz;
5518   ULONG  ulGPUReservedSysMemBaseAddrLo;
5519   ULONG  ulGPUReservedSysMemBaseAddrHi;
5520   ATOM_CLK_VOLT_CAPABILITY   s5thDISPCLK_Voltage;
5521   ULONG  ulReserved5;
5522   USHORT usMaxLVDSPclkFreqInSingleLink;
5523   UCHAR  ucLvdsMisc;
5524   UCHAR  ucTravisLVDSVolAdjust;
5525   UCHAR  ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5526   UCHAR  ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5527   UCHAR  ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5528   UCHAR  ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5529   UCHAR  ucLVDSOffToOnDelay_in4Ms;
5530   UCHAR  ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5531   UCHAR  ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5532   UCHAR  ucMinAllowedBL_Level;
5533   ULONG  ulLCDBitDepthControlVal;
5534   ULONG  ulNbpStateMemclkFreq[4];
5535   ULONG  ulPSPVersion;
5536   ULONG  ulNbpStateNClkFreq[4];
5537   USHORT usNBPStateVoltage[4];
5538   USHORT usBootUpNBVoltage;
5539   USHORT usReserved2;
5540   ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
5541 }ATOM_INTEGRATED_SYSTEM_INFO_V1_8;
5542
5543 /**********************************************************************************************************************
5544   ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description
5545 ulBootUpEngineClock:              VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock
5546 ulDentistVCOFreq:                 Dentist VCO clock in 10kHz unit.
5547 ulBootUpUMAClock:                 System memory boot up clock frequency in 10Khz unit.
5548 sDISPCLK_Voltage:                 Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels).
5549
5550 ulBootUpReqDisplayVector:         VBIOS boot up display IDs, following are supported devices in Trinity projects:
5551                                   ATOM_DEVICE_CRT1_SUPPORT                  0x0001
5552                                   ATOM_DEVICE_DFP1_SUPPORT                  0x0008
5553                                   ATOM_DEVICE_DFP6_SUPPORT                  0x0040
5554                                   ATOM_DEVICE_DFP2_SUPPORT                  0x0080
5555                                   ATOM_DEVICE_DFP3_SUPPORT                  0x0200
5556                                   ATOM_DEVICE_DFP4_SUPPORT                  0x0400
5557                                   ATOM_DEVICE_DFP5_SUPPORT                  0x0800
5558                                   ATOM_DEVICE_LCD1_SUPPORT                  0x0002
5559
5560 ulVBIOSMisc:                       Miscellenous flags for VBIOS requirement and interface
5561                                   bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS.
5562                                         =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS.
5563                                   bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS
5564                                         =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS
5565                                   bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS
5566                                         =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS
5567                                   bit[3]=0: VBIOS fast boot is disable
5568                                         =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open)
5569
5570 ulGPUCapInfo:                     bit[0~2]= Reserved
5571                                   bit[3]=0: Enable AUX HW mode detection logic
5572                                         =1: Disable AUX HW mode detection logic
5573                                   bit[4]=0: Disable DFS bypass feature
5574                                         =1: Enable DFS bypass feature
5575
5576 usRequestedPWMFreqInHz:           When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW).
5577                                   Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0;
5578
5579                                   When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below:
5580                                   1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use;
5581                                   VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result,
5582                                   Changing BL using VBIOS function is functional in both driver and non-driver present environment;
5583                                   and enabling VariBri under the driver environment from PP table is optional.
5584
5585                                   2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating
5586                                   that BL control from GPU is expected.
5587                                   VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1
5588                                   Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but
5589                                   it's per platform
5590                                   and enabling VariBri under the driver environment from PP table is optional.
5591
5592 ucHtcTmpLmt:                      Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state.
5593 ucHtcHystLmt:                     Refer to D18F3x64 bit[27:24], HtcHystLmt.
5594                                   To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt.
5595
5596 ulSystemConfig:                   Bit[0]=0: PCIE Power Gating Disabled
5597                                         =1: PCIE Power Gating Enabled
5598                                   Bit[1]=0: DDR-DLL shut-down feature disabled.
5599                                          1: DDR-DLL shut-down feature enabled.
5600                                   Bit[2]=0: DDR-PLL Power down feature disabled.
5601                                          1: DDR-PLL Power down feature enabled.
5602                                   Bit[3]=0: GNB DPM is disabled
5603                                         =1: GNB DPM is enabled
5604 ulCPUCapInfo:                     TBD
5605
5606 usExtDispConnInfoOffset:          Offset to sExtDispConnInfo inside the structure
5607 usPanelRefreshRateRange:          Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set
5608                                   to indicate a range.
5609                                   SUPPORTED_LCD_REFRESHRATE_30Hz          0x0004
5610                                   SUPPORTED_LCD_REFRESHRATE_40Hz          0x0008
5611                                   SUPPORTED_LCD_REFRESHRATE_50Hz          0x0010
5612                                   SUPPORTED_LCD_REFRESHRATE_60Hz          0x0020
5613
5614 ucMemoryType:                     [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved.
5615 ucUMAChannelNumber:                 System memory channel numbers.
5616
5617 strVBIOSMsg[40]:                  VBIOS boot up customized message string
5618
5619 sAvail_SCLK[5]:                   Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high
5620
5621 ulGMCRestoreResetTime:            GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns.
5622 ulIdleNClk:                       NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz.
5623 ulDDR_DLL_PowerUpTime:            DDR PHY DLL power up time. Unit in ns.
5624 ulDDR_PLL_PowerUpTime:            DDR PHY PLL power up time. Unit in ns.
5625
5626 usPCIEClkSSPercentage:            PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%.
5627 usPCIEClkSSType:                  PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread.
5628 usLvdsSSPercentage:               LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting.
5629 usLvdsSSpreadRateIn10Hz:          LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting.
5630 usHDMISSPercentage:               HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
5631 usHDMISSpreadRateIn10Hz:          HDMI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
5632 usDVISSPercentage:                DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%,  =0, use VBIOS default setting.
5633 usDVISSpreadRateIn10Hz:           DVI Spread Spectrum frequency in unit of 10Hz,  =0, use VBIOS default setting.
5634
5635 usGPUReservedSysMemSize:          Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB.
5636 ulGPUReservedSysMemBaseAddrLo:    Low 32 bits base address to the reserved system memory.
5637 ulGPUReservedSysMemBaseAddrHi:    High 32 bits base address to the reserved system memory.
5638
5639 usMaxLVDSPclkFreqInSingleLink:    Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz
5640 ucLVDSMisc:                       [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode
5641                                   [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped
5642                                   [bit2] LVDS 888bit per color mode  =0: 666 bit per color =1:888 bit per color
5643                                   [bit3] LVDS parameter override enable  =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used
5644                                   [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low )
5645                                   [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4
5646 ucTravisLVDSVolAdjust             When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust
5647                                   value to program Travis register LVDS_CTRL_4
5648 ucLVDSPwrOnSeqDIGONtoDE_in4Ms:
5649                                   LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ).
5650                                   =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5651                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5652 ucLVDSPwrOnDEtoVARY_BL_in4Ms:
5653                                   LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ).
5654                                   =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON.
5655                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5656 ucLVDSPwrOffVARY_BLtoDE_in4Ms:
5657                                   LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off.
5658                                   =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5659                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5660 ucLVDSPwrOffDEtoDIGON_in4Ms:
5661                                    LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off.
5662                                   =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON
5663                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5664 ucLVDSOffToOnDelay_in4Ms:
5665                                   LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active.
5666                                   =0 means to use VBIOS default delay which is 125 ( 500ms ).
5667                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5668 ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms:
5669                                   LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active.
5670                                   =0 means to use VBIOS default delay which is 0 ( 0ms ).
5671                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5672
5673 ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms:
5674                                   LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off.
5675                                   =0 means to use VBIOS default delay which is 0 ( 0ms ).
5676                                   This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable.
5677 ucMinAllowedBL_Level:             Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0.
5678
5679 ulLCDBitDepthControlVal:          GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL
5680
5681 ulNbpStateMemclkFreq[4]:          system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3).
5682 ulNbpStateNClkFreq[4]:            NB P-State NClk frequency in different NB P-State
5683 usNBPStateVoltage[4]:             NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage
5684 usBootUpNBVoltage:                NB P-State voltage during boot up before driver loaded
5685 sExtDispConnInfo:                 Display connector information table provided to VBIOS
5686
5687 **********************************************************************************************************************/
5688
5689 // this Table is used for Kaveri/Kabini APU
5690 typedef struct _ATOM_FUSION_SYSTEM_INFO_V2
5691 {
5692   ATOM_INTEGRATED_SYSTEM_INFO_V1_8    sIntegratedSysInfo;       // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
5693   ULONG                               ulPowerplayTable[128];    // Update comments here to link new powerplay table definition structure
5694 }ATOM_FUSION_SYSTEM_INFO_V2;
5695
5696
5697 typedef struct _ATOM_I2C_REG_INFO
5698 {
5699   UCHAR ucI2cRegIndex;
5700   UCHAR ucI2cRegVal;
5701 }ATOM_I2C_REG_INFO;
5702
5703 // this IntegrateSystemInfoTable is used for Carrizo
5704 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9
5705 {
5706   ATOM_COMMON_TABLE_HEADER   sHeader;
5707   ULONG  ulBootUpEngineClock;
5708   ULONG  ulDentistVCOFreq;
5709   ULONG  ulBootUpUMAClock;
5710   ATOM_CLK_VOLT_CAPABILITY   sDISPCLK_Voltage[4];       // no longer used, keep it as is to avoid driver compiling error
5711   ULONG  ulBootUpReqDisplayVector;
5712   ULONG  ulVBIOSMisc;
5713   ULONG  ulGPUCapInfo;
5714   ULONG  ulDISP_CLK2Freq;
5715   USHORT usRequestedPWMFreqInHz;
5716   UCHAR  ucHtcTmpLmt;
5717   UCHAR  ucHtcHystLmt;
5718   ULONG  ulReserved2;
5719   ULONG  ulSystemConfig;
5720   ULONG  ulCPUCapInfo;
5721   ULONG  ulReserved3;
5722   USHORT usGPUReservedSysMemSize;
5723   USHORT usExtDispConnInfoOffset;
5724   USHORT usPanelRefreshRateRange;
5725   UCHAR  ucMemoryType;
5726   UCHAR  ucUMAChannelNumber;
5727   UCHAR  strVBIOSMsg[40];
5728   ATOM_TDP_CONFIG  asTdpConfig;
5729   UCHAR  ucExtHDMIReDrvSlvAddr;
5730   UCHAR  ucExtHDMIReDrvRegNum;
5731   ATOM_I2C_REG_INFO asExtHDMIRegSetting[9];
5732   ULONG  ulReserved[2];
5733   ATOM_CLK_VOLT_CAPABILITY_V2   sDispClkVoltageMapping[8];
5734   ATOM_AVAILABLE_SCLK_LIST   sAvail_SCLK[5];            // no longer used, keep it as is to avoid driver compiling error
5735   ULONG  ulGMCRestoreResetTime;
5736   ULONG  ulReserved4;
5737   ULONG  ulIdleNClk;
5738   ULONG  ulDDR_DLL_PowerUpTime;
5739   ULONG  ulDDR_PLL_PowerUpTime;
5740   USHORT usPCIEClkSSPercentage;
5741   USHORT usPCIEClkSSType;
5742   USHORT usLvdsSSPercentage;
5743   USHORT usLvdsSSpreadRateIn10Hz;
5744   USHORT usHDMISSPercentage;
5745   USHORT usHDMISSpreadRateIn10Hz;
5746   USHORT usDVISSPercentage;
5747   USHORT usDVISSpreadRateIn10Hz;
5748   ULONG  ulGPUReservedSysMemBaseAddrLo;
5749   ULONG  ulGPUReservedSysMemBaseAddrHi;
5750   ULONG  ulReserved5[3];
5751   USHORT usMaxLVDSPclkFreqInSingleLink;
5752   UCHAR  ucLvdsMisc;
5753   UCHAR  ucTravisLVDSVolAdjust;
5754   UCHAR  ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5755   UCHAR  ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5756   UCHAR  ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5757   UCHAR  ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5758   UCHAR  ucLVDSOffToOnDelay_in4Ms;
5759   UCHAR  ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5760   UCHAR  ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5761   UCHAR  ucMinAllowedBL_Level;
5762   ULONG  ulLCDBitDepthControlVal;
5763   ULONG  ulNbpStateMemclkFreq[4];          // only 2 level is changed.
5764   ULONG  ulPSPVersion;
5765   ULONG  ulNbpStateNClkFreq[4];
5766   USHORT usNBPStateVoltage[4];
5767   USHORT usBootUpNBVoltage;
5768   UCHAR  ucEDPv1_4VSMode;
5769   UCHAR  ucReserved2;
5770   ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
5771 }ATOM_INTEGRATED_SYSTEM_INFO_V1_9;
5772
5773
5774 // definition for ucEDPv1_4VSMode
5775 #define EDP_VS_LEGACY_MODE                  0
5776 #define EDP_VS_LOW_VDIFF_MODE               1
5777 #define EDP_VS_HIGH_VDIFF_MODE              2
5778 #define EDP_VS_STRETCH_MODE                 3
5779 #define EDP_VS_SINGLE_VDIFF_MODE            4
5780 #define EDP_VS_VARIABLE_PREM_MODE           5
5781
5782
5783 // this IntegrateSystemInfoTable is used for Carrizo
5784 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10
5785 {
5786   ATOM_COMMON_TABLE_HEADER   sHeader;
5787   ULONG  ulBootUpEngineClock;
5788   ULONG  ulDentistVCOFreq;
5789   ULONG  ulBootUpUMAClock;
5790   ULONG  ulReserved0[8];
5791   ULONG  ulBootUpReqDisplayVector;
5792   ULONG  ulVBIOSMisc;
5793   ULONG  ulGPUCapInfo;
5794   ULONG  ulReserved1;
5795   USHORT usRequestedPWMFreqInHz;
5796   UCHAR  ucHtcTmpLmt;
5797   UCHAR  ucHtcHystLmt;
5798   ULONG  ulReserved2;
5799   ULONG  ulSystemConfig;
5800   ULONG  ulCPUCapInfo;
5801   ULONG  ulReserved3;
5802   USHORT usGPUReservedSysMemSize;
5803   USHORT usExtDispConnInfoOffset;
5804   USHORT usPanelRefreshRateRange;
5805   UCHAR  ucMemoryType;
5806   UCHAR  ucUMAChannelNumber;
5807   UCHAR  strVBIOSMsg[40];
5808   ATOM_TDP_CONFIG  asTdpConfig;
5809   ULONG  ulReserved[7];
5810   ATOM_CLK_VOLT_CAPABILITY_V2   sDispClkVoltageMapping[8];
5811   ULONG  ulReserved6[10];
5812   ULONG  ulGMCRestoreResetTime;
5813   ULONG  ulReserved4;
5814   ULONG  ulIdleNClk;
5815   ULONG  ulDDR_DLL_PowerUpTime;
5816   ULONG  ulDDR_PLL_PowerUpTime;
5817   USHORT usPCIEClkSSPercentage;
5818   USHORT usPCIEClkSSType;
5819   USHORT usLvdsSSPercentage;
5820   USHORT usLvdsSSpreadRateIn10Hz;
5821   USHORT usHDMISSPercentage;
5822   USHORT usHDMISSpreadRateIn10Hz;
5823   USHORT usDVISSPercentage;
5824   USHORT usDVISSpreadRateIn10Hz;
5825   ULONG  ulGPUReservedSysMemBaseAddrLo;
5826   ULONG  ulGPUReservedSysMemBaseAddrHi;
5827   ULONG  ulReserved5[3];
5828   USHORT usMaxLVDSPclkFreqInSingleLink;
5829   UCHAR  ucLvdsMisc;
5830   UCHAR  ucTravisLVDSVolAdjust;
5831   UCHAR  ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5832   UCHAR  ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5833   UCHAR  ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5834   UCHAR  ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5835   UCHAR  ucLVDSOffToOnDelay_in4Ms;
5836   UCHAR  ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5837   UCHAR  ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5838   UCHAR  ucMinAllowedBL_Level;
5839   ULONG  ulLCDBitDepthControlVal;
5840   ULONG  ulNbpStateMemclkFreq[2];
5841   ULONG  ulReserved7[2];
5842   ULONG  ulPSPVersion;
5843   ULONG  ulNbpStateNClkFreq[4];
5844   USHORT usNBPStateVoltage[4];
5845   USHORT usBootUpNBVoltage;
5846   UCHAR  ucEDPv1_4VSMode;
5847   UCHAR  ucReserved2;
5848   ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo;
5849 }ATOM_INTEGRATED_SYSTEM_INFO_V1_10;
5850
5851 /**************************************************************************/
5852 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design
5853 //Memory SS Info Table
5854 //Define Memory Clock SS chip ID
5855 #define ICS91719  1
5856 #define ICS91720  2
5857
5858 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol
5859 typedef struct _ATOM_I2C_DATA_RECORD
5860 {
5861   UCHAR         ucNunberOfBytes;                                              //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
5862   UCHAR         ucI2CData[1];                                                 //I2C data in bytes, should be less than 16 bytes usually
5863 }ATOM_I2C_DATA_RECORD;
5864
5865
5866 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information
5867 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO
5868 {
5869   ATOM_I2C_ID_CONFIG_ACCESS       sucI2cId;               //I2C line and HW/SW assisted cap.
5870   UCHAR                              ucSSChipID;             //SS chip being used
5871   UCHAR                              ucSSChipSlaveAddr;      //Slave Address to set up this SS chip
5872   UCHAR                           ucNumOfI2CDataRecords;  //number of data block
5873   ATOM_I2C_DATA_RECORD            asI2CData[1];
5874 }ATOM_I2C_DEVICE_SETUP_INFO;
5875
5876 //==========================================================================================
5877 typedef struct  _ATOM_ASIC_MVDD_INFO
5878 {
5879   ATOM_COMMON_TABLE_HEADER         sHeader;
5880   ATOM_I2C_DEVICE_SETUP_INFO      asI2CSetup[1];
5881 }ATOM_ASIC_MVDD_INFO;
5882
5883 //==========================================================================================
5884 #define ATOM_MCLK_SS_INFO         ATOM_ASIC_MVDD_INFO
5885
5886 //==========================================================================================
5887 /**************************************************************************/
5888
5889 typedef struct _ATOM_ASIC_SS_ASSIGNMENT
5890 {
5891    ULONG                        ulTargetClockRange;                  //Clock Out frequence (VCO ), in unit of 10Khz
5892   USHORT              usSpreadSpectrumPercentage;      //in unit of 0.01%
5893    USHORT                     usSpreadRateInKhz;                  //in unit of kHz, modulation freq
5894   UCHAR               ucClockIndication;                 //Indicate which clock source needs SS
5895    UCHAR                        ucSpreadSpectrumMode;               //Bit1=0 Down Spread,=1 Center Spread.
5896    UCHAR                        ucReserved[2];
5897 }ATOM_ASIC_SS_ASSIGNMENT;
5898
5899 //Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type.
5900 //SS is not required or enabled if a match is not found.
5901 #define ASIC_INTERNAL_MEMORY_SS            1
5902 #define ASIC_INTERNAL_ENGINE_SS            2
5903 #define ASIC_INTERNAL_UVD_SS             3
5904 #define ASIC_INTERNAL_SS_ON_TMDS         4
5905 #define ASIC_INTERNAL_SS_ON_HDMI         5
5906 #define ASIC_INTERNAL_SS_ON_LVDS         6
5907 #define ASIC_INTERNAL_SS_ON_DP           7
5908 #define ASIC_INTERNAL_SS_ON_DCPLL        8
5909 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK     9
5910 #define ASIC_INTERNAL_VCE_SS             10
5911 #define ASIC_INTERNAL_GPUPLL_SS          11
5912
5913
5914 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2
5915 {
5916    ULONG                        ulTargetClockRange;                  //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5917                                                     //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
5918   USHORT              usSpreadSpectrumPercentage;      //in unit of 0.01%
5919    USHORT                     usSpreadRateIn10Hz;                  //in unit of 10Hz, modulation freq
5920   UCHAR               ucClockIndication;                 //Indicate which clock source needs SS
5921    UCHAR                        ucSpreadSpectrumMode;               //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5922    UCHAR                        ucReserved[2];
5923 }ATOM_ASIC_SS_ASSIGNMENT_V2;
5924
5925 //ucSpreadSpectrumMode
5926 //#define ATOM_SS_DOWN_SPREAD_MODE_MASK          0x00000000
5927 //#define ATOM_SS_DOWN_SPREAD_MODE               0x00000000
5928 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK        0x00000001
5929 //#define ATOM_SS_CENTRE_SPREAD_MODE             0x00000001
5930 //#define ATOM_INTERNAL_SS_MASK                  0x00000000
5931 //#define ATOM_EXTERNAL_SS_MASK                  0x00000002
5932
5933 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO
5934 {
5935   ATOM_COMMON_TABLE_HEADER         sHeader;
5936   ATOM_ASIC_SS_ASSIGNMENT            asSpreadSpectrum[4];
5937 }ATOM_ASIC_INTERNAL_SS_INFO;
5938
5939 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2
5940 {
5941   ATOM_COMMON_TABLE_HEADER         sHeader;
5942   ATOM_ASIC_SS_ASSIGNMENT_V2        asSpreadSpectrum[1];      //this is point only.
5943 }ATOM_ASIC_INTERNAL_SS_INFO_V2;
5944
5945 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3
5946 {
5947    ULONG                        ulTargetClockRange;                  //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz
5948                                                     //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 )
5949   USHORT              usSpreadSpectrumPercentage;      //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4
5950    USHORT                     usSpreadRateIn10Hz;                  //in unit of 10Hz, modulation freq
5951   UCHAR               ucClockIndication;                 //Indicate which clock source needs SS
5952    UCHAR                        ucSpreadSpectrumMode;               //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
5953    UCHAR                        ucReserved[2];
5954 }ATOM_ASIC_SS_ASSIGNMENT_V3;
5955
5956 //ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode
5957 #define SS_MODE_V3_CENTRE_SPREAD_MASK             0x01
5958 #define SS_MODE_V3_EXTERNAL_SS_MASK               0x02
5959 #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK    0x10
5960
5961 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3
5962 {
5963   ATOM_COMMON_TABLE_HEADER         sHeader;
5964   ATOM_ASIC_SS_ASSIGNMENT_V3        asSpreadSpectrum[1];      //this is pointer only.
5965 }ATOM_ASIC_INTERNAL_SS_INFO_V3;
5966
5967
5968 //==============================Scratch Pad Definition Portion===============================
5969 #define ATOM_DEVICE_CONNECT_INFO_DEF  0
5970 #define ATOM_ROM_LOCATION_DEF         1
5971 #define ATOM_TV_STANDARD_DEF          2
5972 #define ATOM_ACTIVE_INFO_DEF          3
5973 #define ATOM_LCD_INFO_DEF             4
5974 #define ATOM_DOS_REQ_INFO_DEF         5
5975 #define ATOM_ACC_CHANGE_INFO_DEF      6
5976 #define ATOM_DOS_MODE_INFO_DEF        7
5977 #define ATOM_I2C_CHANNEL_STATUS_DEF   8
5978 #define ATOM_I2C_CHANNEL_STATUS1_DEF  9
5979 #define ATOM_INTERNAL_TIMER_DEF       10
5980
5981 // BIOS_0_SCRATCH Definition
5982 #define ATOM_S0_CRT1_MONO               0x00000001L
5983 #define ATOM_S0_CRT1_COLOR              0x00000002L
5984 #define ATOM_S0_CRT1_MASK               (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR)
5985
5986 #define ATOM_S0_TV1_COMPOSITE_A         0x00000004L
5987 #define ATOM_S0_TV1_SVIDEO_A            0x00000008L
5988 #define ATOM_S0_TV1_MASK_A              (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A)
5989
5990 #define ATOM_S0_CV_A                    0x00000010L
5991 #define ATOM_S0_CV_DIN_A                0x00000020L
5992 #define ATOM_S0_CV_MASK_A               (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A)
5993
5994
5995 #define ATOM_S0_CRT2_MONO               0x00000100L
5996 #define ATOM_S0_CRT2_COLOR              0x00000200L
5997 #define ATOM_S0_CRT2_MASK               (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR)
5998
5999 #define ATOM_S0_TV1_COMPOSITE           0x00000400L
6000 #define ATOM_S0_TV1_SVIDEO              0x00000800L
6001 #define ATOM_S0_TV1_SCART               0x00004000L
6002 #define ATOM_S0_TV1_MASK                (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART)
6003
6004 #define ATOM_S0_CV                      0x00001000L
6005 #define ATOM_S0_CV_DIN                  0x00002000L
6006 #define ATOM_S0_CV_MASK                 (ATOM_S0_CV+ATOM_S0_CV_DIN)
6007
6008 #define ATOM_S0_DFP1                    0x00010000L
6009 #define ATOM_S0_DFP2                    0x00020000L
6010 #define ATOM_S0_LCD1                    0x00040000L
6011 #define ATOM_S0_LCD2                    0x00080000L
6012 #define ATOM_S0_DFP6                    0x00100000L
6013 #define ATOM_S0_DFP3                    0x00200000L
6014 #define ATOM_S0_DFP4                    0x00400000L
6015 #define ATOM_S0_DFP5                    0x00800000L
6016
6017
6018 #define ATOM_S0_DFP_MASK                ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6
6019
6020 #define ATOM_S0_FAD_REGISTER_BUG        0x02000000L // If set, indicates we are running a PCIE asic with
6021                                                     // the FAD/HDP reg access bug.  Bit is read by DAL, this is obsolete from RV5xx
6022
6023 #define ATOM_S0_THERMAL_STATE_MASK      0x1C000000L
6024 #define ATOM_S0_THERMAL_STATE_SHIFT     26
6025
6026 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L
6027 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29
6028
6029 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC     1
6030 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC     2
6031 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3
6032 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4
6033
6034 //Byte aligned defintion for BIOS usage
6035 #define ATOM_S0_CRT1_MONOb0             0x01
6036 #define ATOM_S0_CRT1_COLORb0            0x02
6037 #define ATOM_S0_CRT1_MASKb0             (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0)
6038
6039 #define ATOM_S0_TV1_COMPOSITEb0         0x04
6040 #define ATOM_S0_TV1_SVIDEOb0            0x08
6041 #define ATOM_S0_TV1_MASKb0              (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0)
6042
6043 #define ATOM_S0_CVb0                    0x10
6044 #define ATOM_S0_CV_DINb0                0x20
6045 #define ATOM_S0_CV_MASKb0               (ATOM_S0_CVb0+ATOM_S0_CV_DINb0)
6046
6047 #define ATOM_S0_CRT2_MONOb1             0x01
6048 #define ATOM_S0_CRT2_COLORb1            0x02
6049 #define ATOM_S0_CRT2_MASKb1             (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1)
6050
6051 #define ATOM_S0_TV1_COMPOSITEb1         0x04
6052 #define ATOM_S0_TV1_SVIDEOb1            0x08
6053 #define ATOM_S0_TV1_SCARTb1             0x40
6054 #define ATOM_S0_TV1_MASKb1              (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1)
6055
6056 #define ATOM_S0_CVb1                    0x10
6057 #define ATOM_S0_CV_DINb1                0x20
6058 #define ATOM_S0_CV_MASKb1               (ATOM_S0_CVb1+ATOM_S0_CV_DINb1)
6059
6060 #define ATOM_S0_DFP1b2                  0x01
6061 #define ATOM_S0_DFP2b2                  0x02
6062 #define ATOM_S0_LCD1b2                  0x04
6063 #define ATOM_S0_LCD2b2                  0x08
6064 #define ATOM_S0_DFP6b2                  0x10
6065 #define ATOM_S0_DFP3b2                  0x20
6066 #define ATOM_S0_DFP4b2                  0x40
6067 #define ATOM_S0_DFP5b2                  0x80
6068
6069
6070 #define ATOM_S0_THERMAL_STATE_MASKb3    0x1C
6071 #define ATOM_S0_THERMAL_STATE_SHIFTb3   2
6072
6073 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0
6074 #define ATOM_S0_LCD1_SHIFT              18
6075
6076 // BIOS_1_SCRATCH Definition
6077 #define ATOM_S1_ROM_LOCATION_MASK       0x0000FFFFL
6078 #define ATOM_S1_PCI_BUS_DEV_MASK        0xFFFF0000L
6079
6080 //   BIOS_2_SCRATCH Definition
6081 #define ATOM_S2_TV1_STANDARD_MASK       0x0000000FL
6082 #define ATOM_S2_CURRENT_BL_LEVEL_MASK   0x0000FF00L
6083 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT  8
6084
6085 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK       0x0C000000L
6086 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26
6087 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE     0x10000000L
6088
6089 #define ATOM_S2_DEVICE_DPMS_STATE       0x00010000L
6090 #define ATOM_S2_VRI_BRIGHT_ENABLE       0x20000000L
6091
6092 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE     0x0
6093 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE    0x1
6094 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE   0x2
6095 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE   0x3
6096 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30
6097 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK   0xC0000000L
6098
6099
6100 //Byte aligned defintion for BIOS usage
6101 #define ATOM_S2_TV1_STANDARD_MASKb0     0x0F
6102 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF
6103 #define ATOM_S2_DEVICE_DPMS_STATEb2     0x01
6104
6105 #define ATOM_S2_TMDS_COHERENT_MODEb3    0x10          // used by VBIOS code only, use coherent mode for TMDS/HDMI mode
6106 #define ATOM_S2_VRI_BRIGHT_ENABLEb3     0x20
6107 #define ATOM_S2_ROTATION_STATE_MASKb3   0xC0
6108
6109
6110 // BIOS_3_SCRATCH Definition
6111 #define ATOM_S3_CRT1_ACTIVE             0x00000001L
6112 #define ATOM_S3_LCD1_ACTIVE             0x00000002L
6113 #define ATOM_S3_TV1_ACTIVE              0x00000004L
6114 #define ATOM_S3_DFP1_ACTIVE             0x00000008L
6115 #define ATOM_S3_CRT2_ACTIVE             0x00000010L
6116 #define ATOM_S3_LCD2_ACTIVE             0x00000020L
6117 #define ATOM_S3_DFP6_ACTIVE                     0x00000040L
6118 #define ATOM_S3_DFP2_ACTIVE             0x00000080L
6119 #define ATOM_S3_CV_ACTIVE               0x00000100L
6120 #define ATOM_S3_DFP3_ACTIVE                     0x00000200L
6121 #define ATOM_S3_DFP4_ACTIVE                     0x00000400L
6122 #define ATOM_S3_DFP5_ACTIVE                     0x00000800L
6123
6124
6125 #define ATOM_S3_DEVICE_ACTIVE_MASK      0x00000FFFL
6126
6127 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE         0x00001000L
6128 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L
6129
6130 #define ATOM_S3_CRT1_CRTC_ACTIVE        0x00010000L
6131 #define ATOM_S3_LCD1_CRTC_ACTIVE        0x00020000L
6132 #define ATOM_S3_TV1_CRTC_ACTIVE         0x00040000L
6133 #define ATOM_S3_DFP1_CRTC_ACTIVE        0x00080000L
6134 #define ATOM_S3_CRT2_CRTC_ACTIVE        0x00100000L
6135 #define ATOM_S3_LCD2_CRTC_ACTIVE        0x00200000L
6136 #define ATOM_S3_DFP6_CRTC_ACTIVE        0x00400000L
6137 #define ATOM_S3_DFP2_CRTC_ACTIVE        0x00800000L
6138 #define ATOM_S3_CV_CRTC_ACTIVE          0x01000000L
6139 #define ATOM_S3_DFP3_CRTC_ACTIVE            0x02000000L
6140 #define ATOM_S3_DFP4_CRTC_ACTIVE            0x04000000L
6141 #define ATOM_S3_DFP5_CRTC_ACTIVE            0x08000000L
6142
6143
6144 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L
6145 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG    0x20000000L
6146 //Below two definitions are not supported in pplib, but in the old powerplay in DAL
6147 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH   0x40000000L
6148 #define ATOM_S3_RQST_GPU_USE_MIN_PWR    0x80000000L
6149
6150
6151
6152 //Byte aligned defintion for BIOS usage
6153 #define ATOM_S3_CRT1_ACTIVEb0           0x01
6154 #define ATOM_S3_LCD1_ACTIVEb0           0x02
6155 #define ATOM_S3_TV1_ACTIVEb0            0x04
6156 #define ATOM_S3_DFP1_ACTIVEb0           0x08
6157 #define ATOM_S3_CRT2_ACTIVEb0           0x10
6158 #define ATOM_S3_LCD2_ACTIVEb0           0x20
6159 #define ATOM_S3_DFP6_ACTIVEb0           0x40
6160 #define ATOM_S3_DFP2_ACTIVEb0           0x80
6161 #define ATOM_S3_CV_ACTIVEb1             0x01
6162 #define ATOM_S3_DFP3_ACTIVEb1                  0x02
6163 #define ATOM_S3_DFP4_ACTIVEb1                  0x04
6164 #define ATOM_S3_DFP5_ACTIVEb1                  0x08
6165
6166
6167 #define ATOM_S3_ACTIVE_CRTC1w0          0xFFF
6168
6169 #define ATOM_S3_CRT1_CRTC_ACTIVEb2      0x01
6170 #define ATOM_S3_LCD1_CRTC_ACTIVEb2      0x02
6171 #define ATOM_S3_TV1_CRTC_ACTIVEb2       0x04
6172 #define ATOM_S3_DFP1_CRTC_ACTIVEb2      0x08
6173 #define ATOM_S3_CRT2_CRTC_ACTIVEb2      0x10
6174 #define ATOM_S3_LCD2_CRTC_ACTIVEb2      0x20
6175 #define ATOM_S3_DFP6_CRTC_ACTIVEb2      0x40
6176 #define ATOM_S3_DFP2_CRTC_ACTIVEb2      0x80
6177 #define ATOM_S3_CV_CRTC_ACTIVEb3        0x01
6178 #define ATOM_S3_DFP3_CRTC_ACTIVEb3         0x02
6179 #define ATOM_S3_DFP4_CRTC_ACTIVEb3         0x04
6180 #define ATOM_S3_DFP5_CRTC_ACTIVEb3         0x08
6181
6182
6183 #define ATOM_S3_ACTIVE_CRTC2w1          0xFFF
6184
6185
6186 // BIOS_4_SCRATCH Definition
6187 #define ATOM_S4_LCD1_PANEL_ID_MASK      0x000000FFL
6188 #define ATOM_S4_LCD1_REFRESH_MASK       0x0000FF00L
6189 #define ATOM_S4_LCD1_REFRESH_SHIFT      8
6190
6191 //Byte aligned defintion for BIOS usage
6192 #define ATOM_S4_LCD1_PANEL_ID_MASKb0    0x0FF
6193 #define ATOM_S4_LCD1_REFRESH_MASKb1     ATOM_S4_LCD1_PANEL_ID_MASKb0
6194 #define ATOM_S4_VRAM_INFO_MASKb2        ATOM_S4_LCD1_PANEL_ID_MASKb0
6195
6196 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!!
6197 #define ATOM_S5_DOS_REQ_CRT1b0          0x01
6198 #define ATOM_S5_DOS_REQ_LCD1b0          0x02
6199 #define ATOM_S5_DOS_REQ_TV1b0           0x04
6200 #define ATOM_S5_DOS_REQ_DFP1b0          0x08
6201 #define ATOM_S5_DOS_REQ_CRT2b0          0x10
6202 #define ATOM_S5_DOS_REQ_LCD2b0          0x20
6203 #define ATOM_S5_DOS_REQ_DFP6b0          0x40
6204 #define ATOM_S5_DOS_REQ_DFP2b0          0x80
6205 #define ATOM_S5_DOS_REQ_CVb1            0x01
6206 #define ATOM_S5_DOS_REQ_DFP3b1          0x02
6207 #define ATOM_S5_DOS_REQ_DFP4b1          0x04
6208 #define ATOM_S5_DOS_REQ_DFP5b1          0x08
6209
6210
6211 #define ATOM_S5_DOS_REQ_DEVICEw0        0x0FFF
6212
6213 #define ATOM_S5_DOS_REQ_CRT1            0x0001
6214 #define ATOM_S5_DOS_REQ_LCD1            0x0002
6215 #define ATOM_S5_DOS_REQ_TV1             0x0004
6216 #define ATOM_S5_DOS_REQ_DFP1            0x0008
6217 #define ATOM_S5_DOS_REQ_CRT2            0x0010
6218 #define ATOM_S5_DOS_REQ_LCD2            0x0020
6219 #define ATOM_S5_DOS_REQ_DFP6            0x0040
6220 #define ATOM_S5_DOS_REQ_DFP2            0x0080
6221 #define ATOM_S5_DOS_REQ_CV              0x0100
6222 #define ATOM_S5_DOS_REQ_DFP3            0x0200
6223 #define ATOM_S5_DOS_REQ_DFP4            0x0400
6224 #define ATOM_S5_DOS_REQ_DFP5            0x0800
6225
6226 #define ATOM_S5_DOS_FORCE_CRT1b2        ATOM_S5_DOS_REQ_CRT1b0
6227 #define ATOM_S5_DOS_FORCE_TV1b2         ATOM_S5_DOS_REQ_TV1b0
6228 #define ATOM_S5_DOS_FORCE_CRT2b2        ATOM_S5_DOS_REQ_CRT2b0
6229 #define ATOM_S5_DOS_FORCE_CVb3          ATOM_S5_DOS_REQ_CVb1
6230 #define ATOM_S5_DOS_FORCE_DEVICEw1      (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\
6231                                         (ATOM_S5_DOS_FORCE_CVb3<<8))
6232 // BIOS_6_SCRATCH Definition
6233 #define ATOM_S6_DEVICE_CHANGE           0x00000001L
6234 #define ATOM_S6_SCALER_CHANGE           0x00000002L
6235 #define ATOM_S6_LID_CHANGE              0x00000004L
6236 #define ATOM_S6_DOCKING_CHANGE          0x00000008L
6237 #define ATOM_S6_ACC_MODE                0x00000010L
6238 #define ATOM_S6_EXT_DESKTOP_MODE        0x00000020L
6239 #define ATOM_S6_LID_STATE               0x00000040L
6240 #define ATOM_S6_DOCK_STATE              0x00000080L
6241 #define ATOM_S6_CRITICAL_STATE          0x00000100L
6242 #define ATOM_S6_HW_I2C_BUSY_STATE       0x00000200L
6243 #define ATOM_S6_THERMAL_STATE_CHANGE    0x00000400L
6244 #define ATOM_S6_INTERRUPT_SET_BY_BIOS   0x00000800L
6245 #define ATOM_S6_REQ_LCD_EXPANSION_FULL         0x00001000L //Normal expansion Request bit for LCD
6246 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO  0x00002000L //Aspect ratio expansion Request bit for LCD
6247
6248 #define ATOM_S6_DISPLAY_STATE_CHANGE    0x00004000L        //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion
6249 #define ATOM_S6_I2C_STATE_CHANGE        0x00008000L        //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion
6250
6251 #define ATOM_S6_ACC_REQ_CRT1            0x00010000L
6252 #define ATOM_S6_ACC_REQ_LCD1            0x00020000L
6253 #define ATOM_S6_ACC_REQ_TV1             0x00040000L
6254 #define ATOM_S6_ACC_REQ_DFP1            0x00080000L
6255 #define ATOM_S6_ACC_REQ_CRT2            0x00100000L
6256 #define ATOM_S6_ACC_REQ_LCD2            0x00200000L
6257 #define ATOM_S6_ACC_REQ_DFP6            0x00400000L
6258 #define ATOM_S6_ACC_REQ_DFP2            0x00800000L
6259 #define ATOM_S6_ACC_REQ_CV              0x01000000L
6260 #define ATOM_S6_ACC_REQ_DFP3                  0x02000000L
6261 #define ATOM_S6_ACC_REQ_DFP4                  0x04000000L
6262 #define ATOM_S6_ACC_REQ_DFP5                  0x08000000L
6263
6264 #define ATOM_S6_ACC_REQ_MASK                0x0FFF0000L
6265 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE    0x10000000L
6266 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH    0x20000000L
6267 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE       0x40000000L
6268 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK  0x80000000L
6269
6270 //Byte aligned defintion for BIOS usage
6271 #define ATOM_S6_DEVICE_CHANGEb0         0x01
6272 #define ATOM_S6_SCALER_CHANGEb0         0x02
6273 #define ATOM_S6_LID_CHANGEb0            0x04
6274 #define ATOM_S6_DOCKING_CHANGEb0        0x08
6275 #define ATOM_S6_ACC_MODEb0              0x10
6276 #define ATOM_S6_EXT_DESKTOP_MODEb0      0x20
6277 #define ATOM_S6_LID_STATEb0             0x40
6278 #define ATOM_S6_DOCK_STATEb0            0x80
6279 #define ATOM_S6_CRITICAL_STATEb1        0x01
6280 #define ATOM_S6_HW_I2C_BUSY_STATEb1     0x02
6281 #define ATOM_S6_THERMAL_STATE_CHANGEb1  0x04
6282 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08
6283 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1        0x10
6284 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20
6285
6286 #define ATOM_S6_ACC_REQ_CRT1b2          0x01
6287 #define ATOM_S6_ACC_REQ_LCD1b2          0x02
6288 #define ATOM_S6_ACC_REQ_TV1b2           0x04
6289 #define ATOM_S6_ACC_REQ_DFP1b2          0x08
6290 #define ATOM_S6_ACC_REQ_CRT2b2          0x10
6291 #define ATOM_S6_ACC_REQ_LCD2b2          0x20
6292 #define ATOM_S6_ACC_REQ_DFP6b2          0x40
6293 #define ATOM_S6_ACC_REQ_DFP2b2          0x80
6294 #define ATOM_S6_ACC_REQ_CVb3            0x01
6295 #define ATOM_S6_ACC_REQ_DFP3b3          0x02
6296 #define ATOM_S6_ACC_REQ_DFP4b3          0x04
6297 #define ATOM_S6_ACC_REQ_DFP5b3          0x08
6298
6299 #define ATOM_S6_ACC_REQ_DEVICEw1        ATOM_S5_DOS_REQ_DEVICEw0
6300 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10
6301 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20
6302 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3    0x40
6303 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3    0x80
6304
6305 #define ATOM_S6_DEVICE_CHANGE_SHIFT             0
6306 #define ATOM_S6_SCALER_CHANGE_SHIFT             1
6307 #define ATOM_S6_LID_CHANGE_SHIFT                2
6308 #define ATOM_S6_DOCKING_CHANGE_SHIFT            3
6309 #define ATOM_S6_ACC_MODE_SHIFT                  4
6310 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT          5
6311 #define ATOM_S6_LID_STATE_SHIFT                 6
6312 #define ATOM_S6_DOCK_STATE_SHIFT                7
6313 #define ATOM_S6_CRITICAL_STATE_SHIFT            8
6314 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT         9
6315 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT      10
6316 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT     11
6317 #define ATOM_S6_REQ_SCALER_SHIFT                12
6318 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT         13
6319 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT      14
6320 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT          15
6321 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT  28
6322 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT  29
6323 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT     30
6324 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT     31
6325
6326 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!!
6327 #define ATOM_S7_DOS_MODE_TYPEb0             0x03
6328 #define ATOM_S7_DOS_MODE_VGAb0              0x00
6329 #define ATOM_S7_DOS_MODE_VESAb0             0x01
6330 #define ATOM_S7_DOS_MODE_EXTb0              0x02
6331 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0      0x0C
6332 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0     0xF0
6333 #define ATOM_S7_DOS_8BIT_DAC_ENb1           0x01
6334 #define ATOM_S7_ASIC_INIT_COMPLETEb1        0x02
6335 #define ATOM_S7_ASIC_INIT_COMPLETE_MASK     0x00000200
6336 #define ATOM_S7_DOS_MODE_NUMBERw1           0x0FFFF
6337
6338 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT       8
6339
6340 // BIOS_8_SCRATCH Definition
6341 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK       0x00000FFFF
6342 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK     0x0FFFF0000
6343
6344 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT      0
6345 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT       16
6346
6347 // BIOS_9_SCRATCH Definition
6348 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK
6349 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK  0x0000FFFF
6350 #endif
6351 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK
6352 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK    0xFFFF0000
6353 #endif
6354 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT
6355 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0
6356 #endif
6357 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT
6358 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT   16
6359 #endif
6360
6361
6362 #define ATOM_FLAG_SET                         0x20
6363 #define ATOM_FLAG_CLEAR                       0
6364 #define CLEAR_ATOM_S6_ACC_MODE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR)
6365 #define SET_ATOM_S6_DEVICE_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET)
6366 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET)
6367 #define SET_ATOM_S6_SCALER_CHANGE             ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET)
6368 #define SET_ATOM_S6_LID_CHANGE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET)
6369
6370 #define SET_ATOM_S6_LID_STATE                 ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET)
6371 #define CLEAR_ATOM_S6_LID_STATE               ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR)
6372
6373 #define SET_ATOM_S6_DOCK_CHANGE                   ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET)
6374 #define SET_ATOM_S6_DOCK_STATE                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET)
6375 #define CLEAR_ATOM_S6_DOCK_STATE              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR)
6376
6377 #define SET_ATOM_S6_THERMAL_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET)
6378 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE  ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET)
6379 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS     ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET)
6380
6381 #define SET_ATOM_S6_CRITICAL_STATE            ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET)
6382 #define CLEAR_ATOM_S6_CRITICAL_STATE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR)
6383
6384 #define SET_ATOM_S6_REQ_SCALER                ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET)
6385 #define CLEAR_ATOM_S6_REQ_SCALER              ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR )
6386
6387 #define SET_ATOM_S6_REQ_SCALER_ARATIO         ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET )
6388 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO       ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR )
6389
6390 #define SET_ATOM_S6_I2C_STATE_CHANGE          ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
6391
6392 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE      ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET )
6393
6394 #define SET_ATOM_S6_DEVICE_RECONFIG           ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET)
6395 #define CLEAR_ATOM_S0_LCD1                    ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )|  ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR )
6396 #define SET_ATOM_S7_DOS_8BIT_DAC_EN           ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET )
6397 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN         ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR )
6398
6399 /****************************************************************************/
6400 //Portion II: Definitinos only used in Driver
6401 /****************************************************************************/
6402
6403 // Macros used by driver
6404
6405 #ifdef __cplusplus
6406 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT))
6407
6408 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F)
6409 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F)
6410 #else // not __cplusplus
6411 #define   GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT))
6412
6413 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F)
6414 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET)  ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F)
6415 #endif // __cplusplus
6416
6417 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION
6418 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION
6419
6420 /****************************************************************************/
6421 //Portion III: Definitinos only used in VBIOS
6422 /****************************************************************************/
6423 #define ATOM_DAC_SRC               0x80
6424 #define ATOM_SRC_DAC1               0
6425 #define ATOM_SRC_DAC2               0x80
6426
6427
6428
6429 typedef struct _MEMORY_PLLINIT_PARAMETERS
6430 {
6431   ULONG ulTargetMemoryClock; //In 10Khz unit
6432   UCHAR   ucAction;                //not define yet
6433   UCHAR   ucFbDiv_Hi;             //Fbdiv Hi byte
6434   UCHAR   ucFbDiv;                //FB value
6435   UCHAR   ucPostDiv;             //Post div
6436 }MEMORY_PLLINIT_PARAMETERS;
6437
6438 #define MEMORY_PLLINIT_PS_ALLOCATION  MEMORY_PLLINIT_PARAMETERS
6439
6440
6441 #define   GPIO_PIN_WRITE                                       0x01
6442 #define   GPIO_PIN_READ                                          0x00
6443
6444 typedef struct  _GPIO_PIN_CONTROL_PARAMETERS
6445 {
6446   UCHAR ucGPIO_ID;           //return value, read from GPIO pins
6447   UCHAR ucGPIOBitShift;        //define which bit in uGPIOBitVal need to be update
6448    UCHAR ucGPIOBitVal;           //Set/Reset corresponding bit defined in ucGPIOBitMask
6449   UCHAR ucAction;                 //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
6450 }GPIO_PIN_CONTROL_PARAMETERS;
6451
6452 typedef struct _ENABLE_SCALER_PARAMETERS
6453 {
6454   UCHAR ucScaler;            // ATOM_SCALER1, ATOM_SCALER2
6455   UCHAR ucEnable;            // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
6456   UCHAR ucTVStandard;        //
6457   UCHAR ucPadding[1];
6458 }ENABLE_SCALER_PARAMETERS;
6459 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS
6460
6461 //ucEnable:
6462 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION    0
6463 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION  1
6464 #define SCALER_ENABLE_2TAP_ALPHA_MODE               2
6465 #define SCALER_ENABLE_MULTITAP_MODE                 3
6466
6467 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS
6468 {
6469   ULONG  usHWIconHorzVertPosn;        // Hardware Icon Vertical position
6470   UCHAR  ucHWIconVertOffset;          // Hardware Icon Vertical offset
6471   UCHAR  ucHWIconHorzOffset;          // Hardware Icon Horizontal offset
6472   UCHAR  ucSelection;                 // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
6473   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
6474 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS;
6475
6476 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION
6477 {
6478   ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS  sEnableIcon;
6479   ENABLE_CRTC_PARAMETERS                  sReserved;
6480 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION;
6481
6482 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS
6483 {
6484   USHORT usHight;                     // Image Hight
6485   USHORT usWidth;                     // Image Width
6486   UCHAR  ucSurface;                   // Surface 1 or 2
6487   UCHAR  ucPadding[3];
6488 }ENABLE_GRAPH_SURFACE_PARAMETERS;
6489
6490 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2
6491 {
6492   USHORT usHight;                     // Image Hight
6493   USHORT usWidth;                     // Image Width
6494   UCHAR  ucSurface;                   // Surface 1 or 2
6495   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
6496   UCHAR  ucPadding[2];
6497 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2;
6498
6499 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3
6500 {
6501   USHORT usHight;                     // Image Hight
6502   USHORT usWidth;                     // Image Width
6503   UCHAR  ucSurface;                   // Surface 1 or 2
6504   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
6505   USHORT usDeviceId;                  // Active Device Id for this surface. If no device, set to 0.
6506 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3;
6507
6508 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4
6509 {
6510   USHORT usHight;                     // Image Hight
6511   USHORT usWidth;                     // Image Width
6512   USHORT usGraphPitch;
6513   UCHAR  ucColorDepth;
6514   UCHAR  ucPixelFormat;
6515   UCHAR  ucSurface;                   // Surface 1 or 2
6516   UCHAR  ucEnable;                    // ATOM_ENABLE or ATOM_DISABLE
6517   UCHAR  ucModeType;
6518   UCHAR  ucReserved;
6519 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4;
6520
6521 // ucEnable
6522 #define ATOM_GRAPH_CONTROL_SET_PITCH             0x0f
6523 #define ATOM_GRAPH_CONTROL_SET_DISP_START        0x10
6524
6525 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION
6526 {
6527   ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface;
6528   ENABLE_YUV_PS_ALLOCATION        sReserved; // Don't set this one
6529 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION;
6530
6531 typedef struct _MEMORY_CLEAN_UP_PARAMETERS
6532 {
6533   USHORT  usMemoryStart;                //in 8Kb boundry, offset from memory base address
6534   USHORT  usMemorySize;                 //8Kb blocks aligned
6535 }MEMORY_CLEAN_UP_PARAMETERS;
6536
6537 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS
6538
6539 typedef struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS
6540 {
6541   USHORT  usX_Size;                     //When use as input parameter, usX_Size indicates which CRTC
6542   USHORT  usY_Size;
6543 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS;
6544
6545 typedef struct  _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2
6546 {
6547   union{
6548     USHORT  usX_Size;                     //When use as input parameter, usX_Size indicates which CRTC
6549     USHORT  usSurface;
6550   };
6551   USHORT usY_Size;
6552   USHORT usDispXStart;
6553   USHORT usDispYStart;
6554 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2;
6555
6556
6557 typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3
6558 {
6559   UCHAR  ucLutId;
6560   UCHAR  ucAction;
6561   USHORT usLutStartIndex;
6562   USHORT usLutLength;
6563   USHORT usLutOffsetInVram;
6564 }PALETTE_DATA_CONTROL_PARAMETERS_V3;
6565
6566 // ucAction:
6567 #define PALETTE_DATA_AUTO_FILL            1
6568 #define PALETTE_DATA_READ                 2
6569 #define PALETTE_DATA_WRITE                3
6570
6571
6572 typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2
6573 {
6574   UCHAR  ucInterruptId;
6575   UCHAR  ucServiceId;
6576   UCHAR  ucStatus;
6577   UCHAR  ucReserved;
6578 }INTERRUPT_SERVICE_PARAMETER_V2;
6579
6580 // ucInterruptId
6581 #define HDP1_INTERRUPT_ID                 1
6582 #define HDP2_INTERRUPT_ID                 2
6583 #define HDP3_INTERRUPT_ID                 3
6584 #define HDP4_INTERRUPT_ID                 4
6585 #define HDP5_INTERRUPT_ID                 5
6586 #define HDP6_INTERRUPT_ID                 6
6587 #define SW_INTERRUPT_ID                   11
6588
6589 // ucAction
6590 #define INTERRUPT_SERVICE_GEN_SW_INT      1
6591 #define INTERRUPT_SERVICE_GET_STATUS      2
6592
6593  // ucStatus
6594 #define INTERRUPT_STATUS__INT_TRIGGER     1
6595 #define INTERRUPT_STATUS__HPD_HIGH        2
6596
6597 typedef struct _EFUSE_INPUT_PARAMETER
6598 {
6599   USHORT usEfuseIndex;
6600   UCHAR  ucBitShift;
6601   UCHAR  ucBitLength;
6602 }EFUSE_INPUT_PARAMETER;
6603
6604 // ReadEfuseValue command table input/output parameter
6605 typedef union _READ_EFUSE_VALUE_PARAMETER
6606 {
6607   EFUSE_INPUT_PARAMETER sEfuse;
6608   ULONG                 ulEfuseValue;
6609 }READ_EFUSE_VALUE_PARAMETER;
6610
6611 typedef struct _INDIRECT_IO_ACCESS
6612 {
6613   ATOM_COMMON_TABLE_HEADER sHeader;
6614   UCHAR                    IOAccessSequence[256];
6615 } INDIRECT_IO_ACCESS;
6616
6617 #define INDIRECT_READ              0x00
6618 #define INDIRECT_WRITE             0x80
6619
6620 #define INDIRECT_IO_MM             0
6621 #define INDIRECT_IO_PLL            1
6622 #define INDIRECT_IO_MC             2
6623 #define INDIRECT_IO_PCIE           3
6624 #define INDIRECT_IO_PCIEP          4
6625 #define INDIRECT_IO_NBMISC         5
6626 #define INDIRECT_IO_SMU            5
6627
6628 #define INDIRECT_IO_PLL_READ       INDIRECT_IO_PLL   | INDIRECT_READ
6629 #define INDIRECT_IO_PLL_WRITE      INDIRECT_IO_PLL   | INDIRECT_WRITE
6630 #define INDIRECT_IO_MC_READ        INDIRECT_IO_MC    | INDIRECT_READ
6631 #define INDIRECT_IO_MC_WRITE       INDIRECT_IO_MC    | INDIRECT_WRITE
6632 #define INDIRECT_IO_PCIE_READ      INDIRECT_IO_PCIE  | INDIRECT_READ
6633 #define INDIRECT_IO_PCIE_WRITE     INDIRECT_IO_PCIE  | INDIRECT_WRITE
6634 #define INDIRECT_IO_PCIEP_READ     INDIRECT_IO_PCIEP | INDIRECT_READ
6635 #define INDIRECT_IO_PCIEP_WRITE    INDIRECT_IO_PCIEP | INDIRECT_WRITE
6636 #define INDIRECT_IO_NBMISC_READ    INDIRECT_IO_NBMISC | INDIRECT_READ
6637 #define INDIRECT_IO_NBMISC_WRITE   INDIRECT_IO_NBMISC | INDIRECT_WRITE
6638 #define INDIRECT_IO_SMU_READ       INDIRECT_IO_SMU | INDIRECT_READ
6639 #define INDIRECT_IO_SMU_WRITE      INDIRECT_IO_SMU | INDIRECT_WRITE
6640
6641
6642 typedef struct _ATOM_OEM_INFO
6643 {
6644   ATOM_COMMON_TABLE_HEADER   sHeader;
6645   ATOM_I2C_ID_CONFIG_ACCESS sucI2cId;
6646 }ATOM_OEM_INFO;
6647
6648 typedef struct _ATOM_TV_MODE
6649 {
6650    UCHAR   ucVMode_Num;           //Video mode number
6651    UCHAR   ucTV_Mode_Num;         //Internal TV mode number
6652 }ATOM_TV_MODE;
6653
6654 typedef struct _ATOM_BIOS_INT_TVSTD_MODE
6655 {
6656   ATOM_COMMON_TABLE_HEADER sHeader;
6657    USHORT   usTV_Mode_LUT_Offset;   // Pointer to standard to internal number conversion table
6658    USHORT   usTV_FIFO_Offset;        // Pointer to FIFO entry table
6659    USHORT   usNTSC_Tbl_Offset;      // Pointer to SDTV_Mode_NTSC table
6660    USHORT   usPAL_Tbl_Offset;        // Pointer to SDTV_Mode_PAL table
6661    USHORT   usCV_Tbl_Offset;        // Pointer to SDTV_Mode_PAL table
6662 }ATOM_BIOS_INT_TVSTD_MODE;
6663
6664
6665 typedef struct _ATOM_TV_MODE_SCALER_PTR
6666 {
6667    USHORT   ucFilter0_Offset;      //Pointer to filter format 0 coefficients
6668    USHORT   usFilter1_Offset;      //Pointer to filter format 0 coefficients
6669    UCHAR   ucTV_Mode_Num;
6670 }ATOM_TV_MODE_SCALER_PTR;
6671
6672 typedef struct _ATOM_STANDARD_VESA_TIMING
6673 {
6674   ATOM_COMMON_TABLE_HEADER sHeader;
6675   ATOM_DTD_FORMAT              aModeTimings[16];      // 16 is not the real array number, just for initial allocation
6676 }ATOM_STANDARD_VESA_TIMING;
6677
6678
6679 typedef struct _ATOM_STD_FORMAT
6680 {
6681   USHORT    usSTD_HDisp;
6682   USHORT    usSTD_VDisp;
6683   USHORT    usSTD_RefreshRate;
6684   USHORT    usReserved;
6685 }ATOM_STD_FORMAT;
6686
6687 typedef struct _ATOM_VESA_TO_EXTENDED_MODE
6688 {
6689   USHORT  usVESA_ModeNumber;
6690   USHORT  usExtendedModeNumber;
6691 }ATOM_VESA_TO_EXTENDED_MODE;
6692
6693 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT
6694 {
6695   ATOM_COMMON_TABLE_HEADER   sHeader;
6696   ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76];
6697 }ATOM_VESA_TO_INTENAL_MODE_LUT;
6698
6699 /*************** ATOM Memory Related Data Structure ***********************/
6700 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{
6701    UCHAR                                    ucMemoryType;
6702    UCHAR                                    ucMemoryVendor;
6703    UCHAR                                    ucAdjMCId;
6704    UCHAR                                    ucDynClkId;
6705    ULONG                                    ulDllResetClkRange;
6706 }ATOM_MEMORY_VENDOR_BLOCK;
6707
6708
6709 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{
6710 #if ATOM_BIG_ENDIAN
6711         ULONG                                                                                           ucMemBlkId:8;
6712         ULONG                                                                                           ulMemClockRange:24;
6713 #else
6714         ULONG                                                                                           ulMemClockRange:24;
6715         ULONG                                                                                           ucMemBlkId:8;
6716 #endif
6717 }ATOM_MEMORY_SETTING_ID_CONFIG;
6718
6719 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS
6720 {
6721   ATOM_MEMORY_SETTING_ID_CONFIG slAccess;
6722   ULONG                         ulAccess;
6723 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS;
6724
6725
6726 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{
6727    ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS  ulMemoryID;
6728    ULONG                                 aulMemData[1];
6729 }ATOM_MEMORY_SETTING_DATA_BLOCK;
6730
6731
6732 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{
6733     USHORT usRegIndex;                                     // MC register index
6734     UCHAR  ucPreRegDataLength;                             // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
6735 }ATOM_INIT_REG_INDEX_FORMAT;
6736
6737
6738 typedef struct _ATOM_INIT_REG_BLOCK{
6739    USHORT                           usRegIndexTblSize;          //size of asRegIndexBuf
6740    USHORT                           usRegDataBlkSize;           //size of ATOM_MEMORY_SETTING_DATA_BLOCK
6741    ATOM_INIT_REG_INDEX_FORMAT       asRegIndexBuf[1];
6742    ATOM_MEMORY_SETTING_DATA_BLOCK   asRegDataBuf[1];
6743 }ATOM_INIT_REG_BLOCK;
6744
6745 #define END_OF_REG_INDEX_BLOCK  0x0ffff
6746 #define END_OF_REG_DATA_BLOCK   0x00000000
6747 #define ATOM_INIT_REG_MASK_FLAG 0x80               //Not used in BIOS
6748 #define CLOCK_RANGE_HIGHEST     0x00ffffff
6749
6750 #define VALUE_DWORD             SIZEOF ULONG
6751 #define VALUE_SAME_AS_ABOVE     0
6752 #define VALUE_MASK_DWORD        0x84
6753
6754 #define INDEX_ACCESS_RANGE_BEGIN       (VALUE_DWORD + 1)
6755 #define INDEX_ACCESS_RANGE_END          (INDEX_ACCESS_RANGE_BEGIN + 1)
6756 #define VALUE_INDEX_ACCESS_SINGLE       (INDEX_ACCESS_RANGE_END + 1)
6757 //#define ACCESS_MCIODEBUGIND            0x40       //defined in BIOS code
6758 #define ACCESS_PLACEHOLDER             0x80
6759
6760
6761 typedef struct _ATOM_MC_INIT_PARAM_TABLE
6762 {
6763   ATOM_COMMON_TABLE_HEADER      sHeader;
6764   USHORT                        usAdjustARB_SEQDataOffset;
6765   USHORT                        usMCInitMemTypeTblOffset;
6766   USHORT                        usMCInitCommonTblOffset;
6767   USHORT                        usMCInitPowerDownTblOffset;
6768   ULONG                         ulARB_SEQDataBuf[32];
6769   ATOM_INIT_REG_BLOCK           asMCInitMemType;
6770   ATOM_INIT_REG_BLOCK           asMCInitCommon;
6771 }ATOM_MC_INIT_PARAM_TABLE;
6772
6773
6774 typedef struct _ATOM_REG_INIT_SETTING
6775 {
6776   USHORT  usRegIndex;
6777   ULONG   ulRegValue;
6778 }ATOM_REG_INIT_SETTING;
6779
6780 typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1
6781 {
6782   ATOM_COMMON_TABLE_HEADER      sHeader;
6783   ULONG                         ulMCUcodeVersion;
6784   ULONG                         ulMCUcodeRomStartAddr;
6785   ULONG                         ulMCUcodeLength;
6786   USHORT                        usMcRegInitTableOffset;     // offset of ATOM_REG_INIT_SETTING array for MC core register settings.
6787   USHORT                        usReserved;                 // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting
6788 }ATOM_MC_INIT_PARAM_TABLE_V2_1;
6789
6790
6791 #define _4Mx16              0x2
6792 #define _4Mx32              0x3
6793 #define _8Mx16              0x12
6794 #define _8Mx32              0x13
6795 #define _8Mx128             0x15
6796 #define _16Mx16             0x22
6797 #define _16Mx32             0x23
6798 #define _16Mx128            0x25
6799 #define _32Mx16             0x32
6800 #define _32Mx32             0x33
6801 #define _32Mx128            0x35
6802 #define _64Mx32             0x43
6803 #define _64Mx8              0x41
6804 #define _64Mx16             0x42
6805 #define _128Mx8             0x51
6806 #define _128Mx16            0x52
6807 #define _128Mx32            0x53
6808 #define _256Mx8             0x61
6809 #define _256Mx16            0x62
6810 #define _512Mx8             0x71
6811
6812
6813 #define SAMSUNG             0x1
6814 #define INFINEON            0x2
6815 #define ELPIDA              0x3
6816 #define ETRON               0x4
6817 #define NANYA               0x5
6818 #define HYNIX               0x6
6819 #define MOSEL               0x7
6820 #define WINBOND             0x8
6821 #define ESMT                0x9
6822 #define MICRON              0xF
6823
6824 #define QIMONDA             INFINEON
6825 #define PROMOS              MOSEL
6826 #define KRETON              INFINEON
6827 #define ELIXIR              NANYA
6828 #define MEZZA               ELPIDA
6829
6830
6831 /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM/////////////
6832
6833 #define UCODE_ROM_START_ADDRESS      0x1b800
6834 #define   UCODE_SIGNATURE         0x4375434d // 'MCuC' - MC uCode
6835
6836 //uCode block header for reference
6837
6838 typedef struct _MCuCodeHeader
6839 {
6840   ULONG  ulSignature;
6841   UCHAR  ucRevision;
6842   UCHAR  ucChecksum;
6843   UCHAR  ucReserved1;
6844   UCHAR  ucReserved2;
6845   USHORT usParametersLength;
6846   USHORT usUCodeLength;
6847   USHORT usReserved1;
6848   USHORT usReserved2;
6849 } MCuCodeHeader;
6850
6851 //////////////////////////////////////////////////////////////////////////////////
6852
6853 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE   16
6854
6855 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK   0xF
6856 typedef struct _ATOM_VRAM_MODULE_V1
6857 {
6858   ULONG                      ulReserved;
6859   USHORT                     usEMRSValue;
6860   USHORT                     usMRSValue;
6861   USHORT                     usReserved;
6862   UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6863   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
6864   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender
6865   UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
6866   UCHAR                      ucRow;             // Number of Row,in power of 2;
6867   UCHAR                      ucColumn;          // Number of Column,in power of 2;
6868   UCHAR                      ucBank;            // Nunber of Bank;
6869   UCHAR                      ucRank;            // Number of Rank, in power of 2
6870   UCHAR                      ucChannelNum;      // Number of channel;
6871   UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
6872   UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6873   UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6874   UCHAR                      ucReserved[2];
6875 }ATOM_VRAM_MODULE_V1;
6876
6877
6878 typedef struct _ATOM_VRAM_MODULE_V2
6879 {
6880   ULONG                      ulReserved;
6881   ULONG                      ulFlags;              // To enable/disable functionalities based on memory type
6882   ULONG                      ulEngineClock;     // Override of default engine clock for particular memory type
6883   ULONG                      ulMemoryClock;     // Override of default memory clock for particular memory type
6884   USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
6885   USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
6886   USHORT                     usEMRSValue;
6887   USHORT                     usMRSValue;
6888   USHORT                     usReserved;
6889   UCHAR                      ucExtMemoryID;     // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
6890   UCHAR                      ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
6891   UCHAR                      ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
6892   UCHAR                      ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
6893   UCHAR                      ucRow;             // Number of Row,in power of 2;
6894   UCHAR                      ucColumn;          // Number of Column,in power of 2;
6895   UCHAR                      ucBank;            // Nunber of Bank;
6896   UCHAR                      ucRank;            // Number of Rank, in power of 2
6897   UCHAR                      ucChannelNum;      // Number of channel;
6898   UCHAR                      ucChannelConfig;   // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
6899   UCHAR                      ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
6900   UCHAR                      ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
6901   UCHAR                      ucRefreshRateFactor;
6902   UCHAR                      ucReserved[3];
6903 }ATOM_VRAM_MODULE_V2;
6904
6905
6906 typedef   struct _ATOM_MEMORY_TIMING_FORMAT
6907 {
6908    ULONG                     ulClkRange;            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6909   union{
6910     USHORT                   usMRS;                 // mode register
6911     USHORT                   usDDR3_MR0;
6912   };
6913   union{
6914     USHORT                   usEMRS;                  // extended mode register
6915     USHORT                   usDDR3_MR1;
6916   };
6917    UCHAR                     ucCL;                    // CAS latency
6918    UCHAR                     ucWL;                    // WRITE Latency
6919    UCHAR                     uctRAS;                  // tRAS
6920    UCHAR                     uctRC;                   // tRC
6921    UCHAR                     uctRFC;                  // tRFC
6922    UCHAR                     uctRCDR;                 // tRCDR
6923    UCHAR                     uctRCDW;                 // tRCDW
6924    UCHAR                     uctRP;                   // tRP
6925    UCHAR                     uctRRD;                  // tRRD
6926    UCHAR                     uctWR;                   // tWR
6927    UCHAR                     uctWTR;                  // tWTR
6928    UCHAR                     uctPDIX;                 // tPDIX
6929    UCHAR                     uctFAW;                  // tFAW
6930    UCHAR                     uctAOND;                 // tAOND
6931   union
6932   {
6933     struct {
6934        UCHAR                                  ucflag;                  // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6935        UCHAR                                  ucReserved;
6936     };
6937     USHORT                   usDDR3_MR2;
6938   };
6939 }ATOM_MEMORY_TIMING_FORMAT;
6940
6941
6942 typedef   struct _ATOM_MEMORY_TIMING_FORMAT_V1
6943 {
6944    ULONG                      ulClkRange;            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6945    USHORT                     usMRS;                 // mode register
6946    USHORT                     usEMRS;                // extended mode register
6947    UCHAR                      ucCL;                  // CAS latency
6948    UCHAR                      ucWL;                  // WRITE Latency
6949    UCHAR                      uctRAS;                // tRAS
6950    UCHAR                      uctRC;                 // tRC
6951    UCHAR                      uctRFC;                // tRFC
6952    UCHAR                      uctRCDR;               // tRCDR
6953    UCHAR                      uctRCDW;               // tRCDW
6954    UCHAR                      uctRP;                 // tRP
6955    UCHAR                      uctRRD;                // tRRD
6956    UCHAR                      uctWR;                 // tWR
6957    UCHAR                      uctWTR;                // tWTR
6958    UCHAR                      uctPDIX;               // tPDIX
6959    UCHAR                      uctFAW;                // tFAW
6960    UCHAR                      uctAOND;               // tAOND
6961    UCHAR                      ucflag;                // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6962 ////////////////////////////////////GDDR parameters///////////////////////////////////
6963    UCHAR                      uctCCDL;               //
6964    UCHAR                      uctCRCRL;              //
6965    UCHAR                      uctCRCWL;              //
6966    UCHAR                      uctCKE;                //
6967    UCHAR                      uctCKRSE;              //
6968    UCHAR                      uctCKRSX;              //
6969    UCHAR                      uctFAW32;              //
6970    UCHAR                      ucMR5lo;               //
6971    UCHAR                      ucMR5hi;               //
6972    UCHAR                      ucTerminator;
6973 }ATOM_MEMORY_TIMING_FORMAT_V1;
6974
6975
6976
6977
6978 typedef   struct _ATOM_MEMORY_TIMING_FORMAT_V2
6979 {
6980    ULONG                                  ulClkRange;            // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing
6981    USHORT                               usMRS;                     // mode register
6982    USHORT                               usEMRS;                  // extended mode register
6983    UCHAR                                  ucCL;                     // CAS latency
6984    UCHAR                                  ucWL;                     // WRITE Latency
6985    UCHAR                                  uctRAS;                  // tRAS
6986    UCHAR                                  uctRC;                     // tRC
6987    UCHAR                                  uctRFC;                  // tRFC
6988    UCHAR                                  uctRCDR;                  // tRCDR
6989    UCHAR                                  uctRCDW;                  // tRCDW
6990    UCHAR                                  uctRP;                     // tRP
6991    UCHAR                                  uctRRD;                  // tRRD
6992    UCHAR                                  uctWR;                     // tWR
6993    UCHAR                                  uctWTR;                  // tWTR
6994    UCHAR                                  uctPDIX;                  // tPDIX
6995    UCHAR                                  uctFAW;                  // tFAW
6996    UCHAR                                  uctAOND;                  // tAOND
6997    UCHAR                                  ucflag;                  // flag to control memory timing calculation. bit0= control EMRS2 Infineon
6998 ////////////////////////////////////GDDR parameters///////////////////////////////////
6999    UCHAR                                  uctCCDL;                  //
7000    UCHAR                                  uctCRCRL;                  //
7001    UCHAR                                  uctCRCWL;                  //
7002    UCHAR                                  uctCKE;                  //
7003    UCHAR                                  uctCKRSE;                  //
7004    UCHAR                                  uctCKRSX;                  //
7005    UCHAR                                  uctFAW32;                  //
7006    UCHAR                                  ucMR4lo;               //
7007    UCHAR                                  ucMR4hi;               //
7008    UCHAR                                  ucMR5lo;               //
7009    UCHAR                                  ucMR5hi;               //
7010    UCHAR                                  ucTerminator;
7011    UCHAR                                  ucReserved;
7012 }ATOM_MEMORY_TIMING_FORMAT_V2;
7013
7014
7015 typedef   struct _ATOM_MEMORY_FORMAT
7016 {
7017    ULONG                       ulDllDisClock;     // memory DLL will be disable when target memory clock is below this clock
7018   union{
7019     USHORT                     usEMRS2Value;      // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7020     USHORT                     usDDR3_Reserved;   // Not used for DDR3 memory
7021   };
7022   union{
7023     USHORT                     usEMRS3Value;      // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7024     USHORT                     usDDR3_MR3;        // Used for DDR3 memory
7025   };
7026   UCHAR                        ucMemoryType;      // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
7027   UCHAR                        ucMemoryVenderID;  // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
7028   UCHAR                        ucRow;             // Number of Row,in power of 2;
7029   UCHAR                        ucColumn;          // Number of Column,in power of 2;
7030   UCHAR                        ucBank;            // Nunber of Bank;
7031   UCHAR                        ucRank;            // Number of Rank, in power of 2
7032   UCHAR                        ucBurstSize;           // burst size, 0= burst size=4  1= burst size=8
7033   UCHAR                        ucDllDisBit;           // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
7034   UCHAR                        ucRefreshRateFactor;   // memory refresh rate in unit of ms
7035   UCHAR                        ucDensity;             // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7036   UCHAR                        ucPreamble;            // [7:4] Write Preamble, [3:0] Read Preamble
7037   UCHAR                        ucMemAttrib;           // Memory Device Addribute, like RDBI/WDBI etc
7038   ATOM_MEMORY_TIMING_FORMAT    asMemTiming[5];        // Memory Timing block sort from lower clock to higher clock
7039 }ATOM_MEMORY_FORMAT;
7040
7041
7042 typedef struct _ATOM_VRAM_MODULE_V3
7043 {
7044   ULONG                      ulChannelMapCfg;     // board dependent paramenter:Channel combination
7045   USHORT                     usSize;              // size of ATOM_VRAM_MODULE_V3
7046   USHORT                     usDefaultMVDDQ;      // board dependent parameter:Default Memory Core Voltage
7047   USHORT                     usDefaultMVDDC;      // board dependent parameter:Default Memory IO Voltage
7048   UCHAR                      ucExtMemoryID;       // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7049   UCHAR                      ucChannelNum;        // board dependent parameter:Number of channel;
7050   UCHAR                      ucChannelSize;       // board dependent parameter:32bit or 64bit
7051   UCHAR                      ucVREFI;             // board dependnt parameter: EXT or INT +160mv to -140mv
7052   UCHAR                      ucNPL_RT;            // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7053   UCHAR                      ucFlag;              // To enable/disable functionalities based on memory type
7054   ATOM_MEMORY_FORMAT         asMemory;            // describ all of video memory parameters from memory spec
7055 }ATOM_VRAM_MODULE_V3;
7056
7057
7058 //ATOM_VRAM_MODULE_V3.ucNPL_RT
7059 #define NPL_RT_MASK                                         0x0f
7060 #define BATTERY_ODT_MASK                                    0xc0
7061
7062 #define ATOM_VRAM_MODULE       ATOM_VRAM_MODULE_V3
7063
7064 typedef struct _ATOM_VRAM_MODULE_V4
7065 {
7066   ULONG     ulChannelMapCfg;                   // board dependent parameter: Channel combination
7067   USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7068   USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7069                                             // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7070   USHORT  usReserved;
7071   UCHAR   ucExtMemoryID;                      // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7072   UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7073   UCHAR   ucChannelNum;                     // Number of channels present in this module config
7074   UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
7075    UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7076    UCHAR     ucFlag;                                  // To enable/disable functionalities based on memory type
7077    UCHAR     ucMisc;                                  // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
7078   UCHAR      ucVREFI;                          // board dependent parameter
7079   UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7080   UCHAR      ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
7081   UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7082                                             // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7083   UCHAR   ucReserved[3];
7084
7085 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
7086   union{
7087     USHORT   usEMRS2Value;                   // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7088     USHORT  usDDR3_Reserved;
7089   };
7090   union{
7091     USHORT   usEMRS3Value;                   // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7092     USHORT  usDDR3_MR3;                     // Used for DDR3 memory
7093   };
7094   UCHAR   ucMemoryVenderID;                    // Predefined, If not predefined, vendor detection table gets executed
7095   UCHAR     ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7096   UCHAR   ucReserved2[2];
7097   ATOM_MEMORY_TIMING_FORMAT  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
7098 }ATOM_VRAM_MODULE_V4;
7099
7100 #define VRAM_MODULE_V4_MISC_RANK_MASK       0x3
7101 #define VRAM_MODULE_V4_MISC_DUAL_RANK       0x1
7102 #define VRAM_MODULE_V4_MISC_BL_MASK         0x4
7103 #define VRAM_MODULE_V4_MISC_BL8             0x4
7104 #define VRAM_MODULE_V4_MISC_DUAL_CS         0x10
7105
7106 typedef struct _ATOM_VRAM_MODULE_V5
7107 {
7108   ULONG     ulChannelMapCfg;                   // board dependent parameter: Channel combination
7109   USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7110   USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7111                                             // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7112   USHORT  usReserved;
7113   UCHAR   ucExtMemoryID;                      // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7114   UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7115   UCHAR   ucChannelNum;                     // Number of channels present in this module config
7116   UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
7117    UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7118    UCHAR     ucFlag;                                  // To enable/disable functionalities based on memory type
7119    UCHAR     ucMisc;                                  // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
7120   UCHAR      ucVREFI;                          // board dependent parameter
7121   UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7122   UCHAR      ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
7123   UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7124                                             // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7125   UCHAR   ucReserved[3];
7126
7127 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
7128   USHORT   usEMRS2Value;                        // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7129   USHORT   usEMRS3Value;                        // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7130   UCHAR   ucMemoryVenderID;                    // Predefined, If not predefined, vendor detection table gets executed
7131   UCHAR     ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7132   UCHAR     ucFIFODepth;                         // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
7133   UCHAR   ucCDR_Bandwidth;         // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7134   ATOM_MEMORY_TIMING_FORMAT_V1  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
7135 }ATOM_VRAM_MODULE_V5;
7136
7137
7138 typedef struct _ATOM_VRAM_MODULE_V6
7139 {
7140   ULONG     ulChannelMapCfg;                   // board dependent parameter: Channel combination
7141   USHORT  usModuleSize;                     // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE
7142   USHORT  usPrivateReserved;                // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7143                                             // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7144   USHORT  usReserved;
7145   UCHAR   ucExtMemoryID;                      // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7146   UCHAR   ucMemoryType;                     // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7147   UCHAR   ucChannelNum;                     // Number of channels present in this module config
7148   UCHAR   ucChannelWidth;                   // 0 - 32 bits; 1 - 64 bits
7149    UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7150    UCHAR     ucFlag;                                  // To enable/disable functionalities based on memory type
7151    UCHAR     ucMisc;                                  // bit0: 0 - single rank; 1 - dual rank;   bit2: 0 - burstlength 4, 1 - burstlength 8
7152   UCHAR      ucVREFI;                          // board dependent parameter
7153   UCHAR   ucNPL_RT;                         // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7154   UCHAR      ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
7155   UCHAR   ucMemorySize;                     // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7156                                             // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7157   UCHAR   ucReserved[3];
7158
7159 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level
7160   USHORT   usEMRS2Value;                        // EMRS2 Value is used for GDDR2 and GDDR4 memory type
7161   USHORT   usEMRS3Value;                        // EMRS3 Value is used for GDDR2 and GDDR4 memory type
7162   UCHAR   ucMemoryVenderID;                    // Predefined, If not predefined, vendor detection table gets executed
7163   UCHAR     ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7164   UCHAR     ucFIFODepth;                         // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
7165   UCHAR   ucCDR_Bandwidth;         // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7166   ATOM_MEMORY_TIMING_FORMAT_V2  asMemTiming[5];//Memory Timing block sort from lower clock to higher clock
7167 }ATOM_VRAM_MODULE_V6;
7168
7169 typedef struct _ATOM_VRAM_MODULE_V7
7170 {
7171 // Design Specific Values
7172   ULONG   ulChannelMapCfg;                   // mmMC_SHARED_CHREMAP
7173   USHORT  usModuleSize;                     // Size of ATOM_VRAM_MODULE_V7
7174   USHORT  usPrivateReserved;                // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7175   USHORT  usEnableChannels;                 // bit vector which indicate which channels are enabled
7176   UCHAR   ucExtMemoryID;                    // Current memory module ID
7177   UCHAR   ucMemoryType;                     // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7178   UCHAR   ucChannelNum;                     // Number of mem. channels supported in this module
7179   UCHAR   ucChannelWidth;                   // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7180   UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7181   UCHAR   ucReserve;                        // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used.
7182   UCHAR   ucMisc;                           // RANK_OF_THISMEMORY etc.
7183   UCHAR   ucVREFI;                          // Not used.
7184   UCHAR   ucNPL_RT;                         // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7185   UCHAR   ucPreamble;                       // [7:4] Write Preamble, [3:0] Read Preamble
7186   UCHAR   ucMemorySize;                     // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7187   USHORT  usSEQSettingOffset;
7188   UCHAR   ucReserved;
7189 // Memory Module specific values
7190   USHORT  usEMRS2Value;                     // EMRS2/MR2 Value.
7191   USHORT  usEMRS3Value;                     // EMRS3/MR3 Value.
7192   UCHAR   ucMemoryVenderID;                 // [7:4] Revision, [3:0] Vendor code
7193   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7194   UCHAR   ucFIFODepth;                      // FIFO depth can be detected during vendor detection, here is hardcoded per memory
7195   UCHAR   ucCDR_Bandwidth;                  // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7196   char    strMemPNString[20];               // part number end with '0'.
7197 }ATOM_VRAM_MODULE_V7;
7198
7199
7200 typedef struct _ATOM_VRAM_MODULE_V8
7201 {
7202 // Design Specific Values
7203   ULONG   ulChannelMapCfg;                  // mmMC_SHARED_CHREMAP
7204   USHORT  usModuleSize;                     // Size of ATOM_VRAM_MODULE_V7
7205   USHORT  usMcRamCfg;                       // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS)
7206   USHORT  usEnableChannels;                 // bit vector which indicate which channels are enabled
7207   UCHAR   ucExtMemoryID;                    // Current memory module ID
7208   UCHAR   ucMemoryType;                     // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7209   UCHAR   ucChannelNum;                     // Number of mem. channels supported in this module
7210   UCHAR   ucChannelWidth;                   // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7211   UCHAR   ucDensity;                        // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7212   UCHAR   ucBankCol;                        // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit )
7213   UCHAR   ucMisc;                           // RANK_OF_THISMEMORY etc.
7214   UCHAR   ucVREFI;                          // Not used.
7215   USHORT  usReserved;                       // Not used
7216   USHORT  usMemorySize;                     // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
7217   UCHAR   ucMcTunningSetId;                 // MC phy registers set per.
7218   UCHAR   ucRowNum;
7219 // Memory Module specific values
7220   USHORT  usEMRS2Value;                     // EMRS2/MR2 Value.
7221   USHORT  usEMRS3Value;                     // EMRS3/MR3 Value.
7222   UCHAR   ucMemoryVenderID;                 // [7:4] Revision, [3:0] Vendor code
7223   UCHAR   ucRefreshRateFactor;              // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7224   UCHAR   ucFIFODepth;                      // FIFO depth can be detected during vendor detection, here is hardcoded per memory
7225   UCHAR   ucCDR_Bandwidth;                  // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7226
7227   ULONG   ulChannelMapCfg1;                 // channel mapping for channel8~15
7228   ULONG   ulBankMapCfg;
7229   ULONG   ulReserved;
7230   char    strMemPNString[20];               // part number end with '0'.
7231 }ATOM_VRAM_MODULE_V8;
7232
7233
7234 typedef struct _ATOM_VRAM_INFO_V2
7235 {
7236   ATOM_COMMON_TABLE_HEADER   sHeader;
7237   UCHAR                      ucNumOfVRAMModule;
7238   ATOM_VRAM_MODULE           aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7239 }ATOM_VRAM_INFO_V2;
7240
7241 typedef struct _ATOM_VRAM_INFO_V3
7242 {
7243   ATOM_COMMON_TABLE_HEADER  sHeader;
7244   USHORT                    usMemAdjustTblOffset;                            // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7245   USHORT                    usMemClkPatchTblOffset;                          // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7246   USHORT                    usRerseved;
7247   UCHAR                     aVID_PinsShift[9];                               // 8 bit strap maximum+terminator
7248   UCHAR                     ucNumOfVRAMModule;
7249   ATOM_VRAM_MODULE          aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];       // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7250   ATOM_INIT_REG_BLOCK       asMemPatch;                                      // for allocation
7251
7252 }ATOM_VRAM_INFO_V3;
7253
7254 #define   ATOM_VRAM_INFO_LAST        ATOM_VRAM_INFO_V3
7255
7256 typedef struct _ATOM_VRAM_INFO_V4
7257 {
7258   ATOM_COMMON_TABLE_HEADER   sHeader;
7259   USHORT                     usMemAdjustTblOffset;                           // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7260   USHORT                     usMemClkPatchTblOffset;                         // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7261   USHORT                     usRerseved;
7262   UCHAR                      ucMemDQ7_0ByteRemap;                            // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
7263   ULONG                      ulMemDQ7_0BitRemap;                             // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21]
7264   UCHAR                      ucReservde[4];
7265   UCHAR                      ucNumOfVRAMModule;
7266   ATOM_VRAM_MODULE_V4        aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7267   ATOM_INIT_REG_BLOCK        asMemPatch;                                     // for allocation
7268 }ATOM_VRAM_INFO_V4;
7269
7270 typedef struct _ATOM_VRAM_INFO_HEADER_V2_1
7271 {
7272   ATOM_COMMON_TABLE_HEADER   sHeader;
7273   USHORT                     usMemAdjustTblOffset;                           // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7274   USHORT                     usMemClkPatchTblOffset;                         // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7275   USHORT                     usPerBytePresetOffset;                          // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
7276   USHORT                     usReserved[3];
7277   UCHAR                      ucNumOfVRAMModule;                              // indicate number of VRAM module
7278   UCHAR                      ucMemoryClkPatchTblVer;                         // version of memory AC timing register list
7279   UCHAR                      ucVramModuleVer;                                // indicate ATOM_VRAM_MODUE version
7280   UCHAR                      ucReserved;
7281   ATOM_VRAM_MODULE_V7        aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7282 }ATOM_VRAM_INFO_HEADER_V2_1;
7283
7284 typedef struct _ATOM_VRAM_INFO_HEADER_V2_2
7285 {
7286   ATOM_COMMON_TABLE_HEADER   sHeader;
7287   USHORT                     usMemAdjustTblOffset;                           // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting
7288   USHORT                     usMemClkPatchTblOffset;                         // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting
7289   USHORT                     usMcAdjustPerTileTblOffset;                     // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings
7290   USHORT                     usMcPhyInitTableOffset;                         // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set
7291   USHORT                     usDramDataRemapTblOffset;                       // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping
7292   USHORT                     usReserved1;
7293   UCHAR                      ucNumOfVRAMModule;                              // indicate number of VRAM module
7294   UCHAR                      ucMemoryClkPatchTblVer;                         // version of memory AC timing register list
7295   UCHAR                      ucVramModuleVer;                                // indicate ATOM_VRAM_MODUE version
7296   UCHAR                      ucMcPhyTileNum;                                 // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
7297   ATOM_VRAM_MODULE_V8        aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE];      // just for allocation, real number of blocks is in ucNumOfVRAMModule;
7298 }ATOM_VRAM_INFO_HEADER_V2_2;
7299
7300
7301 typedef struct _ATOM_DRAM_DATA_REMAP
7302 {
7303   UCHAR ucByteRemapCh0;
7304   UCHAR ucByteRemapCh1;
7305   ULONG ulByte0BitRemapCh0;
7306   ULONG ulByte1BitRemapCh0;
7307   ULONG ulByte2BitRemapCh0;
7308   ULONG ulByte3BitRemapCh0;
7309   ULONG ulByte0BitRemapCh1;
7310   ULONG ulByte1BitRemapCh1;
7311   ULONG ulByte2BitRemapCh1;
7312   ULONG ulByte3BitRemapCh1;
7313 }ATOM_DRAM_DATA_REMAP;
7314
7315 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO
7316 {
7317   ATOM_COMMON_TABLE_HEADER   sHeader;
7318   UCHAR                      aVID_PinsShift[9];                              // 8 bit strap maximum+terminator
7319 }ATOM_VRAM_GPIO_DETECTION_INFO;
7320
7321
7322 typedef struct _ATOM_MEMORY_TRAINING_INFO
7323 {
7324    ATOM_COMMON_TABLE_HEADER   sHeader;
7325    UCHAR                                  ucTrainingLoop;
7326    UCHAR                                  ucReserved[3];
7327    ATOM_INIT_REG_BLOCK             asMemTrainingSetting;
7328 }ATOM_MEMORY_TRAINING_INFO;
7329
7330
7331 typedef struct SW_I2C_CNTL_DATA_PARAMETERS
7332 {
7333   UCHAR    ucControl;
7334   UCHAR    ucData;
7335   UCHAR    ucSatus;
7336   UCHAR    ucTemp;
7337 } SW_I2C_CNTL_DATA_PARAMETERS;
7338
7339 #define SW_I2C_CNTL_DATA_PS_ALLOCATION  SW_I2C_CNTL_DATA_PARAMETERS
7340
7341 typedef struct _SW_I2C_IO_DATA_PARAMETERS
7342 {
7343   USHORT   GPIO_Info;
7344   UCHAR    ucAct;
7345   UCHAR    ucData;
7346  } SW_I2C_IO_DATA_PARAMETERS;
7347
7348 #define SW_I2C_IO_DATA_PS_ALLOCATION  SW_I2C_IO_DATA_PARAMETERS
7349
7350 /****************************SW I2C CNTL DEFINITIONS**********************/
7351 #define SW_I2C_IO_RESET       0
7352 #define SW_I2C_IO_GET         1
7353 #define SW_I2C_IO_DRIVE       2
7354 #define SW_I2C_IO_SET         3
7355 #define SW_I2C_IO_START       4
7356
7357 #define SW_I2C_IO_CLOCK       0
7358 #define SW_I2C_IO_DATA        0x80
7359
7360 #define SW_I2C_IO_ZERO        0
7361 #define SW_I2C_IO_ONE         0x100
7362
7363 #define SW_I2C_CNTL_READ      0
7364 #define SW_I2C_CNTL_WRITE     1
7365 #define SW_I2C_CNTL_START     2
7366 #define SW_I2C_CNTL_STOP      3
7367 #define SW_I2C_CNTL_OPEN      4
7368 #define SW_I2C_CNTL_CLOSE     5
7369 #define SW_I2C_CNTL_WRITE1BIT 6
7370
7371 //==============================VESA definition Portion===============================
7372 #define VESA_OEM_PRODUCT_REV                     '01.00'
7373 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT        0xBB   //refer to VBE spec p.32, no TTY support
7374 #define VESA_MODE_WIN_ATTRIBUTE                       7
7375 #define VESA_WIN_SIZE                                      64
7376
7377 typedef struct _PTR_32_BIT_STRUCTURE
7378 {
7379    USHORT   Offset16;
7380    USHORT   Segment16;
7381 } PTR_32_BIT_STRUCTURE;
7382
7383 typedef union _PTR_32_BIT_UNION
7384 {
7385    PTR_32_BIT_STRUCTURE   SegmentOffset;
7386    ULONG                       Ptr32_Bit;
7387 } PTR_32_BIT_UNION;
7388
7389 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE
7390 {
7391    UCHAR                  VbeSignature[4];
7392    USHORT                VbeVersion;
7393    PTR_32_BIT_UNION   OemStringPtr;
7394    UCHAR                  Capabilities[4];
7395    PTR_32_BIT_UNION   VideoModePtr;
7396    USHORT                TotalMemory;
7397 } VBE_1_2_INFO_BLOCK_UPDATABLE;
7398
7399
7400 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE
7401 {
7402    VBE_1_2_INFO_BLOCK_UPDATABLE   CommonBlock;
7403    USHORT                         OemSoftRev;
7404    PTR_32_BIT_UNION            OemVendorNamePtr;
7405    PTR_32_BIT_UNION            OemProductNamePtr;
7406    PTR_32_BIT_UNION            OemProductRevPtr;
7407 } VBE_2_0_INFO_BLOCK_UPDATABLE;
7408
7409 typedef union _VBE_VERSION_UNION
7410 {
7411    VBE_2_0_INFO_BLOCK_UPDATABLE   VBE_2_0_InfoBlock;
7412    VBE_1_2_INFO_BLOCK_UPDATABLE   VBE_1_2_InfoBlock;
7413 } VBE_VERSION_UNION;
7414
7415 typedef struct _VBE_INFO_BLOCK
7416 {
7417    VBE_VERSION_UNION         UpdatableVBE_Info;
7418    UCHAR                        Reserved[222];
7419    UCHAR                        OemData[256];
7420 } VBE_INFO_BLOCK;
7421
7422 typedef struct _VBE_FP_INFO
7423 {
7424   USHORT   HSize;
7425   USHORT   VSize;
7426   USHORT   FPType;
7427   UCHAR    RedBPP;
7428   UCHAR    GreenBPP;
7429   UCHAR    BlueBPP;
7430   UCHAR    ReservedBPP;
7431   ULONG    RsvdOffScrnMemSize;
7432   ULONG    RsvdOffScrnMEmPtr;
7433   UCHAR    Reserved[14];
7434 } VBE_FP_INFO;
7435
7436 typedef struct _VESA_MODE_INFO_BLOCK
7437 {
7438 // Mandatory information for all VBE revisions
7439   USHORT   ModeAttributes;  //         dw   ?   ; mode attributes
7440   UCHAR    WinAAttributes;  //         db   ?   ; window A attributes
7441   UCHAR    WinBAttributes;  //         db   ?   ; window B attributes
7442   USHORT   WinGranularity;  //         dw   ?   ; window granularity
7443   USHORT   WinSize;         //         dw   ?   ; window size
7444   USHORT   WinASegment;     //         dw   ?   ; window A start segment
7445   USHORT   WinBSegment;     //         dw   ?   ; window B start segment
7446   ULONG    WinFuncPtr;      //         dd   ?   ; real mode pointer to window function
7447   USHORT   BytesPerScanLine;//         dw   ?   ; bytes per scan line
7448
7449 //; Mandatory information for VBE 1.2 and above
7450   USHORT   XResolution;      //         dw   ?   ; horizontal resolution in pixels or characters
7451   USHORT   YResolution;      //         dw   ?   ; vertical resolution in pixels or characters
7452   UCHAR    XCharSize;        //         db   ?   ; character cell width in pixels
7453   UCHAR    YCharSize;        //         db   ?   ; character cell height in pixels
7454   UCHAR    NumberOfPlanes;   //         db   ?   ; number of memory planes
7455   UCHAR    BitsPerPixel;     //         db   ?   ; bits per pixel
7456   UCHAR    NumberOfBanks;    //         db   ?   ; number of banks
7457   UCHAR    MemoryModel;      //         db   ?   ; memory model type
7458   UCHAR    BankSize;         //         db   ?   ; bank size in KB
7459   UCHAR    NumberOfImagePages;//        db   ?   ; number of images
7460   UCHAR    ReservedForPageFunction;//db   1   ; reserved for page function
7461
7462 //; Direct Color fields(required for direct/6 and YUV/7 memory models)
7463   UCHAR    RedMaskSize;        //      db   ?   ; size of direct color red mask in bits
7464   UCHAR    RedFieldPosition;   //      db   ?   ; bit position of lsb of red mask
7465   UCHAR    GreenMaskSize;      //      db   ?   ; size of direct color green mask in bits
7466   UCHAR    GreenFieldPosition; //      db   ?   ; bit position of lsb of green mask
7467   UCHAR    BlueMaskSize;       //      db   ?   ; size of direct color blue mask in bits
7468   UCHAR    BlueFieldPosition;  //      db   ?   ; bit position of lsb of blue mask
7469   UCHAR    RsvdMaskSize;       //      db   ?   ; size of direct color reserved mask in bits
7470   UCHAR    RsvdFieldPosition;  //      db   ?   ; bit position of lsb of reserved mask
7471   UCHAR    DirectColorModeInfo;//      db   ?   ; direct color mode attributes
7472
7473 //; Mandatory information for VBE 2.0 and above
7474   ULONG    PhysBasePtr;        //      dd   ?   ; physical address for flat memory frame buffer
7475   ULONG    Reserved_1;         //      dd   0   ; reserved - always set to 0
7476   USHORT   Reserved_2;         //     dw   0   ; reserved - always set to 0
7477
7478 //; Mandatory information for VBE 3.0 and above
7479   USHORT   LinBytesPerScanLine;  //   dw   ?   ; bytes per scan line for linear modes
7480   UCHAR    BnkNumberOfImagePages;//   db   ?   ; number of images for banked modes
7481   UCHAR    LinNumberOfImagPages; //   db   ?   ; number of images for linear modes
7482   UCHAR    LinRedMaskSize;       //   db   ?   ; size of direct color red mask(linear modes)
7483   UCHAR    LinRedFieldPosition;  //   db   ?   ; bit position of lsb of red mask(linear modes)
7484   UCHAR    LinGreenMaskSize;     //   db   ?   ; size of direct color green mask(linear modes)
7485   UCHAR    LinGreenFieldPosition;//   db   ?   ; bit position of lsb of green mask(linear modes)
7486   UCHAR    LinBlueMaskSize;      //   db   ?   ; size of direct color blue mask(linear modes)
7487   UCHAR    LinBlueFieldPosition; //   db   ?   ; bit position of lsb of blue mask(linear modes)
7488   UCHAR    LinRsvdMaskSize;      //   db   ?   ; size of direct color reserved mask(linear modes)
7489   UCHAR    LinRsvdFieldPosition; //   db   ?   ; bit position of lsb of reserved mask(linear modes)
7490   ULONG    MaxPixelClock;        //   dd   ?   ; maximum pixel clock(in Hz) for graphics mode
7491   UCHAR    Reserved;             //   db   190 dup (0)
7492 } VESA_MODE_INFO_BLOCK;
7493
7494 // BIOS function CALLS
7495 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE        0xA0           // ATI Extended Function code
7496 #define ATOM_BIOS_FUNCTION_COP_MODE             0x00
7497 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1         0x04
7498 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2         0x05
7499 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3         0x06
7500 #define ATOM_BIOS_FUNCTION_GET_DDC              0x0B
7501 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE          0x0E
7502 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY           0x0F
7503 #define ATOM_BIOS_FUNCTION_STV_STD              0x16
7504 #define ATOM_BIOS_FUNCTION_DEVICE_DET           0x17
7505 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH        0x18
7506
7507 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL        0x82
7508 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET       0x83
7509 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH    0x84
7510 #define ATOM_BIOS_FUNCTION_HW_ICON              0x8A
7511 #define ATOM_BIOS_FUNCTION_SET_CMOS             0x8B
7512 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO        0x8000          // Sub function 80
7513 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO      0x8100          // Sub function 80
7514
7515 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO         0x8D
7516 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF        0x8E
7517 #define ATOM_BIOS_FUNCTION_VIDEO_STATE          0x8F
7518 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE    0x0300          // Sub function 03
7519 #define ATOM_SUB_FUNCTION_GET_LIDSTATE          0x0700          // Sub function 7
7520 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE  0x1400          // Notify caller the current thermal state
7521 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300          // Notify caller the current critical state
7522 #define ATOM_SUB_FUNCTION_SET_LIDSTATE          0x8500          // Sub function 85
7523 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89
7524 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT    0x9400          // Notify caller that ADC is supported
7525
7526
7527 #define ATOM_BIOS_FUNCTION_VESA_DPMS            0x4F10          // Set DPMS
7528 #define ATOM_SUB_FUNCTION_SET_DPMS              0x0001          // BL: Sub function 01
7529 #define ATOM_SUB_FUNCTION_GET_DPMS              0x0002          // BL: Sub function 02
7530 #define ATOM_PARAMETER_VESA_DPMS_ON             0x0000          // BH Parameter for DPMS ON.
7531 #define ATOM_PARAMETER_VESA_DPMS_STANDBY        0x0100          // BH Parameter for DPMS STANDBY
7532 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND        0x0200          // BH Parameter for DPMS SUSPEND
7533 #define ATOM_PARAMETER_VESA_DPMS_OFF            0x0400          // BH Parameter for DPMS OFF
7534 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON      0x0800          // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED)
7535
7536 #define ATOM_BIOS_RETURN_CODE_MASK              0x0000FF00L
7537 #define ATOM_BIOS_REG_HIGH_MASK                 0x0000FF00L
7538 #define ATOM_BIOS_REG_LOW_MASK                  0x000000FFL
7539
7540 // structure used for VBIOS only
7541
7542 //DispOutInfoTable
7543 typedef struct _ASIC_TRANSMITTER_INFO
7544 {
7545    USHORT usTransmitterObjId;
7546    USHORT usSupportDevice;
7547   UCHAR  ucTransmitterCmdTblId;
7548    UCHAR  ucConfig;
7549    UCHAR  ucEncoderID;                //available 1st encoder ( default )
7550    UCHAR  ucOptionEncoderID;    //available 2nd encoder ( optional )
7551    UCHAR  uc2ndEncoderID;
7552    UCHAR  ucReserved;
7553 }ASIC_TRANSMITTER_INFO;
7554
7555 #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE          0x01
7556 #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE         0x02
7557 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK    0xc4
7558 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A             0x00
7559 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B             0x04
7560 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C             0x40
7561 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D             0x44
7562 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E             0x80
7563 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F             0x84
7564
7565 typedef struct _ASIC_ENCODER_INFO
7566 {
7567    UCHAR ucEncoderID;
7568    UCHAR ucEncoderConfig;
7569   USHORT usEncoderCmdTblId;
7570 }ASIC_ENCODER_INFO;
7571
7572 typedef struct _ATOM_DISP_OUT_INFO
7573 {
7574   ATOM_COMMON_TABLE_HEADER sHeader;
7575    USHORT ptrTransmitterInfo;
7576    USHORT ptrEncoderInfo;
7577    ASIC_TRANSMITTER_INFO  asTransmitterInfo[1];
7578    ASIC_ENCODER_INFO      asEncoderInfo[1];
7579 }ATOM_DISP_OUT_INFO;
7580
7581
7582 typedef struct _ATOM_DISP_OUT_INFO_V2
7583 {
7584   ATOM_COMMON_TABLE_HEADER sHeader;
7585    USHORT ptrTransmitterInfo;
7586    USHORT ptrEncoderInfo;
7587   USHORT ptrMainCallParserFar;                  // direct address of main parser call in VBIOS binary.
7588    ASIC_TRANSMITTER_INFO  asTransmitterInfo[1];
7589    ASIC_ENCODER_INFO      asEncoderInfo[1];
7590 }ATOM_DISP_OUT_INFO_V2;
7591
7592
7593 typedef struct _ATOM_DISP_CLOCK_ID {
7594   UCHAR ucPpllId;
7595   UCHAR ucPpllAttribute;
7596 }ATOM_DISP_CLOCK_ID;
7597
7598 // ucPpllAttribute
7599 #define CLOCK_SOURCE_SHAREABLE            0x01
7600 #define CLOCK_SOURCE_DP_MODE              0x02
7601 #define CLOCK_SOURCE_NONE_DP_MODE         0x04
7602
7603 //DispOutInfoTable
7604 typedef struct _ASIC_TRANSMITTER_INFO_V2
7605 {
7606    USHORT usTransmitterObjId;
7607    USHORT usDispClkIdOffset;    // point to clock source id list supported by Encoder Object
7608   UCHAR  ucTransmitterCmdTblId;
7609    UCHAR  ucConfig;
7610    UCHAR  ucEncoderID;                // available 1st encoder ( default )
7611    UCHAR  ucOptionEncoderID;    // available 2nd encoder ( optional )
7612    UCHAR  uc2ndEncoderID;
7613    UCHAR  ucReserved;
7614 }ASIC_TRANSMITTER_INFO_V2;
7615
7616 typedef struct _ATOM_DISP_OUT_INFO_V3
7617 {
7618   ATOM_COMMON_TABLE_HEADER sHeader;
7619   USHORT ptrTransmitterInfo;
7620   USHORT ptrEncoderInfo;
7621   USHORT ptrMainCallParserFar;                  // direct address of main parser call in VBIOS binary.
7622   USHORT usReserved;
7623   UCHAR  ucDCERevision;
7624   UCHAR  ucMaxDispEngineNum;
7625   UCHAR  ucMaxActiveDispEngineNum;
7626   UCHAR  ucMaxPPLLNum;
7627   UCHAR  ucCoreRefClkSource;                    // value of CORE_REF_CLK_SOURCE
7628   UCHAR  ucDispCaps;
7629   UCHAR  ucReserved[2];
7630   ASIC_TRANSMITTER_INFO_V2  asTransmitterInfo[1];     // for alligment only
7631 }ATOM_DISP_OUT_INFO_V3;
7632
7633 //ucDispCaps
7634 #define DISPLAY_CAPS__DP_PCLK_FROM_PPLL        0x01
7635 #define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED  0x02
7636
7637 typedef enum CORE_REF_CLK_SOURCE{
7638   CLOCK_SRC_XTALIN=0,
7639   CLOCK_SRC_XO_IN=1,
7640   CLOCK_SRC_XO_IN2=2,
7641 }CORE_REF_CLK_SOURCE;
7642
7643 // DispDevicePriorityInfo
7644 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO
7645 {
7646   ATOM_COMMON_TABLE_HEADER sHeader;
7647    USHORT asDevicePriority[16];
7648 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO;
7649
7650 //ProcessAuxChannelTransactionTable
7651 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
7652 {
7653    USHORT  lpAuxRequest;
7654    USHORT  lpDataOut;
7655    UCHAR   ucChannelID;
7656    union
7657    {
7658   UCHAR   ucReplyStatus;
7659    UCHAR   ucDelay;
7660    };
7661   UCHAR   ucDataOutLen;
7662    UCHAR   ucReserved;
7663 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS;
7664
7665 //ProcessAuxChannelTransactionTable
7666 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2
7667 {
7668    USHORT   lpAuxRequest;
7669    USHORT  lpDataOut;
7670    UCHAR      ucChannelID;
7671    union
7672    {
7673   UCHAR   ucReplyStatus;
7674    UCHAR   ucDelay;
7675    };
7676   UCHAR   ucDataOutLen;
7677    UCHAR   ucHPD_ID;                                       //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
7678 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2;
7679
7680 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION         PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS
7681
7682 //GetSinkType
7683
7684 typedef struct _DP_ENCODER_SERVICE_PARAMETERS
7685 {
7686    USHORT ucLinkClock;
7687    union
7688    {
7689    UCHAR ucConfig;            // for DP training command
7690    UCHAR ucI2cId;            // use for GET_SINK_TYPE command
7691    };
7692    UCHAR ucAction;
7693    UCHAR ucStatus;
7694    UCHAR ucLaneNum;
7695    UCHAR ucReserved[2];
7696 }DP_ENCODER_SERVICE_PARAMETERS;
7697
7698 // ucAction
7699 #define ATOM_DP_ACTION_GET_SINK_TYPE                     0x01
7700
7701 #define DP_ENCODER_SERVICE_PS_ALLOCATION            WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
7702
7703
7704 typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2
7705 {
7706    USHORT usExtEncoderObjId;   // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
7707   UCHAR  ucAuxId;
7708   UCHAR  ucAction;
7709   UCHAR  ucSinkType;          // Iput and Output parameters.
7710   UCHAR  ucHPDId;             // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
7711    UCHAR  ucReserved[2];
7712 }DP_ENCODER_SERVICE_PARAMETERS_V2;
7713
7714 typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2
7715 {
7716   DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam;
7717   PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam;
7718 }DP_ENCODER_SERVICE_PS_ALLOCATION_V2;
7719
7720 // ucAction
7721 #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE                     0x01
7722 #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION             0x02
7723
7724
7725 // DP_TRAINING_TABLE
7726 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR            ATOM_DP_TRAINING_TBL_ADDR
7727 #define DPCD_SET_SS_CNTL_TBL_ADDR                                       (ATOM_DP_TRAINING_TBL_ADDR + 8 )
7728 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR                     (ATOM_DP_TRAINING_TBL_ADDR + 16 )
7729 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR                        (ATOM_DP_TRAINING_TBL_ADDR + 24 )
7730 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR                        (ATOM_DP_TRAINING_TBL_ADDR + 32)
7731 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR                     (ATOM_DP_TRAINING_TBL_ADDR + 40)
7732 #define   DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR                     (ATOM_DP_TRAINING_TBL_ADDR + 48)
7733 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR                        (ATOM_DP_TRAINING_TBL_ADDR + 60)
7734 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR                                 (ATOM_DP_TRAINING_TBL_ADDR + 64)
7735 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR                        (ATOM_DP_TRAINING_TBL_ADDR + 72)
7736 #define DP_I2C_AUX_DDC_READ_TBL_ADDR                                 (ATOM_DP_TRAINING_TBL_ADDR + 76)
7737 #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR                 (ATOM_DP_TRAINING_TBL_ADDR + 80)
7738 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR                           (ATOM_DP_TRAINING_TBL_ADDR + 84)
7739
7740
7741 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
7742 {
7743    UCHAR   ucI2CSpeed;
7744     union
7745    {
7746    UCHAR ucRegIndex;
7747    UCHAR ucStatus;
7748    };
7749    USHORT  lpI2CDataOut;
7750   UCHAR   ucFlag;
7751   UCHAR   ucTransBytes;
7752   UCHAR   ucSlaveAddr;
7753   UCHAR   ucLineNumber;
7754 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS;
7755
7756 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION       PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS
7757
7758 //ucFlag
7759 #define HW_I2C_WRITE        1
7760 #define HW_I2C_READ         0
7761 #define I2C_2BYTE_ADDR      0x02
7762
7763 /****************************************************************************/
7764 // Structures used by HW_Misc_OperationTable
7765 /****************************************************************************/
7766 typedef struct  _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1
7767 {
7768   UCHAR  ucCmd;                //  Input: To tell which action to take
7769   UCHAR  ucReserved[3];
7770   ULONG  ulReserved;
7771 }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1;
7772
7773 typedef struct  _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1
7774 {
7775   UCHAR  ucReturnCode;        // Output: Return value base on action was taken
7776   UCHAR  ucReserved[3];
7777   ULONG  ulReserved;
7778 }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1;
7779
7780 // Actions code
7781 #define  ATOM_GET_SDI_SUPPORT              0xF0
7782
7783 // Return code
7784 #define  ATOM_UNKNOWN_CMD                   0
7785 #define  ATOM_FEATURE_NOT_SUPPORTED         1
7786 #define  ATOM_FEATURE_SUPPORTED             2
7787
7788 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION
7789 {
7790    ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1        sInput_Output;
7791    PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS         sReserved;
7792 }ATOM_HW_MISC_OPERATION_PS_ALLOCATION;
7793
7794 /****************************************************************************/
7795
7796 typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2
7797 {
7798    UCHAR ucHWBlkInst;                // HW block instance, 0, 1, 2, ...
7799    UCHAR ucReserved[3];
7800 }SET_HWBLOCK_INSTANCE_PARAMETER_V2;
7801
7802 #define HWBLKINST_INSTANCE_MASK       0x07
7803 #define HWBLKINST_HWBLK_MASK          0xF0
7804 #define HWBLKINST_HWBLK_SHIFT         0x04
7805
7806 //ucHWBlock
7807 #define SELECT_DISP_ENGINE            0
7808 #define SELECT_DISP_PLL               1
7809 #define SELECT_DCIO_UNIPHY_LINK0      2
7810 #define SELECT_DCIO_UNIPHY_LINK1      3
7811 #define SELECT_DCIO_IMPCAL            4
7812 #define SELECT_DCIO_DIG               6
7813 #define SELECT_CRTC_PIXEL_RATE        7
7814 #define SELECT_VGA_BLK                8
7815
7816 // DIGTransmitterInfoTable structure used to program UNIPHY settings
7817 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{
7818   ATOM_COMMON_TABLE_HEADER sHeader;
7819   USHORT usDPVsPreEmphSettingOffset;     // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
7820   USHORT usPhyAnalogRegListOffset;       // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
7821   USHORT usPhyAnalogSettingOffset;       // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
7822   USHORT usPhyPllRegListOffset;          // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
7823   USHORT usPhyPllSettingOffset;          // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
7824 }DIG_TRANSMITTER_INFO_HEADER_V3_1;
7825
7826 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{
7827   ATOM_COMMON_TABLE_HEADER sHeader;
7828   USHORT usDPVsPreEmphSettingOffset;     // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
7829   USHORT usPhyAnalogRegListOffset;       // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
7830   USHORT usPhyAnalogSettingOffset;       // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
7831   USHORT usPhyPllRegListOffset;          // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
7832   USHORT usPhyPllSettingOffset;          // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
7833   USHORT usDPSSRegListOffset;            // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
7834   USHORT usDPSSSettingOffset;            // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
7835 }DIG_TRANSMITTER_INFO_HEADER_V3_2;
7836
7837
7838 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{
7839   ATOM_COMMON_TABLE_HEADER sHeader;
7840   USHORT usDPVsPreEmphSettingOffset;     // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock
7841   USHORT usPhyAnalogRegListOffset;       // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info
7842   USHORT usPhyAnalogSettingOffset;       // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range
7843   USHORT usPhyPllRegListOffset;          // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info
7844   USHORT usPhyPllSettingOffset;          // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings
7845   USHORT usDPSSRegListOffset;            // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info
7846   USHORT usDPSSSettingOffset;            // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings
7847   USHORT usEDPVsLegacyModeOffset;        // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock
7848   USHORT useDPVsLowVdiffModeOffset;      // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
7849   USHORT useDPVsHighVdiffModeOffset;     // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock
7850   USHORT useDPVsStretchModeOffset;       // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock
7851   USHORT useDPVsSingleVdiffModeOffset;   // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock
7852   USHORT useDPVsVariablePremModeOffset;  // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock
7853 }DIG_TRANSMITTER_INFO_HEADER_V3_3;
7854
7855
7856 typedef struct _CLOCK_CONDITION_REGESTER_INFO{
7857   USHORT usRegisterIndex;
7858   UCHAR  ucStartBit;
7859   UCHAR  ucEndBit;
7860 }CLOCK_CONDITION_REGESTER_INFO;
7861
7862 typedef struct _CLOCK_CONDITION_SETTING_ENTRY{
7863   USHORT usMaxClockFreq;
7864   UCHAR  ucEncodeMode;
7865   UCHAR  ucPhySel;
7866   ULONG  ulAnalogSetting[1];
7867 }CLOCK_CONDITION_SETTING_ENTRY;
7868
7869 typedef struct _CLOCK_CONDITION_SETTING_INFO{
7870   USHORT usEntrySize;
7871   CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1];
7872 }CLOCK_CONDITION_SETTING_INFO;
7873
7874 typedef struct _PHY_CONDITION_REG_VAL{
7875   ULONG  ulCondition;
7876   ULONG  ulRegVal;
7877 }PHY_CONDITION_REG_VAL;
7878
7879 typedef struct _PHY_CONDITION_REG_VAL_V2{
7880   ULONG  ulCondition;
7881   UCHAR  ucCondition2;
7882   ULONG  ulRegVal;
7883 }PHY_CONDITION_REG_VAL_V2;
7884
7885 typedef struct _PHY_CONDITION_REG_INFO{
7886   USHORT usRegIndex;
7887   USHORT usSize;
7888   PHY_CONDITION_REG_VAL asRegVal[1];
7889 }PHY_CONDITION_REG_INFO;
7890
7891 typedef struct _PHY_CONDITION_REG_INFO_V2{
7892   USHORT usRegIndex;
7893   USHORT usSize;
7894   PHY_CONDITION_REG_VAL_V2 asRegVal[1];
7895 }PHY_CONDITION_REG_INFO_V2;
7896
7897 typedef struct _PHY_ANALOG_SETTING_INFO{
7898   UCHAR  ucEncodeMode;
7899   UCHAR  ucPhySel;
7900   USHORT usSize;
7901   PHY_CONDITION_REG_INFO  asAnalogSetting[1];
7902 }PHY_ANALOG_SETTING_INFO;
7903
7904 typedef struct _PHY_ANALOG_SETTING_INFO_V2{
7905   UCHAR  ucEncodeMode;
7906   UCHAR  ucPhySel;
7907   USHORT usSize;
7908   PHY_CONDITION_REG_INFO_V2  asAnalogSetting[1];
7909 }PHY_ANALOG_SETTING_INFO_V2;
7910
7911
7912 typedef struct _GFX_HAVESTING_PARAMETERS {
7913   UCHAR ucGfxBlkId;                        //GFX blk id to be harvested, like CU, RB or PRIM
7914   UCHAR ucReserved;                        //reserved
7915   UCHAR ucActiveUnitNumPerSH;              //requested active CU/RB/PRIM number per shader array
7916   UCHAR ucMaxUnitNumPerSH;                 //max CU/RB/PRIM number per shader array
7917 } GFX_HAVESTING_PARAMETERS;
7918
7919 //ucGfxBlkId
7920 #define GFX_HARVESTING_CU_ID               0
7921 #define GFX_HARVESTING_RB_ID               1
7922 #define GFX_HARVESTING_PRIM_ID             2
7923
7924
7925 typedef struct _VBIOS_ROM_HEADER{
7926   UCHAR  PciRomSignature[2];
7927   UCHAR  ucPciRomSizeIn512bytes;
7928   UCHAR  ucJumpCoreMainInitBIOS;
7929   USHORT usLabelCoreMainInitBIOS;
7930   UCHAR  PciReservedSpace[18];
7931   USHORT usPciDataStructureOffset;
7932   UCHAR  Rsvd1d_1a[4];
7933   char   strIbm[3];
7934   UCHAR  CheckSum[14];
7935   UCHAR  ucBiosMsgNumber;
7936   char   str761295520[16];
7937   USHORT usLabelCoreVPOSTNoMode;
7938   USHORT usSpecialPostOffset;
7939   UCHAR  ucSpeicalPostImageSizeIn512Bytes;
7940   UCHAR  Rsved47_45[3];
7941   USHORT usROM_HeaderInformationTableOffset;
7942   UCHAR  Rsved4f_4a[6];
7943   char   strBuildTimeStamp[20];
7944   UCHAR  ucJumpCoreXFuncFarHandler;
7945   USHORT usCoreXFuncFarHandlerOffset;
7946   UCHAR  ucRsved67;
7947   UCHAR  ucJumpCoreVFuncFarHandler;
7948   USHORT usCoreVFuncFarHandlerOffset;
7949   UCHAR  Rsved6d_6b[3];
7950   USHORT usATOM_BIOS_MESSAGE_Offset;
7951 }VBIOS_ROM_HEADER;
7952
7953 /****************************************************************************/
7954 //Portion VI: Definitinos for vbios MC scratch registers that driver used
7955 /****************************************************************************/
7956
7957 #define MC_MISC0__MEMORY_TYPE_MASK    0xF0000000
7958 #define MC_MISC0__MEMORY_TYPE__GDDR1  0x10000000
7959 #define MC_MISC0__MEMORY_TYPE__DDR2   0x20000000
7960 #define MC_MISC0__MEMORY_TYPE__GDDR3  0x30000000
7961 #define MC_MISC0__MEMORY_TYPE__GDDR4  0x40000000
7962 #define MC_MISC0__MEMORY_TYPE__GDDR5  0x50000000
7963 #define MC_MISC0__MEMORY_TYPE__HBM    0x60000000
7964 #define MC_MISC0__MEMORY_TYPE__DDR3   0xB0000000
7965
7966 #define ATOM_MEM_TYPE_DDR_STRING      "DDR"
7967 #define ATOM_MEM_TYPE_DDR2_STRING     "DDR2"
7968 #define ATOM_MEM_TYPE_GDDR3_STRING    "GDDR3"
7969 #define ATOM_MEM_TYPE_GDDR4_STRING    "GDDR4"
7970 #define ATOM_MEM_TYPE_GDDR5_STRING    "GDDR5"
7971 #define ATOM_MEM_TYPE_HBM_STRING      "HBM"
7972 #define ATOM_MEM_TYPE_DDR3_STRING     "DDR3"
7973
7974 /****************************************************************************/
7975 //Portion VII: Definitinos being oboselete
7976 /****************************************************************************/
7977
7978 //==========================================================================================
7979 //Remove the definitions below when driver is ready!
7980 typedef struct _ATOM_DAC_INFO
7981 {
7982   ATOM_COMMON_TABLE_HEADER sHeader;
7983   USHORT                   usMaxFrequency;      // in 10kHz unit
7984   USHORT                   usReserved;
7985 }ATOM_DAC_INFO;
7986
7987
7988 typedef struct  _COMPASSIONATE_DATA
7989 {
7990   ATOM_COMMON_TABLE_HEADER sHeader;
7991
7992   //==============================  DAC1 portion
7993   UCHAR   ucDAC1_BG_Adjustment;
7994   UCHAR   ucDAC1_DAC_Adjustment;
7995   USHORT  usDAC1_FORCE_Data;
7996   //==============================  DAC2 portion
7997   UCHAR   ucDAC2_CRT2_BG_Adjustment;
7998   UCHAR   ucDAC2_CRT2_DAC_Adjustment;
7999   USHORT  usDAC2_CRT2_FORCE_Data;
8000   USHORT  usDAC2_CRT2_MUX_RegisterIndex;
8001   UCHAR   ucDAC2_CRT2_MUX_RegisterInfo;     //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8002   UCHAR   ucDAC2_NTSC_BG_Adjustment;
8003   UCHAR   ucDAC2_NTSC_DAC_Adjustment;
8004   USHORT  usDAC2_TV1_FORCE_Data;
8005   USHORT  usDAC2_TV1_MUX_RegisterIndex;
8006   UCHAR   ucDAC2_TV1_MUX_RegisterInfo;      //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8007   UCHAR   ucDAC2_CV_BG_Adjustment;
8008   UCHAR   ucDAC2_CV_DAC_Adjustment;
8009   USHORT  usDAC2_CV_FORCE_Data;
8010   USHORT  usDAC2_CV_MUX_RegisterIndex;
8011   UCHAR   ucDAC2_CV_MUX_RegisterInfo;       //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8012   UCHAR   ucDAC2_PAL_BG_Adjustment;
8013   UCHAR   ucDAC2_PAL_DAC_Adjustment;
8014   USHORT  usDAC2_TV2_FORCE_Data;
8015 }COMPASSIONATE_DATA;
8016
8017 /****************************Supported Device Info Table Definitions**********************/
8018 //  ucConnectInfo:
8019 //    [7:4] - connector type
8020 //      = 1   - VGA connector
8021 //      = 2   - DVI-I
8022 //      = 3   - DVI-D
8023 //      = 4   - DVI-A
8024 //      = 5   - SVIDEO
8025 //      = 6   - COMPOSITE
8026 //      = 7   - LVDS
8027 //      = 8   - DIGITAL LINK
8028 //      = 9   - SCART
8029 //      = 0xA - HDMI_type A
8030 //      = 0xB - HDMI_type B
8031 //      = 0xE - Special case1 (DVI+DIN)
8032 //      Others=TBD
8033 //    [3:0] - DAC Associated
8034 //      = 0   - no DAC
8035 //      = 1   - DACA
8036 //      = 2   - DACB
8037 //      = 3   - External DAC
8038 //      Others=TBD
8039 //
8040
8041 typedef struct _ATOM_CONNECTOR_INFO
8042 {
8043 #if ATOM_BIG_ENDIAN
8044   UCHAR   bfConnectorType:4;
8045   UCHAR   bfAssociatedDAC:4;
8046 #else
8047   UCHAR   bfAssociatedDAC:4;
8048   UCHAR   bfConnectorType:4;
8049 #endif
8050 }ATOM_CONNECTOR_INFO;
8051
8052 typedef union _ATOM_CONNECTOR_INFO_ACCESS
8053 {
8054   ATOM_CONNECTOR_INFO sbfAccess;
8055   UCHAR               ucAccess;
8056 }ATOM_CONNECTOR_INFO_ACCESS;
8057
8058 typedef struct _ATOM_CONNECTOR_INFO_I2C
8059 {
8060   ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo;
8061   ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;
8062 }ATOM_CONNECTOR_INFO_I2C;
8063
8064
8065 typedef struct _ATOM_SUPPORTED_DEVICES_INFO
8066 {
8067   ATOM_COMMON_TABLE_HEADER   sHeader;
8068   USHORT                    usDeviceSupport;
8069   ATOM_CONNECTOR_INFO_I2C   asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO];
8070 }ATOM_SUPPORTED_DEVICES_INFO;
8071
8072 #define NO_INT_SRC_MAPPED       0xFF
8073
8074 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP
8075 {
8076   UCHAR   ucIntSrcBitmap;
8077 }ATOM_CONNECTOR_INC_SRC_BITMAP;
8078
8079 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2
8080 {
8081   ATOM_COMMON_TABLE_HEADER      sHeader;
8082   USHORT                        usDeviceSupport;
8083   ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
8084   ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2];
8085 }ATOM_SUPPORTED_DEVICES_INFO_2;
8086
8087 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1
8088 {
8089   ATOM_COMMON_TABLE_HEADER      sHeader;
8090   USHORT                        usDeviceSupport;
8091   ATOM_CONNECTOR_INFO_I2C       asConnInfo[ATOM_MAX_SUPPORTED_DEVICE];
8092   ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE];
8093 }ATOM_SUPPORTED_DEVICES_INFO_2d1;
8094
8095 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1
8096
8097
8098
8099 typedef struct _ATOM_MISC_CONTROL_INFO
8100 {
8101    USHORT usFrequency;
8102    UCHAR  ucPLL_ChargePump;                            // PLL charge-pump gain control
8103    UCHAR  ucPLL_DutyCycle;                            // PLL duty cycle control
8104    UCHAR  ucPLL_VCO_Gain;                              // PLL VCO gain control
8105    UCHAR  ucPLL_VoltageSwing;                         // PLL driver voltage swing control
8106 }ATOM_MISC_CONTROL_INFO;
8107
8108
8109 #define ATOM_MAX_MISC_INFO       4
8110
8111 typedef struct _ATOM_TMDS_INFO
8112 {
8113   ATOM_COMMON_TABLE_HEADER sHeader;
8114   USHORT                     usMaxFrequency;             // in 10Khz
8115   ATOM_MISC_CONTROL_INFO            asMiscInfo[ATOM_MAX_MISC_INFO];
8116 }ATOM_TMDS_INFO;
8117
8118
8119 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE
8120 {
8121   UCHAR ucTVStandard;     //Same as TV standards defined above,
8122   UCHAR ucPadding[1];
8123 }ATOM_ENCODER_ANALOG_ATTRIBUTE;
8124
8125 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE
8126 {
8127   UCHAR ucAttribute;      //Same as other digital encoder attributes defined above
8128   UCHAR ucPadding[1];
8129 }ATOM_ENCODER_DIGITAL_ATTRIBUTE;
8130
8131 typedef union _ATOM_ENCODER_ATTRIBUTE
8132 {
8133   ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib;
8134   ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib;
8135 }ATOM_ENCODER_ATTRIBUTE;
8136
8137
8138 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS
8139 {
8140   USHORT usPixelClock;
8141   USHORT usEncoderID;
8142   UCHAR  ucDeviceType;                                    //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
8143   UCHAR  ucAction;                                          //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
8144   ATOM_ENCODER_ATTRIBUTE usDevAttr;
8145 }DVO_ENCODER_CONTROL_PARAMETERS;
8146
8147 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION
8148 {
8149   DVO_ENCODER_CONTROL_PARAMETERS    sDVOEncoder;
8150   WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION      sReserved;     //Caller doesn't need to init this portion
8151 }DVO_ENCODER_CONTROL_PS_ALLOCATION;
8152
8153
8154 #define ATOM_XTMDS_ASIC_SI164_ID        1
8155 #define ATOM_XTMDS_ASIC_SI178_ID        2
8156 #define ATOM_XTMDS_ASIC_TFP513_ID       3
8157 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001
8158 #define ATOM_XTMDS_SUPPORTED_DUALLINK   0x00000002
8159 #define ATOM_XTMDS_MVPU_FPGA            0x00000004
8160
8161
8162 typedef struct _ATOM_XTMDS_INFO
8163 {
8164   ATOM_COMMON_TABLE_HEADER   sHeader;
8165   USHORT                     usSingleLinkMaxFrequency;
8166   ATOM_I2C_ID_CONFIG_ACCESS  sucI2cId;           //Point the ID on which I2C is used to control external chip
8167   UCHAR                      ucXtransimitterID;
8168   UCHAR                      ucSupportedLink;    // Bit field, bit0=1, single link supported;bit1=1,dual link supported
8169   UCHAR                      ucSequnceAlterID;   // Even with the same external TMDS asic, it's possible that the program seqence alters
8170                                                  // due to design. This ID is used to alert driver that the sequence is not "standard"!
8171   UCHAR                      ucMasterAddress;    // Address to control Master xTMDS Chip
8172   UCHAR                      ucSlaveAddress;     // Address to control Slave xTMDS Chip
8173 }ATOM_XTMDS_INFO;
8174
8175 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS
8176 {
8177   UCHAR ucEnable;                     // ATOM_ENABLE=On or ATOM_DISABLE=Off
8178   UCHAR ucDevice;                     // ATOM_DEVICE_DFP1_INDEX....
8179   UCHAR ucPadding[2];
8180 }DFP_DPMS_STATUS_CHANGE_PARAMETERS;
8181
8182 /****************************Legacy Power Play Table Definitions **********************/
8183
8184 //Definitions for ulPowerPlayMiscInfo
8185 #define ATOM_PM_MISCINFO_SPLIT_CLOCK                     0x00000000L
8186 #define ATOM_PM_MISCINFO_USING_MCLK_SRC                  0x00000001L
8187 #define ATOM_PM_MISCINFO_USING_SCLK_SRC                  0x00000002L
8188
8189 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT            0x00000004L
8190 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH        0x00000008L
8191
8192 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN             0x00000010L
8193
8194 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN          0x00000020L
8195 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN          0x00000040L
8196 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE                 0x00000080L  //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program
8197
8198 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN      0x00000100L
8199 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN         0x00000200L
8200 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN              0x00000400L
8201 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN                 0x00000800L
8202 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE     0x00001000L
8203 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L
8204 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE            0x00004000L
8205
8206 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE             0x00008000L
8207 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE                 0x00010000L
8208 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE                 0x00020000L
8209 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE               0x00040000L
8210 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE              0x00080000L
8211
8212 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK           0x00300000L  //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved
8213 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT          20
8214
8215 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE                 0x00400000L
8216 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2      0x00800000L
8217 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4      0x01000000L
8218 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN            0x02000000L  //When set, Dynamic
8219 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN        0x04000000L  //When set, Dynamic
8220 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN              0x08000000L  //When set, This mode is for acceleated 3D mode
8221
8222 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK   0x70000000L  //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks)
8223 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT  28
8224 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS                0x80000000L
8225
8226 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE            0x00000001L
8227 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT          0x00000002L
8228 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN           0x00000004L
8229 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO            0x00000008L
8230 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE              0x00000010L
8231 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN       0x00000020L
8232 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE         0x00000040L  //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption.
8233                                                                       //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback
8234 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC                0x00000080L
8235 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN                0x00000100L
8236 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE               0x00000200L
8237
8238 //ucTableFormatRevision=1
8239 //ucTableContentRevision=1
8240 typedef struct  _ATOM_POWERMODE_INFO
8241 {
8242   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
8243   ULONG     ulReserved1;                // must set to 0
8244   ULONG     ulReserved2;                // must set to 0
8245   USHORT    usEngineClock;
8246   USHORT    usMemoryClock;
8247   UCHAR     ucVoltageDropIndex;         // index to GPIO table
8248   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
8249   UCHAR     ucMinTemperature;
8250   UCHAR     ucMaxTemperature;
8251   UCHAR     ucNumPciELanes;             // number of PCIE lanes
8252 }ATOM_POWERMODE_INFO;
8253
8254 //ucTableFormatRevision=2
8255 //ucTableContentRevision=1
8256 typedef struct  _ATOM_POWERMODE_INFO_V2
8257 {
8258   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
8259   ULONG     ulMiscInfo2;
8260   ULONG     ulEngineClock;
8261   ULONG     ulMemoryClock;
8262   UCHAR     ucVoltageDropIndex;         // index to GPIO table
8263   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
8264   UCHAR     ucMinTemperature;
8265   UCHAR     ucMaxTemperature;
8266   UCHAR     ucNumPciELanes;             // number of PCIE lanes
8267 }ATOM_POWERMODE_INFO_V2;
8268
8269 //ucTableFormatRevision=2
8270 //ucTableContentRevision=2
8271 typedef struct  _ATOM_POWERMODE_INFO_V3
8272 {
8273   ULONG     ulMiscInfo;                 //The power level should be arranged in ascending order
8274   ULONG     ulMiscInfo2;
8275   ULONG     ulEngineClock;
8276   ULONG     ulMemoryClock;
8277   UCHAR     ucVoltageDropIndex;         // index to Core (VDDC) votage table
8278   UCHAR     ucSelectedPanel_RefreshRate;// panel refresh rate
8279   UCHAR     ucMinTemperature;
8280   UCHAR     ucMaxTemperature;
8281   UCHAR     ucNumPciELanes;             // number of PCIE lanes
8282   UCHAR     ucVDDCI_VoltageDropIndex;   // index to VDDCI votage table
8283 }ATOM_POWERMODE_INFO_V3;
8284
8285
8286 #define ATOM_MAX_NUMBEROF_POWER_BLOCK  8
8287
8288 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN            0x01
8289 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE         0x02
8290
8291 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63      0x01
8292 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032   0x02
8293 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030   0x03
8294 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649   0x04
8295 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64      0x05
8296 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375    0x06
8297 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512   0x07   // Andigilog
8298
8299
8300 typedef struct  _ATOM_POWERPLAY_INFO
8301 {
8302   ATOM_COMMON_TABLE_HEADER   sHeader;
8303   UCHAR    ucOverdriveThermalController;
8304   UCHAR    ucOverdriveI2cLine;
8305   UCHAR    ucOverdriveIntBitmap;
8306   UCHAR    ucOverdriveControllerAddress;
8307   UCHAR    ucSizeOfPowerModeEntry;
8308   UCHAR    ucNumOfPowerModeEntries;
8309   ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
8310 }ATOM_POWERPLAY_INFO;
8311
8312 typedef struct  _ATOM_POWERPLAY_INFO_V2
8313 {
8314   ATOM_COMMON_TABLE_HEADER   sHeader;
8315   UCHAR    ucOverdriveThermalController;
8316   UCHAR    ucOverdriveI2cLine;
8317   UCHAR    ucOverdriveIntBitmap;
8318   UCHAR    ucOverdriveControllerAddress;
8319   UCHAR    ucSizeOfPowerModeEntry;
8320   UCHAR    ucNumOfPowerModeEntries;
8321   ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
8322 }ATOM_POWERPLAY_INFO_V2;
8323
8324 typedef struct  _ATOM_POWERPLAY_INFO_V3
8325 {
8326   ATOM_COMMON_TABLE_HEADER   sHeader;
8327   UCHAR    ucOverdriveThermalController;
8328   UCHAR    ucOverdriveI2cLine;
8329   UCHAR    ucOverdriveIntBitmap;
8330   UCHAR    ucOverdriveControllerAddress;
8331   UCHAR    ucSizeOfPowerModeEntry;
8332   UCHAR    ucNumOfPowerModeEntries;
8333   ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK];
8334 }ATOM_POWERPLAY_INFO_V3;
8335
8336
8337
8338 /**************************************************************************/
8339
8340
8341 // Following definitions are for compatiblity issue in different SW components.
8342 #define ATOM_MASTER_DATA_TABLE_REVISION   0x01
8343 #define Object_Info                       Object_Header
8344 #define AdjustARB_SEQ                     MC_InitParameter
8345 #define VRAM_GPIO_DetectionInfo           VoltageObjectInfo
8346 #define ASIC_VDDCI_Info                   ASIC_ProfilingInfo
8347 #define ASIC_MVDDQ_Info                   MemoryTrainingInfo
8348 #define SS_Info                           PPLL_SS_Info
8349 #define ASIC_MVDDC_Info                   ASIC_InternalSS_Info
8350 #define DispDevicePriorityInfo            SaveRestoreInfo
8351 #define DispOutInfo                       TV_VideoMode
8352
8353
8354 #define ATOM_ENCODER_OBJECT_TABLE         ATOM_OBJECT_TABLE
8355 #define ATOM_CONNECTOR_OBJECT_TABLE       ATOM_OBJECT_TABLE
8356
8357 //New device naming, remove them when both DAL/VBIOS is ready
8358 #define DFP2I_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
8359 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS
8360
8361 #define DFP1X_OUTPUT_CONTROL_PARAMETERS    CRT1_OUTPUT_CONTROL_PARAMETERS
8362 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS
8363
8364 #define DFP1I_OUTPUT_CONTROL_PARAMETERS    DFP1_OUTPUT_CONTROL_PARAMETERS
8365 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION
8366
8367 #define ATOM_DEVICE_DFP1I_SUPPORT          ATOM_DEVICE_DFP1_SUPPORT
8368 #define ATOM_DEVICE_DFP1X_SUPPORT          ATOM_DEVICE_DFP2_SUPPORT
8369
8370 #define ATOM_DEVICE_DFP1I_INDEX            ATOM_DEVICE_DFP1_INDEX
8371 #define ATOM_DEVICE_DFP1X_INDEX            ATOM_DEVICE_DFP2_INDEX
8372
8373 #define ATOM_DEVICE_DFP2I_INDEX            0x00000009
8374 #define ATOM_DEVICE_DFP2I_SUPPORT          (0x1L << ATOM_DEVICE_DFP2I_INDEX)
8375
8376 #define ATOM_S0_DFP1I                      ATOM_S0_DFP1
8377 #define ATOM_S0_DFP1X                      ATOM_S0_DFP2
8378
8379 #define ATOM_S0_DFP2I                      0x00200000L
8380 #define ATOM_S0_DFP2Ib2                    0x20
8381
8382 #define ATOM_S2_DFP1I_DPMS_STATE           ATOM_S2_DFP1_DPMS_STATE
8383 #define ATOM_S2_DFP1X_DPMS_STATE           ATOM_S2_DFP2_DPMS_STATE
8384
8385 #define ATOM_S2_DFP2I_DPMS_STATE           0x02000000L
8386 #define ATOM_S2_DFP2I_DPMS_STATEb3         0x02
8387
8388 #define ATOM_S3_DFP2I_ACTIVEb1             0x02
8389
8390 #define ATOM_S3_DFP1I_ACTIVE               ATOM_S3_DFP1_ACTIVE
8391 #define ATOM_S3_DFP1X_ACTIVE               ATOM_S3_DFP2_ACTIVE
8392
8393 #define ATOM_S3_DFP2I_ACTIVE               0x00000200L
8394
8395 #define ATOM_S3_DFP1I_CRTC_ACTIVE          ATOM_S3_DFP1_CRTC_ACTIVE
8396 #define ATOM_S3_DFP1X_CRTC_ACTIVE          ATOM_S3_DFP2_CRTC_ACTIVE
8397 #define ATOM_S3_DFP2I_CRTC_ACTIVE          0x02000000L
8398
8399
8400 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3        0x02
8401 #define ATOM_S5_DOS_REQ_DFP2Ib1            0x02
8402
8403 #define ATOM_S5_DOS_REQ_DFP2I              0x0200
8404 #define ATOM_S6_ACC_REQ_DFP1I              ATOM_S6_ACC_REQ_DFP1
8405 #define ATOM_S6_ACC_REQ_DFP1X              ATOM_S6_ACC_REQ_DFP2
8406
8407 #define ATOM_S6_ACC_REQ_DFP2Ib3            0x02
8408 #define ATOM_S6_ACC_REQ_DFP2I              0x02000000L
8409
8410 #define TMDS1XEncoderControl               DVOEncoderControl
8411 #define DFP1XOutputControl                 DVOOutputControl
8412
8413 #define ExternalDFPOutputControl           DFP1XOutputControl
8414 #define EnableExternalTMDS_Encoder         TMDS1XEncoderControl
8415
8416 #define DFP1IOutputControl                 TMDSAOutputControl
8417 #define DFP2IOutputControl                 LVTMAOutputControl
8418
8419 #define DAC1_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
8420 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
8421
8422 #define DAC2_ENCODER_CONTROL_PARAMETERS    DAC_ENCODER_CONTROL_PARAMETERS
8423 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION
8424
8425 #define ucDac1Standard  ucDacStandard
8426 #define ucDac2Standard  ucDacStandard
8427
8428 #define TMDS1EncoderControl TMDSAEncoderControl
8429 #define TMDS2EncoderControl LVTMAEncoderControl
8430
8431 #define DFP1OutputControl   TMDSAOutputControl
8432 #define DFP2OutputControl   LVTMAOutputControl
8433 #define CRT1OutputControl   DAC1OutputControl
8434 #define CRT2OutputControl   DAC2OutputControl
8435
8436 //These two lines will be removed for sure in a few days, will follow up with Michael V.
8437 #define EnableLVDS_SS   EnableSpreadSpectrumOnPPLL
8438 #define ENABLE_LVDS_SS_PARAMETERS_V3  ENABLE_SPREAD_SPECTRUM_ON_PPLL
8439
8440 #define ATOM_S2_CRT1_DPMS_STATE         0x00010000L
8441 #define ATOM_S2_LCD1_DPMS_STATE           ATOM_S2_CRT1_DPMS_STATE
8442 #define ATOM_S2_TV1_DPMS_STATE          ATOM_S2_CRT1_DPMS_STATE
8443 #define ATOM_S2_DFP1_DPMS_STATE         ATOM_S2_CRT1_DPMS_STATE
8444 #define ATOM_S2_CRT2_DPMS_STATE         ATOM_S2_CRT1_DPMS_STATE
8445
8446 #define ATOM_S6_ACC_REQ_TV2             0x00400000L
8447 #define ATOM_DEVICE_TV2_INDEX           0x00000006
8448 #define ATOM_DEVICE_TV2_SUPPORT         (0x1L << ATOM_DEVICE_TV2_INDEX)
8449 #define ATOM_S0_TV2                     0x00100000L
8450 #define ATOM_S3_TV2_ACTIVE              ATOM_S3_DFP6_ACTIVE
8451 #define ATOM_S3_TV2_CRTC_ACTIVE         ATOM_S3_DFP6_CRTC_ACTIVE
8452
8453 /*********************************************************************************/
8454
8455 #pragma pack() // BIOS data must use byte aligment
8456
8457 #pragma pack(1)
8458
8459 typedef struct _ATOM_HOLE_INFO
8460 {
8461         USHORT  usOffset;               // offset of the hole ( from the start of the binary )
8462         USHORT  usLength;               // length of the hole ( in bytes )
8463 }ATOM_HOLE_INFO;
8464
8465 typedef struct _ATOM_SERVICE_DESCRIPTION
8466 {
8467    UCHAR   ucRevision;                               // Holes set revision
8468    UCHAR   ucAlgorithm;                              // Hash algorithm
8469    UCHAR   ucSignatureType;                                                      // Signature type ( 0 - no signature, 1 - test, 2 - production )
8470    UCHAR   ucReserved;
8471    USHORT  usSigOffset;                                                      // Signature offset ( from the start of the binary )
8472    USHORT  usSigLength;                              // Signature length
8473 }ATOM_SERVICE_DESCRIPTION;
8474
8475
8476 typedef struct _ATOM_SERVICE_INFO
8477 {
8478       ATOM_COMMON_TABLE_HEADER      asHeader;
8479       ATOM_SERVICE_DESCRIPTION          asDescr;
8480           UCHAR                                                 ucholesNo;              // number of holes that follow
8481           ATOM_HOLE_INFO                                holes[1];       // array of hole descriptions
8482 }ATOM_SERVICE_INFO;
8483
8484
8485
8486 #pragma pack() // BIOS data must use byte aligment
8487
8488 //
8489 // AMD ACPI Table
8490 //
8491 #pragma pack(1)
8492
8493 typedef struct {
8494   ULONG Signature;
8495   ULONG TableLength;      //Length
8496   UCHAR Revision;
8497   UCHAR Checksum;
8498   UCHAR OemId[6];
8499   UCHAR OemTableId[8];    //UINT64  OemTableId;
8500   ULONG OemRevision;
8501   ULONG CreatorId;
8502   ULONG CreatorRevision;
8503 } AMD_ACPI_DESCRIPTION_HEADER;
8504 /*
8505 //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h
8506 typedef struct {
8507   UINT32  Signature;       //0x0
8508   UINT32  Length;          //0x4
8509   UINT8   Revision;        //0x8
8510   UINT8   Checksum;        //0x9
8511   UINT8   OemId[6];        //0xA
8512   UINT64  OemTableId;      //0x10
8513   UINT32  OemRevision;     //0x18
8514   UINT32  CreatorId;       //0x1C
8515   UINT32  CreatorRevision; //0x20
8516 }EFI_ACPI_DESCRIPTION_HEADER;
8517 */
8518 typedef struct {
8519   AMD_ACPI_DESCRIPTION_HEADER SHeader;
8520   UCHAR TableUUID[16];    //0x24
8521   ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
8522   ULONG Lib1ImageOffset;  //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
8523   ULONG Reserved[4];      //0x3C
8524 }UEFI_ACPI_VFCT;
8525
8526 typedef struct {
8527   ULONG  PCIBus;          //0x4C
8528   ULONG  PCIDevice;       //0x50
8529   ULONG  PCIFunction;     //0x54
8530   USHORT VendorID;        //0x58
8531   USHORT DeviceID;        //0x5A
8532   USHORT SSVID;           //0x5C
8533   USHORT SSID;            //0x5E
8534   ULONG  Revision;        //0x60
8535   ULONG  ImageLength;     //0x64
8536 }VFCT_IMAGE_HEADER;
8537
8538
8539 typedef struct {
8540   VFCT_IMAGE_HEADER   VbiosHeader;
8541   UCHAR   VbiosContent[1];
8542 }GOP_VBIOS_CONTENT;
8543
8544 typedef struct {
8545   VFCT_IMAGE_HEADER   Lib1Header;
8546   UCHAR   Lib1Content[1];
8547 }GOP_LIB1_CONTENT;
8548
8549 #pragma pack()
8550
8551
8552 #endif /* _ATOMBIOS_H */
8553
8554 #include "pptable.h"
8555