sys/dev/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include <drm/radeon_drm.h>
  31 #include "radeon_asic.h"
  32 #include "radeon_kms.h"
  33
  34 #include <linux/vga_switcheroo.h>
  35 #include <linux/slab.h>
  36 #include <linux/pm_runtime.h>
  37
  38 #include "radeon_kfd.h"
  39
  40 #if defined(CONFIG_VGA_SWITCHEROO)
  41 bool radeon_has_atpx(void);
  42 #else
  43 static inline bool radeon_has_atpx(void) { return false; }
  44 #endif
  45
  46 /**
  47  * radeon_driver_unload_kms - Main unload function for KMS.
  48  *
  49  * @dev: drm dev pointer
  50  *
  51  * This is the main unload function for KMS (all asics).
  52  * It calls radeon_modeset_fini() to tear down the
  53  * displays, and radeon_device_fini() to tear down
  54  * the rest of the device (CP, writeback, etc.).
  55  * Returns 0 on success.
  56  */
  57 int radeon_driver_unload_kms(struct drm_device *dev)
  58 {
  59         struct radeon_device *rdev = dev->dev_private;
  60
  61         if (rdev == NULL)
  62                 return 0;
  63
  64         if (rdev->rmmio == NULL)
  65                 goto done_free;
  66
  67 #ifdef PM_TODO
  68         pm_runtime_get_sync(dev->dev);
  69 #endif
  70
  71         radeon_kfd_device_fini(rdev);
  72
  73         radeon_acpi_fini(rdev);
  74         radeon_modeset_fini(rdev);
  75         radeon_device_fini(rdev);
  76
  77 done_free:
  78         /* XXX pending drm update, after this accessing pdev is illegal! */
  79         drm_fini_pdev(&dev->pdev);
  80         kfree(rdev);
  81         dev->dev_private = NULL;
  82         return 0;
  83 }
  84
  85 /**
  86  * radeon_driver_load_kms - Main load function for KMS.
  87  *
  88  * @dev: drm dev pointer
  89  * @flags: device flags
  90  *
  91  * This is the main load function for KMS (all asics).
  92  * It calls radeon_device_init() to set up the non-display
  93  * parts of the chip (asic init, CP, writeback, etc.), and
  94  * radeon_modeset_init() to set up the display parts
  95  * (crtcs, encoders, hotplug detect, etc.).
  96  * Returns 0 on success, error on failure.
  97  */
  98 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  99 {
 100         struct radeon_device *rdev;
 101         int r, acpi_status;
 102
 103         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
 104         if (rdev == NULL) {
 105                 return -ENOMEM;
 106         }
 107         dev->dev_private = (void *)rdev;
 108
 109         /* update BUS flag */
 110         if (drm_pci_device_is_agp(dev)) {
 111                 DRM_INFO("RADEON_IS_AGP\n");
 112                 flags |= RADEON_IS_AGP;
 113         } else if (pci_is_pcie(dev->dev->bsddev)) {
 114                 DRM_INFO("RADEON_IS_PCIE\n");
 115                 flags |= RADEON_IS_PCIE;
 116         } else {
 117                 DRM_INFO("RADEON_IS_PCI\n");
 118                 flags |= RADEON_IS_PCI;
 119         }
 120
 121 #ifdef PM_TODO
 122         if ((radeon_runtime_pm != 0) &&
 123             radeon_has_atpx() &&
 124             ((flags & RADEON_IS_IGP) == 0))
 125 #endif
 126
 127         /* radeon_device_init should report only fatal error
 128          * like memory allocation failure or iomapping failure,
 129          * or memory manager initialization failure, it must
 130          * properly initialize the GPU MC controller and permit
 131          * VRAM allocation
 132          */
 133         r = radeon_device_init(rdev, dev, dev->pdev, flags);
 134         if (r) {
 135                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 136                 goto out;
 137         }
 138
 139         /* Again modeset_init should fail only on fatal error
 140          * otherwise it should provide enough functionalities
 141          * for shadowfb to run
 142          */
 143         r = radeon_modeset_init(rdev);
 144         if (r)
 145                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
 146
 147         /* Call ACPI methods: require modeset init
 148          * but failure is not fatal
 149          */
 150         if (!r) {
 151                 acpi_status = radeon_acpi_init(rdev);
 152                 if (acpi_status)
 153                 dev_dbg(&dev->pdev->dev,
 154                                 "Error during ACPI methods call\n");
 155         }
 156
 157         radeon_kfd_device_probe(rdev);
 158         radeon_kfd_device_init(rdev);
 159
 160 #ifdef PM_TODO
 161         if (radeon_is_px(dev)) {
 162                 pm_runtime_use_autosuspend(dev->dev);
 163                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 164                 pm_runtime_set_active(dev->dev);
 165                 pm_runtime_allow(dev->dev);
 166                 pm_runtime_mark_last_busy(dev->dev);
 167                 pm_runtime_put_autosuspend(dev->dev);
 168         }
 169 #endif
 170
 171 out:
 172         if (r)
 173                 radeon_driver_unload_kms(dev);
 174
 175
 176         return r;
 177 }
 178
 179 /**
 180  * radeon_set_filp_rights - Set filp right.
 181  *
 182  * @dev: drm dev pointer
 183  * @owner: drm file
 184  * @applier: drm file
 185  * @value: value
 186  *
 187  * Sets the filp rights for the device (all asics).
 188  */
 189 static void radeon_set_filp_rights(struct drm_device *dev,
 190                                    struct drm_file **owner,
 191                                    struct drm_file *applier,
 192                                    uint32_t *value)
 193 {
 194         struct radeon_device *rdev = dev->dev_private;
 195
 196         mutex_lock(&rdev->gem.mutex);
 197         if (*value == 1) {
 198                 /* wants rights */
 199                 if (!*owner)
 200                         *owner = applier;
 201         } else if (*value == 0) {
 202                 /* revokes rights */
 203                 if (*owner == applier)
 204                         *owner = NULL;
 205         }
 206         *value = *owner == applier ? 1 : 0;
 207         mutex_unlock(&rdev->gem.mutex);
 208 }
 209
 210 /*
 211  * Userspace get information ioctl
 212  */
 213 /**
 214  * radeon_info_ioctl - answer a device specific request.
 215  *
 216  * @rdev: radeon device pointer
 217  * @data: request object
 218  * @filp: drm filp
 219  *
 220  * This function is used to pass device specific parameters to the userspace
 221  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 222  * etc. (all asics).
 223  * Returns 0 on success, -EINVAL on failure.
 224  */
 225 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 226 {
 227         struct radeon_device *rdev = dev->dev_private;
 228         struct drm_radeon_info *info = data;
 229         struct radeon_mode_info *minfo = &rdev->mode_info;
 230         uint32_t *value, value_tmp, *value_ptr, value_size;
 231         uint64_t value64;
 232         struct drm_crtc *crtc;
 233         int i, found;
 234
 235         value_ptr = (uint32_t *)((unsigned long)info->value);
 236         value = &value_tmp;
 237         value_size = sizeof(uint32_t);
 238
 239         switch (info->request) {
 240         case RADEON_INFO_DEVICE_ID:
 241                 *value = dev->pdev->device;
 242                 break;
 243         case RADEON_INFO_NUM_GB_PIPES:
 244                 *value = rdev->num_gb_pipes;
 245                 break;
 246         case RADEON_INFO_NUM_Z_PIPES:
 247                 *value = rdev->num_z_pipes;
 248                 break;
 249         case RADEON_INFO_ACCEL_WORKING:
 250                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 251                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 252                         *value = false;
 253                 else
 254                         *value = rdev->accel_working;
 255                 break;
 256         case RADEON_INFO_CRTC_FROM_ID:
 257                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 258                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 259                         return -EFAULT;
 260                 }
 261                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 262                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 263                         if (crtc && crtc->base.id == *value) {
 264                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 265                                 *value = radeon_crtc->crtc_id;
 266                                 found = 1;
 267                                 break;
 268                         }
 269                 }
 270                 if (!found) {
 271                         DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
 272                         return -EINVAL;
 273                 }
 274                 break;
 275         case RADEON_INFO_ACCEL_WORKING2:
 276                 if (rdev->family == CHIP_HAWAII) {
 277                         if (rdev->accel_working) {
 278                                 if (rdev->new_fw)
 279                                         *value = 3;
 280                                 else
 281                                         *value = 2;
 282                         } else {
 283                                 *value = 0;
 284                         }
 285                 } else {
 286                         *value = rdev->accel_working;
 287                 }
 288                 break;
 289         case RADEON_INFO_TILING_CONFIG:
 290                 if (rdev->family >= CHIP_BONAIRE)
 291                         *value = rdev->config.cik.tile_config;
 292                 else if (rdev->family >= CHIP_TAHITI)
 293                         *value = rdev->config.si.tile_config;
 294                 else if (rdev->family >= CHIP_CAYMAN)
 295                         *value = rdev->config.cayman.tile_config;
 296                 else if (rdev->family >= CHIP_CEDAR)
 297                         *value = rdev->config.evergreen.tile_config;
 298                 else if (rdev->family >= CHIP_RV770)
 299                         *value = rdev->config.rv770.tile_config;
 300                 else if (rdev->family >= CHIP_R600)
 301                         *value = rdev->config.r600.tile_config;
 302                 else {
 303                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 304                         return -EINVAL;
 305                 }
 306                 break;
 307         case RADEON_INFO_WANT_HYPERZ:
 308                 /* The "value" here is both an input and output parameter.
 309                  * If the input value is 1, filp requests hyper-z access.
 310                  * If the input value is 0, filp revokes its hyper-z access.
 311                  *
 312                  * When returning, the value is 1 if filp owns hyper-z access,
 313                  * 0 otherwise. */
 314                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 315                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 316                         return -EFAULT;
 317                 }
 318                 if (*value >= 2) {
 319                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
 320                         return -EINVAL;
 321                 }
 322                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
 323                 break;
 324         case RADEON_INFO_WANT_CMASK:
 325                 /* The same logic as Hyper-Z. */
 326                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 327                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 328                         return -EFAULT;
 329                 }
 330                 if (*value >= 2) {
 331                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
 332                         return -EINVAL;
 333                 }
 334                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
 335                 break;
 336         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 337                 /* return clock value in KHz */
 338                 if (rdev->asic->get_xclk)
 339                         *value = radeon_get_xclk(rdev) * 10;
 340                 else
 341                         *value = rdev->clock.spll.reference_freq * 10;
 342                 break;
 343         case RADEON_INFO_NUM_BACKENDS:
 344                 if (rdev->family >= CHIP_BONAIRE)
 345                         *value = rdev->config.cik.max_backends_per_se *
 346                                 rdev->config.cik.max_shader_engines;
 347                 else if (rdev->family >= CHIP_TAHITI)
 348                         *value = rdev->config.si.max_backends_per_se *
 349                                 rdev->config.si.max_shader_engines;
 350                 else if (rdev->family >= CHIP_CAYMAN)
 351                         *value = rdev->config.cayman.max_backends_per_se *
 352                                 rdev->config.cayman.max_shader_engines;
 353                 else if (rdev->family >= CHIP_CEDAR)
 354                         *value = rdev->config.evergreen.max_backends;
 355                 else if (rdev->family >= CHIP_RV770)
 356                         *value = rdev->config.rv770.max_backends;
 357                 else if (rdev->family >= CHIP_R600)
 358                         *value = rdev->config.r600.max_backends;
 359                 else {
 360                         return -EINVAL;
 361                 }
 362                 break;
 363         case RADEON_INFO_NUM_TILE_PIPES:
 364                 if (rdev->family >= CHIP_BONAIRE)
 365                         *value = rdev->config.cik.max_tile_pipes;
 366                 else if (rdev->family >= CHIP_TAHITI)
 367                         *value = rdev->config.si.max_tile_pipes;
 368                 else if (rdev->family >= CHIP_CAYMAN)
 369                         *value = rdev->config.cayman.max_tile_pipes;
 370                 else if (rdev->family >= CHIP_CEDAR)
 371                         *value = rdev->config.evergreen.max_tile_pipes;
 372                 else if (rdev->family >= CHIP_RV770)
 373                         *value = rdev->config.rv770.max_tile_pipes;
 374                 else if (rdev->family >= CHIP_R600)
 375                         *value = rdev->config.r600.max_tile_pipes;
 376                 else {
 377                         return -EINVAL;
 378                 }
 379                 break;
 380         case RADEON_INFO_FUSION_GART_WORKING:
 381                 *value = 1;
 382                 break;
 383         case RADEON_INFO_BACKEND_MAP:
 384                 if (rdev->family >= CHIP_BONAIRE)
 385                         *value = rdev->config.cik.backend_map;
 386                 else if (rdev->family >= CHIP_TAHITI)
 387                         *value = rdev->config.si.backend_map;
 388                 else if (rdev->family >= CHIP_CAYMAN)
 389                         *value = rdev->config.cayman.backend_map;
 390                 else if (rdev->family >= CHIP_CEDAR)
 391                         *value = rdev->config.evergreen.backend_map;
 392                 else if (rdev->family >= CHIP_RV770)
 393                         *value = rdev->config.rv770.backend_map;
 394                 else if (rdev->family >= CHIP_R600)
 395                         *value = rdev->config.r600.backend_map;
 396                 else {
 397                         return -EINVAL;
 398                 }
 399                 break;
 400         case RADEON_INFO_VA_START:
 401                 /* this is where we report if vm is supported or not */
 402                 if (rdev->family < CHIP_CAYMAN)
 403                         return -EINVAL;
 404                 *value = RADEON_VA_RESERVED_SIZE;
 405                 break;
 406         case RADEON_INFO_IB_VM_MAX_SIZE:
 407                 /* this is where we report if vm is supported or not */
 408                 if (rdev->family < CHIP_CAYMAN)
 409                         return -EINVAL;
 410                 *value = RADEON_IB_VM_MAX_SIZE;
 411                 break;
 412         case RADEON_INFO_MAX_PIPES:
 413                 if (rdev->family >= CHIP_BONAIRE)
 414                         *value = rdev->config.cik.max_cu_per_sh;
 415                 else if (rdev->family >= CHIP_TAHITI)
 416                         *value = rdev->config.si.max_cu_per_sh;
 417                 else if (rdev->family >= CHIP_CAYMAN)
 418                         *value = rdev->config.cayman.max_pipes_per_simd;
 419                 else if (rdev->family >= CHIP_CEDAR)
 420                         *value = rdev->config.evergreen.max_pipes;
 421                 else if (rdev->family >= CHIP_RV770)
 422                         *value = rdev->config.rv770.max_pipes;
 423                 else if (rdev->family >= CHIP_R600)
 424                         *value = rdev->config.r600.max_pipes;
 425                 else {
 426                         return -EINVAL;
 427                 }
 428                 break;
 429         case RADEON_INFO_TIMESTAMP:
 430                 if (rdev->family < CHIP_R600) {
 431                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
 432                         return -EINVAL;
 433                 }
 434                 value = (uint32_t*)&value64;
 435                 value_size = sizeof(uint64_t);
 436                 value64 = radeon_get_gpu_clock_counter(rdev);
 437                 break;
 438         case RADEON_INFO_MAX_SE:
 439                 if (rdev->family >= CHIP_BONAIRE)
 440                         *value = rdev->config.cik.max_shader_engines;
 441                 else if (rdev->family >= CHIP_TAHITI)
 442                         *value = rdev->config.si.max_shader_engines;
 443                 else if (rdev->family >= CHIP_CAYMAN)
 444                         *value = rdev->config.cayman.max_shader_engines;
 445                 else if (rdev->family >= CHIP_CEDAR)
 446                         *value = rdev->config.evergreen.num_ses;
 447                 else
 448                         *value = 1;
 449                 break;
 450         case RADEON_INFO_MAX_SH_PER_SE:
 451                 if (rdev->family >= CHIP_BONAIRE)
 452                         *value = rdev->config.cik.max_sh_per_se;
 453                 else if (rdev->family >= CHIP_TAHITI)
 454                         *value = rdev->config.si.max_sh_per_se;
 455                 else
 456                         return -EINVAL;
 457                 break;
 458         case RADEON_INFO_FASTFB_WORKING:
 459                 *value = rdev->fastfb_working;
 460                 break;
 461         case RADEON_INFO_RING_WORKING:
 462                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 463                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 464                         return -EFAULT;
 465                 }
 466                 switch (*value) {
 467                 case RADEON_CS_RING_GFX:
 468                 case RADEON_CS_RING_COMPUTE:
 469                         *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
 470                         break;
 471                 case RADEON_CS_RING_DMA:
 472                         *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
 473                         *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
 474                         break;
 475                 case RADEON_CS_RING_UVD:
 476                         *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
 477                         break;
 478                 case RADEON_CS_RING_VCE:
 479                         *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
 480                         break;
 481                 default:
 482                         return -EINVAL;
 483                 }
 484                 break;
 485         case RADEON_INFO_SI_TILE_MODE_ARRAY:
 486                 if (rdev->family >= CHIP_BONAIRE) {
 487                         value = rdev->config.cik.tile_mode_array;
 488                         value_size = sizeof(uint32_t)*32;
 489                 } else if (rdev->family >= CHIP_TAHITI) {
 490                         value = rdev->config.si.tile_mode_array;
 491                         value_size = sizeof(uint32_t)*32;
 492                 } else {
 493                         DRM_DEBUG_KMS("tile mode array is si+ only!\n");
 494                         return -EINVAL;
 495                 }
 496                 break;
 497         case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
 498                 if (rdev->family >= CHIP_BONAIRE) {
 499                         value = rdev->config.cik.macrotile_mode_array;
 500                         value_size = sizeof(uint32_t)*16;
 501                 } else {
 502                         DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
 503                         return -EINVAL;
 504                 }
 505                 break;
 506         case RADEON_INFO_SI_CP_DMA_COMPUTE:
 507                 *value = 1;
 508                 break;
 509         case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
 510                 if (rdev->family >= CHIP_BONAIRE) {
 511                         *value = rdev->config.cik.backend_enable_mask;
 512                 } else if (rdev->family >= CHIP_TAHITI) {
 513                         *value = rdev->config.si.backend_enable_mask;
 514                 } else {
 515                         DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
 516                 }
 517                 break;
 518         case RADEON_INFO_MAX_SCLK:
 519                 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
 520                     rdev->pm.dpm_enabled)
 521                         *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
 522                 else
 523                         *value = rdev->pm.default_sclk * 10;
 524                 break;
 525         case RADEON_INFO_VCE_FW_VERSION:
 526                 *value = rdev->vce.fw_version;
 527                 break;
 528         case RADEON_INFO_VCE_FB_VERSION:
 529                 *value = rdev->vce.fb_version;
 530                 break;
 531         case RADEON_INFO_NUM_BYTES_MOVED:
 532                 value = (uint32_t*)&value64;
 533                 value_size = sizeof(uint64_t);
 534                 value64 = atomic64_read(&rdev->num_bytes_moved);
 535                 break;
 536         case RADEON_INFO_VRAM_USAGE:
 537                 value = (uint32_t*)&value64;
 538                 value_size = sizeof(uint64_t);
 539                 value64 = atomic64_read(&rdev->vram_usage);
 540                 break;
 541         case RADEON_INFO_GTT_USAGE:
 542                 value = (uint32_t*)&value64;
 543                 value_size = sizeof(uint64_t);
 544                 value64 = atomic64_read(&rdev->gtt_usage);
 545                 break;
 546         case RADEON_INFO_ACTIVE_CU_COUNT:
 547                 if (rdev->family >= CHIP_BONAIRE)
 548                         *value = rdev->config.cik.active_cus;
 549                 else if (rdev->family >= CHIP_TAHITI)
 550                         *value = rdev->config.si.active_cus;
 551                 else if (rdev->family >= CHIP_CAYMAN)
 552                         *value = rdev->config.cayman.active_simds;
 553                 else if (rdev->family >= CHIP_CEDAR)
 554                         *value = rdev->config.evergreen.active_simds;
 555                 else if (rdev->family >= CHIP_RV770)
 556                         *value = rdev->config.rv770.active_simds;
 557                 else if (rdev->family >= CHIP_R600)
 558                         *value = rdev->config.r600.active_simds;
 559                 else
 560                         *value = 1;
 561                 break;
 562         case RADEON_INFO_CURRENT_GPU_TEMP:
 563                 /* get temperature in millidegrees C */
 564                 if (rdev->asic->pm.get_temperature)
 565                         *value = radeon_get_temperature(rdev);
 566                 else
 567                         *value = 0;
 568                 break;
 569         case RADEON_INFO_CURRENT_GPU_SCLK:
 570                 /* get sclk in Mhz */
 571                 if (rdev->pm.dpm_enabled)
 572                         *value = radeon_dpm_get_current_sclk(rdev) / 100;
 573                 else
 574                         *value = rdev->pm.current_sclk / 100;
 575                 break;
 576         case RADEON_INFO_CURRENT_GPU_MCLK:
 577                 /* get mclk in Mhz */
 578                 if (rdev->pm.dpm_enabled)
 579                         *value = radeon_dpm_get_current_mclk(rdev) / 100;
 580                 else
 581                         *value = rdev->pm.current_mclk / 100;
 582                 break;
 583         case RADEON_INFO_READ_REG:
 584                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 585                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 586                         return -EFAULT;
 587                 }
 588                 if (radeon_get_allowed_info_register(rdev, *value, value))
 589                         return -EINVAL;
 590                 break;
 591         case RADEON_INFO_GPU_RESET_COUNTER:
 592                 *value = atomic_read(&rdev->gpu_reset_counter);
 593                 break;
 594         default:
 595                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 596                 return -EINVAL;
 597         }
 598         if (copy_to_user(value_ptr, (char*)value, value_size)) {
 599                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 600                 return -EFAULT;
 601         }
 602         return 0;
 603 }
 604
 605
 606 /*
 607  * Outdated mess for old drm with Xorg being in charge (void function now).
 608  */
 609 /**
 610  * radeon_driver_lastclose_kms - drm callback for last close
 611  *
 612  * @dev: drm dev pointer
 613  *
 614  * Switch vga_switcheroo state after last close (all asics).
 615  */
 616 void radeon_driver_lastclose_kms(struct drm_device *dev)
 617 {
 618         struct radeon_device *rdev = dev->dev_private;
 619
 620         radeon_fbdev_restore_mode(rdev);
 621         vga_switcheroo_process_delayed_switch();
 622 }
 623
 624 /**
 625  * radeon_driver_open_kms - drm callback for open
 626  *
 627  * @dev: drm dev pointer
 628  * @file_priv: drm file
 629  *
 630  * On device open, init vm on cayman+ (all asics).
 631  * Returns 0 on success, error on failure.
 632  */
 633 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 634 {
 635         struct radeon_device *rdev = dev->dev_private;
 636
 637         file_priv->driver_priv = NULL;
 638
 639 #ifdef PM_TODO
 640         r = pm_runtime_get_sync(dev->dev);
 641         if (r < 0)
 642                 return r;
 643 #endif
 644
 645         /* new gpu have virtual address space support */
 646         if (rdev->family >= CHIP_CAYMAN) {
 647                 struct radeon_fpriv *fpriv;
 648                 struct radeon_vm *vm;
 649                 int r;
 650
 651                 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 652                 if (unlikely(!fpriv)) {
 653                         return -ENOMEM;
 654                 }
 655
 656                 if (rdev->accel_working) {
 657                         vm = &fpriv->vm;
 658                         r = radeon_vm_init(rdev, vm);
 659                         if (r) {
 660                                 kfree(fpriv);
 661                                 return r;
 662                         }
 663
 664                         r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 665                         if (r) {
 666                                 radeon_vm_fini(rdev, vm);
 667                                 kfree(fpriv);
 668                                 return r;
 669                         }
 670
 671                         /* map the ib pool buffer read only into
 672                          * virtual address space */
 673                         vm->ib_bo_va = radeon_vm_bo_add(rdev, vm,
 674                                                         rdev->ring_tmp_bo.bo);
 675                         r = radeon_vm_bo_set_addr(rdev, vm->ib_bo_va,
 676                                                   RADEON_VA_IB_OFFSET,
 677                                                   RADEON_VM_PAGE_READABLE |
 678                                                   RADEON_VM_PAGE_SNOOPED);
 679                         if (r) {
 680                                 radeon_vm_fini(rdev, vm);
 681                                 kfree(fpriv);
 682                                 return r;
 683                         }
 684                 }
 685                 file_priv->driver_priv = fpriv;
 686         }
 687
 688 #ifdef PM_TODO
 689         pm_runtime_mark_last_busy(dev->dev);
 690         pm_runtime_put_autosuspend(dev->dev);
 691 #endif
 692         return 0;
 693 }
 694
 695 /**
 696  * radeon_driver_postclose_kms - drm callback for post close
 697  *
 698  * @dev: drm dev pointer
 699  * @file_priv: drm file
 700  *
 701  * On device post close, tear down vm on cayman+ (all asics).
 702  */
 703 void radeon_driver_postclose_kms(struct drm_device *dev,
 704                                  struct drm_file *file_priv)
 705 {
 706         struct radeon_device *rdev = dev->dev_private;
 707
 708         /* new gpu have virtual address space support */
 709         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
 710                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
 711                 struct radeon_vm *vm = &fpriv->vm;
 712                 int r;
 713
 714                 if (rdev->accel_working) {
 715                         r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 716                         if (!r) {
 717                                 if (vm->ib_bo_va)
 718                                         radeon_vm_bo_rmv(rdev, vm->ib_bo_va);
 719                                 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 720                         }
 721                         radeon_vm_fini(rdev, vm);
 722                 }
 723
 724                 kfree(fpriv);
 725                 file_priv->driver_priv = NULL;
 726         }
 727 }
 728
 729 /**
 730  * radeon_driver_preclose_kms - drm callback for pre close
 731  *
 732  * @dev: drm dev pointer
 733  * @file_priv: drm file
 734  *
 735  * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
 736  * (all asics).
 737  */
 738 void radeon_driver_preclose_kms(struct drm_device *dev,
 739                                 struct drm_file *file_priv)
 740 {
 741         struct radeon_device *rdev = dev->dev_private;
 742
 743         mutex_lock(&rdev->gem.mutex);
 744         if (rdev->hyperz_filp == file_priv)
 745                 rdev->hyperz_filp = NULL;
 746         if (rdev->cmask_filp == file_priv)
 747                 rdev->cmask_filp = NULL;
 748         mutex_unlock(&rdev->gem.mutex);
 749
 750         radeon_uvd_free_handles(rdev, file_priv);
 751         radeon_vce_free_handles(rdev, file_priv);
 752 }
 753
 754 /*
 755  * VBlank related functions.
 756  */
 757 /**
 758  * radeon_get_vblank_counter_kms - get frame count
 759  *
 760  * @dev: drm dev pointer
 761  * @crtc: crtc to get the frame count from
 762  *
 763  * Gets the frame count on the requested crtc (all asics).
 764  * Returns frame count on success, -EINVAL on failure.
 765  */
 766 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc);
 767 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 768 {
 769         int vpos, hpos, stat;
 770         u32 count;
 771         struct radeon_device *rdev = dev->dev_private;
 772
 773         if (crtc < 0 || crtc >= rdev->num_crtc) {
 774                 DRM_ERROR("Invalid crtc %d\n", crtc);
 775                 return -EINVAL;
 776         }
 777
 778         /* The hw increments its frame counter at start of vsync, not at start
 779          * of vblank, as is required by DRM core vblank counter handling.
 780          * Cook the hw count here to make it appear to the caller as if it
 781          * incremented at start of vblank. We measure distance to start of
 782          * vblank in vpos. vpos therefore will be >= 0 between start of vblank
 783          * and start of vsync, so vpos >= 0 means to bump the hw frame counter
 784          * result by 1 to give the proper appearance to caller.
 785          */
 786         if (rdev->mode_info.crtcs[crtc]) {
 787                 /* Repeat readout if needed to provide stable result if
 788                  * we cross start of vsync during the queries.
 789                  */
 790                 do {
 791                         count = radeon_get_vblank_counter(rdev, crtc);
 792                         /* Ask radeon_get_crtc_scanoutpos to return vpos as
 793                          * distance to start of vblank, instead of regular
 794                          * vertical scanout pos.
 795                          */
 796                         stat = radeon_get_crtc_scanoutpos(
 797                                 dev, crtc, GET_DISTANCE_TO_VBLANKSTART,
 798                                 &vpos, &hpos, NULL, NULL,
 799                                 &rdev->mode_info.crtcs[crtc]->base.hwmode);
 800                 } while (count != radeon_get_vblank_counter(rdev, crtc));
 801
 802                 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
 803                     (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
 804                         DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
 805                 }
 806                 else {
 807                         DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
 808                                       crtc, vpos);
 809
 810                         /* Bump counter if we are at >= leading edge of vblank,
 811                          * but before vsync where vpos would turn negative and
 812                          * the hw counter really increments.
 813                          */
 814                         if (vpos >= 0)
 815                                 count++;
 816                 }
 817         }
 818         else {
 819             /* Fallback to use value as is. */
 820             count = radeon_get_vblank_counter(rdev, crtc);
 821             DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
 822         }
 823
 824         return count;
 825 }
 826
 827 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc);
 828 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc);
 829 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 830                                     int *max_error,
 831                                     struct timeval *vblank_time,
 832                                     unsigned flags);
 833
 834 /**
 835  * radeon_enable_vblank_kms - enable vblank interrupt
 836  *
 837  * @dev: drm dev pointer
 838  * @crtc: crtc to enable vblank interrupt for
 839  *
 840  * Enable the interrupt on the requested crtc (all asics).
 841  * Returns 0 on success, -EINVAL on failure.
 842  */
 843 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 844 {
 845         struct radeon_device *rdev = dev->dev_private;
 846         unsigned long irqflags;
 847         int r;
 848
 849         if (crtc < 0 || crtc >= rdev->num_crtc) {
 850                 DRM_ERROR("Invalid crtc %d\n", crtc);
 851                 return -EINVAL;
 852         }
 853
 854         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 855         rdev->irq.crtc_vblank_int[crtc] = true;
 856         r = radeon_irq_set(rdev);
 857         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 858         return r;
 859 }
 860
 861 /**
 862  * radeon_disable_vblank_kms - disable vblank interrupt
 863  *
 864  * @dev: drm dev pointer
 865  * @crtc: crtc to disable vblank interrupt for
 866  *
 867  * Disable the interrupt on the requested crtc (all asics).
 868  */
 869 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 870 {
 871         struct radeon_device *rdev = dev->dev_private;
 872         unsigned long irqflags;
 873
 874         if (crtc < 0 || crtc >= rdev->num_crtc) {
 875                 DRM_ERROR("Invalid crtc %d\n", crtc);
 876                 return;
 877         }
 878
 879         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 880         rdev->irq.crtc_vblank_int[crtc] = false;
 881         radeon_irq_set(rdev);
 882         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 883 }
 884
 885 /**
 886  * radeon_get_vblank_timestamp_kms - get vblank timestamp
 887  *
 888  * @dev: drm dev pointer
 889  * @crtc: crtc to get the timestamp for
 890  * @max_error: max error
 891  * @vblank_time: time value
 892  * @flags: flags passed to the driver
 893  *
 894  * Gets the timestamp on the requested crtc based on the
 895  * scanout position.  (all asics).
 896  * Returns postive status flags on success, negative error on failure.
 897  */
 898 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 899                                     int *max_error,
 900                                     struct timeval *vblank_time,
 901                                     unsigned flags)
 902 {
 903         struct drm_crtc *drmcrtc;
 904         struct radeon_device *rdev = dev->dev_private;
 905
 906         if (crtc < 0 || crtc >= dev->num_crtcs) {
 907                 DRM_ERROR("Invalid crtc %d\n", crtc);
 908                 return -EINVAL;
 909         }
 910
 911         /* Get associated drm_crtc: */
 912         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
 913         if (!drmcrtc)
 914                 return -EINVAL;
 915
 916         /* Helper routine in DRM core does all the work: */
 917         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
 918                                                      vblank_time, flags,
 919                                                      &drmcrtc->hwmode);
 920 }
 921
 922 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
 923         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 924         DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 925         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 926         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 927         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH),
 928         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH),
 929         DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH),
 930         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH),
 931         DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH),
 932         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH),
 933         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH),
 934         DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH),
 935         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH),
 936         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH),
 937         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 938         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH),
 939         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH),
 940         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH),
 941         DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH),
 942         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH),
 943         DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH),
 944         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 945         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH),
 946         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH),
 947         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH),
 948         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH),
 949         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH),
 950         /* KMS */
 951         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 952         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 953         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 954         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 955         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
 956         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
 957         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 958         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 959         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 960         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 961         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 962         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 963         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 964         DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 965 #if 0
 966         DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 967 #endif
 968 };
 969 int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms);