2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_sf.c,v 1.18.2.8 2001/12/16 15:46:07 luigi Exp $
33 * $DragonFly: src/sys/dev/netif/sf/if_sf.c,v 1.28 2006/08/01 18:08:24 swildner Exp $
37 * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
38 * Programming manual is available from:
39 * ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
41 * Written by Bill Paul <wpaul@ctr.columbia.edu>
42 * Department of Electical Engineering
43 * Columbia University, New York City
47 * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
48 * controller designed with flexibility and reducing CPU load in mind.
49 * The Starfire offers high and low priority buffer queues, a
50 * producer/consumer index mechanism and several different buffer
51 * queue and completion queue descriptor types. Any one of a number
52 * of different driver designs can be used, depending on system and
53 * OS requirements. This driver makes use of type0 transmit frame
54 * descriptors (since BSD fragments packets across an mbuf chain)
55 * and two RX buffer queues prioritized on size (one queue for small
56 * frames that will fit into a single mbuf, another with full size
57 * mbuf clusters for everything else). The producer/consumer indexes
58 * and completion queues are also used.
60 * One downside to the Starfire has to do with alignment: buffer
61 * queues must be aligned on 256-byte boundaries, and receive buffers
62 * must be aligned on longword boundaries. The receive buffer alignment
63 * causes problems on the Alpha platform, where the packet payload
64 * should be longword aligned. There is no simple way around this.
66 * For receive filtering, the Starfire offers 16 perfect filter slots
67 * and a 512-bit hash table.
69 * The Starfire has no internal transceiver, relying instead on an
70 * external MII-based transceiver. Accessing registers on external
71 * PHYs is done through a special register map rather than with the
72 * usual bitbang MDIO method.
74 * Acesssing the registers on the Starfire is a little tricky. The
75 * Starfire has a 512K internal register space. When programmed for
76 * PCI memory mapped mode, the entire register space can be accessed
77 * directly. However in I/O space mode, only 256 bytes are directly
78 * mapped into PCI I/O space. The other registers can be accessed
79 * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
80 * registers inside the 256-byte I/O window.
83 #include <sys/param.h>
84 #include <sys/systm.h>
85 #include <sys/sockio.h>
87 #include <sys/malloc.h>
88 #include <sys/kernel.h>
89 #include <sys/socket.h>
90 #include <sys/serialize.h>
92 #include <sys/thread2.h>
95 #include <net/ifq_var.h>
96 #include <net/if_arp.h>
97 #include <net/ethernet.h>
98 #include <net/if_dl.h>
99 #include <net/if_media.h>
103 #include <vm/vm.h> /* for vtophys */
104 #include <vm/pmap.h> /* for vtophys */
105 #include <machine/clock.h> /* for DELAY */
106 #include <machine/bus_pio.h>
107 #include <machine/bus_memio.h>
108 #include <machine/bus.h>
109 #include <machine/resource.h>
111 #include <sys/rman.h>
113 #include "../mii_layer/mii.h"
114 #include "../mii_layer/miivar.h"
116 /* "controller miibus0" required. See GENERIC if you get errors here. */
117 #include "miibus_if.h"
119 #include <bus/pci/pcidevs.h>
120 #include <bus/pci/pcireg.h>
121 #include <bus/pci/pcivar.h>
123 #define SF_USEIOSPACE
125 #include "if_sfreg.h"
127 static struct sf_type sf_devs[] = {
128 { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC6915,
129 "Adaptec AIC-6915 10/100BaseTX" },
133 static int sf_probe (device_t);
134 static int sf_attach (device_t);
135 static int sf_detach (device_t);
136 static void sf_intr (void *);
137 static void sf_stats_update (void *);
138 static void sf_rxeof (struct sf_softc *);
139 static void sf_txeof (struct sf_softc *);
140 static int sf_encap (struct sf_softc *,
141 struct sf_tx_bufdesc_type0 *,
143 static void sf_start (struct ifnet *);
144 static int sf_ioctl (struct ifnet *, u_long, caddr_t,
146 static void sf_init (void *);
147 static void sf_stop (struct sf_softc *);
148 static void sf_watchdog (struct ifnet *);
149 static void sf_shutdown (device_t);
150 static int sf_ifmedia_upd (struct ifnet *);
151 static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *);
152 static void sf_reset (struct sf_softc *);
153 static int sf_init_rx_ring (struct sf_softc *);
154 static void sf_init_tx_ring (struct sf_softc *);
155 static int sf_newbuf (struct sf_softc *,
156 struct sf_rx_bufdesc_type0 *,
158 static void sf_setmulti (struct sf_softc *);
159 static int sf_setperf (struct sf_softc *, int, caddr_t);
160 static int sf_sethash (struct sf_softc *, caddr_t, int);
162 static int sf_setvlan (struct sf_softc *, int, u_int32_t);
165 static u_int8_t sf_read_eeprom (struct sf_softc *, int);
166 static u_int32_t sf_calchash (caddr_t);
168 static int sf_miibus_readreg (device_t, int, int);
169 static int sf_miibus_writereg (device_t, int, int, int);
170 static void sf_miibus_statchg (device_t);
172 static u_int32_t csr_read_4 (struct sf_softc *, int);
173 static void csr_write_4 (struct sf_softc *, int, u_int32_t);
174 static void sf_txthresh_adjust (struct sf_softc *);
177 #define SF_RES SYS_RES_IOPORT
178 #define SF_RID SF_PCI_LOIO
180 #define SF_RES SYS_RES_MEMORY
181 #define SF_RID SF_PCI_LOMEM
184 static device_method_t sf_methods[] = {
185 /* Device interface */
186 DEVMETHOD(device_probe, sf_probe),
187 DEVMETHOD(device_attach, sf_attach),
188 DEVMETHOD(device_detach, sf_detach),
189 DEVMETHOD(device_shutdown, sf_shutdown),
192 DEVMETHOD(bus_print_child, bus_generic_print_child),
193 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
196 DEVMETHOD(miibus_readreg, sf_miibus_readreg),
197 DEVMETHOD(miibus_writereg, sf_miibus_writereg),
198 DEVMETHOD(miibus_statchg, sf_miibus_statchg),
203 static driver_t sf_driver = {
206 sizeof(struct sf_softc),
209 static devclass_t sf_devclass;
211 DECLARE_DUMMY_MODULE(if_sf);
212 DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
213 DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
215 #define SF_SETBIT(sc, reg, x) \
216 csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
218 #define SF_CLRBIT(sc, reg, x) \
219 csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
222 csr_read_4(struct sf_softc *sc, int reg)
227 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
228 val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
230 val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
237 sf_read_eeprom(struct sf_softc *sc, int reg)
241 val = (csr_read_4(sc, SF_EEADDR_BASE +
242 (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
248 csr_write_4(struct sf_softc *sc, int reg, u_int32_t val)
251 CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
252 CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
254 CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
260 sf_calchash(caddr_t addr)
262 u_int32_t crc, carry;
266 /* Compute CRC for the address value. */
267 crc = 0xFFFFFFFF; /* initial value */
269 for (i = 0; i < 6; i++) {
271 for (j = 0; j < 8; j++) {
272 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
276 crc = (crc ^ 0x04c11db6) | carry;
280 /* return the filter bit position */
281 return(crc >> 23 & 0x1FF);
285 * Copy the address 'mac' into the perfect RX filter entry at
286 * offset 'idx.' The perfect filter only has 16 entries so do
290 sf_setperf(struct sf_softc *sc, int idx, caddr_t mac)
294 if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
300 p = (u_int16_t *)mac;
302 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
303 (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
304 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
305 (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
306 csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
307 (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
313 * Set the bit in the 512-bit hash table that corresponds to the
314 * specified mac address 'mac.' If 'prio' is nonzero, update the
315 * priority hash table instead of the filter hash table.
318 sf_sethash(struct sf_softc *sc, caddr_t mac, int prio)
325 h = sf_calchash(mac);
328 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
329 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
331 SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
332 (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
340 * Set a VLAN tag in the receive filter.
343 sf_setvlan(struct sf_softc *sc, int idx, u_int32_t vlan)
345 if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
348 csr_write_4(sc, SF_RXFILT_HASH_BASE +
349 (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
356 sf_miibus_readreg(device_t dev, int phy, int reg)
362 sc = device_get_softc(dev);
364 for (i = 0; i < SF_TIMEOUT; i++) {
365 val = csr_read_4(sc, SF_PHY_REG(phy, reg));
366 if (val & SF_MII_DATAVALID)
373 if ((val & 0x0000FFFF) == 0xFFFF)
376 return(val & 0x0000FFFF);
380 sf_miibus_writereg(device_t dev, int phy, int reg, int val)
386 sc = device_get_softc(dev);
388 csr_write_4(sc, SF_PHY_REG(phy, reg), val);
390 for (i = 0; i < SF_TIMEOUT; i++) {
391 busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
392 if (!(busy & SF_MII_BUSY))
400 sf_miibus_statchg(device_t dev)
403 struct mii_data *mii;
405 sc = device_get_softc(dev);
406 mii = device_get_softc(sc->sf_miibus);
408 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
409 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
410 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
412 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
413 csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
420 sf_setmulti(struct sf_softc *sc)
424 struct ifmultiaddr *ifma;
425 u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
427 ifp = &sc->arpcom.ac_if;
429 /* First zot all the existing filters. */
430 for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
431 sf_setperf(sc, i, (char *)&dummy);
432 for (i = SF_RXFILT_HASH_BASE;
433 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
434 csr_write_4(sc, i, 0);
435 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
437 /* Now program new ones. */
438 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
439 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
442 /* First find the tail of the list. */
443 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
444 ifma = ifma->ifma_link.le_next) {
445 if (ifma->ifma_link.le_next == NULL)
448 /* Now traverse the list backwards. */
449 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs;
450 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) {
451 if (ifma->ifma_addr->sa_family != AF_LINK)
454 * Program the first 15 multicast groups
455 * into the perfect filter. For all others,
456 * use the hash table.
458 if (i < SF_RXFILT_PERFECT_CNT) {
460 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
466 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
477 sf_ifmedia_upd(struct ifnet *ifp)
480 struct mii_data *mii;
483 mii = device_get_softc(sc->sf_miibus);
485 if (mii->mii_instance) {
486 struct mii_softc *miisc;
487 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
488 miisc = LIST_NEXT(miisc, mii_list))
489 mii_phy_reset(miisc);
497 * Report current media status.
500 sf_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
503 struct mii_data *mii;
506 mii = device_get_softc(sc->sf_miibus);
509 ifmr->ifm_active = mii->mii_media_active;
510 ifmr->ifm_status = mii->mii_media_status;
516 sf_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
518 struct sf_softc *sc = ifp->if_softc;
519 struct ifreq *ifr = (struct ifreq *) data;
520 struct mii_data *mii;
525 if (ifp->if_flags & IFF_UP) {
526 if (ifp->if_flags & IFF_RUNNING &&
527 ifp->if_flags & IFF_PROMISC &&
528 !(sc->sf_if_flags & IFF_PROMISC)) {
529 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
530 } else if (ifp->if_flags & IFF_RUNNING &&
531 !(ifp->if_flags & IFF_PROMISC) &&
532 sc->sf_if_flags & IFF_PROMISC) {
533 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
534 } else if (!(ifp->if_flags & IFF_RUNNING))
537 if (ifp->if_flags & IFF_RUNNING)
540 sc->sf_if_flags = ifp->if_flags;
550 mii = device_get_softc(sc->sf_miibus);
551 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
554 error = ether_ioctl(ifp, command, data);
562 sf_reset(struct sf_softc *sc)
566 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
567 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
569 SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
571 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
573 for (i = 0; i < SF_TIMEOUT; i++) {
575 if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
580 printf("sf%d: reset never completed!\n", sc->sf_unit);
582 /* Wait a little while for the chip to get its brains in order. */
588 * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
589 * IDs against our list and return a device name if we find a match.
590 * We also check the subsystem ID so that we can identify exactly which
591 * NIC has been found, if possible.
594 sf_probe(device_t dev)
600 while(t->sf_name != NULL) {
601 if ((pci_get_vendor(dev) == t->sf_vid) &&
602 (pci_get_device(dev) == t->sf_did)) {
603 switch((pci_read_config(dev,
604 SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
605 case AD_SUBSYSID_62011_REV0:
606 case AD_SUBSYSID_62011_REV1:
608 "Adaptec ANA-62011 10/100BaseTX");
611 case AD_SUBSYSID_62022:
613 "Adaptec ANA-62022 10/100BaseTX");
616 case AD_SUBSYSID_62044_REV0:
617 case AD_SUBSYSID_62044_REV1:
619 "Adaptec ANA-62044 10/100BaseTX");
622 case AD_SUBSYSID_62020:
624 "Adaptec ANA-62020 10/100BaseFX");
627 case AD_SUBSYSID_69011:
629 "Adaptec ANA-69011 10/100BaseTX");
633 device_set_desc(dev, t->sf_name);
645 * Attach the interface. Allocate softc structures, do ifmedia
646 * setup and ethernet/BPF attach.
649 sf_attach(device_t dev)
655 int unit, rid, error = 0;
657 sc = device_get_softc(dev);
658 unit = device_get_unit(dev);
661 * Handle power management nonsense.
663 command = pci_read_config(dev, SF_PCI_CAPID, 4) & 0x000000FF;
664 if (command == 0x01) {
666 command = pci_read_config(dev, SF_PCI_PWRMGMTCTRL, 4);
667 if (command & SF_PSTATE_MASK) {
668 u_int32_t iobase, membase, irq;
670 /* Save important PCI config data. */
671 iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
672 membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
673 irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
675 /* Reset the power state. */
676 printf("sf%d: chip is in D%d power mode "
677 "-- setting to D0\n", unit, command & SF_PSTATE_MASK);
678 command &= 0xFFFFFFFC;
679 pci_write_config(dev, SF_PCI_PWRMGMTCTRL, command, 4);
681 /* Restore PCI config data. */
682 pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
683 pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
684 pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
689 * Map control/status registers.
691 command = pci_read_config(dev, PCIR_COMMAND, 4);
692 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
693 pci_write_config(dev, PCIR_COMMAND, command, 4);
694 command = pci_read_config(dev, PCIR_COMMAND, 4);
697 if (!(command & PCIM_CMD_PORTEN)) {
698 printf("sf%d: failed to enable I/O ports!\n", unit);
703 if (!(command & PCIM_CMD_MEMEN)) {
704 printf("sf%d: failed to enable memory mapping!\n", unit);
711 sc->sf_res = bus_alloc_resource_any(dev, SF_RES, &rid, RF_ACTIVE);
713 if (sc->sf_res == NULL) {
714 printf ("sf%d: couldn't map ports\n", unit);
719 sc->sf_btag = rman_get_bustag(sc->sf_res);
720 sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
722 /* Allocate interrupt */
724 sc->sf_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
725 RF_SHAREABLE | RF_ACTIVE);
727 if (sc->sf_irq == NULL) {
728 printf("sf%d: couldn't map interrupt\n", unit);
733 callout_init(&sc->sf_stat_timer);
735 /* Reset the adapter. */
739 * Get station address from the EEPROM.
741 for (i = 0; i < ETHER_ADDR_LEN; i++)
742 sc->arpcom.ac_enaddr[i] =
743 sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
747 /* Allocate the descriptor queues. */
748 sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
749 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
751 if (sc->sf_ldata == NULL) {
752 printf("sf%d: no memory for list buffers!\n", unit);
757 bzero(sc->sf_ldata, sizeof(struct sf_list_data));
760 if (mii_phy_probe(dev, &sc->sf_miibus,
761 sf_ifmedia_upd, sf_ifmedia_sts)) {
762 printf("sf%d: MII without any phy!\n", sc->sf_unit);
767 ifp = &sc->arpcom.ac_if;
769 if_initname(ifp, "sf", unit);
770 ifp->if_mtu = ETHERMTU;
771 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
772 ifp->if_ioctl = sf_ioctl;
773 ifp->if_start = sf_start;
774 ifp->if_watchdog = sf_watchdog;
775 ifp->if_init = sf_init;
776 ifp->if_baudrate = 10000000;
777 ifq_set_maxlen(&ifp->if_snd, SF_TX_DLIST_CNT - 1);
778 ifq_set_ready(&ifp->if_snd);
781 * Call MI attach routine.
783 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
785 error = bus_setup_intr(dev, sc->sf_irq, INTR_NETSAFE,
786 sf_intr, sc, &sc->sf_intrhand,
791 device_printf(dev, "couldn't set up irq\n");
803 sf_detach(device_t dev)
805 struct sf_softc *sc = device_get_softc(dev);
806 struct ifnet *ifp = &sc->arpcom.ac_if;
808 if (device_is_attached(dev)) {
809 lwkt_serialize_enter(ifp->if_serializer);
811 bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
812 lwkt_serialize_exit(ifp->if_serializer);
818 device_delete_child(dev, sc->sf_miibus);
819 bus_generic_detach(dev);
822 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
824 bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
827 contigfree(sc->sf_ldata, sizeof(struct sf_list_data),
835 sf_init_rx_ring(struct sf_softc *sc)
837 struct sf_list_data *ld;
842 bzero((char *)ld->sf_rx_dlist_big,
843 sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
844 bzero((char *)ld->sf_rx_clist,
845 sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
847 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
848 if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
856 sf_init_tx_ring(struct sf_softc *sc)
858 struct sf_list_data *ld;
863 bzero((char *)ld->sf_tx_dlist,
864 sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
865 bzero((char *)ld->sf_tx_clist,
866 sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
868 for (i = 0; i < SF_TX_DLIST_CNT; i++)
869 ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
870 for (i = 0; i < SF_TX_CLIST_CNT; i++)
871 ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
873 ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
880 sf_newbuf(struct sf_softc *sc, struct sf_rx_bufdesc_type0 *c,
883 struct mbuf *m_new = NULL;
886 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
890 MCLGET(m_new, MB_DONTWAIT);
891 if (!(m_new->m_flags & M_EXT)) {
895 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
898 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
899 m_new->m_data = m_new->m_ext.ext_buf;
902 m_adj(m_new, sizeof(u_int64_t));
905 c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
912 * The starfire is programmed to use 'normal' mode for packet reception,
913 * which means we use the consumer/producer model for both the buffer
914 * descriptor queue and the completion descriptor queue. The only problem
915 * with this is that it involves a lot of register accesses: we have to
916 * read the RX completion consumer and producer indexes and the RX buffer
917 * producer index, plus the RX completion consumer and RX buffer producer
918 * indexes have to be updated. It would have been easier if Adaptec had
919 * put each index in a separate register, especially given that the damn
920 * NIC has a 512K register space.
922 * In spite of all the lovely features that Adaptec crammed into the 6915,
923 * it is marred by one truly stupid design flaw, which is that receive
924 * buffer addresses must be aligned on a longword boundary. This forces
925 * the packet payload to be unaligned, which is suboptimal on the x86 and
926 * completely unuseable on the Alpha. Our only recourse is to copy received
927 * packets into properly aligned buffers before handing them off.
931 sf_rxeof(struct sf_softc *sc)
935 struct sf_rx_bufdesc_type0 *desc;
936 struct sf_rx_cmpdesc_type3 *cur_rx;
937 u_int32_t rxcons, rxprod;
938 int cmpprodidx, cmpconsidx, bufprodidx;
940 ifp = &sc->arpcom.ac_if;
942 rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
943 rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
944 cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
945 cmpconsidx = SF_IDX_LO(rxcons);
946 bufprodidx = SF_IDX_LO(rxprod);
948 while (cmpconsidx != cmpprodidx) {
951 cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
952 desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
954 SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
955 SF_INC(bufprodidx, SF_RX_DLIST_CNT);
957 if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
959 sf_newbuf(sc, desc, m);
963 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
964 cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL);
965 sf_newbuf(sc, desc, m);
970 m_adj(m0, ETHER_ALIGN);
975 ifp->if_input(ifp, m);
978 csr_write_4(sc, SF_CQ_CONSIDX,
979 (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
980 csr_write_4(sc, SF_RXDQ_PTR_Q1,
981 (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
987 * Read the transmit status from the completion queue and release
988 * mbufs. Note that the buffer descriptor index in the completion
989 * descriptor is an offset from the start of the transmit buffer
990 * descriptor list in bytes. This is important because the manual
991 * gives the impression that it should match the producer/consumer
992 * index, which is the offset in 8 byte blocks.
995 sf_txeof(struct sf_softc *sc)
997 int txcons, cmpprodidx, cmpconsidx;
998 struct sf_tx_cmpdesc_type1 *cur_cmp;
999 struct sf_tx_bufdesc_type0 *cur_tx;
1002 ifp = &sc->arpcom.ac_if;
1004 txcons = csr_read_4(sc, SF_CQ_CONSIDX);
1005 cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
1006 cmpconsidx = SF_IDX_HI(txcons);
1008 while (cmpconsidx != cmpprodidx) {
1009 cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
1010 cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
1012 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
1015 if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
1016 sf_txthresh_adjust(sc);
1021 if (cur_tx->sf_mbuf != NULL) {
1022 m_freem(cur_tx->sf_mbuf);
1023 cur_tx->sf_mbuf = NULL;
1026 SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
1030 ifp->if_flags &= ~IFF_OACTIVE;
1032 csr_write_4(sc, SF_CQ_CONSIDX,
1033 (txcons & ~SF_CQ_CONSIDX_TXQ) |
1034 ((cmpconsidx << 16) & 0xFFFF0000));
1040 sf_txthresh_adjust(struct sf_softc *sc)
1045 txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
1046 txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
1047 if (txthresh < 0xFF) {
1049 txfctl &= ~SF_TXFRMCTL_TXTHRESH;
1052 printf("sf%d: tx underrun, increasing "
1053 "tx threshold to %d bytes\n",
1054 sc->sf_unit, txthresh * 4);
1056 csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
1065 struct sf_softc *sc;
1070 ifp = &sc->arpcom.ac_if;
1072 if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED))
1075 /* Disable interrupts. */
1076 csr_write_4(sc, SF_IMR, 0x00000000);
1079 status = csr_read_4(sc, SF_ISR);
1081 csr_write_4(sc, SF_ISR, status);
1083 if (!(status & SF_INTRS))
1086 if (status & SF_ISR_RXDQ1_DMADONE)
1089 if (status & SF_ISR_TX_TXDONE ||
1090 status & SF_ISR_TX_DMADONE ||
1091 status & SF_ISR_TX_QUEUEDONE)
1094 if (status & SF_ISR_TX_LOFIFO)
1095 sf_txthresh_adjust(sc);
1097 if (status & SF_ISR_ABNORMALINTR) {
1098 if (status & SF_ISR_STATSOFLOW) {
1099 callout_stop(&sc->sf_stat_timer);
1100 sf_stats_update(sc);
1106 /* Re-enable interrupts. */
1107 csr_write_4(sc, SF_IMR, SF_INTRS);
1109 if (!ifq_is_empty(&ifp->if_snd))
1118 struct sf_softc *sc = xsc;
1119 struct ifnet *ifp = &sc->arpcom.ac_if;
1125 /* Init all the receive filter registers */
1126 for (i = SF_RXFILT_PERFECT_BASE;
1127 i < (SF_RXFILT_HASH_MAX + 1); i += 4)
1128 csr_write_4(sc, i, 0);
1130 /* Empty stats counter registers. */
1131 for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
1132 csr_write_4(sc, SF_STATS_BASE +
1133 (i + sizeof(u_int32_t)), 0);
1135 /* Init our MAC address */
1136 csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1137 csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1138 sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
1140 if (sf_init_rx_ring(sc) == ENOBUFS) {
1141 printf("sf%d: initialization failed: no "
1142 "memory for rx buffers\n", sc->sf_unit);
1146 sf_init_tx_ring(sc);
1148 csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
1150 /* If we want promiscuous mode, set the allframes bit. */
1151 if (ifp->if_flags & IFF_PROMISC) {
1152 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1154 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
1157 if (ifp->if_flags & IFF_BROADCAST) {
1158 SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1160 SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
1164 * Load the multicast filter.
1168 /* Init the completion queue indexes */
1169 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1170 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1172 /* Init the RX completion queue */
1173 csr_write_4(sc, SF_RXCQ_CTL_1,
1174 vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
1175 SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
1177 /* Init RX DMA control. */
1178 SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
1180 /* Init the RX buffer descriptor queue. */
1181 csr_write_4(sc, SF_RXDQ_ADDR_Q1,
1182 vtophys(sc->sf_ldata->sf_rx_dlist_big));
1183 csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
1184 csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
1186 /* Init the TX completion queue */
1187 csr_write_4(sc, SF_TXCQ_CTL,
1188 vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
1190 /* Init the TX buffer descriptor queue. */
1191 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
1192 vtophys(sc->sf_ldata->sf_tx_dlist));
1193 SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
1194 csr_write_4(sc, SF_TXDQ_CTL,
1195 SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
1196 SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
1198 /* Enable autopadding of short TX frames. */
1199 SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
1201 /* Enable interrupts. */
1202 csr_write_4(sc, SF_IMR, SF_INTRS);
1203 SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
1205 /* Enable the RX and TX engines. */
1206 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
1207 SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
1209 /*mii_mediachg(mii);*/
1210 sf_ifmedia_upd(ifp);
1212 ifp->if_flags |= IFF_RUNNING;
1213 ifp->if_flags &= ~IFF_OACTIVE;
1215 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
1219 sf_encap(struct sf_softc *sc, struct sf_tx_bufdesc_type0 *c,
1220 struct mbuf *m_head)
1223 struct sf_frag *f = NULL;
1228 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1229 if (m->m_len != 0) {
1230 if (frag == SF_MAXFRAGS)
1232 f = &c->sf_frags[frag];
1234 f->sf_pktlen = m_head->m_pkthdr.len;
1235 f->sf_fraglen = m->m_len;
1236 f->sf_addr = vtophys(mtod(m, vm_offset_t));
1242 struct mbuf *m_new = NULL;
1244 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1245 if (m_new == NULL) {
1246 printf("sf%d: no memory for tx list", sc->sf_unit);
1250 if (m_head->m_pkthdr.len > MHLEN) {
1251 MCLGET(m_new, MB_DONTWAIT);
1252 if (!(m_new->m_flags & M_EXT)) {
1254 printf("sf%d: no memory for tx list",
1259 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1260 mtod(m_new, caddr_t));
1261 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1264 f = &c->sf_frags[0];
1265 f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
1266 f->sf_addr = vtophys(mtod(m_head, caddr_t));
1270 c->sf_mbuf = m_head;
1271 c->sf_id = SF_TX_BUFDESC_ID;
1272 c->sf_fragcnt = frag;
1281 sf_start(struct ifnet *ifp)
1283 struct sf_softc *sc;
1284 struct sf_tx_bufdesc_type0 *cur_tx = NULL;
1285 struct mbuf *m_head = NULL;
1293 if (ifp->if_flags & IFF_OACTIVE)
1296 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1297 i = SF_IDX_HI(txprod) >> 4;
1299 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1300 printf("sf%d: TX ring full, resetting\n", sc->sf_unit);
1302 txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
1303 i = SF_IDX_HI(txprod) >> 4;
1306 while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
1307 if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
1308 ifp->if_flags |= IFF_OACTIVE;
1312 m_head = ifq_poll(&ifp->if_snd);
1316 cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
1317 if (sf_encap(sc, cur_tx, m_head)) {
1318 ifp->if_flags |= IFF_OACTIVE;
1322 ifq_dequeue(&ifp->if_snd, m_head);
1323 BPF_MTAP(ifp, cur_tx->sf_mbuf);
1325 SF_INC(i, SF_TX_DLIST_CNT);
1328 * Don't get the TX DMA queue get too full.
1330 if (sc->sf_tx_cnt > 64)
1338 csr_write_4(sc, SF_TXDQ_PRODIDX,
1339 (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
1340 ((i << 20) & 0xFFFF0000));
1348 sf_stop(struct sf_softc *sc)
1353 ifp = &sc->arpcom.ac_if;
1355 callout_stop(&sc->sf_stat_timer);
1357 csr_write_4(sc, SF_GEN_ETH_CTL, 0);
1358 csr_write_4(sc, SF_CQ_CONSIDX, 0);
1359 csr_write_4(sc, SF_CQ_PRODIDX, 0);
1360 csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
1361 csr_write_4(sc, SF_RXDQ_CTL_1, 0);
1362 csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
1363 csr_write_4(sc, SF_TXCQ_CTL, 0);
1364 csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
1365 csr_write_4(sc, SF_TXDQ_CTL, 0);
1370 for (i = 0; i < SF_RX_DLIST_CNT; i++) {
1371 if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
1372 m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
1373 sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
1377 for (i = 0; i < SF_TX_DLIST_CNT; i++) {
1378 if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
1379 m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
1380 sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
1384 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1390 * Note: it is important that this function not be interrupted. We
1391 * use a two-stage register access scheme: if we are interrupted in
1392 * between setting the indirect address register and reading from the
1393 * indirect data register, the contents of the address register could
1394 * be changed out from under us.
1397 sf_stats_update(void *xsc)
1399 struct sf_softc *sc = xsc;
1400 struct ifnet *ifp = &sc->arpcom.ac_if;
1401 struct mii_data *mii = device_get_softc(sc->sf_miibus);
1402 struct sf_stats stats;
1406 lwkt_serialize_enter(ifp->if_serializer);
1408 ptr = (u_int32_t *)&stats;
1409 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1410 ptr[i] = csr_read_4(sc, SF_STATS_BASE +
1411 (i + sizeof(u_int32_t)));
1413 for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
1414 csr_write_4(sc, SF_STATS_BASE +
1415 (i + sizeof(u_int32_t)), 0);
1417 ifp->if_collisions += stats.sf_tx_single_colls +
1418 stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
1423 if (mii->mii_media_status & IFM_ACTIVE &&
1424 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
1426 if (!ifq_is_empty(&ifp->if_snd))
1430 callout_reset(&sc->sf_stat_timer, hz, sf_stats_update, sc);
1432 lwkt_serialize_exit(ifp->if_serializer);
1436 sf_watchdog(struct ifnet *ifp)
1438 struct sf_softc *sc;
1443 printf("sf%d: watchdog timeout\n", sc->sf_unit);
1449 if (!ifq_is_empty(&ifp->if_snd))
1456 sf_shutdown(device_t dev)
1458 struct sf_softc *sc;
1461 sc = device_get_softc(dev);
1462 ifp = &sc->arpcom.ac_if;
1463 lwkt_serialize_enter(ifp->if_serializer);
1465 lwkt_serialize_exit(ifp->if_serializer);