sys/dev/disk/aic7xxx/aic79xx_pci.c

   1 /*
   2  * Product specific probe and attach routines for:
   3  *      aic7901 and aic7902 SCSI controllers
   4  *
   5  * Copyright (c) 1994-2001 Justin T. Gibbs.
   6  * Copyright (c) 2000-2002 Adaptec Inc.
   7  * All rights reserved.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  16  *    substantially similar to the "NO WARRANTY" disclaimer below
  17  *    ("Disclaimer") and any redistribution must be conditioned upon
  18  *    including a substantially similar Disclaimer requirement for further
  19  *    binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  35  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  36  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  37  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  38  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  39  * POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  * $Id: //depot/aic7xxx/aic7xxx/aic79xx_pci.c#86 $
  42  *
  43  * $FreeBSD: src/sys/dev/aic7xxx/aic79xx_pci.c,v 1.18 2004/02/04 16:38:38 gibbs Exp $
  44  * $DragonFly: src/sys/dev/disk/aic7xxx/aic79xx_pci.c,v 1.10 2007/07/06 00:56:38 pavalos Exp $
  45  */
  46
  47 #ifdef __linux__
  48 #include "aic79xx_osm.h"
  49 #include "aic79xx_inline.h"
  50 #else
  51 #include "aic79xx_osm.h"
  52 #include "aic79xx_inline.h"
  53 #endif
  54
  55 static __inline uint64_t
  56 ahd_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
  57 {
  58         uint64_t id;
  59
  60         id = subvendor
  61            | (subdevice << 16)
  62            | ((uint64_t)vendor << 32)
  63            | ((uint64_t)device << 48);
  64
  65         return (id);
  66 }
  67
  68 #define ID_ALL_MASK                     0xFFFFFFFFFFFFFFFFull
  69 #define ID_ALL_IROC_MASK                0xFF7FFFFFFFFFFFFFull
  70 #define ID_DEV_VENDOR_MASK              0xFFFFFFFF00000000ull
  71 #define ID_9005_GENERIC_MASK            0xFFF0FFFF00000000ull
  72 #define ID_9005_GENERIC_IROC_MASK       0xFF70FFFF00000000ull
  73
  74 #define ID_AIC7901                      0x800F9005FFFF9005ull
  75 #define ID_AHA_29320A                   0x8000900500609005ull
  76 #define ID_AHA_29320ALP                 0x8017900500449005ull
  77
  78 #define ID_AIC7901A                     0x801E9005FFFF9005ull
  79 #define ID_AHA_29320LP                  0x8014900500449005ull
  80
  81 #define ID_AIC7902                      0x801F9005FFFF9005ull
  82 #define ID_AIC7902_B                    0x801D9005FFFF9005ull
  83 #define ID_AHA_39320                    0x8010900500409005ull
  84 #define ID_AHA_29320                    0x8012900500429005ull
  85 #define ID_AHA_29320B                   0x8013900500439005ull
  86 #define ID_AHA_39320_B                  0x8015900500409005ull
  87 #define ID_AHA_39320A                   0x8016900500409005ull
  88 #define ID_AHA_39320D                   0x8011900500419005ull
  89 #define ID_AHA_39320D_B                 0x801C900500419005ull
  90 #define ID_AHA_39320D_HP                0x8011900500AC0E11ull
  91 #define ID_AHA_39320D_B_HP              0x801C900500AC0E11ull
  92 #define ID_AIC7902_PCI_REV_A4           0x3
  93 #define ID_AIC7902_PCI_REV_B0           0x10
  94 #define SUBID_HP                        0x0E11
  95
  96 #define DEVID_9005_HOSTRAID(id) ((id) & 0x80)
  97
  98 #define DEVID_9005_TYPE(id) ((id) & 0xF)
  99 #define         DEVID_9005_TYPE_HBA             0x0     /* Standard Card */
 100 #define         DEVID_9005_TYPE_HBA_2EXT        0x1     /* 2 External Ports */
 101 #define         DEVID_9005_TYPE_MB              0xF     /* On Motherboard */
 102
 103 #define DEVID_9005_MFUNC(id) ((id) & 0x10)
 104
 105 #define DEVID_9005_PACKETIZED(id) ((id) & 0x8000)
 106
 107 #define SUBID_9005_TYPE(id) ((id) & 0xF)
 108 #define         SUBID_9005_TYPE_HBA             0x0     /* Standard Card */
 109 #define         SUBID_9005_TYPE_MB              0xF     /* On Motherboard */
 110
 111 #define SUBID_9005_AUTOTERM(id) (((id) & 0x10) == 0)
 112
 113 #define SUBID_9005_LEGACYCONN_FUNC(id) ((id) & 0x20)
 114
 115 #define SUBID_9005_SEEPTYPE(id) ((id) & 0x0C0) >> 6)
 116 #define         SUBID_9005_SEEPTYPE_NONE        0x0
 117 #define         SUBID_9005_SEEPTYPE_4K          0x1
 118
 119 static ahd_device_setup_t ahd_aic7901_setup;
 120 static ahd_device_setup_t ahd_aic7901A_setup;
 121 static ahd_device_setup_t ahd_aic7902_setup;
 122 static ahd_device_setup_t ahd_aic790X_setup;
 123
 124 struct ahd_pci_identity ahd_pci_ident_table [] =
 125 {
 126         /* aic7901 based controllers */
 127         {
 128                 ID_AHA_29320A,
 129                 ID_ALL_MASK,
 130                 "Adaptec 29320A Ultra320 SCSI adapter",
 131                 ahd_aic7901_setup
 132         },
 133         {
 134                 ID_AHA_29320ALP,
 135                 ID_ALL_MASK,
 136                 "Adaptec 29320ALP Ultra320 SCSI adapter",
 137                 ahd_aic7901_setup
 138         },
 139         /* aic7901A based controllers */
 140         {
 141                 ID_AHA_29320LP,
 142                 ID_ALL_MASK,
 143                 "Adaptec 29320LP Ultra320 SCSI adapter",
 144                 ahd_aic7901A_setup
 145         },
 146         /* aic7902 based controllers */
 147         {
 148                 ID_AHA_29320,
 149                 ID_ALL_MASK,
 150                 "Adaptec 29320 Ultra320 SCSI adapter",
 151                 ahd_aic7902_setup
 152         },
 153         {
 154                 ID_AHA_29320B,
 155                 ID_ALL_MASK,
 156                 "Adaptec 29320B Ultra320 SCSI adapter",
 157                 ahd_aic7902_setup
 158         },
 159         {
 160                 ID_AHA_39320,
 161                 ID_ALL_MASK,
 162                 "Adaptec 39320 Ultra320 SCSI adapter",
 163                 ahd_aic7902_setup
 164         },
 165         {
 166                 ID_AHA_39320_B,
 167                 ID_ALL_MASK,
 168                 "Adaptec 39320 Ultra320 SCSI adapter",
 169                 ahd_aic7902_setup
 170         },
 171         {
 172                 ID_AHA_39320A,
 173                 ID_ALL_MASK,
 174                 "Adaptec 39320A Ultra320 SCSI adapter",
 175                 ahd_aic7902_setup
 176         },
 177         {
 178                 ID_AHA_39320D,
 179                 ID_ALL_MASK,
 180                 "Adaptec 39320D Ultra320 SCSI adapter",
 181                 ahd_aic7902_setup
 182         },
 183         {
 184                 ID_AHA_39320D_HP,
 185                 ID_ALL_MASK,
 186                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 187                 ahd_aic7902_setup
 188         },
 189         {
 190                 ID_AHA_39320D_B,
 191                 ID_ALL_MASK,
 192                 "Adaptec 39320D Ultra320 SCSI adapter",
 193                 ahd_aic7902_setup
 194         },
 195         {
 196                 ID_AHA_39320D_B_HP,
 197                 ID_ALL_MASK,
 198                 "Adaptec (HP OEM) 39320D Ultra320 SCSI adapter",
 199                 ahd_aic7902_setup
 200         },
 201         /* Generic chip probes for devices we don't know 'exactly' */
 202         {
 203                 ID_AIC7901 & ID_9005_GENERIC_MASK,
 204                 ID_DEV_VENDOR_MASK,
 205                 "Adaptec AIC7901 Ultra320 SCSI adapter",
 206                 ahd_aic7901_setup
 207         },
 208         {
 209                 ID_AIC7901A & ID_DEV_VENDOR_MASK,
 210                 ID_DEV_VENDOR_MASK,
 211                 "Adaptec AIC7901A Ultra320 SCSI adapter",
 212                 ahd_aic7901A_setup
 213         },
 214         {
 215                 ID_AIC7902 & ID_9005_GENERIC_MASK,
 216                 ID_9005_GENERIC_MASK,
 217                 "Adaptec AIC7902 Ultra320 SCSI adapter",
 218                 ahd_aic7902_setup
 219         }
 220 };
 221
 222 const u_int ahd_num_pci_devs = NUM_ELEMENTS(ahd_pci_ident_table);
 223
 224 #define DEVCONFIG               0x40
 225 #define         PCIXINITPAT     0x0000E000ul
 226 #define                 PCIXINIT_PCI33_66       0x0000E000ul
 227 #define                 PCIXINIT_PCIX50_66      0x0000C000ul
 228 #define                 PCIXINIT_PCIX66_100     0x0000A000ul
 229 #define                 PCIXINIT_PCIX100_133    0x00008000ul
 230 #define PCI_BUS_MODES_INDEX(devconfig)  \
 231         (((devconfig) & PCIXINITPAT) >> 13)
 232 static const char *pci_bus_modes[] =
 233 {
 234         "PCI bus mode unknown",
 235         "PCI bus mode unknown",
 236         "PCI bus mode unknown",
 237         "PCI bus mode unknown",
 238         "PCI-X 101-133Mhz",
 239         "PCI-X 67-100Mhz",
 240         "PCI-X 50-66Mhz",
 241         "PCI 33 or 66Mhz"
 242 };
 243
 244 #define         TESTMODE        0x00000800ul
 245 #define         IRDY_RST        0x00000200ul
 246 #define         FRAME_RST       0x00000100ul
 247 #define         PCI64BIT        0x00000080ul
 248 #define         MRDCEN          0x00000040ul
 249 #define         ENDIANSEL       0x00000020ul
 250 #define         MIXQWENDIANEN   0x00000008ul
 251 #define         DACEN           0x00000004ul
 252 #define         STPWLEVEL       0x00000002ul
 253 #define         QWENDIANSEL     0x00000001ul
 254
 255 #define DEVCONFIG1              0x44
 256 #define         PREQDIS         0x01
 257
 258 #define CSIZE_LATTIME           0x0c
 259 #define         CACHESIZE       0x000000fful
 260 #define         LATTIME         0x0000ff00ul
 261
 262 static int      ahd_check_extport(struct ahd_softc *ahd);
 263 static void     ahd_configure_termination(struct ahd_softc *ahd,
 264                                           u_int adapter_control);
 265 static void     ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat);
 266
 267 struct ahd_pci_identity *
 268 ahd_find_pci_device(aic_dev_softc_t pci)
 269 {
 270         uint64_t  full_id;
 271         uint16_t  device;
 272         uint16_t  vendor;
 273         uint16_t  subdevice;
 274         uint16_t  subvendor;
 275         struct    ahd_pci_identity *entry;
 276         u_int     i;
 277
 278         vendor = aic_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2);
 279         device = aic_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2);
 280         subvendor = aic_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2);
 281         subdevice = aic_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2);
 282         full_id = ahd_compose_id(device,
 283                                  vendor,
 284                                  subdevice,
 285                                  subvendor);
 286
 287         /*
 288          * If we are configured to attach to HostRAID
 289          * controllers, mask out the IROC/HostRAID bit
 290          * in the
 291          */
 292         if (ahd_attach_to_HostRAID_controllers)
 293                 full_id &= ID_ALL_IROC_MASK;
 294
 295         for (i = 0; i < ahd_num_pci_devs; i++) {
 296                 entry = &ahd_pci_ident_table[i];
 297                 if (entry->full_id == (full_id & entry->id_mask)) {
 298                         /* Honor exclusion entries. */
 299                         if (entry->name == NULL)
 300                                 return (NULL);
 301                         return (entry);
 302                 }
 303         }
 304         return (NULL);
 305 }
 306
 307 int
 308 ahd_pci_config(struct ahd_softc *ahd, struct ahd_pci_identity *entry)
 309 {
 310         struct scb_data *shared_scb_data;
 311         u_int            command;
 312         uint32_t         devconfig;
 313         uint16_t         device;
 314         uint16_t         subvendor;
 315         int              error;
 316
 317         shared_scb_data = NULL;
 318         ahd->description = entry->name;
 319         /*
 320          * Record if this is a HostRAID board.
 321          */
 322         device = aic_pci_read_config(ahd->dev_softc,
 323                                      PCIR_DEVICE, /*bytes*/2);
 324         if (DEVID_9005_HOSTRAID(device))
 325                 ahd->flags |= AHD_HOSTRAID_BOARD;
 326
 327         /*
 328          * Record if this is an HP board.
 329          */
 330         subvendor = aic_pci_read_config(ahd->dev_softc,
 331                                         PCIR_SUBVEND_0, /*bytes*/2);
 332         if (subvendor == SUBID_HP)
 333                 ahd->flags |= AHD_HP_BOARD;
 334
 335         error = entry->setup(ahd);
 336         if (error != 0)
 337                 return (error);
 338
 339         devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 340         if ((devconfig & PCIXINITPAT) == PCIXINIT_PCI33_66) {
 341                 ahd->chip |= AHD_PCI;
 342                 /* Disable PCIX workarounds when running in PCI mode. */
 343                 ahd->bugs &= ~AHD_PCIX_BUG_MASK;
 344         } else {
 345                 ahd->chip |= AHD_PCIX;
 346         }
 347         ahd->bus_description = pci_bus_modes[PCI_BUS_MODES_INDEX(devconfig)];
 348
 349         aic_power_state_change(ahd, AIC_POWER_STATE_D0);
 350
 351         error = ahd_pci_map_registers(ahd);
 352         if (error != 0)
 353                 return (error);
 354
 355         /*
 356          * If we need to support high memory, enable dual
 357          * address cycles.  This bit must be set to enable
 358          * high address bit generation even if we are on a
 359          * 64bit bus (PCI64BIT set in devconfig).
 360          */
 361         if ((ahd->flags & (AHD_39BIT_ADDRESSING|AHD_64BIT_ADDRESSING)) != 0) {
 362                 uint32_t devconfig;
 363
 364                 if (bootverbose)
 365                         kprintf("%s: Enabling 39Bit Addressing\n",
 366                                ahd_name(ahd));
 367                 devconfig = aic_pci_read_config(ahd->dev_softc,
 368                                                 DEVCONFIG, /*bytes*/4);
 369                 devconfig |= DACEN;
 370                 aic_pci_write_config(ahd->dev_softc, DEVCONFIG,
 371                                      devconfig, /*bytes*/4);
 372         }
 373
 374         /* Ensure busmastering is enabled */
 375         command = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 376         command |= PCIM_CMD_BUSMASTEREN;
 377         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, command, /*bytes*/2);
 378
 379         error = ahd_softc_init(ahd);
 380         if (error != 0)
 381                 return (error);
 382
 383         ahd->bus_intr = ahd_pci_intr;
 384
 385         error = ahd_reset(ahd, /*reinit*/FALSE);
 386         if (error != 0)
 387                 return (ENXIO);
 388
 389         ahd->pci_cachesize =
 390             aic_pci_read_config(ahd->dev_softc, CSIZE_LATTIME,
 391                                 /*bytes*/1) & CACHESIZE;
 392         ahd->pci_cachesize *= 4;
 393
 394         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 395         /* See if we have a SEEPROM and perform auto-term */
 396         error = ahd_check_extport(ahd);
 397         if (error != 0)
 398                 return (error);
 399
 400         /* Core initialization */
 401         error = ahd_init(ahd);
 402         if (error != 0)
 403                 return (error);
 404
 405         /*
 406          * Allow interrupts now that we are completely setup.
 407          */
 408         error = ahd_pci_map_int(ahd);
 409         if (error != 0)
 410                 return (error);
 411
 412         /*
 413          * Link this softc in with all other ahd instances.
 414          */
 415         ahd_softc_insert(ahd);
 416         return (0);
 417 }
 418
 419 /*
 420  * Perform some simple tests that should catch situations where
 421  * our registers are invalidly mapped.
 422  */
 423 int
 424 ahd_pci_test_register_access(struct ahd_softc *ahd)
 425 {
 426         uint32_t cmd;
 427         u_int    targpcistat;
 428         u_int    pci_status1;
 429         int      error;
 430         uint8_t  hcntrl;
 431
 432         error = EIO;
 433
 434         /*
 435          * Enable PCI error interrupt status, but suppress NMIs
 436          * generated by SERR raised due to target aborts.
 437          */
 438         cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
 439         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
 440                              cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2);
 441
 442         /*
 443          * First a simple test to see if any
 444          * registers can be read.  Reading
 445          * HCNTRL has no side effects and has
 446          * at least one bit that is guaranteed to
 447          * be zero so it is a good register to
 448          * use for this test.
 449          */
 450         hcntrl = ahd_inb(ahd, HCNTRL);
 451         if (hcntrl == 0xFF)
 452                 goto fail;
 453
 454         /*
 455          * Next create a situation where write combining
 456          * or read prefetching could be initiated by the
 457          * CPU or host bridge.  Our device does not support
 458          * either, so look for data corruption and/or flaged
 459          * PCI errors.  First pause without causing another
 460          * chip reset.
 461          */
 462         hcntrl &= ~CHIPRST;
 463         ahd_outb(ahd, HCNTRL, hcntrl|PAUSE);
 464         while (ahd_is_paused(ahd) == 0)
 465                 ;
 466
 467         /* Clear any PCI errors that occurred before our driver attached. */
 468         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 469         targpcistat = ahd_inb(ahd, TARGPCISTAT);
 470         ahd_outb(ahd, TARGPCISTAT, targpcistat);
 471         pci_status1 = aic_pci_read_config(ahd->dev_softc,
 472                                           PCIR_STATUS + 1, /*bytes*/1);
 473         aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 474                              pci_status1, /*bytes*/1);
 475         ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
 476         ahd_outb(ahd, CLRINT, CLRPCIINT);
 477
 478         ahd_outb(ahd, SEQCTL0, PERRORDIS);
 479         ahd_outl(ahd, SRAM_BASE, 0x5aa555aa);
 480         if (ahd_inl(ahd, SRAM_BASE) != 0x5aa555aa)
 481                 goto fail;
 482
 483         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 484                 u_int targpcistat;
 485
 486                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 487                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 488                 if ((targpcistat & STA) != 0)
 489                         goto fail;
 490         }
 491
 492         error = 0;
 493
 494 fail:
 495         if ((ahd_inb(ahd, INTSTAT) & PCIINT) != 0) {
 496
 497                 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 498                 targpcistat = ahd_inb(ahd, TARGPCISTAT);
 499
 500                 /* Silently clear any latched errors. */
 501                 ahd_outb(ahd, TARGPCISTAT, targpcistat);
 502                 pci_status1 = aic_pci_read_config(ahd->dev_softc,
 503                                                   PCIR_STATUS + 1, /*bytes*/1);
 504                 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 505                                      pci_status1, /*bytes*/1);
 506                 ahd_outb(ahd, CLRINT, CLRPCIINT);
 507         }
 508         ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS);
 509         aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
 510         return (error);
 511 }
 512
 513 /*
 514  * Check the external port logic for a serial eeprom
 515  * and termination/cable detection contrls.
 516  */
 517 static int
 518 ahd_check_extport(struct ahd_softc *ahd)
 519 {
 520         struct  vpd_config vpd;
 521         struct  seeprom_config *sc;
 522         u_int   adapter_control;
 523         int     have_seeprom;
 524         int     error;
 525
 526         sc = ahd->seep_config;
 527         have_seeprom = ahd_acquire_seeprom(ahd);
 528         if (have_seeprom) {
 529                 u_int start_addr;
 530
 531                 /*
 532                  * Fetch VPD for this function and parse it.
 533                  */
 534                 if (bootverbose)
 535                         kprintf("%s: Reading VPD from SEEPROM...",
 536                                ahd_name(ahd));
 537
 538                 /* Address is always in units of 16bit words */
 539                 start_addr = ((2 * sizeof(*sc))
 540                             + (sizeof(vpd) * (ahd->channel - 'A'))) / 2;
 541
 542                 error = ahd_read_seeprom(ahd, (uint16_t *)&vpd,
 543                                          start_addr, sizeof(vpd)/2,
 544                                          /*bytestream*/TRUE);
 545                 if (error == 0)
 546                         error = ahd_parse_vpddata(ahd, &vpd);
 547                 if (bootverbose)
 548                         kprintf("%s: VPD parsing %s\n",
 549                                ahd_name(ahd),
 550                                error == 0 ? "successful" : "failed");
 551
 552                 if (bootverbose)
 553                         kprintf("%s: Reading SEEPROM...", ahd_name(ahd));
 554
 555                 /* Address is always in units of 16bit words */
 556                 start_addr = (sizeof(*sc) / 2) * (ahd->channel - 'A');
 557
 558                 error = ahd_read_seeprom(ahd, (uint16_t *)sc,
 559                                          start_addr, sizeof(*sc)/2,
 560                                          /*bytestream*/FALSE);
 561
 562                 if (error != 0) {
 563                         kprintf("Unable to read SEEPROM\n");
 564                         have_seeprom = 0;
 565                 } else {
 566                         have_seeprom = ahd_verify_cksum(sc);
 567
 568                         if (bootverbose) {
 569                                 if (have_seeprom == 0)
 570                                         kprintf ("checksum error\n");
 571                                 else
 572                                         kprintf ("done.\n");
 573                         }
 574                 }
 575                 ahd_release_seeprom(ahd);
 576         }
 577
 578         if (!have_seeprom) {
 579                 u_int     nvram_scb;
 580
 581                 /*
 582                  * Pull scratch ram settings and treat them as
 583                  * if they are the contents of an seeprom if
 584                  * the 'ADPT', 'BIOS', or 'ASPI' signature is found
 585                  * in SCB 0xFF.  We manually compose the data as 16bit
 586                  * values to avoid endian issues.
 587                  */
 588                 ahd_set_scbptr(ahd, 0xFF);
 589                 nvram_scb = ahd_inb_scbram(ahd, SCB_BASE + NVRAM_SCB_OFFSET);
 590                 if (nvram_scb != 0xFF
 591                  && ((ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 592                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'D'
 593                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 594                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'T')
 595                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'B'
 596                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'I'
 597                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'O'
 598                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'S')
 599                   || (ahd_inb_scbram(ahd, SCB_BASE + 0) == 'A'
 600                    && ahd_inb_scbram(ahd, SCB_BASE + 1) == 'S'
 601                    && ahd_inb_scbram(ahd, SCB_BASE + 2) == 'P'
 602                    && ahd_inb_scbram(ahd, SCB_BASE + 3) == 'I'))) {
 603                         uint16_t *sc_data;
 604                         int       i;
 605
 606                         ahd_set_scbptr(ahd, nvram_scb);
 607                         sc_data = (uint16_t *)sc;
 608                         for (i = 0; i < 64; i += 2)
 609                                 *sc_data++ = ahd_inw_scbram(ahd, SCB_BASE+i);
 610                         have_seeprom = ahd_verify_cksum(sc);
 611                         if (have_seeprom)
 612                                 ahd->flags |= AHD_SCB_CONFIG_USED;
 613                 }
 614         }
 615
 616 #if AHD_DEBUG
 617         if (have_seeprom != 0
 618          && (ahd_debug & AHD_DUMP_SEEPROM) != 0) {
 619                 uint16_t *sc_data;
 620                 int       i;
 621
 622                 kprintf("%s: Seeprom Contents:", ahd_name(ahd));
 623                 sc_data = (uint16_t *)sc;
 624                 for (i = 0; i < (sizeof(*sc)); i += 2)
 625                         kprintf("\n\t0x%.4x", sc_data[i]);
 626                 kprintf("\n");
 627         }
 628 #endif
 629
 630         if (!have_seeprom) {
 631                 if (bootverbose)
 632                         kprintf("%s: No SEEPROM available.\n", ahd_name(ahd));
 633                 ahd->flags |= AHD_USEDEFAULTS;
 634                 error = ahd_default_config(ahd);
 635                 adapter_control = CFAUTOTERM|CFSEAUTOTERM;
 636                 kfree(ahd->seep_config, M_DEVBUF);
 637                 ahd->seep_config = NULL;
 638         } else {
 639                 error = ahd_parse_cfgdata(ahd, sc);
 640                 adapter_control = sc->adapter_control;
 641         }
 642         if (error != 0)
 643                 return (error);
 644
 645         ahd_configure_termination(ahd, adapter_control);
 646
 647         return (0);
 648 }
 649
 650 static void
 651 ahd_configure_termination(struct ahd_softc *ahd, u_int adapter_control)
 652 {
 653         int      error;
 654         u_int    sxfrctl1;
 655         uint8_t  termctl;
 656         uint32_t devconfig;
 657
 658         devconfig = aic_pci_read_config(ahd->dev_softc, DEVCONFIG, /*bytes*/4);
 659         devconfig &= ~STPWLEVEL;
 660         if ((ahd->flags & AHD_STPWLEVEL_A) != 0)
 661                 devconfig |= STPWLEVEL;
 662         if (bootverbose)
 663                 kprintf("%s: STPWLEVEL is %s\n",
 664                        ahd_name(ahd), (devconfig & STPWLEVEL) ? "on" : "off");
 665         aic_pci_write_config(ahd->dev_softc, DEVCONFIG, devconfig, /*bytes*/4);
 666
 667         /* Make sure current sensing is off. */
 668         if ((ahd->flags & AHD_CURRENT_SENSING) != 0) {
 669                 (void)ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
 670         }
 671
 672         /*
 673          * Read to sense.  Write to set.
 674          */
 675         error = ahd_read_flexport(ahd, FLXADDR_TERMCTL, &termctl);
 676         if ((adapter_control & CFAUTOTERM) == 0) {
 677                 if (bootverbose)
 678                         kprintf("%s: Manual Primary Termination\n",
 679                                ahd_name(ahd));
 680                 termctl &= ~(FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH);
 681                 if ((adapter_control & CFSTERM) != 0)
 682                         termctl |= FLX_TERMCTL_ENPRILOW;
 683                 if ((adapter_control & CFWSTERM) != 0)
 684                         termctl |= FLX_TERMCTL_ENPRIHIGH;
 685         } else if (error != 0) {
 686                 kprintf("%s: Primary Auto-Term Sensing failed! "
 687                        "Using Defaults.\n", ahd_name(ahd));
 688                 termctl = FLX_TERMCTL_ENPRILOW|FLX_TERMCTL_ENPRIHIGH;
 689         }
 690
 691         if ((adapter_control & CFSEAUTOTERM) == 0) {
 692                 if (bootverbose)
 693                         kprintf("%s: Manual Secondary Termination\n",
 694                                ahd_name(ahd));
 695                 termctl &= ~(FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH);
 696                 if ((adapter_control & CFSELOWTERM) != 0)
 697                         termctl |= FLX_TERMCTL_ENSECLOW;
 698                 if ((adapter_control & CFSEHIGHTERM) != 0)
 699                         termctl |= FLX_TERMCTL_ENSECHIGH;
 700         } else if (error != 0) {
 701                 kprintf("%s: Secondary Auto-Term Sensing failed! "
 702                        "Using Defaults.\n", ahd_name(ahd));
 703                 termctl |= FLX_TERMCTL_ENSECLOW|FLX_TERMCTL_ENSECHIGH;
 704         }
 705
 706         /*
 707          * Now set the termination based on what we found.
 708          */
 709         sxfrctl1 = ahd_inb(ahd, SXFRCTL1) & ~STPWEN;
 710         ahd->flags &= ~AHD_TERM_ENB_A;
 711         if ((termctl & FLX_TERMCTL_ENPRILOW) != 0) {
 712                 ahd->flags |= AHD_TERM_ENB_A;
 713                 sxfrctl1 |= STPWEN;
 714         }
 715         /* Must set the latch once in order to be effective. */
 716         ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
 717         ahd_outb(ahd, SXFRCTL1, sxfrctl1);
 718
 719         error = ahd_write_flexport(ahd, FLXADDR_TERMCTL, termctl);
 720         if (error != 0) {
 721                 kprintf("%s: Unable to set termination settings!\n",
 722                        ahd_name(ahd));
 723         } else if (bootverbose) {
 724                 kprintf("%s: Primary High byte termination %sabled\n",
 725                        ahd_name(ahd),
 726                        (termctl & FLX_TERMCTL_ENPRIHIGH) ? "En" : "Dis");
 727
 728                 kprintf("%s: Primary Low byte termination %sabled\n",
 729                        ahd_name(ahd),
 730                        (termctl & FLX_TERMCTL_ENPRILOW) ? "En" : "Dis");
 731
 732                 kprintf("%s: Secondary High byte termination %sabled\n",
 733                        ahd_name(ahd),
 734                        (termctl & FLX_TERMCTL_ENSECHIGH) ? "En" : "Dis");
 735
 736                 kprintf("%s: Secondary Low byte termination %sabled\n",
 737                        ahd_name(ahd),
 738                        (termctl & FLX_TERMCTL_ENSECLOW) ? "En" : "Dis");
 739         }
 740         return;
 741 }
 742
 743 #define DPE     0x80
 744 #define SSE     0x40
 745 #define RMA     0x20
 746 #define RTA     0x10
 747 #define STA     0x08
 748 #define DPR     0x01
 749
 750 static const char *split_status_source[] =
 751 {
 752         "DFF0",
 753         "DFF1",
 754         "OVLY",
 755         "CMC",
 756 };
 757
 758 static const char *pci_status_source[] =
 759 {
 760         "DFF0",
 761         "DFF1",
 762         "SG",
 763         "CMC",
 764         "OVLY",
 765         "NONE",
 766         "MSI",
 767         "TARG"
 768 };
 769
 770 static const char *split_status_strings[] =
 771 {
 772         "%s: Received split response in %s.\n",
 773         "%s: Received split completion error message in %s\n",
 774         "%s: Receive overrun in %s\n",
 775         "%s: Count not complete in %s\n",
 776         "%s: Split completion data bucket in %s\n",
 777         "%s: Split completion address error in %s\n",
 778         "%s: Split completion byte count error in %s\n",
 779         "%s: Signaled Target-abort to early terminate a split in %s\n"
 780 };
 781
 782 static const char *pci_status_strings[] =
 783 {
 784         "%s: Data Parity Error has been reported via PERR# in %s\n",
 785         "%s: Target initial wait state error in %s\n",
 786         "%s: Split completion read data parity error in %s\n",
 787         "%s: Split completion address attribute parity error in %s\n",
 788         "%s: Received a Target Abort in %s\n",
 789         "%s: Received a Master Abort in %s\n",
 790         "%s: Signal System Error Detected in %s\n",
 791         "%s: Address or Write Phase Parity Error Detected in %s.\n"
 792 };
 793
 794 void
 795 ahd_pci_intr(struct ahd_softc *ahd)
 796 {
 797         uint8_t         pci_status[8];
 798         ahd_mode_state  saved_modes;
 799         u_int           pci_status1;
 800         u_int           intstat;
 801         u_int           i;
 802         u_int           reg;
 803
 804         intstat = ahd_inb(ahd, INTSTAT);
 805
 806         if ((intstat & SPLTINT) != 0)
 807                 ahd_pci_split_intr(ahd, intstat);
 808
 809         if ((intstat & PCIINT) == 0)
 810                 return;
 811
 812         kprintf("%s: PCI error Interrupt\n", ahd_name(ahd));
 813         saved_modes = ahd_save_modes(ahd);
 814         ahd_dump_card_state(ahd);
 815         ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
 816         for (i = 0, reg = DF0PCISTAT; i < 8; i++, reg++) {
 817
 818                 if (i == 5)
 819                         continue;
 820                 pci_status[i] = ahd_inb(ahd, reg);
 821                 /* Clear latched errors.  So our interrupt deasserts. */
 822                 ahd_outb(ahd, reg, pci_status[i]);
 823         }
 824
 825         for (i = 0; i < 8; i++) {
 826                 u_int bit;
 827
 828                 if (i == 5)
 829                         continue;
 830
 831                 for (bit = 0; bit < 8; bit++) {
 832
 833                         if ((pci_status[i] & (0x1 << bit)) != 0) {
 834                                 static const char *s;
 835
 836                                 s = pci_status_strings[bit];
 837                                 if (i == 7/*TARG*/ && bit == 3)
 838                                         s = "%s: Signaled Target Abort\n";
 839                                 kprintf(s, ahd_name(ahd), pci_status_source[i]);
 840                         }
 841                 }
 842         }
 843         pci_status1 = aic_pci_read_config(ahd->dev_softc,
 844                                           PCIR_STATUS + 1, /*bytes*/1);
 845         aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
 846                              pci_status1, /*bytes*/1);
 847         ahd_restore_modes(ahd, saved_modes);
 848         ahd_outb(ahd, CLRINT, CLRPCIINT);
 849         ahd_unpause(ahd);
 850 }
 851
 852 static void
 853 ahd_pci_split_intr(struct ahd_softc *ahd, u_int intstat)
 854 {
 855         uint8_t         split_status[4];
 856         uint8_t         split_status1[4];
 857         uint8_t         sg_split_status[2];
 858         uint8_t         sg_split_status1[2];
 859         ahd_mode_state  saved_modes;
 860         u_int           i;
 861         uint16_t        pcix_status;
 862
 863         /*
 864          * Check for splits in all modes.  Modes 0 and 1
 865          * additionally have SG engine splits to look at.
 866          */
 867         pcix_status = aic_pci_read_config(ahd->dev_softc, PCIXR_STATUS,
 868                                           /*bytes*/2);
 869         kprintf("%s: PCI Split Interrupt - PCI-X status = 0x%x\n",
 870                ahd_name(ahd), pcix_status);
 871         saved_modes = ahd_save_modes(ahd);
 872         for (i = 0; i < 4; i++) {
 873                 ahd_set_modes(ahd, i, i);
 874
 875                 split_status[i] = ahd_inb(ahd, DCHSPLTSTAT0);
 876                 split_status1[i] = ahd_inb(ahd, DCHSPLTSTAT1);
 877                 /* Clear latched errors.  So our interrupt deasserts. */
 878                 ahd_outb(ahd, DCHSPLTSTAT0, split_status[i]);
 879                 ahd_outb(ahd, DCHSPLTSTAT1, split_status1[i]);
 880                 if (i > 1)
 881                         continue;
 882                 sg_split_status[i] = ahd_inb(ahd, SGSPLTSTAT0);
 883                 sg_split_status1[i] = ahd_inb(ahd, SGSPLTSTAT1);
 884                 /* Clear latched errors.  So our interrupt deasserts. */
 885                 ahd_outb(ahd, SGSPLTSTAT0, sg_split_status[i]);
 886                 ahd_outb(ahd, SGSPLTSTAT1, sg_split_status1[i]);
 887         }
 888
 889         for (i = 0; i < 4; i++) {
 890                 u_int bit;
 891
 892                 for (bit = 0; bit < 8; bit++) {
 893
 894                         if ((split_status[i] & (0x1 << bit)) != 0) {
 895                                 static const char *s;
 896
 897                                 s = split_status_strings[bit];
 898                                 kprintf(s, ahd_name(ahd),
 899                                        split_status_source[i]);
 900                         }
 901
 902                         if (i > 1)
 903                                 continue;
 904
 905                         if ((sg_split_status[i] & (0x1 << bit)) != 0) {
 906                                 static const char *s;
 907
 908                                 s = split_status_strings[bit];
 909                                 kprintf(s, ahd_name(ahd), "SG");
 910                         }
 911                 }
 912         }
 913         /*
 914          * Clear PCI-X status bits.
 915          */
 916         aic_pci_write_config(ahd->dev_softc, PCIXR_STATUS,
 917                              pcix_status, /*bytes*/2);
 918         ahd_outb(ahd, CLRINT, CLRSPLTINT);
 919         ahd_restore_modes(ahd, saved_modes);
 920 }
 921
 922 static int
 923 ahd_aic7901_setup(struct ahd_softc *ahd)
 924 {
 925
 926         ahd->chip = AHD_AIC7901;
 927         ahd->features = AHD_AIC7901_FE;
 928         return (ahd_aic790X_setup(ahd));
 929 }
 930
 931 static int
 932 ahd_aic7901A_setup(struct ahd_softc *ahd)
 933 {
 934
 935         ahd->chip = AHD_AIC7901A;
 936         ahd->features = AHD_AIC7901A_FE;
 937         return (ahd_aic790X_setup(ahd));
 938 }
 939
 940 static int
 941 ahd_aic7902_setup(struct ahd_softc *ahd)
 942 {
 943         ahd->chip = AHD_AIC7902;
 944         ahd->features = AHD_AIC7902_FE;
 945         return (ahd_aic790X_setup(ahd));
 946 }
 947
 948 static int
 949 ahd_aic790X_setup(struct ahd_softc *ahd)
 950 {
 951         aic_dev_softc_t pci;
 952         u_int rev;
 953
 954         pci = ahd->dev_softc;
 955         rev = aic_pci_read_config(pci, PCIR_REVID, /*bytes*/1);
 956         if (rev < ID_AIC7902_PCI_REV_A4) {
 957                 kprintf("%s: Unable to attach to unsupported chip revision %d\n",
 958                        ahd_name(ahd), rev);
 959                 aic_pci_write_config(pci, PCIR_COMMAND, 0, /*bytes*/2);
 960                 return (ENXIO);
 961         }
 962         ahd->channel = aic_get_pci_function(pci) + 'A';
 963         if (rev < ID_AIC7902_PCI_REV_B0) {
 964                 /*
 965                  * Enable A series workarounds.
 966                  */
 967                 ahd->bugs |= AHD_SENT_SCB_UPDATE_BUG|AHD_ABORT_LQI_BUG
 968                           |  AHD_PKT_BITBUCKET_BUG|AHD_LONG_SETIMO_BUG
 969                           |  AHD_NLQICRC_DELAYED_BUG|AHD_SCSIRST_BUG
 970                           |  AHD_LQO_ATNO_BUG|AHD_AUTOFLUSH_BUG
 971                           |  AHD_CLRLQO_AUTOCLR_BUG|AHD_PCIX_MMAPIO_BUG
 972                           |  AHD_PCIX_CHIPRST_BUG|AHD_PCIX_SCBRAM_RD_BUG
 973                           |  AHD_PKTIZED_STATUS_BUG|AHD_PKT_LUN_BUG
 974                           |  AHD_MDFF_WSCBPTR_BUG|AHD_REG_SLOW_SETTLE_BUG
 975                           |  AHD_SET_MODE_BUG|AHD_BUSFREEREV_BUG
 976                           |  AHD_NONPACKFIFO_BUG|AHD_PACED_NEGTABLE_BUG
 977                           |  AHD_FAINT_LED_BUG;
 978
 979                 /*
 980                  * IO Cell paramter setup.
 981                  */
 982                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
 983
 984                 if ((ahd->flags & AHD_HP_BOARD) == 0)
 985                         AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVA);
 986         } else {
 987                 u_int devconfig1;
 988
 989                 ahd->features |= AHD_RTI|AHD_NEW_IOCELL_OPTS
 990                               |  AHD_NEW_DFCNTRL_OPTS|AHD_FAST_CDB_DELIVERY;
 991                 ahd->bugs |= AHD_LQOOVERRUN_BUG|AHD_EARLY_REQ_BUG;
 992
 993                 /*
 994                  * Some issues have been resolved in the 7901B.
 995                  */
 996                 if ((ahd->features & AHD_MULTI_FUNC) != 0)
 997                         ahd->bugs |= AHD_INTCOLLISION_BUG|AHD_ABORT_LQI_BUG;
 998
 999                 /*
1000                  * IO Cell paramter setup.
1001                  */
1002                 AHD_SET_PRECOMP(ahd, AHD_PRECOMP_CUTBACK_29);
1003                 AHD_SET_SLEWRATE(ahd, AHD_SLEWRATE_DEF_REVB);
1004                 AHD_SET_AMPLITUDE(ahd, AHD_AMPLITUDE_DEF);
1005
1006                 /*
1007                  * Set the PREQDIS bit for H2B which disables some workaround
1008                  * that doesn't work on regular PCI busses.
1009                  * XXX - Find out exactly what this does from the hardware
1010                  *       folks!
1011                  */
1012                 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1013                 aic_pci_write_config(pci, DEVCONFIG1,
1014                                      devconfig1|PREQDIS, /*bytes*/1);
1015                 devconfig1 = aic_pci_read_config(pci, DEVCONFIG1, /*bytes*/1);
1016         }
1017
1018         return (0);
1019 }