2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/module.h>
38 #include <sys/malloc.h>
39 #include <sys/devicestat.h>
40 #include <sys/sysctl.h>
42 #include <sys/machintr.h>
44 #include <machine/stdarg.h>
45 #include <machine/clock.h>
47 #include <bus/pci/pcivar.h>
48 #include <bus/pci/pcireg.h>
51 /* device structures */
52 struct ata_pci_controller {
53 struct resource *bmio;
60 #define IOMASK 0xfffffffc
61 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
62 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
63 (pci_get_progif(dev) & 0x05) != 0x05)
66 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
71 if (device_get_children(device_get_parent(dev), &children, &nchildren))
74 for (i = 0; i < nchildren; i++) {
75 if (pci_get_devid(children[i]) == devid &&
76 pci_get_revid(children[i]) >= revid) {
77 kfree(children, M_TEMP);
81 kfree(children, M_TEMP);
86 ata_via_southbridge_fixup(device_t dev)
91 if (device_get_children(device_get_parent(dev), &children, &nchildren))
94 for (i = 0; i < nchildren; i++) {
95 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
96 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
97 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
98 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
99 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
101 if ((reg76 & 0xf0) != 0xd0) {
103 "Correcting VIA config for southbridge data corruption bug\n");
104 pci_write_config(children[i], 0x75, 0x80, 1);
105 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
110 kfree(children, M_TEMP);
114 ata_pci_match(device_t dev)
116 if (pci_get_class(dev) != PCIC_STORAGE)
119 switch (pci_get_devid(dev)) {
120 /* supported chipsets */
122 return "Intel PIIX ATA controller";
125 return "Intel PIIX3 ATA controller";
130 return "Intel PIIX4 ATA33 controller";
133 return "Intel ICH0 ATA33 controller";
137 return "Intel ICH ATA66 controller";
141 return "Intel ICH2 ATA100 controller";
145 return "Intel ICH3 ATA100 controller";
149 return "Intel ICH4 ATA100 controller";
152 return "Intel ICH5 SATA150 controller";
155 return "Intel ICH5 ATA100 controller";
159 return "Intel ICH6 SATA300 controller";
162 return "Intel ICH6/W SATA150 controller";
165 return "Intel ICH6R/RW SATA150 controller";
168 return "Intel ICH6M SATA150 controller";
171 return "Intel ICH6R/RW ATA100 controller";
174 return "Intel ICH7 ATA controller";
177 return "Intel ICH7M SATA controller";
180 if (pci_get_revid(dev) >= 0xc4)
181 return "AcerLabs Aladdin ATA100 controller";
182 else if (pci_get_revid(dev) >= 0xc2)
183 return "AcerLabs Aladdin ATA66 controller";
184 else if (pci_get_revid(dev) >= 0x20)
185 return "AcerLabs Aladdin ATA33 controller";
187 return "AcerLabs Aladdin ATA controller";
190 if (ata_find_dev(dev, 0x05861106, 0x02))
191 return "VIA 82C586 ATA33 controller";
192 if (ata_find_dev(dev, 0x05861106, 0))
193 return "VIA 82C586 ATA controller";
194 if (ata_find_dev(dev, 0x05961106, 0x12))
195 return "VIA 82C596 ATA66 controller";
196 if (ata_find_dev(dev, 0x05961106, 0))
197 return "VIA 82C596 ATA33 controller";
198 if (ata_find_dev(dev, 0x06861106, 0x40))
199 return "VIA 82C686 ATA100 controller";
200 if (ata_find_dev(dev, 0x06861106, 0x10))
201 return "VIA 82C686 ATA66 controller";
202 if (ata_find_dev(dev, 0x06861106, 0))
203 return "VIA 82C686 ATA33 controller";
204 if (ata_find_dev(dev, 0x82311106, 0))
205 return "VIA 8231 ATA100 controller";
206 if (ata_find_dev(dev, 0x30741106, 0) ||
207 ata_find_dev(dev, 0x31091106, 0))
208 return "VIA 8233 ATA100 controller";
209 if (ata_find_dev(dev, 0x31471106, 0))
210 return "VIA 8233 ATA133 controller";
211 if (ata_find_dev(dev, 0x31771106, 0))
212 return "VIA 8235 ATA133 controller";
213 if (ata_find_dev(dev, 0x31491106, 0))
214 return "VIA 8237 ATA133 controller";
215 return "VIA Apollo ATA controller";
218 return "VIA 8237 SATA 150 controller";
221 if (ata_find_dev(dev, 0x07461039, 0))
222 return "SiS 5591 ATA133 controller";
223 if (ata_find_dev(dev, 0x06301039, 0x30) ||
224 ata_find_dev(dev, 0x06331039, 0) ||
225 ata_find_dev(dev, 0x06351039, 0) ||
226 ata_find_dev(dev, 0x06401039, 0) ||
227 ata_find_dev(dev, 0x06451039, 0) ||
228 ata_find_dev(dev, 0x06461039, 0) ||
229 ata_find_dev(dev, 0x06481039, 0) ||
230 ata_find_dev(dev, 0x06501039, 0) ||
231 ata_find_dev(dev, 0x07301039, 0) ||
232 ata_find_dev(dev, 0x07331039, 0) ||
233 ata_find_dev(dev, 0x07351039, 0) ||
234 ata_find_dev(dev, 0x07401039, 0) ||
235 ata_find_dev(dev, 0x07451039, 0) ||
236 ata_find_dev(dev, 0x07501039, 0))
237 return "SiS 5591 ATA100 controller";
238 else if (ata_find_dev(dev, 0x05301039, 0) ||
239 ata_find_dev(dev, 0x05401039, 0) ||
240 ata_find_dev(dev, 0x06201039, 0) ||
241 ata_find_dev(dev, 0x06301039, 0))
242 return "SiS 5591 ATA66 controller";
244 return "SiS 5591 ATA33 controller";
247 return "SiI 3512 SATA controller";
250 return "SiI 3112 SATA controller";
253 return "SiI 3114 SATA controller";
256 return "SiI 3124 SATA controller";
259 return "SiI 0680 ATA133 controller";
262 return "CMD 649 ATA100 controller";
265 return "CMD 648 ATA66 controller";
268 return "CMD 646 ATA controller";
271 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
272 return "Cypress 82C693 ATA controller";
276 return "Cyrix 5530 ATA33 controller";
279 return "AMD 756 ATA66 controller";
282 return "AMD 766 ATA100 controller";
285 return "AMD 768 ATA100 controller";
288 return "AMD 8111 UltraATA/133 controller";
291 return "nVIDIA nForce1 ATA100 controller";
294 return "nVIDIA nForce2 ATA133 controller";
297 return "nVIDIA nForce3 ATA133 controller";
300 return "nVIDIA nForce3 PRO S1 controller";
303 return "nVIDIA nForce3 PRO controller";
306 return "ServerWorks ROSB4 ATA33 controller";
309 if (pci_get_revid(dev) >= 0x92)
310 return "ServerWorks CSB5 ATA100 controller";
312 return "ServerWorks CSB5 ATA66 controller";
315 return "ServerWorks CSB6 ATA100 controller (channel 0+1)";
318 return "ServerWorks CSB6 ATA66 controller (channel 2)";
321 return "Promise ATA33 controller";
325 return "Promise ATA66 controller";
329 return "Promise ATA100 controller";
333 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
334 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
335 static long start = 0, end = 0;
337 /* we belive we are on a TX4, now do our (simple) magic */
338 if (pci_get_slot(dev) == 1) {
339 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
340 return "Promise TX4 ATA100 controller (channel 0+1)";
342 else if (pci_get_slot(dev) == 2 && start && end) {
343 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end,
344 machintr_intr_cpuid(start));
346 return "Promise TX4 ATA100 controller (channel 2+3)";
351 return "Promise TX2 ATA100 controller";
357 return "Promise TX2 ATA133 controller";
360 switch (pci_get_revid(dev)) {
363 return "HighPoint HPT366 ATA66 controller";
365 return "HighPoint HPT368 ATA66 controller";
368 return "HighPoint HPT370 ATA100 controller";
370 return "HighPoint HPT372 ATA133 controller";
375 switch (pci_get_revid(dev)) {
378 return "HighPoint HPT372 ATA133 controller";
383 switch (pci_get_revid(dev)) {
385 return "HighPoint HPT374 ATA133 controller";
390 return "Cenatek Rocket Drive controller";
392 /* unsupported but known chipsets, generic DMA only */
395 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
398 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
400 /* unknown chipsets, try generic DMA if it seems possible */
402 if (pci_get_class(dev) == PCIC_STORAGE &&
403 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
404 return "Generic PCI ATA controller";
410 ata_pci_probe(device_t dev)
412 const char *desc = ata_pci_match(dev);
415 device_set_desc(dev, desc);
416 device_set_async_attach(dev, TRUE);
424 ata_pci_add_child(device_t dev, int unit)
428 /* check if this is located at one of the std addresses */
429 if (ATA_MASTERDEV(dev)) {
430 if (!(child = device_add_child(dev, "ata", unit)))
434 if (!(child = device_add_child(dev, "ata", 2)))
441 ata_pci_attach(device_t dev)
443 struct ata_pci_controller *controller = device_get_softc(dev);
444 u_int8_t class, subclass;
449 /* set up vendor-specific stuff */
450 type = pci_get_devid(dev);
451 class = pci_get_class(dev);
452 subclass = pci_get_subclass(dev);
453 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
455 if (!(cmd & PCIM_CMD_PORTEN)) {
456 device_printf(dev, "ATA channel disabled by BIOS\n");
460 /* is busmastering supported ? */
461 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
462 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
464 /* is there a valid port range to connect to ? */
466 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
467 0, ~0, 1, RF_ACTIVE);
468 if (!controller->bmio)
469 device_printf(dev, "Busmastering DMA not configured\n");
472 device_printf(dev, "Busmastering DMA not supported\n");
474 /* do extra chipset specific setups */
478 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
479 pci_write_config(dev, 0x53,
480 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
483 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
486 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
489 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
490 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
493 case 0x00041103: /* HighPoint HPT366/368/370/372 */
494 if (pci_get_revid(dev) < 2) { /* HPT 366 */
495 /* turn off interrupt prediction */
496 pci_write_config(dev, 0x51,
497 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
500 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
501 /* turn off interrupt prediction */
502 pci_write_config(dev, 0x51,
503 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
504 pci_write_config(dev, 0x55,
505 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
507 /* turn on interrupts */
508 pci_write_config(dev, 0x5a,
509 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
512 pci_write_config(dev, 0x5b, 0x22, 1);
517 case 0x00051103: /* HighPoint HPT372 */
518 case 0x00081103: /* HighPoint HPT374 */
519 /* turn off interrupt prediction */
520 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
521 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
523 /* turn on interrupts */
524 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
527 pci_write_config(dev, 0x5b,
528 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
531 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
532 /* prepare for ATA-66 on the 82C686a and 82C596b */
533 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
534 !ata_find_dev(dev, 0x06861106, 0x40)) ||
535 ata_find_dev(dev, 0x05961106, 0x12))
536 pci_write_config(dev, 0x50, 0x030b030b, 4);
538 /* the southbridge might need the data corruption fix */
539 if (ata_find_dev(dev, 0x06861106, 0x40) ||
540 ata_find_dev(dev, 0x82311106, 0x10))
541 ata_via_southbridge_fixup(dev);
543 /* set fifo configuration half'n'half */
544 pci_write_config(dev, 0x43,
545 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
547 /* set status register read retry */
548 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
550 /* set DMA read & end-of-sector fifo flush */
551 pci_write_config(dev, 0x46,
552 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
554 /* set sector size */
555 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
556 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
558 case 0x74111022: /* AMD 766 default setup */
559 flags = 1; /* bugged */
561 case 0x74091022: /* AMD 756 default setup */
562 case 0x74411022: /* AMD 768 default setup */
563 case 0x746d1022: /* AMD 8111 default setup */
565 pci_write_config(dev, 0x41,
566 pci_read_config(dev, 0x41, 1) & 0x0f, 1);
568 pci_write_config(dev, 0x41,
569 pci_read_config(dev, 0x41, 1) | 0xf0, 1);
572 case 0x01bc10de: /* NVIDIA nForce1 default setup */
573 case 0x006510de: /* NVIDIA nForce2 default setup */
576 case 0x00d510de: /* NVIDIA nForce3 default setup */
578 pci_write_config(dev, 0x51,
579 pci_read_config(dev, 0x51, 1) & 0x0f, 1);
581 pci_write_config(dev, 0x51,
582 pci_read_config(dev, 0x51, 1) | 0xf0, 1);
586 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
587 pci_write_config(dev, 0x64,
588 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
592 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
593 pci_write_config(dev, 0x5a,
594 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
595 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
598 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
599 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
600 pci_write_config(dev, 0x8a,
601 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
602 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
603 device_printf(dev, "SiI 0680 could not set clock\n");
608 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
609 pci_write_config(dev, 0x71, 0x01, 1);
612 case 0x10001042: /* RZ 100? known bad, no DMA */
614 case 0x06401095: /* CMD 640 known bad, no DMA */
615 controller->bmio = NULL;
616 device_printf(dev, "Busmastering DMA disabled\n");
619 if (controller->bmio) {
620 controller->bmaddr = rman_get_start(controller->bmio);
621 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
622 SYS_RES_IOPORT, rid, controller->bmio);
623 controller->bmio = NULL;
627 * the Cypress chip is a mess, it contains two ATA functions, but
628 * both channels are visible on the first one.
629 * simply ignore the second function for now, as the right
630 * solution (ignoring the second channel on the first function)
631 * doesn't work with the crappy ATA interrupt setup on the alpha.
633 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
636 ata_pci_add_child(dev, 0);
638 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
639 ata_pci_add_child(dev, 1);
641 return bus_generic_attach(dev);
645 ata_pci_intr(struct ata_channel *ch)
650 * since we might share the IRQ with another device, and in some
651 * cases with our twin channel, we only want to process interrupts
652 * that we know this channel generated.
654 switch (ch->chiptype) {
655 case 0x00041103: /* HighPoint HPT366/368/370/372 */
656 case 0x00051103: /* HighPoint HPT372 */
657 case 0x00081103: /* HighPoint HPT374 */
658 if (((dmastat = ata_dmastatus(ch)) &
659 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
661 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
665 case 0x06481095: /* CMD 648 */
666 case 0x06491095: /* CMD 649 */
667 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
668 (ch->unit ? 0x08 : 0x04)))
670 #if !defined(NO_ATANG)
671 pci_write_config(device_get_parent(ch->dev), 0x71,
672 pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
673 ~(ch->unit ? 0x04 : 0x08), 1);
677 case 0x06801095: /* SiI 680 */
678 if (!(pci_read_config(device_get_parent(ch->dev),
679 (ch->unit ? 0xb1 : 0xa1), 1) & 0x08))
683 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
684 case 0x0d38105a: /* Promise Fasttrak 66 */
685 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
686 case 0x0d30105a: /* Promise OEM ATA100 */
687 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
688 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
689 (ch->unit ? 0x00004000 : 0x00000400)))
693 case 0x4d68105a: /* Promise TX2 ATA100 */
694 case 0x6268105a: /* Promise TX2 ATA100 */
695 case 0x4d69105a: /* Promise TX2 ATA133 */
696 case 0x5275105a: /* Promise TX2 ATA133 */
697 case 0x6269105a: /* Promise TX2 ATA133 */
698 case 0x7275105a: /* Promise TX2 ATA133 */
699 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
700 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
704 case 0x24d18086: /* Intel ICH5 SATA150 */
705 case 0x24db8086: /* Intel ICH5 ATA100 */
706 case 0x26518086: /* Intel ICH6 SATA150 */
707 case 0x26528086: /* Intel ICH6R SATA150 */
708 case 0x26808086: /* Intel ICH6R SATA150 */
709 case 0x260e8086: /* Intel ICH6 SATA300 */
710 dmastat = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
711 if ((dmastat & (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) !=
712 ATA_BMSTAT_INTERRUPT)
714 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat &
715 ~(ATA_BMSTAT_DMA_SIMPLEX | ATA_BMSTAT_ERROR));
721 if (ch->flags & ATA_DMA_ACTIVE) {
722 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
724 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
731 ata_pci_print_child(device_t dev, device_t child)
733 struct ata_channel *ch = device_get_softc(child);
736 retval += bus_print_child_header(dev, child);
737 retval += kprintf(": at 0x%lx", rman_get_start(ch->r_io));
739 if (ATA_MASTERDEV(dev))
740 retval += kprintf(" irq %d", 14 + ch->unit);
742 retval += bus_print_child_footer(dev, child);
747 static struct resource *
748 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
749 u_long start, u_long end, u_long count, u_int flags, int cpuid)
751 struct ata_pci_controller *controller = device_get_softc(dev);
752 struct resource *res = NULL;
753 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
756 if (type == SYS_RES_IOPORT) {
759 if (ATA_MASTERDEV(dev)) {
761 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
762 end = start + ATA_IOSIZE - 1;
764 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
765 SYS_RES_IOPORT, &myrid,
766 start, end, count, flags, cpuid);
769 myrid = 0x10 + 8 * unit;
770 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
771 SYS_RES_IOPORT, &myrid,
772 start, end, count, flags, cpuid);
776 case ATA_ALTADDR_RID:
777 if (ATA_MASTERDEV(dev)) {
779 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
780 end = start + ATA_ALTIOSIZE - 1;
781 count = ATA_ALTIOSIZE;
782 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
783 SYS_RES_IOPORT, &myrid,
784 start, end, count, flags, cpuid);
787 myrid = 0x14 + 8 * unit;
788 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
789 SYS_RES_IOPORT, &myrid,
790 start, end, count, flags, cpuid);
792 start = rman_get_start(res) + 2;
793 end = start + ATA_ALTIOSIZE - 1;
794 count = ATA_ALTIOSIZE;
795 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
796 SYS_RES_IOPORT, myrid, res);
797 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
798 SYS_RES_IOPORT, &myrid,
799 start, end, count, flags,
806 if (controller->bmaddr) {
809 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
810 end = start + ATA_BMIOSIZE - 1;
811 count = ATA_BMIOSIZE;
812 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
813 SYS_RES_IOPORT, &myrid,
814 start, end, count, flags, cpuid);
820 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
821 if (ATA_MASTERDEV(dev)) {
822 int irq = (unit == 0 ? 14 : 15);
824 cpuid = machintr_intr_cpuid(irq);
825 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
826 SYS_RES_IRQ, rid, irq, irq, 1, flags,
830 /* primary and secondary channels share interrupt, keep track */
831 if (!controller->irq) {
832 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
834 rid, 0, ~0, 1, flags,
837 controller->irqcnt++;
838 return controller->irq;
845 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
848 struct ata_pci_controller *controller = device_get_softc(dev);
849 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
851 if (type == SYS_RES_IOPORT) {
854 if (ATA_MASTERDEV(dev))
855 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
856 SYS_RES_IOPORT, 0x0, r);
858 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
859 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
862 case ATA_ALTADDR_RID:
863 if (ATA_MASTERDEV(dev))
864 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
865 SYS_RES_IOPORT, 0x0, r);
867 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
868 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
872 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
873 SYS_RES_IOPORT, 0x20, r);
878 if (type == SYS_RES_IRQ) {
879 if (rid != ATA_IRQ_RID)
882 if (ATA_MASTERDEV(dev)) {
883 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
884 SYS_RES_IRQ, rid, r);
887 /* primary and secondary channels share interrupt, keep track */
888 if (--controller->irqcnt)
890 controller->irq = NULL;
891 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
892 SYS_RES_IRQ, rid, r);
899 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
900 int flags, driver_intr_t *intr, void *arg,
901 void **cookiep, lwkt_serialize_t serializer)
903 if (ATA_MASTERDEV(dev)) {
904 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
905 flags, intr, arg, cookiep, serializer);
908 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
909 flags, intr, arg, cookiep, serializer);
913 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
916 if (ATA_MASTERDEV(dev)) {
917 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
920 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
923 static device_method_t ata_pci_methods[] = {
924 /* device interface */
925 DEVMETHOD(device_probe, ata_pci_probe),
926 DEVMETHOD(device_attach, ata_pci_attach),
927 DEVMETHOD(device_shutdown, bus_generic_shutdown),
928 DEVMETHOD(device_suspend, bus_generic_suspend),
929 DEVMETHOD(device_resume, bus_generic_resume),
932 DEVMETHOD(bus_print_child, ata_pci_print_child),
933 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
934 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
935 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
936 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
937 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
938 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
942 static driver_t ata_pci_driver = {
945 sizeof(struct ata_pci_controller),
948 static devclass_t ata_pci_devclass;
950 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, NULL, NULL);
953 ata_pcisub_probe(device_t dev)
955 struct ata_channel *ch = device_get_softc(dev);
959 /* find channel number on this controller */
960 device_get_children(device_get_parent(dev), &children, &count);
961 for (i = 0; i < count; i++) {
962 if (children[i] == dev)
965 kfree(children, M_TEMP);
966 ch->chiptype = pci_get_devid(device_get_parent(dev));
967 ch->intr_func = ata_pci_intr;
968 return ata_probe(dev);
971 static device_method_t ata_pcisub_methods[] = {
972 /* device interface */
973 DEVMETHOD(device_probe, ata_pcisub_probe),
974 DEVMETHOD(device_attach, ata_attach),
975 DEVMETHOD(device_detach, ata_detach),
976 DEVMETHOD(device_resume, ata_resume),
977 DEVMETHOD(device_suspend, ata_suspend),
981 static driver_t ata_pcisub_driver = {
984 sizeof(struct ata_channel),
987 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, NULL, NULL);