1 /* $OpenBSD: if_iwmreg.h,v 1.4 2015/06/15 08:06:11 stsp Exp $ */
4 /******************************************************************************
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
11 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
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18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
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24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
27 * The full GNU General Public License is included in this distribution
28 * in the file called COPYING.
30 * Contact Information:
31 * Intel Linux Wireless <ilw@linux.intel.com>
32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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63 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
65 *****************************************************************************/
66 #ifndef __IF_IWM_REG_H__
67 #define __IF_IWM_REG_H__
69 #define le16_to_cpup(_a_) (le16toh(*(const uint16_t *)(_a_)))
70 #define le32_to_cpup(_a_) (le32toh(*(const uint32_t *)(_a_)))
73 * CSR (control and status registers)
75 * CSR registers are mapped directly into PCI bus space, and are accessible
76 * whenever platform supplies power to device, even when device is in
77 * low power states due to driver-invoked device resets
78 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
80 * Use iwl_write32() and iwl_read32() family to access these registers;
81 * these provide simple PCI bus access, without waking up the MAC.
82 * Do not use iwl_write_direct32() family for these registers;
83 * no need to "grab nic access" via IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
84 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
87 * NOTE: Device does need to be awake in order to read this memory
88 * via IWM_CSR_EEPROM and IWM_CSR_OTP registers
90 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
91 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
92 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
93 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
94 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
95 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
96 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
97 #define IWM_CSR_GP_CNTRL (0x024)
99 /* 2nd byte of IWM_CSR_INT_COALESCING, not accessible via iwl_write32()! */
100 #define IWM_CSR_INT_PERIODIC_REG (0x005)
103 * Hardware revision info
106 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
107 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
108 * 1-0: "Dash" (-) value, as in A-1, etc.
110 #define IWM_CSR_HW_REV (0x028)
113 * EEPROM and OTP (one-time-programmable) memory reads
115 * NOTE: Device must be awake, initialized via apm_ops.init(),
118 #define IWM_CSR_EEPROM_REG (0x02c)
119 #define IWM_CSR_EEPROM_GP (0x030)
120 #define IWM_CSR_OTP_GP_REG (0x034)
122 #define IWM_CSR_GIO_REG (0x03C)
123 #define IWM_CSR_GP_UCODE_REG (0x048)
124 #define IWM_CSR_GP_DRIVER_REG (0x050)
127 * UCODE-DRIVER GP (general purpose) mailbox registers.
128 * SET/CLR registers set/clear bit(s) if "1" is written.
130 #define IWM_CSR_UCODE_DRV_GP1 (0x054)
131 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
132 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
133 #define IWM_CSR_UCODE_DRV_GP2 (0x060)
135 #define IWM_CSR_MBOX_SET_REG (0x088)
136 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20
138 #define IWM_CSR_LED_REG (0x094)
139 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
140 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
143 /* GIO Chicken Bits (PCI Express bus link power management) */
144 #define IWM_CSR_GIO_CHICKEN_BITS (0x100)
146 /* Analog phase-lock-loop configuration */
147 #define IWM_CSR_ANA_PLL_CFG (0x20c)
150 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
151 * "step" determines CCK backoff for txpower calculation. Used for 4965 only.
152 * See also IWM_CSR_HW_REV register.
154 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
155 * 1-0: "Dash" (-) value, as in C-1, etc.
157 #define IWM_CSR_HW_REV_WA_REG (0x22C)
159 #define IWM_CSR_DBG_HPET_MEM_REG (0x240)
160 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
162 /* Bits for IWM_CSR_HW_IF_CONFIG_REG */
163 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
164 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
165 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
166 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
167 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
170 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
172 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
173 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
174 #define IWM_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
175 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
177 #define IWM_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
179 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
180 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
181 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
182 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
183 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
184 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
185 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
187 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
188 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
190 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
191 * acknowledged (reset) by host writing "1" to flagged bits. */
192 #define IWM_CSR_INT_BIT_FH_RX (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
193 #define IWM_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
194 #define IWM_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
195 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
196 #define IWM_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
197 #define IWM_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
198 #define IWM_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
199 #define IWM_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
200 #define IWM_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
201 #define IWM_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
202 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
204 #define IWM_CSR_INI_SET_MASK (IWM_CSR_INT_BIT_FH_RX | \
205 IWM_CSR_INT_BIT_HW_ERR | \
206 IWM_CSR_INT_BIT_FH_TX | \
207 IWM_CSR_INT_BIT_SW_ERR | \
208 IWM_CSR_INT_BIT_RF_KILL | \
209 IWM_CSR_INT_BIT_SW_RX | \
210 IWM_CSR_INT_BIT_WAKEUP | \
211 IWM_CSR_INT_BIT_ALIVE | \
212 IWM_CSR_INT_BIT_RX_PERIODIC)
214 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
215 #define IWM_CSR_FH_INT_BIT_ERR (1 << 31) /* Error */
216 #define IWM_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
217 #define IWM_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
218 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
219 #define IWM_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
220 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
222 #define IWM_CSR_FH_INT_RX_MASK (IWM_CSR_FH_INT_BIT_HI_PRIOR | \
223 IWM_CSR_FH_INT_BIT_RX_CHNL1 | \
224 IWM_CSR_FH_INT_BIT_RX_CHNL0)
226 #define IWM_CSR_FH_INT_TX_MASK (IWM_CSR_FH_INT_BIT_TX_CHNL1 | \
227 IWM_CSR_FH_INT_BIT_TX_CHNL0)
230 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
231 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
232 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
235 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
236 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
237 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
238 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
239 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
240 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
243 * GP (general purpose) CONTROL REGISTER
246 * Indicates state of (platform's) hardware RF-Kill switch
247 * 26-24: POWER_SAVE_TYPE
248 * Indicates current power-saving mode:
249 * 000 -- No power saving
250 * 001 -- MAC power-down
251 * 010 -- PHY (radio) power-down
254 * Indicates current system configuration, reflecting pins on chip
255 * as forced high/low by device circuit board.
257 * Indicates MAC is entering a power-saving sleep power-down.
258 * Not a good time to access device-internal resources.
260 * Host sets this to request and maintain MAC wakeup, to allow host
261 * access to device-internal resources. Host must wait for
262 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
265 * Host sets this to put device into fully operational D0 power mode.
266 * Host resets this after SW_RESET to put device into low power mode.
268 * Indicates MAC (ucode processor, etc.) is powered up and can run.
269 * Internal resources are accessible.
270 * NOTE: This does not indicate that the processor is actually running.
271 * NOTE: This does not indicate that device has completed
272 * init or post-power-down restore of internal SRAM memory.
273 * Use IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
274 * SRAM is restored and uCode is in normal operation mode.
275 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
276 * do not need to save/restore it.
277 * NOTE: After device reset, this bit remains "0" until host sets
280 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
281 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
282 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
283 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
285 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
287 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
288 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
289 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
293 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
294 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
296 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
297 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
298 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
299 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
300 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
301 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
302 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
303 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
304 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
305 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
306 #define IWM_CSR_HW_REV_TYPE_6x30 IWM_CSR_HW_REV_TYPE_6x05
307 #define IWM_CSR_HW_REV_TYPE_6x35 IWM_CSR_HW_REV_TYPE_6x05
308 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
309 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
310 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
311 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
312 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210)
313 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
316 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
317 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
318 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
319 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
322 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
323 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
324 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
325 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
326 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
327 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
329 /* One-time-programmable memory general purpose reg */
330 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
331 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
332 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
333 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
336 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
337 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
338 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
339 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
340 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
344 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
347 * UCODE-DRIVER GP (general purpose) mailbox register 1
348 * Host driver and uCode write and/or read this register to communicate with
352 * Host sets this to request permanent halt of uCode, same as
353 * sending CARD_STATE command with "halt" bit set.
355 * Host sets this to request exit from CT_KILL state, i.e. host thinks
356 * device temperature is low enough to continue normal operation.
358 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
359 * to release uCode to clear all Tx and command queues, enter
360 * unassociated mode, and power down.
361 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
363 * Host sets this when issuing CARD_STATE command to request
366 * uCode sets this when preparing a power-saving power-down.
367 * uCode resets this when power-up is complete and SRAM is sane.
368 * NOTE: device saves internal SRAM data to host when powering down,
369 * and must restore this data after powering back up.
370 * MAC_SLEEP is the best indication that restore is complete.
371 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
372 * do not need to save/restore it.
374 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
375 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
376 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
377 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
378 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
381 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
382 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
383 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
384 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
385 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
386 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
388 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
390 /* GIO Chicken Bits (PCI Express bus link power management) */
391 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
392 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
395 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
396 #define IWM_CSR_LED_REG_TURN_ON (0x60)
397 #define IWM_CSR_LED_REG_TURN_OFF (0x20)
400 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
403 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
406 #define IWM_CSR_DRAM_INT_TBL_ENABLE (1 << 31)
407 #define IWM_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
408 #define IWM_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
410 /* SECURE boot registers */
411 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
412 enum iwm_secure_boot_config_reg {
413 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP = 0x00000001,
414 IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ = 0x00000002,
417 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
418 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
419 enum iwm_secure_boot_status_reg {
420 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS = 0x00000003,
421 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED = 0x00000002,
422 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS = 0x00000004,
423 IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL = 0x00000008,
424 IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL = 0x00000010,
427 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0
428 #define IWM_CSR_UCODE_LOAD_STATUS_ADDR 0x1e70
429 enum iwm_secure_load_status_reg {
430 IWM_LMPM_CPU_UCODE_LOADING_STARTED = 0x00000001,
431 IWM_LMPM_CPU_HDRS_LOADING_COMPLETED = 0x00000003,
432 IWM_LMPM_CPU_UCODE_LOADING_COMPLETED = 0x00000007,
433 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_COMPLETED = 0x000000F8,
434 IWM_LMPM_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK = 0x0000FF00,
436 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
438 #define IWM_LMPM_SECURE_INSPECTOR_CODE_ADDR 0x1e38
439 #define IWM_LMPM_SECURE_INSPECTOR_DATA_ADDR 0x1e3c
440 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
441 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
443 #define IWM_LMPM_SECURE_INSPECTOR_CODE_MEM_SPACE 0x400000
444 #define IWM_LMPM_SECURE_INSPECTOR_DATA_MEM_SPACE 0x402000
445 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000
446 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400
448 #define IWM_CSR_SECURE_TIME_OUT (100)
450 /* extended range in FW SRAM */
451 #define IWM_FW_MEM_EXTENDED_START 0x40000
452 #define IWM_FW_MEM_EXTENDED_END 0x57FFF
454 /* FW chicken bits */
455 #define IWM_LMPM_CHICK 0xa01ff8
456 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
458 #define IWM_FH_TCSR_0_REG0 (0x1D00)
461 * HBUS (Host-side Bus)
463 * HBUS registers are mapped directly into PCI bus space, but are used
464 * to indirectly access device's internal memory or registers that
465 * may be powered-down.
467 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
468 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
469 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
470 * internal resources.
472 * Do not use iwl_write32()/iwl_read32() family to access these registers;
473 * these provide only simple PCI bus access, without waking up the MAC.
475 #define IWM_HBUS_BASE (0x400)
478 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
479 * structures, error log, event log, verifying uCode load).
480 * First write to address register, then read from or write to data register
481 * to complete the job. Once the address register is set up, accesses to
482 * data registers auto-increment the address by one dword.
483 * Bit usage for address registers (read or write):
484 * 0-31: memory address within device
486 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
487 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
488 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
489 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
491 /* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
492 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
493 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
496 * Registers for accessing device's internal peripheral registers
497 * (e.g. SCD, BSM, etc.). First write to address register,
498 * then read from or write to data register to complete the job.
499 * Bit usage for address registers (read or write):
500 * 0-15: register address (offset) within device
501 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
503 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
504 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
505 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
506 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
508 /* enable the ID buf for read */
509 #define IWM_WFPM_PS_CTL_CLR 0xa0300c
510 #define IWM_WFMP_MAC_ADDR_0 0xa03080
511 #define IWM_WFMP_MAC_ADDR_1 0xa03084
512 #define IWM_LMPM_PMG_EN 0xa01cec
513 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078
514 #define IWM_RFIC_REG_RD 0xad0470
515 #define IWM_WFPM_CTRL_REG 0xa03030
516 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000
517 #define IWM_ENABLE_WFPM 0x80000000
519 #define IWM_AUX_MISC_REG 0xa200b0
520 #define IWM_HW_STEP_LOCATION_BITS 24
522 #define IWM_AUX_MISC_MASTER1_EN 0xa20818
523 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
524 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
525 #define IWM_RSA_ENABLE 0xa24b08
526 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
527 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
528 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
529 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
530 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088
531 #define IWM_SB_CPU_1_STATUS 0xa01e30
532 #define IWM_SB_CPU_2_STATUS 0Xa01e34
534 /* Used to enable DBGM */
535 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
538 * Per-Tx-queue write pointer (index, really!)
539 * Indicates index to next TFD that driver will fill (1 past latest filled).
541 * 0-7: queue write index
542 * 11-8: queue selector
544 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
546 /**********************************************************
548 **********************************************************/
550 * host interrupt timeout value
551 * used with setting interrupt coalescing timer
552 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
554 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
556 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
557 #define IWM_HOST_INT_TIMEOUT_DEF (0x40)
558 #define IWM_HOST_INT_TIMEOUT_MIN (0x0)
559 #define IWM_HOST_INT_OPER_MODE (1 << 31)
561 /*****************************************************************************
562 * 7000/3000 series SHR DTS addresses *
563 *****************************************************************************/
565 /* Diode Results Register Structure: */
566 enum iwm_dtd_diode_reg {
567 IWM_DTS_DIODE_REG_DIG_VAL = 0x000000FF, /* bits [7:0] */
568 IWM_DTS_DIODE_REG_VREF_LOW = 0x0000FF00, /* bits [15:8] */
569 IWM_DTS_DIODE_REG_VREF_HIGH = 0x00FF0000, /* bits [23:16] */
570 IWM_DTS_DIODE_REG_VREF_ID = 0x03000000, /* bits [25:24] */
571 IWM_DTS_DIODE_REG_PASS_ONCE = 0x80000000, /* bits [31:31] */
572 IWM_DTS_DIODE_REG_FLAGS_MSK = 0xFF000000, /* bits [31:24] */
573 /* Those are the masks INSIDE the flags bit-field: */
574 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS = 0,
575 IWM_DTS_DIODE_REG_FLAGS_VREFS_ID = 0x00000003, /* bits [1:0] */
576 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE_POS = 7,
577 IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE = 0x00000080, /* bits [7:7] */
581 * enum iwm_ucode_tlv_flag - ucode API flags
582 * @IWM_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
583 * was a separate TLV but moved here to save space.
584 * @IWM_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
585 * treats good CRC threshold as a boolean
586 * @IWM_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
587 * @IWM_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
588 * @IWM_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
589 * @IWM_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
590 * @IWM_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
591 * offload profile config command.
592 * @IWM_UCODE_TLV_FLAGS_RX_ENERGY_API: supports rx signal strength api
593 * @IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2: using the new time event API.
594 * @IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
595 * (rather than two) IPv6 addresses
596 * @IWM_UCODE_TLV_FLAGS_BF_UPDATED: new beacon filtering API
597 * @IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
598 * from the probe request template.
599 * @IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API: modified D3 API to allow keeping
600 * connection when going back to D0
601 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
602 * @IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
603 * @IWM_UCODE_TLV_FLAGS_SCHED_SCAN: this uCode image supports scheduled scan.
604 * @IWM_UCODE_TLV_FLAGS_STA_KEY_CMD: new ADD_STA and ADD_STA_KEY command API
605 * @IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD: support device wide power command
606 * containing CAM (Continuous Active Mode) indication.
607 * @IWM_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
608 * single bound interface).
609 * @IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
610 * @IWM_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
611 * @IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
612 * @IWM_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
613 * @IWM_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients
616 enum iwm_ucode_tlv_flag {
617 IWM_UCODE_TLV_FLAGS_PAN = (1 << 0),
618 IWM_UCODE_TLV_FLAGS_NEWSCAN = (1 << 1),
619 IWM_UCODE_TLV_FLAGS_MFP = (1 << 2),
620 IWM_UCODE_TLV_FLAGS_P2P = (1 << 3),
621 IWM_UCODE_TLV_FLAGS_DW_BC_TABLE = (1 << 4),
622 IWM_UCODE_TLV_FLAGS_NEWBT_COEX = (1 << 5),
623 IWM_UCODE_TLV_FLAGS_PM_CMD_SUPPORT = (1 << 6),
624 IWM_UCODE_TLV_FLAGS_SHORT_BL = (1 << 7),
625 IWM_UCODE_TLV_FLAGS_RX_ENERGY_API = (1 << 8),
626 IWM_UCODE_TLV_FLAGS_TIME_EVENT_API_V2 = (1 << 9),
627 IWM_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS = (1 << 10),
628 IWM_UCODE_TLV_FLAGS_BF_UPDATED = (1 << 11),
629 IWM_UCODE_TLV_FLAGS_NO_BASIC_SSID = (1 << 12),
630 IWM_UCODE_TLV_FLAGS_D3_CONTINUITY_API = (1 << 14),
631 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL = (1 << 15),
632 IWM_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE = (1 << 16),
633 IWM_UCODE_TLV_FLAGS_SCHED_SCAN = (1 << 17),
634 IWM_UCODE_TLV_FLAGS_STA_KEY_CMD = (1 << 19),
635 IWM_UCODE_TLV_FLAGS_DEVICE_PS_CMD = (1 << 20),
636 IWM_UCODE_TLV_FLAGS_P2P_PS = (1 << 21),
637 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM = (1 << 22),
638 IWM_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM = (1 << 23),
639 IWM_UCODE_TLV_FLAGS_UAPSD_SUPPORT = (1 << 24),
640 IWM_UCODE_TLV_FLAGS_EBS_SUPPORT = (1 << 25),
641 IWM_UCODE_TLV_FLAGS_P2P_PS_UAPSD = (1 << 26),
642 IWM_UCODE_TLV_FLAGS_BCAST_FILTERING = (1 << 29),
643 IWM_UCODE_TLV_FLAGS_GO_UAPSD = (1 << 30),
644 IWM_UCODE_TLV_FLAGS_LTE_COEX = (1 << 31),
647 #define IWM_UCODE_TLV_FLAG_BITS \
648 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERG \
649 Y\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFF \
650 L_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30 \
651 P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
654 * enum iwm_ucode_tlv_api - ucode api
655 * @IWM_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
656 * longer than the passive one, which is essential for fragmented scan.
657 * @IWM_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
658 * @IWM_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header
659 * @IWM_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
660 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority
662 * @IWM_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size
663 * (command version 3) that supports per-chain limits
665 * @IWM_NUM_UCODE_TLV_API: number of bits used
667 enum iwm_ucode_tlv_api {
668 IWM_UCODE_TLV_API_FRAGMENTED_SCAN = (1 << 8),
669 IWM_UCODE_TLV_API_WIFI_MCC_UPDATE = (1 << 9),
670 IWM_UCODE_TLV_API_WIDE_CMD_HDR = (1 << 14),
671 IWM_UCODE_TLV_API_LQ_SS_PARAMS = (1 << 18),
672 IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY = (1 << 24),
673 IWM_UCODE_TLV_API_TX_POWER_CHAIN = (1 << 27),
675 IWM_NUM_UCODE_TLV_API = 32
678 #define IWM_UCODE_TLV_API_BITS \
679 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN"
682 * enum iwm_ucode_tlv_capa - ucode capabilities
683 * @IWM_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
684 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
685 * @IWM_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
686 * @IWM_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
687 * @IWM_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
688 * @IWM_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
689 * @IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
690 * tx power value into TPC Report action frame and Link Measurement Report
692 * @IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
693 * channel in DS parameter set element in probe requests.
694 * @IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
696 * @IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
697 * @IWM_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
698 * which also implies support for the scheduler configuration command
699 * @IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
700 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
701 * @IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
702 * @IWM_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
703 * @IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command
704 * @IWM_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
705 * @IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
706 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD
707 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
708 * @IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
709 * sources for the MCC. This TLV bit is a future replacement to
710 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
712 * @IWM_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
713 * @IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan
714 * @IWM_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN
715 * @IWM_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported,
717 * @IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
718 * @IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
719 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
720 * @IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
721 * antenna the beacon should be transmitted
722 * @IWM_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
723 * from AP and will send it upon d0i3 exit.
724 * @IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2
725 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
726 * @IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
727 * thresholds reporting
728 * @IWM_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
729 * @IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
731 * @IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
732 * memory addresses from the firmware.
733 * @IWM_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
734 * @IWM_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported,
737 * @IWM_NUM_UCODE_TLV_CAPA: number of bits used
739 enum iwm_ucode_tlv_capa {
740 IWM_UCODE_TLV_CAPA_D0I3_SUPPORT = 0,
741 IWM_UCODE_TLV_CAPA_LAR_SUPPORT = 1,
742 IWM_UCODE_TLV_CAPA_UMAC_SCAN = 2,
743 IWM_UCODE_TLV_CAPA_BEAMFORMER = 3,
744 IWM_UCODE_TLV_CAPA_TOF_SUPPORT = 5,
745 IWM_UCODE_TLV_CAPA_TDLS_SUPPORT = 6,
746 IWM_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT = 8,
747 IWM_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT = 9,
748 IWM_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT = 10,
749 IWM_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT = 11,
750 IWM_UCODE_TLV_CAPA_DQA_SUPPORT = 12,
751 IWM_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH = 13,
752 IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG = 17,
753 IWM_UCODE_TLV_CAPA_HOTSPOT_SUPPORT = 18,
754 IWM_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT = 19,
755 IWM_UCODE_TLV_CAPA_2G_COEX_SUPPORT = 20,
756 IWM_UCODE_TLV_CAPA_CSUM_SUPPORT = 21,
757 IWM_UCODE_TLV_CAPA_RADIO_BEACON_STATS = 22,
758 IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD = 26,
759 IWM_UCODE_TLV_CAPA_BT_COEX_PLCR = 28,
760 IWM_UCODE_TLV_CAPA_LAR_MULTI_MCC = 29,
761 IWM_UCODE_TLV_CAPA_BT_COEX_RRC = 30,
762 IWM_UCODE_TLV_CAPA_GSCAN_SUPPORT = 31,
763 IWM_UCODE_TLV_CAPA_NAN_SUPPORT = 34,
764 IWM_UCODE_TLV_CAPA_UMAC_UPLOAD = 35,
765 IWM_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE = 64,
766 IWM_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS = 65,
767 IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT = 67,
768 IWM_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT = 68,
769 IWM_UCODE_TLV_CAPA_BEACON_ANT_SELECTION = 71,
770 IWM_UCODE_TLV_CAPA_BEACON_STORING = 72,
771 IWM_UCODE_TLV_CAPA_LAR_SUPPORT_V2 = 73,
772 IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW = 74,
773 IWM_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT = 75,
774 IWM_UCODE_TLV_CAPA_CTDP_SUPPORT = 76,
775 IWM_UCODE_TLV_CAPA_USNIFFER_UNIFIED = 77,
776 IWM_UCODE_TLV_CAPA_LMAC_UPLOAD = 79,
777 IWM_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG = 80,
778 IWM_UCODE_TLV_CAPA_LQM_SUPPORT = 81,
780 IWM_NUM_UCODE_TLV_CAPA = 128
783 /* The default calibrate table size if not specified by firmware file */
784 #define IWM_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE 18
785 #define IWM_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE 19
786 #define IWM_MAX_PHY_CALIBRATE_TBL_SIZE 253
788 /* The default max probe length if not specified by the firmware file */
789 #define IWM_DEFAULT_MAX_PROBE_LENGTH 200
792 * enumeration of ucode section.
793 * This enumeration is used directly for older firmware (before 16.0).
794 * For new firmware, there can be up to 4 sections (see below) but the
795 * first one packaged into the firmware file is the DATA section and
796 * some debugging code accesses that.
799 IWM_UCODE_SECTION_DATA,
800 IWM_UCODE_SECTION_INST,
803 * For 16.0 uCode and above, there is no differentiation between sections,
804 * just an offset to the HW address.
806 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
807 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB
809 /* uCode version contains 4 values: Major/Minor/API/Serial */
810 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
811 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
812 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
813 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
816 * Calibration control struct.
817 * Sent as part of the phy configuration command.
818 * @flow_trigger: bitmap for which calibrations to perform according to
820 * @event_trigger: bitmap for which calibrations to perform according to
823 struct iwm_tlv_calib_ctrl {
824 uint32_t flow_trigger;
825 uint32_t event_trigger;
828 enum iwm_fw_phy_cfg {
829 IWM_FW_PHY_CFG_RADIO_TYPE_POS = 0,
830 IWM_FW_PHY_CFG_RADIO_TYPE = 0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS,
831 IWM_FW_PHY_CFG_RADIO_STEP_POS = 2,
832 IWM_FW_PHY_CFG_RADIO_STEP = 0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS,
833 IWM_FW_PHY_CFG_RADIO_DASH_POS = 4,
834 IWM_FW_PHY_CFG_RADIO_DASH = 0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS,
835 IWM_FW_PHY_CFG_TX_CHAIN_POS = 16,
836 IWM_FW_PHY_CFG_TX_CHAIN = 0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS,
837 IWM_FW_PHY_CFG_RX_CHAIN_POS = 20,
838 IWM_FW_PHY_CFG_RX_CHAIN = 0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS,
841 #define IWM_UCODE_MAX_CS 1
844 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
845 * @cipher: a cipher suite selector
846 * @flags: cipher scheme flags (currently reserved for a future use)
847 * @hdr_len: a size of MPDU security header
848 * @pn_len: a size of PN
849 * @pn_off: an offset of pn from the beginning of the security header
850 * @key_idx_off: an offset of key index byte in the security header
851 * @key_idx_mask: a bit mask of key_idx bits
852 * @key_idx_shift: bit shift needed to get key_idx
853 * @mic_len: mic length in bytes
854 * @hw_cipher: a HW cipher index used in host commands
856 struct iwm_fw_cipher_scheme {
863 uint8_t key_idx_mask;
864 uint8_t key_idx_shift;
870 * struct iwm_fw_cscheme_list - a cipher scheme list
871 * @size: a number of entries
872 * @cs: cipher scheme entries
874 struct iwm_fw_cscheme_list {
876 struct iwm_fw_cipher_scheme cs[];
879 /* v1/v2 uCode file layout */
880 struct iwm_ucode_header {
881 uint32_t ver; /* major/minor/API/serial */
884 uint32_t inst_size; /* bytes of runtime code */
885 uint32_t data_size; /* bytes of runtime data */
886 uint32_t init_size; /* bytes of init code */
887 uint32_t init_data_size; /* bytes of init data */
888 uint32_t boot_size; /* bytes of bootstrap code */
889 uint8_t data[0]; /* in same order as sizes */
892 uint32_t build; /* build number */
893 uint32_t inst_size; /* bytes of runtime code */
894 uint32_t data_size; /* bytes of runtime data */
895 uint32_t init_size; /* bytes of init code */
896 uint32_t init_data_size; /* bytes of init data */
897 uint32_t boot_size; /* bytes of bootstrap code */
898 uint8_t data[0]; /* in same order as sizes */
904 * new TLV uCode file layout
906 * The new TLV file format contains TLVs, that each specify
907 * some piece of data.
910 enum iwm_ucode_tlv_type {
911 IWM_UCODE_TLV_INVALID = 0, /* unused */
912 IWM_UCODE_TLV_INST = 1,
913 IWM_UCODE_TLV_DATA = 2,
914 IWM_UCODE_TLV_INIT = 3,
915 IWM_UCODE_TLV_INIT_DATA = 4,
916 IWM_UCODE_TLV_BOOT = 5,
917 IWM_UCODE_TLV_PROBE_MAX_LEN = 6, /* a uint32_t value */
918 IWM_UCODE_TLV_PAN = 7,
919 IWM_UCODE_TLV_RUNT_EVTLOG_PTR = 8,
920 IWM_UCODE_TLV_RUNT_EVTLOG_SIZE = 9,
921 IWM_UCODE_TLV_RUNT_ERRLOG_PTR = 10,
922 IWM_UCODE_TLV_INIT_EVTLOG_PTR = 11,
923 IWM_UCODE_TLV_INIT_EVTLOG_SIZE = 12,
924 IWM_UCODE_TLV_INIT_ERRLOG_PTR = 13,
925 IWM_UCODE_TLV_ENHANCE_SENS_TBL = 14,
926 IWM_UCODE_TLV_PHY_CALIBRATION_SIZE = 15,
927 IWM_UCODE_TLV_WOWLAN_INST = 16,
928 IWM_UCODE_TLV_WOWLAN_DATA = 17,
929 IWM_UCODE_TLV_FLAGS = 18,
930 IWM_UCODE_TLV_SEC_RT = 19,
931 IWM_UCODE_TLV_SEC_INIT = 20,
932 IWM_UCODE_TLV_SEC_WOWLAN = 21,
933 IWM_UCODE_TLV_DEF_CALIB = 22,
934 IWM_UCODE_TLV_PHY_SKU = 23,
935 IWM_UCODE_TLV_SECURE_SEC_RT = 24,
936 IWM_UCODE_TLV_SECURE_SEC_INIT = 25,
937 IWM_UCODE_TLV_SECURE_SEC_WOWLAN = 26,
938 IWM_UCODE_TLV_NUM_OF_CPU = 27,
939 IWM_UCODE_TLV_CSCHEME = 28,
942 * Following two are not in our base tag, but allow
943 * handling ucode version 9.
945 IWM_UCODE_TLV_API_CHANGES_SET = 29,
946 IWM_UCODE_TLV_ENABLED_CAPABILITIES = 30,
948 IWM_UCODE_TLV_N_SCAN_CHANNELS = 31,
949 IWM_UCODE_TLV_PAGING = 32,
950 IWM_UCODE_TLV_SEC_RT_USNIFFER = 34,
951 IWM_UCODE_TLV_SDIO_ADMA_ADDR = 35,
952 IWM_UCODE_TLV_FW_VERSION = 36,
953 IWM_UCODE_TLV_FW_DBG_DEST = 38,
954 IWM_UCODE_TLV_FW_DBG_CONF = 39,
955 IWM_UCODE_TLV_FW_DBG_TRIGGER = 40,
956 IWM_UCODE_TLV_FW_GSCAN_CAPA = 50,
959 struct iwm_ucode_tlv {
960 uint32_t type; /* see above */
961 uint32_t length; /* not including type/length fields */
965 struct iwm_ucode_api {
970 struct iwm_ucode_capa {
975 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749
977 struct iwm_tlv_ucode_header {
979 * The TLV style ucode header is distinguished from
980 * the v1/v2 style header by first four bytes being
981 * zero, as such is an invalid combination of
982 * major/minor/API/serial versions.
986 uint8_t human_readable[64];
987 uint32_t ver; /* major/minor/API/serial */
991 * The data contained herein has a TLV layout,
992 * see above for the TLV header and types.
993 * Note that each TLV is padded to a length
994 * that is a multiple of 4 for alignment.
1000 * Registers in this file are internal, not PCI bus memory mapped.
1001 * Driver accesses these via IWM_HBUS_TARG_PRPH_* registers.
1003 #define IWM_PRPH_BASE (0x00000)
1004 #define IWM_PRPH_END (0xFFFFF)
1006 /* APMG (power management) constants */
1007 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
1008 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
1009 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
1010 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
1011 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
1012 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
1013 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
1014 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
1015 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
1016 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
1017 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
1019 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
1020 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
1021 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
1023 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
1024 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
1025 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
1026 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
1027 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
1028 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
1029 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
1031 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
1033 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
1035 /* Device system time */
1036 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
1038 /* Device NMI register */
1039 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30
1040 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01
1041 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80
1042 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24
1043 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000
1046 * Device reset for family 8000
1047 * write to bit 24 in order to reset the CPU
1049 #define IWM_RELEASE_CPU_RESET 0x300c
1050 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000
1053 /*****************************************************************************
1054 * 7000/3000 series SHR DTS addresses *
1055 *****************************************************************************/
1057 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
1058 #define IWM_DTSC_CFG_MODE (0x00a10604)
1059 #define IWM_DTSC_VREF_AVG (0x00a10648)
1060 #define IWM_DTSC_VREF5_AVG (0x00a1064c)
1061 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
1062 #define IWM_DTSC_PTAT_AVG (0x00a10650)
1068 * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs
1069 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
1070 * host DRAM. It steers each frame's Tx command (which contains the frame
1071 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1072 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
1073 * but one DMA channel may take input from several queues.
1075 * Tx DMA FIFOs have dedicated purposes.
1077 * For 5000 series and up, they are used differently
1078 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
1080 * 0 -- EDCA BK (background) frames, lowest priority
1081 * 1 -- EDCA BE (best effort) frames, normal priority
1082 * 2 -- EDCA VI (video) frames, higher priority
1083 * 3 -- EDCA VO (voice) and management frames, highest priority
1089 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1090 * In addition, driver can map the remaining queues to Tx DMA/FIFO
1091 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
1093 * The driver sets up each queue to work in one of two modes:
1095 * 1) Scheduler-Ack, in which the scheduler automatically supports a
1096 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1097 * contains TFDs for a unique combination of Recipient Address (RA)
1098 * and Traffic Identifier (TID), that is, traffic of a given
1099 * Quality-Of-Service (QOS) priority, destined for a single station.
1101 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1102 * each frame within the BA window, including whether it's been transmitted,
1103 * and whether it's been acknowledged by the receiving station. The device
1104 * automatically processes block-acks received from the receiving STA,
1105 * and reschedules un-acked frames to be retransmitted (successful
1106 * Tx completion may end up being out-of-order).
1108 * The driver must maintain the queue's Byte Count table in host DRAM
1110 * This mode does not support fragmentation.
1112 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1113 * The device may automatically retry Tx, but will retry only one frame
1114 * at a time, until receiving ACK from receiving station, or reaching
1115 * retry limit and giving up.
1117 * The command queue (#4/#9) must use this mode!
1118 * This mode does not require use of the Byte Count table in host DRAM.
1120 * Driver controls scheduler operation via 3 means:
1121 * 1) Scheduler registers
1122 * 2) Shared scheduler data base in internal SRAM
1123 * 3) Shared data in host DRAM
1127 * When loading, driver should allocate memory for:
1128 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
1129 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
1130 * (1024 bytes for each queue).
1132 * After receiving "Alive" response from uCode, driver must initialize
1133 * the scheduler (especially for queue #4/#9, the command queue, otherwise
1134 * the driver can't issue commands!):
1136 #define IWM_SCD_MEM_LOWER_BOUND (0x0000)
1139 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1140 * can keep track of at one time when creating block-ack chains of frames.
1141 * Note that "64" matches the number of ack bits in a block-ack packet.
1143 #define IWM_SCD_WIN_SIZE 64
1144 #define IWM_SCD_FRAME_LIMIT 64
1146 #define IWM_SCD_TXFIFO_POS_TID (0)
1147 #define IWM_SCD_TXFIFO_POS_RA (4)
1148 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1151 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
1152 #define IWM_SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
1153 #define IWM_SCD_QUEUE_STTS_REG_POS_WSL (4)
1154 #define IWM_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
1155 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
1157 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
1158 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
1159 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
1160 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
1161 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
1162 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
1163 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1164 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1165 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0)
1166 #define IWM_SCD_GP_CTRL_AUTO_ACTIVE_MODE (1 << 18)
1169 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
1170 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1173 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1174 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1176 /* Translation Data */
1177 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1178 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
1180 #define IWM_SCD_CONTEXT_QUEUE_OFFSET(x)\
1181 (IWM_SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
1183 #define IWM_SCD_TX_STTS_QUEUE_OFFSET(x)\
1184 (IWM_SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
1186 #define IWM_SCD_TRANS_TBL_OFFSET_QUEUE(x) \
1187 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
1189 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
1191 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
1192 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
1193 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
1194 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
1195 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
1196 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
1197 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
1198 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
1199 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
1200 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)
1201 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)
1203 static inline unsigned int IWM_SCD_QUEUE_WRPTR(unsigned int chnl)
1206 return IWM_SCD_BASE + 0x18 + chnl * 4;
1207 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1210 static inline unsigned int IWM_SCD_QUEUE_RDPTR(unsigned int chnl)
1213 return IWM_SCD_BASE + 0x68 + chnl * 4;
1214 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4;
1217 static inline unsigned int IWM_SCD_QUEUE_STATUS_BITS(unsigned int chnl)
1220 return IWM_SCD_BASE + 0x10c + chnl * 4;
1221 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4;
1224 /*********************** END TX SCHEDULER *************************************/
1226 /* Oscillator clock */
1227 #define IWM_OSC_CLK (0xa04068)
1228 #define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1230 /****************************/
1231 /* Flow Handler Definitions */
1232 /****************************/
1235 * This I/O area is directly read/writable by driver (e.g. Linux uses writel())
1236 * Addresses are offsets from device's PCI hardware base address.
1238 #define IWM_FH_MEM_LOWER_BOUND (0x1000)
1239 #define IWM_FH_MEM_UPPER_BOUND (0x2000)
1242 * Keep-Warm (KW) buffer base address.
1244 * Driver must allocate a 4KByte buffer that is for keeping the
1245 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1246 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host
1247 * from going into a power-savings mode that would cause higher DRAM latency,
1248 * and possible data over/under-runs, before all Tx/Rx is complete.
1250 * Driver loads IWM_FH_KW_MEM_ADDR_REG with the physical address (bits 35:4)
1251 * of the buffer, which must be 4K aligned. Once this is set up, the device
1252 * automatically invokes keep-warm accesses when normal accesses might not
1253 * be sufficient to maintain fast DRAM response.
1256 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1258 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1262 * TFD Circular Buffers Base (CBBC) addresses
1264 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1265 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs)
1266 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1267 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1268 * aligned (address bits 0-7 must be 0).
1269 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers
1270 * for them are in different places.
1272 * Bit fields in each pointer register:
1273 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1275 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1276 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1277 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1278 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1279 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1280 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1282 /* Find TFD CB base pointer for given queue */
1283 static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
1286 return IWM_FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl;
1288 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1289 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1294 * Rx SRAM Control and Status Registers (RSCSR)
1296 * These registers provide handshake between driver and device for the Rx queue
1297 * (this queue handles *all* command responses, notifications, Rx data, etc.
1298 * sent from uCode to host driver). Unlike Tx, there is only one Rx
1299 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can
1300 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer
1301 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1
1302 * mapping between RBDs and RBs.
1304 * Driver must allocate host DRAM memory for the following, and set the
1305 * physical address of each into device registers:
1307 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256
1308 * entries (although any power of 2, up to 4096, is selectable by driver).
1309 * Each entry (1 dword) points to a receive buffer (RB) of consistent size
1310 * (typically 4K, although 8K or 16K are also selectable by driver).
1311 * Driver sets up RB size and number of RBDs in the CB via Rx config
1312 * register IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG.
1314 * Bit fields within one RBD:
1315 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1317 * Driver sets physical address [35:8] of base of RBD circular buffer
1318 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1320 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers
1321 * (RBs) have been filled, via a "write pointer", actually the index of
1322 * the RB's corresponding RBD within the circular buffer. Driver sets
1323 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1325 * Bit fields in lower dword of Rx status buffer (upper dword not used
1327 * 31-12: Not used by driver
1328 * 11- 0: Index of last filled Rx buffer descriptor
1329 * (device writes, driver reads this value)
1331 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must
1332 * enter pointers to these RBs into contiguous RBD circular buffer entries,
1333 * and update the device's "write" index register,
1334 * IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG.
1336 * This "write" index corresponds to the *next* RBD that the driver will make
1337 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1338 * the circular buffer. This value should initially be 0 (before preparing any
1339 * RBs), should be 8 after preparing the first 8 RBs (for example), and must
1340 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1341 * "read" index has advanced past 1! See below).
1342 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8.
1344 * As the device fills RBs (referenced from contiguous RBDs within the circular
1345 * buffer), it updates the Rx status buffer in host DRAM, 2) described above,
1346 * to tell the driver the index of the latest filled RBD. The driver must
1347 * read this "read" index from DRAM after receiving an Rx interrupt from device
1349 * The driver must also internally keep track of a third index, which is the
1350 * next RBD to process. When receiving an Rx interrupt, driver should process
1351 * all filled but unprocessed RBs up to, but not including, the RB
1352 * corresponding to the "read" index. For example, if "read" index becomes "1",
1353 * driver may process the RB pointed to by RBD 0. Depending on volume of
1354 * traffic, there may be many RBs to process.
1356 * If read index == write index, device thinks there is no room to put new data.
1357 * Due to this, the maximum number of filled RBs is 255, instead of 256. To
1358 * be safe, make sure that there is a gap of at least 2 RBDs between "write"
1359 * and "read" indexes; that is, make sure that there are no more than 254
1360 * buffers waiting to be filled.
1362 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1363 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1364 #define IWM_FH_MEM_RSCSR_CHNL0 (IWM_FH_MEM_RSCSR_LOWER_BOUND)
1367 * Physical base address of 8-byte Rx Status buffer.
1369 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1371 #define IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0)
1374 * Physical base address of Rx Buffer Descriptor Circular Buffer.
1376 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1378 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1381 * Rx write pointer (index, really!).
1383 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1384 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1386 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1387 #define IWM_FH_RSCSR_CHNL0_WPTR (IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
1389 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1390 #define IWM_FH_RSCSR_CHNL0_RDPTR IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG
1393 * Rx Config/Status Registers (RCSR)
1394 * Rx Config Reg for channel 0 (only channel used)
1396 * Driver must initialize IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for
1397 * normal operation (see bit fields).
1399 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1400 * Driver should poll IWM_FH_MEM_RSSR_RX_STATUS_REG for
1401 * IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing.
1404 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1405 * '10' operate normally
1407 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1408 * min "5" for 32 RBDs, max "12" for 4096 RBDs.
1410 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1411 * '10' 12K, '11' 16K.
1413 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1414 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1415 * typical value 0x10 (about 1/2 msec)
1418 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1419 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1420 #define IWM_FH_MEM_RCSR_CHNL0 (IWM_FH_MEM_RCSR_LOWER_BOUND)
1422 #define IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG (IWM_FH_MEM_RCSR_CHNL0)
1423 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1424 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1426 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1427 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1428 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1429 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1430 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1431 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1433 #define IWM_FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1434 #define IWM_FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1435 #define IWM_RX_RB_TIMEOUT (0x11)
1437 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1438 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1439 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1441 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1442 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1443 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1444 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1446 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1447 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1448 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1451 * Rx Shared Status Registers (RSSR)
1453 * After stopping Rx DMA channel (writing 0 to
1454 * IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll
1455 * IWM_FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle.
1458 * 24: 1 = Channel 0 is idle
1460 * IWM_FH_MEM_RSSR_SHARED_CTRL_REG and IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV
1461 * contain default values that should not be altered by the driver.
1463 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1464 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1466 #define IWM_FH_MEM_RSSR_SHARED_CTRL_REG (IWM_FH_MEM_RSSR_LOWER_BOUND)
1467 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1468 #define IWM_FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1469 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1471 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1473 #define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1475 /* TFDB Area - TFDs buffer table */
1476 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1477 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1478 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1479 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1480 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1483 * Transmit DMA Channel Control/Status Registers (TCSR)
1485 * Device has one configuration register for each of 8 Tx DMA/FIFO channels
1486 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM,
1487 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1489 * To use a Tx DMA channel, driver must initialize its
1490 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with:
1492 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
1493 * IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL
1495 * All other bits should be 0.
1498 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1499 * '10' operate normally
1500 * 29- 4: Reserved, set to "0"
1501 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1502 * 2- 0: Reserved, set to "0"
1504 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1505 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1507 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1508 #define IWM_FH_TCSR_CHNL_NUM (8)
1510 /* TCSR: tx_config register values */
1511 #define IWM_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1512 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1513 #define IWM_FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1514 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1515 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1516 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1518 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1519 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1521 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1522 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1524 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1525 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1526 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1528 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1529 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1530 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1532 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1533 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1534 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1536 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1537 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1538 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1540 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1541 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1544 * Tx Shared Status Registers (TSSR)
1546 * After stopping Tx DMA channel (writing 0 to
1547 * IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll
1548 * IWM_FH_TSSR_TX_STATUS_REG until selected Tx channel is idle
1549 * (channel's buffers empty | no pending requests).
1552 * 31-24: 1 = Channel buffers empty (channel 7:0)
1553 * 23-16: 1 = No pending requests (channel 7:0)
1555 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1556 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1558 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1561 * Bit fields for TSSR(Tx Shared Status & Control) error status register:
1562 * 31: Indicates an address error when accessed to internal memory
1563 * uCode/driver must write "1" in order to clear this flag
1564 * 30: Indicates that Host did not send the expected number of dwords to FH
1565 * uCode/driver must write "1" in order to clear this flag
1566 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1567 * command was received from the scheduler while the TRB was already full
1568 * with previous command
1569 * uCode/driver must write "1" in order to clear this flag
1570 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1571 * bit is set, it indicates that the FH has received a full indication
1572 * from the RTC TxFIFO and the current value of the TxCredit counter was
1573 * not equal to zero. This mean that the credit mechanism was not
1574 * synchronized to the TxFIFO status
1575 * uCode/driver must write "1" in order to clear this flag
1577 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1578 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1580 #define IWM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1582 /* Tx service channels */
1583 #define IWM_FH_SRVC_CHNL (9)
1584 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1585 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1586 #define IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1587 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1589 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1590 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1593 /* Instruct FH to increment the retry count of a packet when
1594 * it is brought from the memory to TX-FIFO
1596 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1598 #define IWM_RX_QUEUE_SIZE 256
1599 #define IWM_RX_QUEUE_MASK 255
1600 #define IWM_RX_QUEUE_SIZE_LOG 8
1603 * RX related structures and functions
1605 #define IWM_RX_FREE_BUFFERS 64
1606 #define IWM_RX_LOW_WATERMARK 8
1609 * struct iwm_rb_status - reseve buffer status
1610 * host memory mapped FH registers
1611 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1612 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1613 * @finished_rb_num [0:11] - Indicates the index of the current RB
1614 * in which the last frame was written to
1615 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1616 * which was transferred
1618 struct iwm_rb_status {
1619 uint16_t closed_rb_num;
1620 uint16_t closed_fr_num;
1621 uint16_t finished_rb_num;
1622 uint16_t finished_fr_nam;
1627 #define IWM_TFD_QUEUE_SIZE_MAX (256)
1628 #define IWM_TFD_QUEUE_SIZE_BC_DUP (64)
1629 #define IWM_TFD_QUEUE_BC_SIZE (IWM_TFD_QUEUE_SIZE_MAX + \
1630 IWM_TFD_QUEUE_SIZE_BC_DUP)
1631 #define IWM_TX_DMA_MASK DMA_BIT_MASK(36)
1632 #define IWM_NUM_OF_TBS 20
1634 static inline uint8_t iwm_get_dma_hi_addr(bus_addr_t addr)
1636 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1639 * struct iwm_tfd_tb transmit buffer descriptor within transmit frame descriptor
1641 * This structure contains dma address and length of transmission address
1643 * @lo: low [31:0] portion of the dma address of TX buffer
1644 * every even is unaligned on 16 bit boundary
1645 * @hi_n_len 0-3 [35:32] portion of dma
1646 * 4-15 length of the tx buffer
1656 * Transmit Frame Descriptor (TFD)
1658 * @ __reserved1[3] reserved
1659 * @ num_tbs 0-4 number of active tbs
1661 * 6-7 padding (not used)
1662 * @ tbs[20] transmit frame buffer descriptors
1665 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1666 * Both driver and device share these circular buffers, each of which must be
1667 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1669 * Driver must indicate the physical address of the base of each
1670 * circular buffer via the IWM_FH_MEM_CBBC_QUEUE registers.
1672 * Each TFD contains pointer/size information for up to 20 data buffers
1673 * in host DRAM. These buffers collectively contain the (one) frame described
1674 * by the TFD. Each buffer must be a single contiguous block of memory within
1675 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1676 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1677 * Tx frame, up to 8 KBytes in size.
1679 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1682 uint8_t __reserved1[3];
1684 struct iwm_tfd_tb tbs[IWM_NUM_OF_TBS];
1688 /* Keep Warm Size */
1689 #define IWM_KW_SIZE 0x1000 /* 4k */
1691 /* Fixed (non-configurable) rx data from phy */
1694 * struct iwm_agn_schedq_bc_tbl scheduler byte count table
1695 * base physical address provided by IWM_SCD_DRAM_BASE_ADDR
1696 * @tfd_offset 0-12 - tx command byte count
1697 * 12-16 - station index
1699 struct iwm_agn_scd_bc_tbl {
1700 uint16_t tfd_offset[IWM_TFD_QUEUE_BC_SIZE];
1703 /* Maximum number of Tx queues. */
1704 #define IWM_MVM_MAX_QUEUES 31
1706 /* Tx queue numbers */
1708 IWM_MVM_OFFCHANNEL_QUEUE = 8,
1709 IWM_MVM_CMD_QUEUE = 9,
1710 IWM_MVM_AUX_QUEUE = 15,
1713 enum iwm_mvm_tx_fifo {
1714 IWM_MVM_TX_FIFO_BK = 0,
1718 IWM_MVM_TX_FIFO_MCAST = 5,
1719 IWM_MVM_TX_FIFO_CMD = 7,
1722 #define IWM_MVM_STATION_COUNT 16
1726 IWM_MVM_ALIVE = 0x1,
1727 IWM_REPLY_ERROR = 0x2,
1729 IWM_INIT_COMPLETE_NOTIF = 0x4,
1731 /* PHY context commands */
1732 IWM_PHY_CONTEXT_CMD = 0x8,
1735 /* UMAC scan commands */
1736 IWM_SCAN_ITERATION_COMPLETE_UMAC = 0xb5,
1737 IWM_SCAN_CFG_CMD = 0xc,
1738 IWM_SCAN_REQ_UMAC = 0xd,
1739 IWM_SCAN_ABORT_UMAC = 0xe,
1740 IWM_SCAN_COMPLETE_UMAC = 0xf,
1743 IWM_ADD_STA_KEY = 0x17,
1745 IWM_REMOVE_STA = 0x19,
1749 IWM_TXPATH_FLUSH = 0x1e,
1750 IWM_MGMT_MCAST_KEY = 0x1f,
1752 /* scheduler config */
1753 IWM_SCD_QUEUE_CFG = 0x1d,
1758 /* MAC and Binding commands */
1759 IWM_MAC_CONTEXT_CMD = 0x28,
1760 IWM_TIME_EVENT_CMD = 0x29, /* both CMD and response */
1761 IWM_TIME_EVENT_NOTIFICATION = 0x2a,
1762 IWM_BINDING_CONTEXT_CMD = 0x2b,
1763 IWM_TIME_QUOTA_CMD = 0x2c,
1764 IWM_NON_QOS_TX_COUNTER_CMD = 0x2d,
1769 IWM_TEMPERATURE_NOTIFICATION = 0x62,
1770 IWM_CALIBRATION_CFG_CMD = 0x65,
1771 IWM_CALIBRATION_RES_NOTIFICATION = 0x66,
1772 IWM_CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
1773 IWM_RADIO_VERSION_NOTIFICATION = 0x68,
1776 IWM_SCAN_OFFLOAD_REQUEST_CMD = 0x51,
1777 IWM_SCAN_OFFLOAD_ABORT_CMD = 0x52,
1778 IWM_HOT_SPOT_CMD = 0x53,
1779 IWM_SCAN_OFFLOAD_COMPLETE = 0x6d,
1780 IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD = 0x6e,
1781 IWM_SCAN_OFFLOAD_CONFIG_CMD = 0x6f,
1782 IWM_MATCH_FOUND_NOTIFICATION = 0xd9,
1783 IWM_SCAN_ITERATION_COMPLETE = 0xe7,
1786 IWM_PHY_CONFIGURATION_CMD = 0x6a,
1787 IWM_CALIB_RES_NOTIF_PHY_DB = 0x6b,
1788 /* IWM_PHY_DB_CMD = 0x6c, */
1790 /* Power - legacy power table command */
1791 IWM_POWER_TABLE_CMD = 0x77,
1792 IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78,
1794 /* Thermal Throttling*/
1795 IWM_REPLY_THERMAL_MNG_BACKOFF = 0x7e,
1798 IWM_SCAN_ABORT_CMD = 0x81,
1799 IWM_SCAN_START_NOTIFICATION = 0x82,
1800 IWM_SCAN_RESULTS_NOTIFICATION = 0x83,
1803 IWM_NVM_ACCESS_CMD = 0x88,
1805 IWM_SET_CALIB_DEFAULT_CMD = 0x8e,
1807 IWM_BEACON_NOTIFICATION = 0x90,
1808 IWM_BEACON_TEMPLATE_CMD = 0x91,
1809 IWM_TX_ANT_CONFIGURATION_CMD = 0x98,
1810 IWM_BT_CONFIG = 0x9b,
1811 IWM_STATISTICS_NOTIFICATION = 0x9d,
1812 IWM_REDUCE_TX_POWER_CMD = 0x9f,
1814 /* RF-KILL commands and notifications */
1815 IWM_CARD_STATE_CMD = 0xa0,
1816 IWM_CARD_STATE_NOTIFICATION = 0xa1,
1818 IWM_MISSED_BEACONS_NOTIFICATION = 0xa2,
1820 IWM_MFUART_LOAD_NOTIFICATION = 0xb1,
1822 /* Power - new power table command */
1823 IWM_MAC_PM_POWER_TABLE = 0xa9,
1825 IWM_REPLY_RX_PHY_CMD = 0xc0,
1826 IWM_REPLY_RX_MPDU_CMD = 0xc1,
1827 IWM_BA_NOTIF = 0xc5,
1829 /* Location Aware Regulatory */
1830 IWM_MCC_UPDATE_CMD = 0xc8,
1831 IWM_MCC_CHUB_UPDATE_CMD = 0xc9,
1834 IWM_BT_COEX_PRIO_TABLE = 0xcc,
1835 IWM_BT_COEX_PROT_ENV = 0xcd,
1836 IWM_BT_PROFILE_NOTIFICATION = 0xce,
1837 IWM_BT_COEX_CI = 0x5d,
1839 IWM_REPLY_SF_CFG_CMD = 0xd1,
1840 IWM_REPLY_BEACON_FILTERING_CMD = 0xd2,
1842 /* DTS measurements */
1843 IWM_CMD_DTS_MEASUREMENT_TRIGGER = 0xdc,
1844 IWM_DTS_MEASUREMENT_NOTIFICATION = 0xdd,
1846 IWM_REPLY_DEBUG_CMD = 0xf0,
1847 IWM_DEBUG_LOG_MSG = 0xf7,
1849 IWM_MCAST_FILTER_CMD = 0xd0,
1851 /* D3 commands/notifications */
1852 IWM_D3_CONFIG_CMD = 0xd3,
1853 IWM_PROT_OFFLOAD_CONFIG_CMD = 0xd4,
1854 IWM_OFFLOADS_QUERY_CMD = 0xd5,
1855 IWM_REMOTE_WAKE_CONFIG_CMD = 0xd6,
1857 /* for WoWLAN in particular */
1858 IWM_WOWLAN_PATTERNS = 0xe0,
1859 IWM_WOWLAN_CONFIGURATION = 0xe1,
1860 IWM_WOWLAN_TSC_RSC_PARAM = 0xe2,
1861 IWM_WOWLAN_TKIP_PARAM = 0xe3,
1862 IWM_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
1863 IWM_WOWLAN_GET_STATUSES = 0xe5,
1864 IWM_WOWLAN_TX_POWER_PER_DB = 0xe6,
1866 /* and for NetDetect */
1867 IWM_NET_DETECT_CONFIG_CMD = 0x54,
1868 IWM_NET_DETECT_PROFILES_QUERY_CMD = 0x56,
1869 IWM_NET_DETECT_PROFILES_CMD = 0x57,
1870 IWM_NET_DETECT_HOTSPOTS_CMD = 0x58,
1871 IWM_NET_DETECT_HOTSPOTS_QUERY_CMD = 0x59,
1873 IWM_REPLY_MAX = 0xff,
1877 * struct iwm_cmd_response - generic response struct for most commands
1878 * @status: status of the command asked, changes for each one
1880 struct iwm_cmd_response {
1885 * struct iwm_tx_ant_cfg_cmd
1886 * @valid: valid antenna configuration
1888 struct iwm_tx_ant_cfg_cmd {
1893 * struct iwm_reduce_tx_power_cmd - TX power reduction command
1894 * IWM_REDUCE_TX_POWER_CMD = 0x9f
1895 * @flags: (reserved for future implementation)
1896 * @mac_context_id: id of the mac ctx for which we are reducing TX power.
1897 * @pwr_restriction: TX power restriction in dBms.
1899 struct iwm_reduce_tx_power_cmd {
1901 uint8_t mac_context_id;
1902 uint16_t pwr_restriction;
1903 } __packed; /* IWM_TX_REDUCED_POWER_API_S_VER_1 */
1906 * Calibration control struct.
1907 * Sent as part of the phy configuration command.
1908 * @flow_trigger: bitmap for which calibrations to perform according to
1910 * @event_trigger: bitmap for which calibrations to perform according to
1913 struct iwm_calib_ctrl {
1914 uint32_t flow_trigger;
1915 uint32_t event_trigger;
1918 /* This enum defines the bitmap of various calibrations to enable in both
1919 * init ucode and runtime ucode through IWM_CALIBRATION_CFG_CMD.
1921 enum iwm_calib_cfg {
1922 IWM_CALIB_CFG_XTAL_IDX = (1 << 0),
1923 IWM_CALIB_CFG_TEMPERATURE_IDX = (1 << 1),
1924 IWM_CALIB_CFG_VOLTAGE_READ_IDX = (1 << 2),
1925 IWM_CALIB_CFG_PAPD_IDX = (1 << 3),
1926 IWM_CALIB_CFG_TX_PWR_IDX = (1 << 4),
1927 IWM_CALIB_CFG_DC_IDX = (1 << 5),
1928 IWM_CALIB_CFG_BB_FILTER_IDX = (1 << 6),
1929 IWM_CALIB_CFG_LO_LEAKAGE_IDX = (1 << 7),
1930 IWM_CALIB_CFG_TX_IQ_IDX = (1 << 8),
1931 IWM_CALIB_CFG_TX_IQ_SKEW_IDX = (1 << 9),
1932 IWM_CALIB_CFG_RX_IQ_IDX = (1 << 10),
1933 IWM_CALIB_CFG_RX_IQ_SKEW_IDX = (1 << 11),
1934 IWM_CALIB_CFG_SENSITIVITY_IDX = (1 << 12),
1935 IWM_CALIB_CFG_CHAIN_NOISE_IDX = (1 << 13),
1936 IWM_CALIB_CFG_DISCONNECTED_ANT_IDX = (1 << 14),
1937 IWM_CALIB_CFG_ANT_COUPLING_IDX = (1 << 15),
1938 IWM_CALIB_CFG_DAC_IDX = (1 << 16),
1939 IWM_CALIB_CFG_ABS_IDX = (1 << 17),
1940 IWM_CALIB_CFG_AGC_IDX = (1 << 18),
1944 * Phy configuration command.
1946 struct iwm_phy_cfg_cmd {
1948 struct iwm_calib_ctrl calib_control;
1951 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
1952 #define IWM_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
1953 #define IWM_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
1954 #define IWM_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
1955 #define IWM_PHY_CFG_TX_CHAIN_A (1 << 8)
1956 #define IWM_PHY_CFG_TX_CHAIN_B (1 << 9)
1957 #define IWM_PHY_CFG_TX_CHAIN_C (1 << 10)
1958 #define IWM_PHY_CFG_RX_CHAIN_A (1 << 12)
1959 #define IWM_PHY_CFG_RX_CHAIN_B (1 << 13)
1960 #define IWM_PHY_CFG_RX_CHAIN_C (1 << 14)
1966 enum iwm_phy_db_section_type {
1968 IWM_PHY_DB_CALIB_NCH,
1970 IWM_PHY_DB_CALIB_CHG_PAPD,
1971 IWM_PHY_DB_CALIB_CHG_TXP,
1975 #define IWM_PHY_DB_CMD 0x6c /* TEMP API - The actual is 0x8c */
1978 * phy db - configure operational ucode
1980 struct iwm_phy_db_cmd {
1986 /* for parsing of tx power channel group data that comes from the firmware */
1987 struct iwm_phy_db_chg_txp {
1989 uint16_t max_channel_idx;
1993 * phy db - Receive phy db chunk after calibrations
1995 struct iwm_calib_res_notif_phy_db {
2002 /* Target of the IWM_NVM_ACCESS_CMD */
2004 IWM_NVM_ACCESS_TARGET_CACHE = 0,
2005 IWM_NVM_ACCESS_TARGET_OTP = 1,
2006 IWM_NVM_ACCESS_TARGET_EEPROM = 2,
2009 /* Section types for IWM_NVM_ACCESS_CMD */
2011 IWM_NVM_SECTION_TYPE_HW = 0,
2012 IWM_NVM_SECTION_TYPE_SW,
2013 IWM_NVM_SECTION_TYPE_PAPD,
2014 IWM_NVM_SECTION_TYPE_REGULATORY,
2015 IWM_NVM_SECTION_TYPE_CALIBRATION,
2016 IWM_NVM_SECTION_TYPE_PRODUCTION,
2017 IWM_NVM_SECTION_TYPE_POST_FCS_CALIB,
2018 /* 7, 8, 9 unknown */
2019 IWM_NVM_SECTION_TYPE_HW_8000 = 10,
2020 IWM_NVM_SECTION_TYPE_MAC_OVERRIDE,
2021 IWM_NVM_SECTION_TYPE_PHY_SKU,
2022 IWM_NVM_NUM_OF_SECTIONS,
2026 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
2027 * @op_code: 0 - read, 1 - write
2028 * @target: IWM_NVM_ACCESS_TARGET_*
2029 * @type: IWM_NVM_SECTION_TYPE_*
2030 * @offset: offset in bytes into the section
2031 * @length: in bytes, to read/write
2032 * @data: if write operation, the data to write. On read its empty
2034 struct iwm_nvm_access_cmd {
2041 } __packed; /* IWM_NVM_ACCESS_CMD_API_S_VER_2 */
2044 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
2045 * @offset: offset in bytes into the section
2046 * @length: in bytes, either how much was written or read
2047 * @type: IWM_NVM_SECTION_TYPE_*
2048 * @status: 0 for success, fail otherwise
2049 * @data: if read operation, the data returned. Empty on write.
2051 struct iwm_nvm_access_resp {
2057 } __packed; /* IWM_NVM_ACCESS_CMD_RESP_API_S_VER_2 */
2059 /* IWM_MVM_ALIVE 0x1 */
2061 /* alive response is_valid values */
2062 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
2063 #define IWM_ALIVE_RESP_RFKILL (1 << 1)
2065 /* alive response ver_type values */
2068 IWM_FW_TYPE_PROT = 1,
2070 IWM_FW_TYPE_WOWLAN = 3,
2071 IWM_FW_TYPE_TIMING = 4,
2072 IWM_FW_TYPE_WIPAN = 5
2075 /* alive response ver_subtype values */
2077 IWM_FW_SUBTYPE_FULL_FEATURE = 0,
2078 IWM_FW_SUBTYPE_BOOTSRAP = 1, /* Not valid */
2079 IWM_FW_SUBTYPE_REDUCED = 2,
2080 IWM_FW_SUBTYPE_ALIVE_ONLY = 3,
2081 IWM_FW_SUBTYPE_WOWLAN = 4,
2082 IWM_FW_SUBTYPE_AP_SUBTYPE = 5,
2083 IWM_FW_SUBTYPE_WIPAN = 6,
2084 IWM_FW_SUBTYPE_INITIALIZE = 9
2087 #define IWM_ALIVE_STATUS_ERR 0xDEAD
2088 #define IWM_ALIVE_STATUS_OK 0xCAFE
2090 #define IWM_ALIVE_FLG_RFKILL (1 << 0)
2092 struct iwm_mvm_alive_resp_v1 {
2095 uint8_t ucode_minor;
2096 uint8_t ucode_major;
2100 uint8_t ver_subtype;
2106 uint32_t error_event_table_ptr; /* SRAM address for error log */
2107 uint32_t log_event_table_ptr; /* SRAM address for event log */
2108 uint32_t cpu_register_ptr;
2109 uint32_t dbgm_config_ptr;
2110 uint32_t alive_counter_ptr;
2111 uint32_t scd_base_ptr; /* SRAM address for SCD */
2112 } __packed; /* IWM_ALIVE_RES_API_S_VER_1 */
2114 struct iwm_mvm_alive_resp_v2 {
2117 uint8_t ucode_minor;
2118 uint8_t ucode_major;
2122 uint8_t ver_subtype;
2128 uint32_t error_event_table_ptr; /* SRAM address for error log */
2129 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2130 uint32_t cpu_register_ptr;
2131 uint32_t dbgm_config_ptr;
2132 uint32_t alive_counter_ptr;
2133 uint32_t scd_base_ptr; /* SRAM address for SCD */
2134 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2135 uint32_t st_fwrd_size;
2136 uint8_t umac_minor; /* UMAC version: minor */
2137 uint8_t umac_major; /* UMAC version: major */
2138 uint16_t umac_id; /* UMAC version: id */
2139 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2140 uint32_t dbg_print_buff_addr;
2141 } __packed; /* ALIVE_RES_API_S_VER_2 */
2143 struct iwm_mvm_alive_resp_v3 {
2146 uint32_t ucode_minor;
2147 uint32_t ucode_major;
2148 uint8_t ver_subtype;
2153 uint32_t error_event_table_ptr; /* SRAM address for error log */
2154 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2155 uint32_t cpu_register_ptr;
2156 uint32_t dbgm_config_ptr;
2157 uint32_t alive_counter_ptr;
2158 uint32_t scd_base_ptr; /* SRAM address for SCD */
2159 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2160 uint32_t st_fwrd_size;
2161 uint32_t umac_minor; /* UMAC version: minor */
2162 uint32_t umac_major; /* UMAC version: major */
2163 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2164 uint32_t dbg_print_buff_addr;
2165 } __packed; /* ALIVE_RES_API_S_VER_3 */
2167 /* Error response/notification */
2169 IWM_FW_ERR_UNKNOWN_CMD = 0x0,
2170 IWM_FW_ERR_INVALID_CMD_PARAM = 0x1,
2171 IWM_FW_ERR_SERVICE = 0x2,
2172 IWM_FW_ERR_ARC_MEMORY = 0x3,
2173 IWM_FW_ERR_ARC_CODE = 0x4,
2174 IWM_FW_ERR_WATCH_DOG = 0x5,
2175 IWM_FW_ERR_WEP_GRP_KEY_INDX = 0x10,
2176 IWM_FW_ERR_WEP_KEY_SIZE = 0x11,
2177 IWM_FW_ERR_OBSOLETE_FUNC = 0x12,
2178 IWM_FW_ERR_UNEXPECTED = 0xFE,
2179 IWM_FW_ERR_FATAL = 0xFF
2183 * struct iwm_error_resp - FW error indication
2184 * ( IWM_REPLY_ERROR = 0x2 )
2185 * @error_type: one of IWM_FW_ERR_*
2186 * @cmd_id: the command ID for which the error occurred
2187 * @bad_cmd_seq_num: sequence number of the erroneous command
2188 * @error_service: which service created the error, applicable only if
2189 * error_type = 2, otherwise 0
2190 * @timestamp: TSF in usecs.
2192 struct iwm_error_resp {
2193 uint32_t error_type;
2196 uint16_t bad_cmd_seq_num;
2197 uint32_t error_service;
2202 /* Common PHY, MAC and Bindings definitions */
2204 #define IWM_MAX_MACS_IN_BINDING (3)
2205 #define IWM_MAX_BINDINGS (4)
2206 #define IWM_AUX_BINDING_INDEX (3)
2207 #define IWM_MAX_PHYS (4)
2209 /* Used to extract ID and color from the context dword */
2210 #define IWM_FW_CTXT_ID_POS (0)
2211 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
2212 #define IWM_FW_CTXT_COLOR_POS (8)
2213 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
2214 #define IWM_FW_CTXT_INVALID (0xffffffff)
2216 #define IWM_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWM_FW_CTXT_ID_POS) |\
2217 (_color << IWM_FW_CTXT_COLOR_POS))
2219 /* Possible actions on PHYs, MACs and Bindings */
2221 IWM_FW_CTXT_ACTION_STUB = 0,
2222 IWM_FW_CTXT_ACTION_ADD,
2223 IWM_FW_CTXT_ACTION_MODIFY,
2224 IWM_FW_CTXT_ACTION_REMOVE,
2225 IWM_FW_CTXT_ACTION_NUM
2226 }; /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2230 /* Time Event types, according to MAC type */
2231 enum iwm_time_event_type {
2232 /* BSS Station Events */
2233 IWM_TE_BSS_STA_AGGRESSIVE_ASSOC,
2234 IWM_TE_BSS_STA_ASSOC,
2235 IWM_TE_BSS_EAP_DHCP_PROT,
2236 IWM_TE_BSS_QUIET_PERIOD,
2238 /* P2P Device Events */
2239 IWM_TE_P2P_DEVICE_DISCOVERABLE,
2240 IWM_TE_P2P_DEVICE_LISTEN,
2241 IWM_TE_P2P_DEVICE_ACTION_SCAN,
2242 IWM_TE_P2P_DEVICE_FULL_SCAN,
2244 /* P2P Client Events */
2245 IWM_TE_P2P_CLIENT_AGGRESSIVE_ASSOC,
2246 IWM_TE_P2P_CLIENT_ASSOC,
2247 IWM_TE_P2P_CLIENT_QUIET_PERIOD,
2250 IWM_TE_P2P_GO_ASSOC_PROT,
2251 IWM_TE_P2P_GO_REPETITIVE_NOA,
2252 IWM_TE_P2P_GO_CT_WINDOW,
2254 /* WiDi Sync Events */
2255 IWM_TE_WIDI_TX_SYNC,
2258 }; /* IWM_MAC_EVENT_TYPE_API_E_VER_1 */
2262 /* Time event - defines for command API v1 */
2265 * @IWM_TE_V1_FRAG_NONE: fragmentation of the time event is NOT allowed.
2266 * @IWM_TE_V1_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2267 * the first fragment is scheduled.
2268 * @IWM_TE_V1_FRAG_DUAL: fragmentation of the time event is allowed, but only
2269 * the first 2 fragments are scheduled.
2270 * @IWM_TE_V1_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2271 * number of fragments are valid.
2273 * Other than the constant defined above, specifying a fragmentation value 'x'
2274 * means that the event can be fragmented but only the first 'x' will be
2278 IWM_TE_V1_FRAG_NONE = 0,
2279 IWM_TE_V1_FRAG_SINGLE = 1,
2280 IWM_TE_V1_FRAG_DUAL = 2,
2281 IWM_TE_V1_FRAG_ENDLESS = 0xffffffff
2284 /* If a Time Event can be fragmented, this is the max number of fragments */
2285 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2286 /* Repeat the time event endlessly (until removed) */
2287 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2288 /* If a Time Event has bounded repetitions, this is the maximal value */
2289 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2291 /* Time Event dependencies: none, on another TE, or in a specific time */
2293 IWM_TE_V1_INDEPENDENT = 0,
2294 IWM_TE_V1_DEP_OTHER = (1 << 0),
2295 IWM_TE_V1_DEP_TSF = (1 << 1),
2296 IWM_TE_V1_EVENT_SOCIOPATHIC = (1 << 2),
2297 }; /* IWM_MAC_EVENT_DEPENDENCY_POLICY_API_E_VER_2 */
2300 * @IWM_TE_V1_NOTIF_NONE: no notifications
2301 * @IWM_TE_V1_NOTIF_HOST_EVENT_START: request/receive notification on event start
2302 * @IWM_TE_V1_NOTIF_HOST_EVENT_END:request/receive notification on event end
2303 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_START: internal FW use
2304 * @IWM_TE_V1_NOTIF_INTERNAL_EVENT_END: internal FW use.
2305 * @IWM_TE_V1_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2306 * @IWM_TE_V1_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2307 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_START: internal FW use.
2308 * @IWM_TE_V1_NOTIF_INTERNAL_FRAG_END: internal FW use.
2310 * Supported Time event notifications configuration.
2311 * A notification (both event and fragment) includes a status indicating weather
2312 * the FW was able to schedule the event or not. For fragment start/end
2313 * notification the status is always success. There is no start/end fragment
2314 * notification for monolithic events.
2317 IWM_TE_V1_NOTIF_NONE = 0,
2318 IWM_TE_V1_NOTIF_HOST_EVENT_START = (1 << 0),
2319 IWM_TE_V1_NOTIF_HOST_EVENT_END = (1 << 1),
2320 IWM_TE_V1_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2321 IWM_TE_V1_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2322 IWM_TE_V1_NOTIF_HOST_FRAG_START = (1 << 4),
2323 IWM_TE_V1_NOTIF_HOST_FRAG_END = (1 << 5),
2324 IWM_TE_V1_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2325 IWM_TE_V1_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2326 IWM_T2_V2_START_IMMEDIATELY = (1 << 11),
2327 }; /* IWM_MAC_EVENT_ACTION_API_E_VER_2 */
2331 * struct iwm_time_event_cmd_api_v1 - configuring Time Events
2332 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 (see also
2333 * with version 2. determined by IWM_UCODE_TLV_FLAGS)
2334 * ( IWM_TIME_EVENT_CMD = 0x29 )
2335 * @id_and_color: ID and color of the relevant MAC
2336 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2337 * @id: this field has two meanings, depending on the action:
2338 * If the action is ADD, then it means the type of event to add.
2339 * For all other actions it is the unique event ID assigned when the
2340 * event was added by the FW.
2341 * @apply_time: When to start the Time Event (in GP2)
2342 * @max_delay: maximum delay to event's start (apply time), in TU
2343 * @depends_on: the unique ID of the event we depend on (if any)
2344 * @interval: interval between repetitions, in TU
2345 * @interval_reciprocal: 2^32 / interval
2346 * @duration: duration of event in TU
2347 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2348 * @dep_policy: one of IWM_TE_V1_INDEPENDENT, IWM_TE_V1_DEP_OTHER, IWM_TE_V1_DEP_TSF
2349 * and IWM_TE_V1_EVENT_SOCIOPATHIC
2350 * @is_present: 0 or 1, are we present or absent during the Time Event
2351 * @max_frags: maximal number of fragments the Time Event can be divided to
2352 * @notify: notifications using IWM_TE_V1_NOTIF_* (whom to notify when)
2354 struct iwm_time_event_cmd_v1 {
2355 /* COMMON_INDEX_HDR_API_S_VER_1 */
2356 uint32_t id_and_color;
2359 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_1 */
2360 uint32_t apply_time;
2362 uint32_t dep_policy;
2363 uint32_t depends_on;
2364 uint32_t is_present;
2367 uint32_t interval_reciprocal;
2371 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_1 */
2374 /* Time event - defines for command API v2 */
2377 * @IWM_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
2378 * @IWM_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
2379 * the first fragment is scheduled.
2380 * @IWM_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
2381 * the first 2 fragments are scheduled.
2382 * @IWM_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
2383 * number of fragments are valid.
2385 * Other than the constant defined above, specifying a fragmentation value 'x'
2386 * means that the event can be fragmented but only the first 'x' will be
2390 IWM_TE_V2_FRAG_NONE = 0,
2391 IWM_TE_V2_FRAG_SINGLE = 1,
2392 IWM_TE_V2_FRAG_DUAL = 2,
2393 IWM_TE_V2_FRAG_MAX = 0xfe,
2394 IWM_TE_V2_FRAG_ENDLESS = 0xff
2397 /* Repeat the time event endlessly (until removed) */
2398 #define IWM_TE_V2_REPEAT_ENDLESS 0xff
2399 /* If a Time Event has bounded repetitions, this is the maximal value */
2400 #define IWM_TE_V2_REPEAT_MAX 0xfe
2402 #define IWM_TE_V2_PLACEMENT_POS 12
2403 #define IWM_TE_V2_ABSENCE_POS 15
2405 /* Time event policy values (for time event cmd api v2)
2406 * A notification (both event and fragment) includes a status indicating weather
2407 * the FW was able to schedule the event or not. For fragment start/end
2408 * notification the status is always success. There is no start/end fragment
2409 * notification for monolithic events.
2411 * @IWM_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
2412 * @IWM_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
2413 * @IWM_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
2414 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
2415 * @IWM_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
2416 * @IWM_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
2417 * @IWM_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
2418 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
2419 * @IWM_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
2420 * @IWM_TE_V2_DEP_OTHER: depends on another time event
2421 * @IWM_TE_V2_DEP_TSF: depends on a specific time
2422 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2423 * @IWM_TE_V2_ABSENCE: are we present or absent during the Time Event.
2426 IWM_TE_V2_DEFAULT_POLICY = 0x0,
2428 /* notifications (event start/stop, fragment start/stop) */
2429 IWM_TE_V2_NOTIF_HOST_EVENT_START = (1 << 0),
2430 IWM_TE_V2_NOTIF_HOST_EVENT_END = (1 << 1),
2431 IWM_TE_V2_NOTIF_INTERNAL_EVENT_START = (1 << 2),
2432 IWM_TE_V2_NOTIF_INTERNAL_EVENT_END = (1 << 3),
2434 IWM_TE_V2_NOTIF_HOST_FRAG_START = (1 << 4),
2435 IWM_TE_V2_NOTIF_HOST_FRAG_END = (1 << 5),
2436 IWM_TE_V2_NOTIF_INTERNAL_FRAG_START = (1 << 6),
2437 IWM_TE_V2_NOTIF_INTERNAL_FRAG_END = (1 << 7),
2439 IWM_TE_V2_NOTIF_MSK = 0xff,
2441 /* placement characteristics */
2442 IWM_TE_V2_DEP_OTHER = (1 << IWM_TE_V2_PLACEMENT_POS),
2443 IWM_TE_V2_DEP_TSF = (1 << (IWM_TE_V2_PLACEMENT_POS + 1)),
2444 IWM_TE_V2_EVENT_SOCIOPATHIC = (1 << (IWM_TE_V2_PLACEMENT_POS + 2)),
2446 /* are we present or absent during the Time Event. */
2447 IWM_TE_V2_ABSENCE = (1 << IWM_TE_V2_ABSENCE_POS),
2451 * struct iwm_time_event_cmd_api_v2 - configuring Time Events
2452 * with struct IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
2453 * with version 1. determined by IWM_UCODE_TLV_FLAGS)
2454 * ( IWM_TIME_EVENT_CMD = 0x29 )
2455 * @id_and_color: ID and color of the relevant MAC
2456 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2457 * @id: this field has two meanings, depending on the action:
2458 * If the action is ADD, then it means the type of event to add.
2459 * For all other actions it is the unique event ID assigned when the
2460 * event was added by the FW.
2461 * @apply_time: When to start the Time Event (in GP2)
2462 * @max_delay: maximum delay to event's start (apply time), in TU
2463 * @depends_on: the unique ID of the event we depend on (if any)
2464 * @interval: interval between repetitions, in TU
2465 * @duration: duration of event in TU
2466 * @repeat: how many repetitions to do, can be IWM_TE_REPEAT_ENDLESS
2467 * @max_frags: maximal number of fragments the Time Event can be divided to
2468 * @policy: defines whether uCode shall notify the host or other uCode modules
2469 * on event and/or fragment start and/or end
2470 * using one of IWM_TE_INDEPENDENT, IWM_TE_DEP_OTHER, IWM_TE_DEP_TSF
2471 * IWM_TE_EVENT_SOCIOPATHIC
2472 * using IWM_TE_ABSENCE and using IWM_TE_NOTIF_*
2474 struct iwm_time_event_cmd_v2 {
2475 /* COMMON_INDEX_HDR_API_S_VER_1 */
2476 uint32_t id_and_color;
2479 /* IWM_MAC_TIME_EVENT_DATA_API_S_VER_2 */
2480 uint32_t apply_time;
2482 uint32_t depends_on;
2488 } __packed; /* IWM_MAC_TIME_EVENT_CMD_API_S_VER_2 */
2491 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2492 * @status: bit 0 indicates success, all others specify errors
2493 * @id: the Time Event type
2494 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
2495 * @id_and_color: ID and color of the relevant MAC
2497 struct iwm_time_event_resp {
2501 uint32_t id_and_color;
2502 } __packed; /* IWM_MAC_TIME_EVENT_RSP_API_S_VER_1 */
2505 * struct iwm_time_event_notif - notifications of time event start/stop
2506 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2507 * @timestamp: action timestamp in GP2
2508 * @session_id: session's unique id
2509 * @unique_id: unique id of the Time Event itself
2510 * @id_and_color: ID and color of the relevant MAC
2511 * @action: one of IWM_TE_NOTIF_START or IWM_TE_NOTIF_END
2512 * @status: true if scheduled, false otherwise (not executed)
2514 struct iwm_time_event_notif {
2516 uint32_t session_id;
2518 uint32_t id_and_color;
2521 } __packed; /* IWM_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
2524 /* Bindings and Time Quota */
2527 * struct iwm_binding_cmd - configuring bindings
2528 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2529 * @id_and_color: ID and color of the relevant Binding
2530 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2531 * @macs: array of MAC id and colors which belong to the binding
2532 * @phy: PHY id and color which belongs to the binding
2534 struct iwm_binding_cmd {
2535 /* COMMON_INDEX_HDR_API_S_VER_1 */
2536 uint32_t id_and_color;
2538 /* IWM_BINDING_DATA_API_S_VER_1 */
2539 uint32_t macs[IWM_MAX_MACS_IN_BINDING];
2541 } __packed; /* IWM_BINDING_CMD_API_S_VER_1 */
2543 /* The maximal number of fragments in the FW's schedule session */
2544 #define IWM_MVM_MAX_QUOTA 128
2547 * struct iwm_time_quota_data - configuration of time quota per binding
2548 * @id_and_color: ID and color of the relevant Binding
2549 * @quota: absolute time quota in TU. The scheduler will try to divide the
2550 * remainig quota (after Time Events) according to this quota.
2551 * @max_duration: max uninterrupted context duration in TU
2553 struct iwm_time_quota_data {
2554 uint32_t id_and_color;
2556 uint32_t max_duration;
2557 } __packed; /* IWM_TIME_QUOTA_DATA_API_S_VER_1 */
2560 * struct iwm_time_quota_cmd - configuration of time quota between bindings
2561 * ( IWM_TIME_QUOTA_CMD = 0x2c )
2562 * @quotas: allocations per binding
2564 struct iwm_time_quota_cmd {
2565 struct iwm_time_quota_data quotas[IWM_MAX_BINDINGS];
2566 } __packed; /* IWM_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
2571 /* Supported bands */
2572 #define IWM_PHY_BAND_5 (0)
2573 #define IWM_PHY_BAND_24 (1)
2575 /* Supported channel width, vary if there is VHT support */
2576 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
2577 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
2578 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
2579 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
2582 * Control channel position:
2583 * For legacy set bit means upper channel, otherwise lower.
2584 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
2585 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
2588 * 40Mhz |_______|_______|
2589 * 80Mhz |_______|_______|_______|_______|
2590 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
2591 * code 011 010 001 000 | 100 101 110 111
2593 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
2594 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
2595 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
2596 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
2597 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
2598 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
2599 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
2600 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
2603 * @band: IWM_PHY_BAND_*
2604 * @channel: channel number
2605 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
2606 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
2608 struct iwm_fw_channel_info {
2615 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
2616 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
2617 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
2618 #define IWM_PHY_RX_CHAIN_VALID_POS (1)
2619 #define IWM_PHY_RX_CHAIN_VALID_MSK \
2620 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
2621 #define IWM_PHY_RX_CHAIN_FORCE_SEL_POS (4)
2622 #define IWM_PHY_RX_CHAIN_FORCE_SEL_MSK \
2623 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
2624 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
2625 #define IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
2626 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
2627 #define IWM_PHY_RX_CHAIN_CNT_POS (10)
2628 #define IWM_PHY_RX_CHAIN_CNT_MSK \
2629 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
2630 #define IWM_PHY_RX_CHAIN_MIMO_CNT_POS (12)
2631 #define IWM_PHY_RX_CHAIN_MIMO_CNT_MSK \
2632 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
2633 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
2634 #define IWM_PHY_RX_CHAIN_MIMO_FORCE_MSK \
2635 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
2637 /* TODO: fix the value, make it depend on firmware at runtime? */
2638 #define IWM_NUM_PHY_CTX 3
2640 /* TODO: complete missing documentation */
2642 * struct iwm_phy_context_cmd - config of the PHY context
2643 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
2644 * @id_and_color: ID and color of the relevant Binding
2645 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
2646 * @apply_time: 0 means immediate apply and context switch.
2647 * other value means apply new params after X usecs
2648 * @tx_param_color: ???
2650 * @txchain_info: ???
2651 * @rxchain_info: ???
2652 * @acquisition_data: ???
2653 * @dsp_cfg_flags: set to 0
2655 struct iwm_phy_context_cmd {
2656 /* COMMON_INDEX_HDR_API_S_VER_1 */
2657 uint32_t id_and_color;
2659 /* IWM_PHY_CONTEXT_DATA_API_S_VER_1 */
2660 uint32_t apply_time;
2661 uint32_t tx_param_color;
2662 struct iwm_fw_channel_info ci;
2663 uint32_t txchain_info;
2664 uint32_t rxchain_info;
2665 uint32_t acquisition_data;
2666 uint32_t dsp_cfg_flags;
2667 } __packed; /* IWM_PHY_CONTEXT_CMD_API_VER_1 */
2669 #define IWM_RX_INFO_PHY_CNT 8
2670 #define IWM_RX_INFO_ENERGY_ANT_ABC_IDX 1
2671 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
2672 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
2673 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
2674 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0
2675 #define IWM_RX_INFO_ENERGY_ANT_B_POS 8
2676 #define IWM_RX_INFO_ENERGY_ANT_C_POS 16
2678 #define IWM_RX_INFO_AGC_IDX 1
2679 #define IWM_RX_INFO_RSSI_AB_IDX 2
2680 #define IWM_OFDM_AGC_A_MSK 0x0000007f
2681 #define IWM_OFDM_AGC_A_POS 0
2682 #define IWM_OFDM_AGC_B_MSK 0x00003f80
2683 #define IWM_OFDM_AGC_B_POS 7
2684 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
2685 #define IWM_OFDM_AGC_CODE_POS 20
2686 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
2687 #define IWM_OFDM_RSSI_A_POS 0
2688 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
2689 #define IWM_OFDM_RSSI_ALLBAND_A_POS 8
2690 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
2691 #define IWM_OFDM_RSSI_B_POS 16
2692 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
2693 #define IWM_OFDM_RSSI_ALLBAND_B_POS 24
2696 * struct iwm_rx_phy_info - phy info
2697 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
2698 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
2699 * @cfg_phy_cnt: configurable DSP phy data byte count
2700 * @stat_id: configurable DSP phy data set ID
2702 * @system_timestamp: GP2 at on air rise
2703 * @timestamp: TSF at on air rise
2704 * @beacon_time_stamp: beacon at on-air rise
2705 * @phy_flags: general phy flags: band, modulation, ...
2706 * @channel: channel number
2707 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
2708 * @rate_n_flags: IWM_RATE_MCS_*
2709 * @byte_count: frame's byte-count
2710 * @frame_time: frame's time on the air, based on byte count and frame rate
2712 * @mac_active_msk: what MACs were active when the frame was received
2714 * Before each Rx, the device sends this data. It contains PHY information
2715 * about the reception of the packet.
2717 struct iwm_rx_phy_info {
2718 uint8_t non_cfg_phy_cnt;
2719 uint8_t cfg_phy_cnt;
2722 uint32_t system_timestamp;
2724 uint32_t beacon_time_stamp;
2726 #define IWM_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
2728 uint32_t non_cfg_phy[IWM_RX_INFO_PHY_CNT];
2732 uint32_t byte_count;
2733 uint16_t mac_active_msk;
2734 uint16_t frame_time;
2737 struct iwm_rx_mpdu_res_start {
2738 uint16_t byte_count;
2743 * enum iwm_rx_phy_flags - to parse %iwm_rx_phy_info phy_flags
2744 * @IWM_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
2745 * @IWM_RX_RES_PHY_FLAGS_MOD_CCK:
2746 * @IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
2747 * @IWM_RX_RES_PHY_FLAGS_NARROW_BAND:
2748 * @IWM_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
2749 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
2750 * @IWM_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
2751 * @IWM_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
2752 * @IWM_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
2754 enum iwm_rx_phy_flags {
2755 IWM_RX_RES_PHY_FLAGS_BAND_24 = (1 << 0),
2756 IWM_RX_RES_PHY_FLAGS_MOD_CCK = (1 << 1),
2757 IWM_RX_RES_PHY_FLAGS_SHORT_PREAMBLE = (1 << 2),
2758 IWM_RX_RES_PHY_FLAGS_NARROW_BAND = (1 << 3),
2759 IWM_RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
2760 IWM_RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
2761 IWM_RX_RES_PHY_FLAGS_AGG = (1 << 7),
2762 IWM_RX_RES_PHY_FLAGS_OFDM_HT = (1 << 8),
2763 IWM_RX_RES_PHY_FLAGS_OFDM_GF = (1 << 9),
2764 IWM_RX_RES_PHY_FLAGS_OFDM_VHT = (1 << 10),
2768 * enum iwm_mvm_rx_status - written by fw for each Rx packet
2769 * @IWM_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
2770 * @IWM_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
2771 * @IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
2772 * @IWM_RX_MPDU_RES_STATUS_KEY_VALID:
2773 * @IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
2774 * @IWM_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
2775 * @IWM_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
2777 * @IWM_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
2778 * @IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
2779 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
2780 * %IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
2781 * @IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
2782 * @IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
2783 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
2784 * @IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
2785 * @IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
2786 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
2787 * @IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
2788 * @IWM_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
2789 * @IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
2790 * @IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
2791 * @IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
2792 * @IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
2793 * @IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
2794 * @IWM_RX_MPDU_RES_STATUS_STA_ID_MSK:
2795 * @IWM_RX_MPDU_RES_STATUS_RRF_KILL:
2796 * @IWM_RX_MPDU_RES_STATUS_FILTERING_MSK:
2797 * @IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK:
2799 enum iwm_mvm_rx_status {
2800 IWM_RX_MPDU_RES_STATUS_CRC_OK = (1 << 0),
2801 IWM_RX_MPDU_RES_STATUS_OVERRUN_OK = (1 << 1),
2802 IWM_RX_MPDU_RES_STATUS_SRC_STA_FOUND = (1 << 2),
2803 IWM_RX_MPDU_RES_STATUS_KEY_VALID = (1 << 3),
2804 IWM_RX_MPDU_RES_STATUS_KEY_PARAM_OK = (1 << 4),
2805 IWM_RX_MPDU_RES_STATUS_ICV_OK = (1 << 5),
2806 IWM_RX_MPDU_RES_STATUS_MIC_OK = (1 << 6),
2807 IWM_RX_MPDU_RES_STATUS_TTAK_OK = (1 << 7),
2808 IWM_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = (1 << 7),
2809 IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
2810 IWM_RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
2811 IWM_RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
2812 IWM_RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
2813 IWM_RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
2814 IWM_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
2815 IWM_RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
2816 IWM_RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
2817 IWM_RX_MPDU_RES_STATUS_DEC_DONE = (1 << 11),
2818 IWM_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP = (1 << 12),
2819 IWM_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = (1 << 13),
2820 IWM_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = (1 << 14),
2821 IWM_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = (1 << 15),
2822 IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK = (0x3F0000),
2823 IWM_RX_MPDU_RES_STATUS_STA_ID_MSK = (0x1f000000),
2824 IWM_RX_MPDU_RES_STATUS_RRF_KILL = (1 << 29),
2825 IWM_RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
2826 IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
2830 * struct iwm_radio_version_notif - information on the radio version
2831 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
2836 struct iwm_radio_version_notif {
2837 uint32_t radio_flavor;
2838 uint32_t radio_step;
2839 uint32_t radio_dash;
2840 } __packed; /* IWM_RADIO_VERSION_NOTOFICATION_S_VER_1 */
2842 enum iwm_card_state_flags {
2843 IWM_CARD_ENABLED = 0x00,
2844 IWM_HW_CARD_DISABLED = 0x01,
2845 IWM_SW_CARD_DISABLED = 0x02,
2846 IWM_CT_KILL_CARD_DISABLED = 0x04,
2847 IWM_HALT_CARD_DISABLED = 0x08,
2848 IWM_CARD_DISABLED_MSK = 0x0f,
2849 IWM_CARD_IS_RX_ON = 0x10,
2853 * struct iwm_radio_version_notif - information on the radio version
2854 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
2855 * @flags: %iwm_card_state_flags
2857 struct iwm_card_state_notif {
2859 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
2862 * struct iwm_missed_beacons_notif - information on missed beacons
2863 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
2864 * @mac_id: interface ID
2865 * @consec_missed_beacons_since_last_rx: number of consecutive missed
2866 * beacons since last RX.
2867 * @consec_missed_beacons: number of consecutive missed beacons
2868 * @num_expected_beacons:
2869 * @num_recvd_beacons:
2871 struct iwm_missed_beacons_notif {
2873 uint32_t consec_missed_beacons_since_last_rx;
2874 uint32_t consec_missed_beacons;
2875 uint32_t num_expected_beacons;
2876 uint32_t num_recvd_beacons;
2877 } __packed; /* IWM_MISSED_BEACON_NTFY_API_S_VER_3 */
2880 * struct iwm_mfuart_load_notif - mfuart image version & status
2881 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 )
2882 * @installed_ver: installed image version
2883 * @external_ver: external image version
2884 * @status: MFUART loading status
2885 * @duration: MFUART loading time
2887 struct iwm_mfuart_load_notif {
2888 uint32_t installed_ver;
2889 uint32_t external_ver;
2892 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
2895 * struct iwm_set_calib_default_cmd - set default value for calibration.
2896 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
2897 * @calib_index: the calibration to set value for
2899 * @data: the value to set for the calibration result
2901 struct iwm_set_calib_default_cmd {
2902 uint16_t calib_index;
2905 } __packed; /* IWM_PHY_CALIB_OVERRIDE_VALUES_S */
2907 #define IWM_MAX_PORT_ID_NUM 2
2908 #define IWM_MAX_MCAST_FILTERING_ADDRESSES 256
2911 * struct iwm_mcast_filter_cmd - configure multicast filter.
2912 * @filter_own: Set 1 to filter out multicast packets sent by station itself
2913 * @port_id: Multicast MAC addresses array specifier. This is a strange way
2914 * to identify network interface adopted in host-device IF.
2915 * It is used by FW as index in array of addresses. This array has
2916 * IWM_MAX_PORT_ID_NUM members.
2917 * @count: Number of MAC addresses in the array
2918 * @pass_all: Set 1 to pass all multicast packets.
2919 * @bssid: current association BSSID.
2920 * @addr_list: Place holder for array of MAC addresses.
2921 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
2923 struct iwm_mcast_filter_cmd {
2929 uint8_t reserved[2];
2930 uint8_t addr_list[0];
2931 } __packed; /* IWM_MCAST_FILTERING_CMD_API_S_VER_1 */
2933 struct iwm_mvm_statistics_dbg {
2934 uint32_t burst_check;
2935 uint32_t burst_count;
2936 uint32_t wait_for_silence_timeout_cnt;
2937 uint32_t reserved[3];
2938 } __packed; /* IWM_STATISTICS_DEBUG_API_S_VER_2 */
2940 struct iwm_mvm_statistics_div {
2944 uint32_t probe_time;
2947 } __packed; /* IWM_STATISTICS_SLOW_DIV_API_S_VER_2 */
2949 struct iwm_mvm_statistics_general_common {
2950 uint32_t temperature; /* radio temperature */
2951 uint32_t temperature_m; /* radio voltage */
2952 struct iwm_mvm_statistics_dbg dbg;
2953 uint32_t sleep_time;
2955 uint32_t slots_idle;
2956 uint32_t ttl_timestamp;
2957 struct iwm_mvm_statistics_div div;
2958 uint32_t rx_enable_counter;
2960 * num_of_sos_states:
2961 * count the number of times we have to re-tune
2962 * in order to get out of bad PHY status
2964 uint32_t num_of_sos_states;
2965 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
2967 struct iwm_mvm_statistics_rx_non_phy {
2968 uint32_t bogus_cts; /* CTS received when not expecting CTS */
2969 uint32_t bogus_ack; /* ACK received when not expecting ACK */
2970 uint32_t non_bssid_frames; /* number of frames with BSSID that
2971 * doesn't belong to the STA BSSID */
2972 uint32_t filtered_frames; /* count frames that were dumped in the
2973 * filtering process */
2974 uint32_t non_channel_beacons; /* beacons with our bss id but not on
2975 * our serving channel */
2976 uint32_t channel_beacons; /* beacons with our bss id and in our
2977 * serving channel */
2978 uint32_t num_missed_bcon; /* number of missed beacons */
2979 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
2980 * ADC was in saturation */
2981 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
2983 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
2984 uint32_t interference_data_flag; /* flag for interference data
2985 * availability. 1 when data is
2987 uint32_t channel_load; /* counts RX Enable time in uSec */
2988 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
2989 * and CCK) counter */
2990 uint32_t beacon_rssi_a;
2991 uint32_t beacon_rssi_b;
2992 uint32_t beacon_rssi_c;
2993 uint32_t beacon_energy_a;
2994 uint32_t beacon_energy_b;
2995 uint32_t beacon_energy_c;
2996 uint32_t num_bt_kills;
2998 uint32_t directed_data_mpdu;
2999 } __packed; /* IWM_STATISTICS_RX_NON_PHY_API_S_VER_3 */
3001 struct iwm_mvm_statistics_rx_phy {
3006 uint32_t overrun_err;
3007 uint32_t early_overrun_err;
3008 uint32_t crc32_good;
3009 uint32_t false_alarm_cnt;
3010 uint32_t fina_sync_err_cnt;
3011 uint32_t sfd_timeout;
3012 uint32_t fina_timeout;
3013 uint32_t unresponded_rts;
3014 uint32_t rxe_frame_limit_overrun;
3015 uint32_t sent_ack_cnt;
3016 uint32_t sent_cts_cnt;
3017 uint32_t sent_ba_rsp_cnt;
3018 uint32_t dsp_self_kill;
3019 uint32_t mh_format_err;
3020 uint32_t re_acq_main_rssi_sum;
3022 } __packed; /* IWM_STATISTICS_RX_PHY_API_S_VER_2 */
3024 struct iwm_mvm_statistics_rx_ht_phy {
3026 uint32_t overrun_err;
3027 uint32_t early_overrun_err;
3028 uint32_t crc32_good;
3030 uint32_t mh_format_err;
3031 uint32_t agg_crc32_good;
3032 uint32_t agg_mpdu_cnt;
3034 uint32_t unsupport_mcs;
3035 } __packed; /* IWM_STATISTICS_HT_RX_PHY_API_S_VER_1 */
3037 #define IWM_MAX_CHAINS 3
3039 struct iwm_mvm_statistics_tx_non_phy_agg {
3040 uint32_t ba_timeout;
3041 uint32_t ba_reschedule_frames;
3042 uint32_t scd_query_agg_frame_cnt;
3043 uint32_t scd_query_no_agg;
3044 uint32_t scd_query_agg;
3045 uint32_t scd_query_mismatch;
3046 uint32_t frame_not_ready;
3048 uint32_t bt_prio_kill;
3049 uint32_t rx_ba_rsp_cnt;
3050 int8_t txpower[IWM_MAX_CHAINS];
3053 } __packed; /* IWM_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
3055 struct iwm_mvm_statistics_tx_channel_width {
3056 uint32_t ext_cca_narrow_ch20[1];
3057 uint32_t ext_cca_narrow_ch40[2];
3058 uint32_t ext_cca_narrow_ch80[3];
3059 uint32_t ext_cca_narrow_ch160[4];
3060 uint32_t last_tx_ch_width_indx;
3061 uint32_t rx_detected_per_ch_width[4];
3062 uint32_t success_per_ch_width[4];
3063 uint32_t fail_per_ch_width[4];
3064 }; /* IWM_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
3066 struct iwm_mvm_statistics_tx {
3067 uint32_t preamble_cnt;
3068 uint32_t rx_detected_cnt;
3069 uint32_t bt_prio_defer_cnt;
3070 uint32_t bt_prio_kill_cnt;
3071 uint32_t few_bytes_cnt;
3072 uint32_t cts_timeout;
3073 uint32_t ack_timeout;
3074 uint32_t expected_ack_cnt;
3075 uint32_t actual_ack_cnt;
3076 uint32_t dump_msdu_cnt;
3077 uint32_t burst_abort_next_frame_mismatch_cnt;
3078 uint32_t burst_abort_missing_next_frame_cnt;
3079 uint32_t cts_timeout_collision;
3080 uint32_t ack_or_ba_timeout_collision;
3081 struct iwm_mvm_statistics_tx_non_phy_agg agg;
3082 struct iwm_mvm_statistics_tx_channel_width channel_width;
3083 } __packed; /* IWM_STATISTICS_TX_API_S_VER_4 */
3086 struct iwm_mvm_statistics_bt_activity {
3087 uint32_t hi_priority_tx_req_cnt;
3088 uint32_t hi_priority_tx_denied_cnt;
3089 uint32_t lo_priority_tx_req_cnt;
3090 uint32_t lo_priority_tx_denied_cnt;
3091 uint32_t hi_priority_rx_req_cnt;
3092 uint32_t hi_priority_rx_denied_cnt;
3093 uint32_t lo_priority_rx_req_cnt;
3094 uint32_t lo_priority_rx_denied_cnt;
3095 } __packed; /* IWM_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3097 struct iwm_mvm_statistics_general {
3098 struct iwm_mvm_statistics_general_common common;
3099 uint32_t beacon_filtered;
3100 uint32_t missed_beacons;
3101 int8_t beacon_filter_average_energy;
3102 int8_t beacon_filter_reason;
3103 int8_t beacon_filter_current_energy;
3104 int8_t beacon_filter_reserved;
3105 uint32_t beacon_filter_delta_time;
3106 struct iwm_mvm_statistics_bt_activity bt_activity;
3107 } __packed; /* IWM_STATISTICS_GENERAL_API_S_VER_5 */
3109 struct iwm_mvm_statistics_rx {
3110 struct iwm_mvm_statistics_rx_phy ofdm;
3111 struct iwm_mvm_statistics_rx_phy cck;
3112 struct iwm_mvm_statistics_rx_non_phy general;
3113 struct iwm_mvm_statistics_rx_ht_phy ofdm_ht;
3114 } __packed; /* IWM_STATISTICS_RX_API_S_VER_3 */
3117 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
3119 * By default, uCode issues this notification after receiving a beacon
3120 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
3121 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
3123 * Statistics counters continue to increment beacon after beacon, but are
3124 * cleared when changing channels or when driver issues IWM_REPLY_STATISTICS_CMD
3125 * 0x9c with CLEAR_STATS bit set (see above).
3127 * uCode also issues this notification during scans. uCode clears statistics
3128 * appropriately so that each notification contains statistics for only the
3129 * one channel that has just been scanned.
3132 struct iwm_notif_statistics { /* IWM_STATISTICS_NTFY_API_S_VER_8 */
3134 struct iwm_mvm_statistics_rx rx;
3135 struct iwm_mvm_statistics_tx tx;
3136 struct iwm_mvm_statistics_general general;
3139 /***********************************
3141 ***********************************/
3142 /* Smart Fifo state */
3144 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
3148 IWM_SF_HW_NUM_STATES
3151 /* Smart Fifo possible scenario */
3152 enum iwm_sf_scenario {
3153 IWM_SF_SCENARIO_SINGLE_UNICAST,
3154 IWM_SF_SCENARIO_AGG_UNICAST,
3155 IWM_SF_SCENARIO_MULTICAST,
3156 IWM_SF_SCENARIO_BA_RESP,
3157 IWM_SF_SCENARIO_TX_RESP,
3161 #define IWM_SF_TRANSIENT_STATES_NUMBER 2 /* IWM_SF_LONG_DELAY_ON and IWM_SF_FULL_ON */
3162 #define IWM_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
3164 /* smart FIFO default values */
3165 #define IWM_SF_W_MARK_SISO 4096
3166 #define IWM_SF_W_MARK_MIMO2 8192
3167 #define IWM_SF_W_MARK_MIMO3 6144
3168 #define IWM_SF_W_MARK_LEGACY 4096
3169 #define IWM_SF_W_MARK_SCAN 4096
3171 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */
3172 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3173 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3174 #define IWM_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3175 #define IWM_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3176 #define IWM_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 uSec */
3177 #define IWM_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
3178 #define IWM_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
3179 #define IWM_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
3180 #define IWM_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
3181 #define IWM_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
3183 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
3184 #define IWM_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3185 #define IWM_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3186 #define IWM_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
3187 #define IWM_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
3188 #define IWM_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
3189 #define IWM_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
3190 #define IWM_SF_BA_IDLE_TIMER 320 /* 300 uSec */
3191 #define IWM_SF_BA_AGING_TIMER 2016 /* 2 mSec */
3192 #define IWM_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
3193 #define IWM_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
3195 #define IWM_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
3197 #define IWM_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
3200 * Smart Fifo configuration command.
3201 * @state: smart fifo state, types listed in enum %iwm_sf_state.
3202 * @watermark: Minimum allowed available free space in RXF for transient state.
3203 * @long_delay_timeouts: aging and idle timer values for each scenario
3204 * in long delay state.
3205 * @full_on_timeouts: timer values for each scenario in full on state.
3207 struct iwm_sf_cfg_cmd {
3209 uint32_t watermark[IWM_SF_TRANSIENT_STATES_NUMBER];
3210 uint32_t long_delay_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3211 uint32_t full_on_timeouts[IWM_SF_NUM_SCENARIO][IWM_SF_NUM_TIMEOUT_TYPES];
3212 } __packed; /* IWM_SF_CFG_API_S_VER_2 */
3215 * The first MAC indices (starting from 0)
3216 * are available to the driver, AUX follows
3218 #define IWM_MAC_INDEX_AUX 4
3219 #define IWM_MAC_INDEX_MIN_DRIVER 0
3220 #define IWM_NUM_MAC_INDEX_DRIVER IWM_MAC_INDEX_AUX
3231 * enum iwm_mac_protection_flags - MAC context flags
3232 * @IWM_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
3233 * this will require CCK RTS/CTS2self.
3234 * RTS/CTS will protect full burst time.
3235 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
3236 * @IWM_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
3237 * @IWM_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
3239 enum iwm_mac_protection_flags {
3240 IWM_MAC_PROT_FLG_TGG_PROTECT = (1 << 3),
3241 IWM_MAC_PROT_FLG_HT_PROT = (1 << 23),
3242 IWM_MAC_PROT_FLG_FAT_PROT = (1 << 24),
3243 IWM_MAC_PROT_FLG_SELF_CTS_EN = (1 << 30),
3246 #define IWM_MAC_FLG_SHORT_SLOT (1 << 4)
3247 #define IWM_MAC_FLG_SHORT_PREAMBLE (1 << 5)
3250 * enum iwm_mac_types - Supported MAC types
3251 * @IWM_FW_MAC_TYPE_FIRST: lowest supported MAC type
3252 * @IWM_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
3253 * @IWM_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
3254 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
3255 * @IWM_FW_MAC_TYPE_IBSS: IBSS
3256 * @IWM_FW_MAC_TYPE_BSS_STA: BSS (managed) station
3257 * @IWM_FW_MAC_TYPE_P2P_DEVICE: P2P Device
3258 * @IWM_FW_MAC_TYPE_P2P_STA: P2P client
3259 * @IWM_FW_MAC_TYPE_GO: P2P GO
3260 * @IWM_FW_MAC_TYPE_TEST: ?
3261 * @IWM_FW_MAC_TYPE_MAX: highest support MAC type
3263 enum iwm_mac_types {
3264 IWM_FW_MAC_TYPE_FIRST = 1,
3265 IWM_FW_MAC_TYPE_AUX = IWM_FW_MAC_TYPE_FIRST,
3266 IWM_FW_MAC_TYPE_LISTENER,
3267 IWM_FW_MAC_TYPE_PIBSS,
3268 IWM_FW_MAC_TYPE_IBSS,
3269 IWM_FW_MAC_TYPE_BSS_STA,
3270 IWM_FW_MAC_TYPE_P2P_DEVICE,
3271 IWM_FW_MAC_TYPE_P2P_STA,
3273 IWM_FW_MAC_TYPE_TEST,
3274 IWM_FW_MAC_TYPE_MAX = IWM_FW_MAC_TYPE_TEST
3275 }; /* IWM_MAC_CONTEXT_TYPE_API_E_VER_1 */
3278 * enum iwm_tsf_id - TSF hw timer ID
3279 * @IWM_TSF_ID_A: use TSF A
3280 * @IWM_TSF_ID_B: use TSF B
3281 * @IWM_TSF_ID_C: use TSF C
3282 * @IWM_TSF_ID_D: use TSF D
3283 * @IWM_NUM_TSF_IDS: number of TSF timers available
3290 IWM_NUM_TSF_IDS = 4,
3291 }; /* IWM_TSF_ID_API_E_VER_1 */
3294 * struct iwm_mac_data_ap - configuration data for AP MAC context
3295 * @beacon_time: beacon transmit time in system time
3296 * @beacon_tsf: beacon transmit time in TSF
3297 * @bi: beacon interval in TU
3298 * @bi_reciprocal: 2^32 / bi
3299 * @dtim_interval: dtim transmit time in TU
3300 * @dtim_reciprocal: 2^32 / dtim_interval
3301 * @mcast_qid: queue ID for multicast traffic
3302 * @beacon_template: beacon template ID
3304 struct iwm_mac_data_ap {
3305 uint32_t beacon_time;
3306 uint64_t beacon_tsf;
3308 uint32_t bi_reciprocal;
3309 uint32_t dtim_interval;
3310 uint32_t dtim_reciprocal;
3312 uint32_t beacon_template;
3313 } __packed; /* AP_MAC_DATA_API_S_VER_1 */
3316 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3317 * @beacon_time: beacon transmit time in system time
3318 * @beacon_tsf: beacon transmit time in TSF
3319 * @bi: beacon interval in TU
3320 * @bi_reciprocal: 2^32 / bi
3321 * @beacon_template: beacon template ID
3323 struct iwm_mac_data_ibss {
3324 uint32_t beacon_time;
3325 uint64_t beacon_tsf;
3327 uint32_t bi_reciprocal;
3328 uint32_t beacon_template;
3329 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
3332 * struct iwm_mac_data_sta - configuration data for station MAC context
3333 * @is_assoc: 1 for associated state, 0 otherwise
3334 * @dtim_time: DTIM arrival time in system time
3335 * @dtim_tsf: DTIM arrival time in TSF
3336 * @bi: beacon interval in TU, applicable only when associated
3337 * @bi_reciprocal: 2^32 / bi , applicable only when associated
3338 * @dtim_interval: DTIM interval in TU, applicable only when associated
3339 * @dtim_reciprocal: 2^32 / dtim_interval , applicable only when associated
3340 * @listen_interval: in beacon intervals, applicable only when associated
3341 * @assoc_id: unique ID assigned by the AP during association
3343 struct iwm_mac_data_sta {
3348 uint32_t bi_reciprocal;
3349 uint32_t dtim_interval;
3350 uint32_t dtim_reciprocal;
3351 uint32_t listen_interval;
3353 uint32_t assoc_beacon_arrive_time;
3354 } __packed; /* IWM_STA_MAC_DATA_API_S_VER_1 */
3357 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3358 * @ap: iwm_mac_data_ap struct with most config data
3359 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3360 * 0 indicates that there is no CT window.
3361 * @opp_ps_enabled: indicate that opportunistic PS allowed
3363 struct iwm_mac_data_go {
3364 struct iwm_mac_data_ap ap;
3366 uint32_t opp_ps_enabled;
3367 } __packed; /* GO_MAC_DATA_API_S_VER_1 */
3370 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3371 * @sta: iwm_mac_data_sta struct with most config data
3372 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
3373 * 0 indicates that there is no CT window.
3375 struct iwm_mac_data_p2p_sta {
3376 struct iwm_mac_data_sta sta;
3378 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
3381 * struct iwm_mac_data_pibss - Pseudo IBSS config data
3382 * @stats_interval: interval in TU between statistics notifications to host.
3384 struct iwm_mac_data_pibss {
3385 uint32_t stats_interval;
3386 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
3389 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
3391 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
3392 * other channels as well. This should be to true only in case that the
3393 * device is discoverable and there is an active GO. Note that setting this
3394 * field when not needed, will increase the number of interrupts and have
3395 * effect on the platform power, as this setting opens the Rx filters on
3398 struct iwm_mac_data_p2p_dev {
3399 uint32_t is_disc_extended;
3400 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
3403 * enum iwm_mac_filter_flags - MAC context filter flags
3404 * @IWM_MAC_FILTER_IN_PROMISC: accept all data frames
3405 * @IWM_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all mangement and
3406 * control frames to the host
3407 * @IWM_MAC_FILTER_ACCEPT_GRP: accept multicast frames
3408 * @IWM_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
3409 * @IWM_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
3410 * @IWM_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
3411 * (in station mode when associated)
3412 * @IWM_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
3413 * @IWM_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
3414 * @IWM_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
3416 enum iwm_mac_filter_flags {
3417 IWM_MAC_FILTER_IN_PROMISC = (1 << 0),
3418 IWM_MAC_FILTER_IN_CONTROL_AND_MGMT = (1 << 1),
3419 IWM_MAC_FILTER_ACCEPT_GRP = (1 << 2),
3420 IWM_MAC_FILTER_DIS_DECRYPT = (1 << 3),
3421 IWM_MAC_FILTER_DIS_GRP_DECRYPT = (1 << 4),
3422 IWM_MAC_FILTER_IN_BEACON = (1 << 6),
3423 IWM_MAC_FILTER_OUT_BCAST = (1 << 8),
3424 IWM_MAC_FILTER_IN_CRC32 = (1 << 11),
3425 IWM_MAC_FILTER_IN_PROBE_REQUEST = (1 << 12),
3429 * enum iwm_mac_qos_flags - QoS flags
3430 * @IWM_MAC_QOS_FLG_UPDATE_EDCA: ?
3431 * @IWM_MAC_QOS_FLG_TGN: HT is enabled
3432 * @IWM_MAC_QOS_FLG_TXOP_TYPE: ?
3435 enum iwm_mac_qos_flags {
3436 IWM_MAC_QOS_FLG_UPDATE_EDCA = (1 << 0),
3437 IWM_MAC_QOS_FLG_TGN = (1 << 1),
3438 IWM_MAC_QOS_FLG_TXOP_TYPE = (1 << 4),
3442 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
3443 * @cw_min: Contention window, start value in numbers of slots.
3444 * Should be a power-of-2, minus 1. Device's default is 0x0f.
3445 * @cw_max: Contention window, max value in numbers of slots.
3446 * Should be a power-of-2, minus 1. Device's default is 0x3f.
3447 * @aifsn: Number of slots in Arbitration Interframe Space (before
3448 * performing random backoff timing prior to Tx). Device default 1.
3449 * @fifos_mask: FIFOs used by this MAC for this AC
3450 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
3452 * One instance of this config struct for each of 4 EDCA access categories
3453 * in struct iwm_qosparam_cmd.
3455 * Device will automatically increase contention window by (2*CW) + 1 for each
3456 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
3457 * value, to cap the CW value.
3465 } __packed; /* IWM_AC_QOS_API_S_VER_2 */
3468 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
3469 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
3470 * @id_and_color: ID and color of the MAC
3471 * @action: action to perform, one of IWM_FW_CTXT_ACTION_*
3472 * @mac_type: one of IWM_FW_MAC_TYPE_*
3473 * @tsd_id: TSF HW timer, one of IWM_TSF_ID_*
3474 * @node_addr: MAC address
3475 * @bssid_addr: BSSID
3476 * @cck_rates: basic rates available for CCK
3477 * @ofdm_rates: basic rates available for OFDM
3478 * @protection_flags: combination of IWM_MAC_PROT_FLG_FLAG_*
3479 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
3480 * @short_slot: 0x10 for enabling short slots, 0 otherwise
3481 * @filter_flags: combination of IWM_MAC_FILTER_*
3482 * @qos_flags: from IWM_MAC_QOS_FLG_*
3483 * @ac: one iwm_mac_qos configuration for each AC
3484 * @mac_specific: one of struct iwm_mac_data_*, according to mac_type
3486 struct iwm_mac_ctx_cmd {
3487 /* COMMON_INDEX_HDR_API_S_VER_1 */
3488 uint32_t id_and_color;
3490 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
3493 uint8_t node_addr[6];
3494 uint16_t reserved_for_node_addr;
3495 uint8_t bssid_addr[6];
3496 uint16_t reserved_for_bssid_addr;
3498 uint32_t ofdm_rates;
3499 uint32_t protection_flags;
3500 uint32_t cck_short_preamble;
3501 uint32_t short_slot;
3502 uint32_t filter_flags;
3503 /* IWM_MAC_QOS_PARAM_API_S_VER_1 */
3505 struct iwm_ac_qos ac[IWM_AC_NUM+1];
3506 /* IWM_MAC_CONTEXT_COMMON_DATA_API_S */
3508 struct iwm_mac_data_ap ap;
3509 struct iwm_mac_data_go go;
3510 struct iwm_mac_data_sta sta;
3511 struct iwm_mac_data_p2p_sta p2p_sta;
3512 struct iwm_mac_data_p2p_dev p2p_dev;
3513 struct iwm_mac_data_pibss pibss;
3514 struct iwm_mac_data_ibss ibss;
3516 } __packed; /* IWM_MAC_CONTEXT_CMD_API_S_VER_1 */
3518 static inline uint32_t iwm_mvm_reciprocal(uint32_t v)
3522 return 0xFFFFFFFF / v;
3525 #define IWM_NONQOS_SEQ_GET 0x1
3526 #define IWM_NONQOS_SEQ_SET 0x2
3527 struct iwm_nonqos_seq_query_cmd {
3528 uint32_t get_set_flag;
3529 uint32_t mac_id_n_color;
3532 } __packed; /* IWM_NON_QOS_TX_COUNTER_GET_SET_API_S_VER_1 */
3534 /* Power Management Commands, Responses, Notifications */
3536 /* Radio LP RX Energy Threshold measured in dBm */
3537 #define IWM_POWER_LPRX_RSSI_THRESHOLD 75
3538 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MAX 94
3539 #define IWM_POWER_LPRX_RSSI_THRESHOLD_MIN 30
3542 * enum iwm_scan_flags - masks for power table command flags
3543 * @IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3544 * receiver and transmitter. '0' - does not allow.
3545 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
3546 * '1' Driver enables PM (use rest of parameters)
3547 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
3548 * '1' PM could sleep over DTIM till listen Interval.
3549 * @IWM_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
3550 * access categories are both delivery and trigger enabled.
3551 * @IWM_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
3552 * PBW Snoozing enabled
3553 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
3554 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
3555 * @IWM_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
3556 * detection enablement
3558 enum iwm_power_flags {
3559 IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3560 IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK = (1 << 1),
3561 IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK = (1 << 2),
3562 IWM_POWER_FLAGS_SNOOZE_ENA_MSK = (1 << 5),
3563 IWM_POWER_FLAGS_BT_SCO_ENA = (1 << 8),
3564 IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK = (1 << 9),
3565 IWM_POWER_FLAGS_LPRX_ENA_MSK = (1 << 11),
3566 IWM_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK = (1 << 12),
3569 #define IWM_POWER_VEC_SIZE 5
3572 * struct iwm_powertable_cmd - legacy power command. Beside old API support this
3573 * is used also with a new power API for device wide power settings.
3574 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
3576 * @flags: Power table command flags from IWM_POWER_FLAGS_*
3577 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3578 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3579 * set regardless of power scheme or current power state.
3580 * FW use this value also when PM is disabled.
3581 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3582 * PSM transition - legacy PM
3583 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3584 * PSM transition - legacy PM
3585 * @sleep_interval: not in use
3586 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3587 * is set. For example, if it is required to skip over
3588 * one DTIM, this value need to be set to 2 (DTIM periods).
3589 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3592 struct iwm_powertable_cmd {
3593 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3595 uint8_t keep_alive_seconds;
3596 uint8_t debug_flags;
3597 uint32_t rx_data_timeout;
3598 uint32_t tx_data_timeout;
3599 uint32_t sleep_interval[IWM_POWER_VEC_SIZE];
3600 uint32_t skip_dtim_periods;
3601 uint32_t lprx_rssi_threshold;
3605 * enum iwm_device_power_flags - masks for device power command flags
3606 * @DEVIC_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
3607 * receiver and transmitter. '0' - does not allow. This flag should be
3608 * always set to '1' unless one need to disable actual power down for debug
3610 * @IWM_DEVICE_POWER_FLAGS_CAM_MSK: '1' CAM (Continuous Active Mode) is set, meaning
3611 * that power management is disabled. '0' Power management is enabled, one
3612 * of power schemes is applied.
3614 enum iwm_device_power_flags {
3615 IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK = (1 << 0),
3616 IWM_DEVICE_POWER_FLAGS_CAM_MSK = (1 << 13),
3620 * struct iwm_device_power_cmd - device wide power command.
3621 * IWM_DEVICE_POWER_CMD = 0x77 (command, has simple generic response)
3623 * @flags: Power table command flags from IWM_DEVICE_POWER_FLAGS_*
3625 struct iwm_device_power_cmd {
3626 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
3632 * struct iwm_mac_power_cmd - New power command containing uAPSD support
3633 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
3634 * @id_and_color: MAC contex identifier
3635 * @flags: Power table command flags from POWER_FLAGS_*
3636 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
3637 * Minimum allowed:- 3 * DTIM. Keep alive period must be
3638 * set regardless of power scheme or current power state.
3639 * FW use this value also when PM is disabled.
3640 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
3641 * PSM transition - legacy PM
3642 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
3643 * PSM transition - legacy PM
3644 * @sleep_interval: not in use
3645 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
3646 * is set. For example, if it is required to skip over
3647 * one DTIM, this value need to be set to 2 (DTIM periods).
3648 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
3649 * PSM transition - uAPSD
3650 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
3651 * PSM transition - uAPSD
3652 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
3654 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
3655 * @snooze_interval: Maximum time between attempts to retrieve buffered data
3656 * from the AP [msec]
3657 * @snooze_window: A window of time in which PBW snoozing insures that all
3658 * packets received. It is also the minimum time from last
3659 * received unicast RX packet, before client stops snoozing
3662 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
3663 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
3664 * each corresponding AC.
3665 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
3666 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
3668 * @heavy_tx_thld_packets: TX threshold measured in number of packets
3669 * @heavy_rx_thld_packets: RX threshold measured in number of packets
3670 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
3671 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
3672 * @limited_ps_threshold:
3674 struct iwm_mac_power_cmd {
3675 /* CONTEXT_DESC_API_T_VER_1 */
3676 uint32_t id_and_color;
3678 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
3680 uint16_t keep_alive_seconds;
3681 uint32_t rx_data_timeout;
3682 uint32_t tx_data_timeout;
3683 uint32_t rx_data_timeout_uapsd;
3684 uint32_t tx_data_timeout_uapsd;
3685 uint8_t lprx_rssi_threshold;
3686 uint8_t skip_dtim_periods;
3687 uint16_t snooze_interval;
3688 uint16_t snooze_window;
3689 uint8_t snooze_step;
3691 uint8_t uapsd_ac_flags;
3692 uint8_t uapsd_max_sp;
3693 uint8_t heavy_tx_thld_packets;
3694 uint8_t heavy_rx_thld_packets;
3695 uint8_t heavy_tx_thld_percentage;
3696 uint8_t heavy_rx_thld_percentage;
3697 uint8_t limited_ps_threshold;
3702 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
3703 * associated AP is identified as improperly implementing uAPSD protocol.
3704 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
3705 * @sta_id: index of station in uCode's station table - associated AP ID in
3708 struct iwm_uapsd_misbehaving_ap_notif {
3711 uint8_t reserved[3];
3715 * struct iwm_beacon_filter_cmd
3716 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
3717 * @id_and_color: MAC contex identifier
3718 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
3719 * to driver if delta in Energy values calculated for this and last
3720 * passed beacon is greater than this threshold. Zero value means that
3721 * the Energy change is ignored for beacon filtering, and beacon will
3722 * not be forced to be sent to driver regardless of this delta. Typical
3724 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
3725 * Send beacon to driver if delta in Energy values calculated for this
3726 * and last passed beacon is greater than this threshold. Zero value
3727 * means that the Energy change is ignored for beacon filtering while in
3728 * Roaming state, typical energy delta 1dB.
3729 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
3730 * calculated for current beacon is less than the threshold, use
3731 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
3732 * Threshold. Typical energy threshold is -72dBm.
3733 * @bf_temp_threshold: This threshold determines the type of temperature
3734 * filtering (Slow or Fast) that is selected (Units are in Celsuis):
3735 * If the current temperature is above this threshold - Fast filter
3736 * will be used, If the current temperature is below this threshold -
3737 * Slow filter will be used.
3738 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
3739 * calculated for this and the last passed beacon is greater than this
3740 * threshold. Zero value means that the temperature change is ignored for
3741 * beacon filtering; beacons will not be forced to be sent to driver
3742 * regardless of whether its temperature has been changed.
3743 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
3744 * calculated for this and the last passed beacon is greater than this
3745 * threshold. Zero value means that the temperature change is ignored for
3746 * beacon filtering; beacons will not be forced to be sent to driver
3747 * regardless of whether its temperature has been changed.
3748 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
3749 * @bf_filter_escape_timer: Send beacons to to driver if no beacons were passed
3750 * for a specific period of time. Units: Beacons.
3751 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
3752 * for a longer period of time then this escape-timeout. Units: Beacons.
3753 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
3755 struct iwm_beacon_filter_cmd {
3756 uint32_t bf_energy_delta;
3757 uint32_t bf_roaming_energy_delta;
3758 uint32_t bf_roaming_state;
3759 uint32_t bf_temp_threshold;
3760 uint32_t bf_temp_fast_filter;
3761 uint32_t bf_temp_slow_filter;
3762 uint32_t bf_enable_beacon_filter;
3763 uint32_t bf_debug_flag;
3764 uint32_t bf_escape_timer;
3765 uint32_t ba_escape_timer;
3766 uint32_t ba_enable_beacon_abort;
3769 /* Beacon filtering and beacon abort */
3770 #define IWM_BF_ENERGY_DELTA_DEFAULT 5
3771 #define IWM_BF_ENERGY_DELTA_MAX 255
3772 #define IWM_BF_ENERGY_DELTA_MIN 0
3774 #define IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
3775 #define IWM_BF_ROAMING_ENERGY_DELTA_MAX 255
3776 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
3778 #define IWM_BF_ROAMING_STATE_DEFAULT 72
3779 #define IWM_BF_ROAMING_STATE_MAX 255
3780 #define IWM_BF_ROAMING_STATE_MIN 0
3782 #define IWM_BF_TEMP_THRESHOLD_DEFAULT 112
3783 #define IWM_BF_TEMP_THRESHOLD_MAX 255
3784 #define IWM_BF_TEMP_THRESHOLD_MIN 0
3786 #define IWM_BF_TEMP_FAST_FILTER_DEFAULT 1
3787 #define IWM_BF_TEMP_FAST_FILTER_MAX 255
3788 #define IWM_BF_TEMP_FAST_FILTER_MIN 0
3790 #define IWM_BF_TEMP_SLOW_FILTER_DEFAULT 5
3791 #define IWM_BF_TEMP_SLOW_FILTER_MAX 255
3792 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0
3794 #define IWM_BF_ENABLE_BEACON_FILTER_DEFAULT 1
3796 #define IWM_BF_DEBUG_FLAG_DEFAULT 0
3798 #define IWM_BF_ESCAPE_TIMER_DEFAULT 50
3799 #define IWM_BF_ESCAPE_TIMER_MAX 1024
3800 #define IWM_BF_ESCAPE_TIMER_MIN 0
3802 #define IWM_BA_ESCAPE_TIMER_DEFAULT 6
3803 #define IWM_BA_ESCAPE_TIMER_D3 9
3804 #define IWM_BA_ESCAPE_TIMER_MAX 1024
3805 #define IWM_BA_ESCAPE_TIMER_MIN 0
3807 #define IWM_BA_ENABLE_BEACON_ABORT_DEFAULT 1
3809 #define IWM_BF_CMD_CONFIG_DEFAULTS \
3810 .bf_energy_delta = htole32(IWM_BF_ENERGY_DELTA_DEFAULT), \
3811 .bf_roaming_energy_delta = \
3812 htole32(IWM_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
3813 .bf_roaming_state = htole32(IWM_BF_ROAMING_STATE_DEFAULT), \
3814 .bf_temp_threshold = htole32(IWM_BF_TEMP_THRESHOLD_DEFAULT), \
3815 .bf_temp_fast_filter = htole32(IWM_BF_TEMP_FAST_FILTER_DEFAULT), \
3816 .bf_temp_slow_filter = htole32(IWM_BF_TEMP_SLOW_FILTER_DEFAULT), \
3817 .bf_debug_flag = htole32(IWM_BF_DEBUG_FLAG_DEFAULT), \
3818 .bf_escape_timer = htole32(IWM_BF_ESCAPE_TIMER_DEFAULT), \
3819 .ba_escape_timer = htole32(IWM_BA_ESCAPE_TIMER_DEFAULT)
3822 * These serve as indexes into
3823 * struct iwm_rate_info fw_rate_idx_to_plcp[IWM_RATE_COUNT];
3824 * TODO: avoid overlap between legacy and HT rates
3827 IWM_RATE_1M_INDEX = 0,
3828 IWM_FIRST_CCK_RATE = IWM_RATE_1M_INDEX,
3832 IWM_LAST_CCK_RATE = IWM_RATE_11M_INDEX,
3834 IWM_FIRST_OFDM_RATE = IWM_RATE_6M_INDEX,
3835 IWM_RATE_MCS_0_INDEX = IWM_RATE_6M_INDEX,
3836 IWM_FIRST_HT_RATE = IWM_RATE_MCS_0_INDEX,
3837 IWM_FIRST_VHT_RATE = IWM_RATE_MCS_0_INDEX,
3840 IWM_RATE_MCS_1_INDEX = IWM_RATE_12M_INDEX,
3842 IWM_RATE_MCS_2_INDEX = IWM_RATE_18M_INDEX,
3844 IWM_RATE_MCS_3_INDEX = IWM_RATE_24M_INDEX,
3846 IWM_RATE_MCS_4_INDEX = IWM_RATE_36M_INDEX,
3848 IWM_RATE_MCS_5_INDEX = IWM_RATE_48M_INDEX,
3850 IWM_RATE_MCS_6_INDEX = IWM_RATE_54M_INDEX,
3851 IWM_LAST_NON_HT_RATE = IWM_RATE_54M_INDEX,
3853 IWM_RATE_MCS_7_INDEX = IWM_RATE_60M_INDEX,
3854 IWM_LAST_HT_RATE = IWM_RATE_MCS_7_INDEX,
3855 IWM_RATE_MCS_8_INDEX,
3856 IWM_RATE_MCS_9_INDEX,
3857 IWM_LAST_VHT_RATE = IWM_RATE_MCS_9_INDEX,
3858 IWM_RATE_COUNT_LEGACY = IWM_LAST_NON_HT_RATE + 1,
3859 IWM_RATE_COUNT = IWM_LAST_VHT_RATE + 1,
3862 #define IWM_RATE_BIT_MSK(r) (1 << (IWM_RATE_##r##M_INDEX))
3864 /* fw API values for legacy bit rates, both OFDM and CCK */
3866 IWM_RATE_6M_PLCP = 13,
3867 IWM_RATE_9M_PLCP = 15,
3868 IWM_RATE_12M_PLCP = 5,
3869 IWM_RATE_18M_PLCP = 7,
3870 IWM_RATE_24M_PLCP = 9,
3871 IWM_RATE_36M_PLCP = 11,
3872 IWM_RATE_48M_PLCP = 1,
3873 IWM_RATE_54M_PLCP = 3,
3874 IWM_RATE_1M_PLCP = 10,
3875 IWM_RATE_2M_PLCP = 20,
3876 IWM_RATE_5M_PLCP = 55,
3877 IWM_RATE_11M_PLCP = 110,
3878 IWM_RATE_INVM_PLCP = -1,
3882 * rate_n_flags bit fields
3884 * The 32-bit value has different layouts in the low 8 bites depending on the
3885 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
3886 * for CCK and OFDM).
3888 * High-throughput (HT) rate format
3889 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
3890 * Very High-throughput (VHT) rate format
3891 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
3892 * Legacy OFDM rate format for bits 7:0
3893 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
3894 * Legacy CCK rate format for bits 7:0:
3895 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
3898 /* Bit 8: (1) HT format, (0) legacy or VHT format */
3899 #define IWM_RATE_MCS_HT_POS 8
3900 #define IWM_RATE_MCS_HT_MSK (1 << IWM_RATE_MCS_HT_POS)
3902 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
3903 #define IWM_RATE_MCS_CCK_POS 9
3904 #define IWM_RATE_MCS_CCK_MSK (1 << IWM_RATE_MCS_CCK_POS)
3906 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
3907 #define IWM_RATE_MCS_VHT_POS 26
3908 #define IWM_RATE_MCS_VHT_MSK (1 << IWM_RATE_MCS_VHT_POS)
3912 * High-throughput (HT) rate format for bits 7:0
3914 * 2-0: MCS rate base
3923 * 4-3: 0) Single stream (SISO)
3924 * 1) Dual stream (MIMO)
3925 * 2) Triple stream (MIMO)
3926 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
3927 * (bits 7-6 are zero)
3929 * Together the low 5 bits work out to the MCS index because we don't
3930 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
3931 * streams and 16-23 have three streams. We could also support MCS 32
3932 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
3934 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
3935 #define IWM_RATE_HT_MCS_NSS_POS 3
3936 #define IWM_RATE_HT_MCS_NSS_MSK (3 << IWM_RATE_HT_MCS_NSS_POS)
3938 /* Bit 10: (1) Use Green Field preamble */
3939 #define IWM_RATE_HT_MCS_GF_POS 10
3940 #define IWM_RATE_HT_MCS_GF_MSK (1 << IWM_RATE_HT_MCS_GF_POS)
3942 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
3945 * Very High-throughput (VHT) rate format for bits 7:0
3947 * 3-0: VHT MCS (0-9)
3948 * 5-4: number of streams - 1:
3949 * 0) Single stream (SISO)
3950 * 1) Dual stream (MIMO)
3951 * 2) Triple stream (MIMO)
3954 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
3955 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
3956 #define IWM_RATE_VHT_MCS_NSS_POS 4
3957 #define IWM_RATE_VHT_MCS_NSS_MSK (3 << IWM_RATE_VHT_MCS_NSS_POS)
3960 * Legacy OFDM rate format for bits 7:0
3972 * Legacy CCK rate format for bits 7:0:
3973 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
3981 #define IWM_RATE_LEGACY_RATE_MSK 0xff
3985 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
3986 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
3988 #define IWM_RATE_MCS_CHAN_WIDTH_POS 11
3989 #define IWM_RATE_MCS_CHAN_WIDTH_MSK (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3990 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3991 #define IWM_RATE_MCS_CHAN_WIDTH_40 (1 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3992 #define IWM_RATE_MCS_CHAN_WIDTH_80 (2 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3993 #define IWM_RATE_MCS_CHAN_WIDTH_160 (3 << IWM_RATE_MCS_CHAN_WIDTH_POS)
3995 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
3996 #define IWM_RATE_MCS_SGI_POS 13
3997 #define IWM_RATE_MCS_SGI_MSK (1 << IWM_RATE_MCS_SGI_POS)
3999 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
4000 #define IWM_RATE_MCS_ANT_POS 14
4001 #define IWM_RATE_MCS_ANT_A_MSK (1 << IWM_RATE_MCS_ANT_POS)
4002 #define IWM_RATE_MCS_ANT_B_MSK (2 << IWM_RATE_MCS_ANT_POS)
4003 #define IWM_RATE_MCS_ANT_C_MSK (4 << IWM_RATE_MCS_ANT_POS)
4004 #define IWM_RATE_MCS_ANT_AB_MSK (IWM_RATE_MCS_ANT_A_MSK | \
4005 IWM_RATE_MCS_ANT_B_MSK)
4006 #define IWM_RATE_MCS_ANT_ABC_MSK (IWM_RATE_MCS_ANT_AB_MSK | \
4007 IWM_RATE_MCS_ANT_C_MSK)
4008 #define IWM_RATE_MCS_ANT_MSK IWM_RATE_MCS_ANT_ABC_MSK
4009 #define IWM_RATE_MCS_ANT_NUM 3
4011 /* Bit 17-18: (0) SS, (1) SS*2 */
4012 #define IWM_RATE_MCS_STBC_POS 17
4013 #define IWM_RATE_MCS_STBC_MSK (1 << IWM_RATE_MCS_STBC_POS)
4015 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
4016 #define IWM_RATE_MCS_BF_POS 19
4017 #define IWM_RATE_MCS_BF_MSK (1 << IWM_RATE_MCS_BF_POS)
4019 /* Bit 20: (0) ZLF is off, (1) ZLF is on */
4020 #define IWM_RATE_MCS_ZLF_POS 20
4021 #define IWM_RATE_MCS_ZLF_MSK (1 << IWM_RATE_MCS_ZLF_POS)
4023 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
4024 #define IWM_RATE_MCS_DUP_POS 24
4025 #define IWM_RATE_MCS_DUP_MSK (3 << IWM_RATE_MCS_DUP_POS)
4027 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
4028 #define IWM_RATE_MCS_LDPC_POS 27
4029 #define IWM_RATE_MCS_LDPC_MSK (1 << IWM_RATE_MCS_LDPC_POS)
4032 /* Link Quality definitions */
4034 /* # entries in rate scale table to support Tx retries */
4035 #define IWM_LQ_MAX_RETRY_NUM 16
4037 /* Link quality command flags bit fields */
4039 /* Bit 0: (0) Don't use RTS (1) Use RTS */
4040 #define IWM_LQ_FLAG_USE_RTS_POS 0
4041 #define IWM_LQ_FLAG_USE_RTS_MSK (1 << IWM_LQ_FLAG_USE_RTS_POS)
4043 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
4044 #define IWM_LQ_FLAG_COLOR_POS 1
4045 #define IWM_LQ_FLAG_COLOR_MSK (7 << IWM_LQ_FLAG_COLOR_POS)
4047 /* Bit 4-5: Tx RTS BW Signalling
4048 * (0) No RTS BW signalling
4049 * (1) Static BW signalling
4050 * (2) Dynamic BW signalling
4052 #define IWM_LQ_FLAG_RTS_BW_SIG_POS 4
4053 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4054 #define IWM_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4055 #define IWM_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4057 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
4058 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
4060 #define IWM_LQ_FLAG_DYNAMIC_BW_POS 6
4061 #define IWM_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWM_LQ_FLAG_DYNAMIC_BW_POS)
4064 * struct iwm_lq_cmd - link quality command
4065 * @sta_id: station to update
4066 * @control: not used
4067 * @flags: combination of IWM_LQ_FLAG_*
4068 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
4070 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
4071 * Should be ANT_[ABC]
4072 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
4073 * @initial_rate_index: first index from rs_table per AC category
4074 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
4075 * value of 100 is one usec. Range is 100 to 8000
4076 * @agg_disable_start_th: try-count threshold for starting aggregation.
4077 * If a frame has higher try-count, it should not be selected for
4078 * starting an aggregation sequence.
4079 * @agg_frame_cnt_limit: max frame count in an aggregation.
4081 * 1: no aggregation (one frame per aggregation)
4082 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
4083 * @rs_table: array of rates for each TX try, each is rate_n_flags,
4084 * meaning it is a combination of IWM_RATE_MCS_* and IWM_RATE_*_PLCP
4085 * @bf_params: beam forming params, currently not used
4091 /* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
4094 uint8_t single_stream_ant_msk;
4095 uint8_t dual_stream_ant_msk;
4096 uint8_t initial_rate_index[IWM_AC_NUM];
4097 /* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
4098 uint16_t agg_time_limit;
4099 uint8_t agg_disable_start_th;
4100 uint8_t agg_frame_cnt_limit;
4102 uint32_t rs_table[IWM_LQ_MAX_RETRY_NUM];
4104 }; /* LINK_QUALITY_CMD_API_S_VER_1 */
4107 * enum iwm_tx_flags - bitmasks for tx_flags in TX command
4108 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
4109 * @IWM_TX_CMD_FLG_ACK: expect ACK from receiving station
4110 * @IWM_TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
4111 * Otherwise, use rate_n_flags from the TX command
4112 * @IWM_TX_CMD_FLG_BA: this frame is a block ack
4113 * @IWM_TX_CMD_FLG_BAR: this frame is a BA request, immediate BAR is expected
4114 * Must set IWM_TX_CMD_FLG_ACK with this flag.
4115 * @IWM_TX_CMD_FLG_TXOP_PROT: protect frame with full TXOP protection
4116 * @IWM_TX_CMD_FLG_VHT_NDPA: mark frame is NDPA for VHT beamformer sequence
4117 * @IWM_TX_CMD_FLG_HT_NDPA: mark frame is NDPA for HT beamformer sequence
4118 * @IWM_TX_CMD_FLG_CSI_FDBK2HOST: mark to send feedback to host (only if good CRC)
4119 * @IWM_TX_CMD_FLG_BT_DIS: disable BT priority for this frame
4120 * @IWM_TX_CMD_FLG_SEQ_CTL: set if FW should override the sequence control.
4121 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
4122 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
4123 * @IWM_TX_CMD_FLG_NEXT_FRAME: this frame includes information of the next frame
4124 * @IWM_TX_CMD_FLG_TSF: FW should calculate and insert TSF in the frame
4125 * Should be set for beacons and probe responses
4126 * @IWM_TX_CMD_FLG_CALIB: activate PA TX power calibrations
4127 * @IWM_TX_CMD_FLG_KEEP_SEQ_CTL: if seq_ctl is set, don't increase inner seq count
4128 * @IWM_TX_CMD_FLG_AGG_START: allow this frame to start aggregation
4129 * @IWM_TX_CMD_FLG_MH_PAD: driver inserted 2 byte padding after MAC header.
4130 * Should be set for 26/30 length MAC headers
4131 * @IWM_TX_CMD_FLG_RESP_TO_DRV: zero this if the response should go only to FW
4132 * @IWM_TX_CMD_FLG_CCMP_AGG: this frame uses CCMP for aggregation acceleration
4133 * @IWM_TX_CMD_FLG_TKIP_MIC_DONE: FW already performed TKIP MIC calculation
4134 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
4135 * @IWM_TX_CMD_FLG_FW_DROP: FW should mark frame to be dropped
4136 * @IWM_TX_CMD_FLG_EXEC_PAPD: execute PAPD
4137 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
4138 * @IWM_TX_CMD_FLG_HCCA_CHUNK: mark start of TSPEC chunk
4141 IWM_TX_CMD_FLG_PROT_REQUIRE = (1 << 0),
4142 IWM_TX_CMD_FLG_ACK = (1 << 3),
4143 IWM_TX_CMD_FLG_STA_RATE = (1 << 4),
4144 IWM_TX_CMD_FLG_BA = (1 << 5),
4145 IWM_TX_CMD_FLG_BAR = (1 << 6),
4146 IWM_TX_CMD_FLG_TXOP_PROT = (1 << 7),
4147 IWM_TX_CMD_FLG_VHT_NDPA = (1 << 8),
4148 IWM_TX_CMD_FLG_HT_NDPA = (1 << 9),
4149 IWM_TX_CMD_FLG_CSI_FDBK2HOST = (1 << 10),
4150 IWM_TX_CMD_FLG_BT_DIS = (1 << 12),
4151 IWM_TX_CMD_FLG_SEQ_CTL = (1 << 13),
4152 IWM_TX_CMD_FLG_MORE_FRAG = (1 << 14),
4153 IWM_TX_CMD_FLG_NEXT_FRAME = (1 << 15),
4154 IWM_TX_CMD_FLG_TSF = (1 << 16),
4155 IWM_TX_CMD_FLG_CALIB = (1 << 17),
4156 IWM_TX_CMD_FLG_KEEP_SEQ_CTL = (1 << 18),
4157 IWM_TX_CMD_FLG_AGG_START = (1 << 19),
4158 IWM_TX_CMD_FLG_MH_PAD = (1 << 20),
4159 IWM_TX_CMD_FLG_RESP_TO_DRV = (1 << 21),
4160 IWM_TX_CMD_FLG_CCMP_AGG = (1 << 22),
4161 IWM_TX_CMD_FLG_TKIP_MIC_DONE = (1 << 23),
4162 IWM_TX_CMD_FLG_DUR = (1 << 25),
4163 IWM_TX_CMD_FLG_FW_DROP = (1 << 26),
4164 IWM_TX_CMD_FLG_EXEC_PAPD = (1 << 27),
4165 IWM_TX_CMD_FLG_PAPD_TYPE = (1 << 28),
4166 IWM_TX_CMD_FLG_HCCA_CHUNK = (1 << 31)
4167 }; /* IWM_TX_FLAGS_BITS_API_S_VER_1 */
4170 * enum iwm_tx_pm_timeouts - pm timeout values in TX command
4171 * @IWM_PM_FRAME_NONE: no need to suspend sleep mode
4172 * @IWM_PM_FRAME_MGMT: fw suspend sleep mode for 100TU
4173 * @IWM_PM_FRAME_ASSOC: fw suspend sleep mode for 10sec
4175 enum iwm_tx_pm_timeouts {
4176 IWM_PM_FRAME_NONE = 0,
4177 IWM_PM_FRAME_MGMT = 2,
4178 IWM_PM_FRAME_ASSOC = 3,
4182 * TX command security control
4184 #define IWM_TX_CMD_SEC_WEP 0x01
4185 #define IWM_TX_CMD_SEC_CCM 0x02
4186 #define IWM_TX_CMD_SEC_TKIP 0x03
4187 #define IWM_TX_CMD_SEC_EXT 0x04
4188 #define IWM_TX_CMD_SEC_MSK 0x07
4189 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_POS 6
4190 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
4191 #define IWM_TX_CMD_SEC_KEY128 0x08
4193 /* TODO: how does these values are OK with only 16 bit variable??? */
4195 * TX command next frame info
4197 * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
4198 * bit 3 - immediate ACK required
4199 * bit 4 - rate is taken from STA table
4200 * bit 5 - frame belongs to BA stream
4201 * bit 6 - immediate BA response expected
4203 * bits 8:15 - Station ID
4206 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
4207 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
4208 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
4209 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
4210 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
4211 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
4212 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
4213 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
4214 #define IWM_TX_CMD_NEXT_FRAME_RATE_POS (16)
4217 * TX command Frame life time in us - to be written in pm_frame_timeout
4219 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
4220 #define IWM_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
4221 #define IWM_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
4222 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
4225 * TID for non QoS frames - to be written in tid_tspec
4227 #define IWM_TID_NON_QOS IWM_MAX_TID_COUNT
4230 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
4232 #define IWM_DEFAULT_TX_RETRY 15
4233 #define IWM_MGMT_DFAULT_RETRY_LIMIT 3
4234 #define IWM_RTS_DFAULT_RETRY_LIMIT 60
4235 #define IWM_BAR_DFAULT_RETRY_LIMIT 60
4236 #define IWM_LOW_RETRY_LIMIT 7
4238 /* TODO: complete documentation for try_cnt and btkill_cnt */
4240 * struct iwm_tx_cmd - TX command struct to FW
4241 * ( IWM_TX_CMD = 0x1c )
4242 * @len: in bytes of the payload, see below for details
4243 * @next_frame_len: same as len, but for next frame (0 if not applicable)
4244 * Used for fragmentation and bursting, but not in 11n aggregation.
4245 * @tx_flags: combination of IWM_TX_CMD_FLG_*
4246 * @rate_n_flags: rate for *all* Tx attempts, if IWM_TX_CMD_FLG_STA_RATE_MSK is
4247 * cleared. Combination of IWM_RATE_MCS_*
4248 * @sta_id: index of destination station in FW station table
4249 * @sec_ctl: security control, IWM_TX_CMD_SEC_*
4250 * @initial_rate_index: index into the rate table for initial TX attempt.
4251 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
4252 * @key: security key
4253 * @next_frame_flags: IWM_TX_CMD_SEC_* and IWM_TX_CMD_NEXT_FRAME_*
4254 * @life_time: frame life time (usecs??)
4255 * @dram_lsb_ptr: Physical address of scratch area in the command (try_cnt +
4256 * btkill_cnd + reserved), first 32 bits. "0" disables usage.
4257 * @dram_msb_ptr: upper bits of the scratch physical address
4258 * @rts_retry_limit: max attempts for RTS
4259 * @data_retry_limit: max attempts to send the data packet
4260 * @tid_spec: TID/tspec
4261 * @pm_frame_timeout: PM TX frame timeout
4262 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not
4263 * specified by HCCA protocol
4265 * The byte count (both len and next_frame_len) includes MAC header
4266 * (24/26/30/32 bytes)
4267 * + 2 bytes pad if 26/30 header size
4268 * + 8 byte IV for CCM or TKIP (not used for WEP)
4270 * + 8-byte MIC (not used for CCM/WEP)
4271 * It does not include post-MAC padding, i.e.,
4272 * MIC (CCM) 8 bytes, ICV (WEP/TKIP/CKIP) 4 bytes, CRC 4 bytes.
4273 * Range of len: 14-2342 bytes.
4275 * After the struct fields the MAC header is placed, plus any padding,
4276 * and then the actial payload.
4280 uint16_t next_frame_len;
4286 } scratch; /* DRAM_SCRATCH_API_U_VER_1 */
4287 uint32_t rate_n_flags;
4290 uint8_t initial_rate_index;
4293 uint16_t next_frame_flags;
4296 uint32_t dram_lsb_ptr;
4297 uint8_t dram_msb_ptr;
4298 uint8_t rts_retry_limit;
4299 uint8_t data_retry_limit;
4301 uint16_t pm_frame_timeout;
4302 uint16_t driver_txop;
4304 struct ieee80211_frame hdr[0];
4305 } __packed; /* IWM_TX_CMD_API_S_VER_3 */
4308 * TX response related data
4312 * enum iwm_tx_status - status that is returned by the fw after attempts to Tx
4313 * @IWM_TX_STATUS_SUCCESS:
4314 * @IWM_TX_STATUS_DIRECT_DONE:
4315 * @IWM_TX_STATUS_POSTPONE_DELAY:
4316 * @IWM_TX_STATUS_POSTPONE_FEW_BYTES:
4317 * @IWM_TX_STATUS_POSTPONE_BT_PRIO:
4318 * @IWM_TX_STATUS_POSTPONE_QUIET_PERIOD:
4319 * @IWM_TX_STATUS_POSTPONE_CALC_TTAK:
4320 * @IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
4321 * @IWM_TX_STATUS_FAIL_SHORT_LIMIT:
4322 * @IWM_TX_STATUS_FAIL_LONG_LIMIT:
4323 * @IWM_TX_STATUS_FAIL_UNDERRUN:
4324 * @IWM_TX_STATUS_FAIL_DRAIN_FLOW:
4325 * @IWM_TX_STATUS_FAIL_RFKILL_FLUSH:
4326 * @IWM_TX_STATUS_FAIL_LIFE_EXPIRE:
4327 * @IWM_TX_STATUS_FAIL_DEST_PS:
4328 * @IWM_TX_STATUS_FAIL_HOST_ABORTED:
4329 * @IWM_TX_STATUS_FAIL_BT_RETRY:
4330 * @IWM_TX_STATUS_FAIL_STA_INVALID:
4331 * @IWM_TX_TATUS_FAIL_FRAG_DROPPED:
4332 * @IWM_TX_STATUS_FAIL_TID_DISABLE:
4333 * @IWM_TX_STATUS_FAIL_FIFO_FLUSHED:
4334 * @IWM_TX_STATUS_FAIL_SMALL_CF_POLL:
4335 * @IWM_TX_STATUS_FAIL_FW_DROP:
4336 * @IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
4338 * @IWM_TX_FRAME_STATUS_INTERNAL_ABORT:
4340 * @IWM_TX_MODE_NO_BURST:
4341 * @IWM_TX_MODE_IN_BURST_SEQ:
4342 * @IWM_TX_MODE_FIRST_IN_BURST:
4343 * @IWM_TX_QUEUE_NUM_MSK:
4345 * Valid only if frame_count =1
4346 * TODO: complete documentation
4348 enum iwm_tx_status {
4349 IWM_TX_STATUS_MSK = 0x000000ff,
4350 IWM_TX_STATUS_SUCCESS = 0x01,
4351 IWM_TX_STATUS_DIRECT_DONE = 0x02,
4353 IWM_TX_STATUS_POSTPONE_DELAY = 0x40,
4354 IWM_TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
4355 IWM_TX_STATUS_POSTPONE_BT_PRIO = 0x42,
4356 IWM_TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
4357 IWM_TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
4359 IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
4360 IWM_TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
4361 IWM_TX_STATUS_FAIL_LONG_LIMIT = 0x83,
4362 IWM_TX_STATUS_FAIL_UNDERRUN = 0x84,
4363 IWM_TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
4364 IWM_TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
4365 IWM_TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
4366 IWM_TX_STATUS_FAIL_DEST_PS = 0x88,
4367 IWM_TX_STATUS_FAIL_HOST_ABORTED = 0x89,
4368 IWM_TX_STATUS_FAIL_BT_RETRY = 0x8a,
4369 IWM_TX_STATUS_FAIL_STA_INVALID = 0x8b,
4370 IWM_TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
4371 IWM_TX_STATUS_FAIL_TID_DISABLE = 0x8d,
4372 IWM_TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
4373 IWM_TX_STATUS_FAIL_SMALL_CF_POLL = 0x8f,
4374 IWM_TX_STATUS_FAIL_FW_DROP = 0x90,
4375 IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH = 0x91,
4376 IWM_TX_STATUS_INTERNAL_ABORT = 0x92,
4377 IWM_TX_MODE_MSK = 0x00000f00,
4378 IWM_TX_MODE_NO_BURST = 0x00000000,
4379 IWM_TX_MODE_IN_BURST_SEQ = 0x00000100,
4380 IWM_TX_MODE_FIRST_IN_BURST = 0x00000200,
4381 IWM_TX_QUEUE_NUM_MSK = 0x0001f000,
4382 IWM_TX_NARROW_BW_MSK = 0x00060000,
4383 IWM_TX_NARROW_BW_1DIV2 = 0x00020000,
4384 IWM_TX_NARROW_BW_1DIV4 = 0x00040000,
4385 IWM_TX_NARROW_BW_1DIV8 = 0x00060000,
4389 * enum iwm_tx_agg_status - TX aggregation status
4390 * @IWM_AGG_TX_STATE_STATUS_MSK:
4391 * @IWM_AGG_TX_STATE_TRANSMITTED:
4392 * @IWM_AGG_TX_STATE_UNDERRUN:
4393 * @IWM_AGG_TX_STATE_BT_PRIO:
4394 * @IWM_AGG_TX_STATE_FEW_BYTES:
4395 * @IWM_AGG_TX_STATE_ABORT:
4396 * @IWM_AGG_TX_STATE_LAST_SENT_TTL:
4397 * @IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT:
4398 * @IWM_AGG_TX_STATE_LAST_SENT_BT_KILL:
4399 * @IWM_AGG_TX_STATE_SCD_QUERY:
4400 * @IWM_AGG_TX_STATE_TEST_BAD_CRC32:
4401 * @IWM_AGG_TX_STATE_RESPONSE:
4402 * @IWM_AGG_TX_STATE_DUMP_TX:
4403 * @IWM_AGG_TX_STATE_DELAY_TX:
4404 * @IWM_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
4405 * occur if tx failed for this frame when it was a member of a previous
4406 * aggregation block). If rate scaling is used, retry count indicates the
4407 * rate table entry used for all frames in the new agg.
4408 *@ IWM_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
4411 * TODO: complete documentation
4413 enum iwm_tx_agg_status {
4414 IWM_AGG_TX_STATE_STATUS_MSK = 0x00fff,
4415 IWM_AGG_TX_STATE_TRANSMITTED = 0x000,
4416 IWM_AGG_TX_STATE_UNDERRUN = 0x001,
4417 IWM_AGG_TX_STATE_BT_PRIO = 0x002,
4418 IWM_AGG_TX_STATE_FEW_BYTES = 0x004,
4419 IWM_AGG_TX_STATE_ABORT = 0x008,
4420 IWM_AGG_TX_STATE_LAST_SENT_TTL = 0x010,
4421 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT = 0x020,
4422 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL = 0x040,
4423 IWM_AGG_TX_STATE_SCD_QUERY = 0x080,
4424 IWM_AGG_TX_STATE_TEST_BAD_CRC32 = 0x0100,
4425 IWM_AGG_TX_STATE_RESPONSE = 0x1ff,
4426 IWM_AGG_TX_STATE_DUMP_TX = 0x200,
4427 IWM_AGG_TX_STATE_DELAY_TX = 0x400,
4428 IWM_AGG_TX_STATE_TRY_CNT_POS = 12,
4429 IWM_AGG_TX_STATE_TRY_CNT_MSK = 0xf << IWM_AGG_TX_STATE_TRY_CNT_POS,
4432 #define IWM_AGG_TX_STATE_LAST_SENT_MSK (IWM_AGG_TX_STATE_LAST_SENT_TTL| \
4433 IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
4434 IWM_AGG_TX_STATE_LAST_SENT_BT_KILL)
4437 * The mask below describes a status where we are absolutely sure that the MPDU
4438 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've
4439 * written the bytes to the TXE, but we know nothing about what the DSP did.
4441 #define IWM_AGG_TX_STAT_FRAME_NOT_SENT (IWM_AGG_TX_STATE_FEW_BYTES | \
4442 IWM_AGG_TX_STATE_ABORT | \
4443 IWM_AGG_TX_STATE_SCD_QUERY)
4446 * IWM_REPLY_TX = 0x1c (response)
4448 * This response may be in one of two slightly different formats, indicated
4449 * by the frame_count field:
4451 * 1) No aggregation (frame_count == 1). This reports Tx results for a single
4452 * frame. Multiple attempts, at various bit rates, may have been made for
4455 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more
4456 * frames that used block-acknowledge. All frames were transmitted at
4457 * same rate. Rate scaling may have been used if first frame in this new
4458 * agg block failed in previous agg block(s).
4460 * Note that, for aggregation, ACK (block-ack) status is not delivered
4461 * here; block-ack has not been received by the time the device records
4463 * This status relates to reasons the tx might have been blocked or aborted
4464 * within the device, rather than whether it was received successfully by
4465 * the destination station.
4469 * struct iwm_agg_tx_status - per packet TX aggregation status
4470 * @status: enum iwm_tx_agg_status
4471 * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
4473 struct iwm_agg_tx_status {
4479 * definitions for initial rate index field
4480 * bits [3:0] initial rate index
4481 * bits [6:4] rate table color, used for the initial rate
4482 * bit-7 invalid rate indication
4484 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f
4485 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70
4486 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80
4488 #define IWM_MVM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
4489 #define IWM_MVM_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)
4492 * struct iwm_mvm_tx_resp - notifies that fw is TXing a packet
4493 * ( IWM_REPLY_TX = 0x1c )
4494 * @frame_count: 1 no aggregation, >1 aggregation
4495 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
4496 * @failure_rts: num of failures due to unsuccessful RTS
4497 * @failure_frame: num failures due to no ACK (unused for agg)
4498 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
4499 * Tx of all the batch. IWM_RATE_MCS_*
4500 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
4501 * for agg: RTS + CTS + aggregation tx time + block-ack time.
4503 * @pa_status: tx power info
4504 * @pa_integ_res_a: tx power info
4505 * @pa_integ_res_b: tx power info
4506 * @pa_integ_res_c: tx power info
4507 * @measurement_req_id: tx power info
4508 * @tfd_info: TFD information set by the FH
4509 * @seq_ctl: sequence control from the Tx cmd
4510 * @byte_cnt: byte count from the Tx cmd
4511 * @tlc_info: TLC rate info
4512 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
4513 * @frame_ctrl: frame control
4514 * @status: for non-agg: frame status IWM_TX_STATUS_*
4515 * for agg: status of 1st frame, IWM_AGG_TX_STATE_*; other frame status fields
4516 * follow this one, up to frame_count.
4518 * After the array of statuses comes the SSN of the SCD. Look at
4519 * %iwm_mvm_get_scd_ssn for more details.
4521 struct iwm_mvm_tx_resp {
4522 uint8_t frame_count;
4523 uint8_t bt_kill_count;
4524 uint8_t failure_rts;
4525 uint8_t failure_frame;
4526 uint32_t initial_rate;
4527 uint16_t wireless_media_time;
4530 uint8_t pa_integ_res_a[3];
4531 uint8_t pa_integ_res_b[3];
4532 uint8_t pa_integ_res_c[3];
4533 uint16_t measurement_req_id;
4541 uint16_t frame_ctrl;
4543 struct iwm_agg_tx_status status;
4544 } __packed; /* IWM_TX_RSP_API_S_VER_3 */
4547 * struct iwm_mvm_ba_notif - notifies about reception of BA
4548 * ( IWM_BA_NOTIF = 0xc5 )
4549 * @sta_addr_lo32: lower 32 bits of the MAC address
4550 * @sta_addr_hi16: upper 16 bits of the MAC address
4551 * @sta_id: Index of recipient (BA-sending) station in fw's station table
4552 * @tid: tid of the session
4554 * @bitmap: the bitmap of the BA notification as seen in the air
4555 * @scd_flow: the tx queue this BA relates to
4556 * @scd_ssn: the index of the last contiguously sent packet
4557 * @txed: number of Txed frames in this batch
4558 * @txed_2_done: number of Acked frames in this batch
4560 struct iwm_mvm_ba_notif {
4561 uint32_t sta_addr_lo32;
4562 uint16_t sta_addr_hi16;
4572 uint8_t txed_2_done;
4577 * struct iwm_mac_beacon_cmd - beacon template command
4578 * @tx: the tx commands associated with the beacon frame
4579 * @template_id: currently equal to the mac context id of the coresponding
4581 * @tim_idx: the offset of the tim IE in the beacon
4582 * @tim_size: the length of the tim IE
4583 * @frame: the template of the beacon frame
4585 struct iwm_mac_beacon_cmd {
4586 struct iwm_tx_cmd tx;
4587 uint32_t template_id;
4590 struct ieee80211_frame frame[0];
4593 struct iwm_beacon_notif {
4594 struct iwm_mvm_tx_resp beacon_notify_hdr;
4596 uint32_t ibss_mgr_status;
4600 * enum iwm_dump_control - dump (flush) control flags
4601 * @IWM_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
4602 * and the TFD queues are empty.
4604 enum iwm_dump_control {
4605 IWM_DUMP_TX_FIFO_FLUSH = (1 << 1),
4609 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
4610 * @queues_ctl: bitmap of queues to flush
4611 * @flush_ctl: control flags
4612 * @reserved: reserved
4614 struct iwm_tx_path_flush_cmd {
4615 uint32_t queues_ctl;
4618 } __packed; /* IWM_TX_PATH_FLUSH_CMD_API_S_VER_1 */
4621 * iwm_mvm_get_scd_ssn - returns the SSN of the SCD
4622 * @tx_resp: the Tx response from the fw (agg or non-agg)
4624 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
4625 * it can't know that everything will go well until the end of the AMPDU, it
4626 * can't know in advance the number of MPDUs that will be sent in the current
4627 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
4628 * Hence, it can't know in advance what the SSN of the SCD will be at the end
4629 * of the batch. This is why the SSN of the SCD is written at the end of the
4630 * whole struct at a variable offset. This function knows how to cope with the
4631 * variable offset and returns the SSN of the SCD.
4633 static inline uint32_t iwm_mvm_get_scd_ssn(struct iwm_mvm_tx_resp *tx_resp)
4635 return le32_to_cpup((uint32_t *)&tx_resp->status +
4636 tx_resp->frame_count) & 0xfff;
4640 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command
4642 * @sta_id: station id
4644 * @scd_queue: scheduler queue to confiug
4645 * @enable: 1 queue enable, 0 queue disable
4646 * @aggregate: 1 aggregated queue, 0 otherwise
4647 * @tx_fifo: %enum iwm_mvm_tx_fifo
4648 * @window: BA window size
4649 * @ssn: SSN for the BA agreement
4651 struct iwm_scd_txq_cfg_cmd {
4662 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */
4665 * struct iwm_scd_txq_cfg_rsp
4666 * @token: taken from the command
4667 * @sta_id: station id from the command
4668 * @tid: tid from the command
4669 * @scd_queue: scd_queue from the command
4671 struct iwm_scd_txq_cfg_rsp {
4676 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */
4679 /* Scan Commands, Responses, Notifications */
4681 /* Max number of IEs for direct SSID scans in a command */
4682 #define IWM_PROBE_OPTION_MAX 20
4685 * struct iwm_ssid_ie - directed scan network information element
4687 * Up to 20 of these may appear in IWM_REPLY_SCAN_CMD,
4688 * selected by "type" bit field in struct iwm_scan_channel;
4689 * each channel may select different ssids from among the 20 entries.
4690 * SSID IEs get transmitted in reverse order of entry.
4692 struct iwm_ssid_ie {
4695 uint8_t ssid[IEEE80211_NWID_LEN];
4696 } __packed; /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
4699 #define IWM_MAX_SCAN_CHANNELS 40
4700 #define IWM_SCAN_MAX_BLACKLIST_LEN 64
4701 #define IWM_SCAN_SHORT_BLACKLIST_LEN 16
4702 #define IWM_SCAN_MAX_PROFILES 11
4703 #define IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
4705 /* Default watchdog (in MS) for scheduled scan iteration */
4706 #define IWM_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
4708 #define IWM_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
4709 #define IWM_CAN_ABORT_STATUS 1
4711 #define IWM_FULL_SCAN_MULTIPLIER 5
4712 #define IWM_FAST_SCHED_SCAN_ITERATIONS 3
4713 #define IWM_MAX_SCHED_SCAN_PLANS 2
4715 /* Maximal number of channels to scan */
4716 #define IWM_MAX_NUM_SCAN_CHANNELS 0x24
4719 * iwm_scan_schedule_lmac - schedule of scan offload
4720 * @delay: delay between iterations, in seconds.
4721 * @iterations: num of scan iterations
4722 * @full_scan_mul: number of partial scans before each full scan
4724 struct iwm_scan_schedule_lmac {
4727 uint8_t full_scan_mul;
4728 } __packed; /* SCAN_SCHEDULE_API_S */
4731 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S
4732 * @tx_flags: combination of TX_CMD_FLG_*
4733 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
4734 * cleared. Combination of RATE_MCS_*
4735 * @sta_id: index of destination station in FW station table
4736 * @reserved: for alignment and future use
4738 struct iwm_scan_req_tx_cmd {
4740 uint32_t rate_n_flags;
4742 uint8_t reserved[3];
4745 enum iwm_scan_channel_flags_lmac {
4746 IWM_UNIFIED_SCAN_CHANNEL_FULL = (1 << 27),
4747 IWM_UNIFIED_SCAN_CHANNEL_PARTIAL = (1 << 28),
4751 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
4752 * @flags: bits 1-20: directed scan to i'th ssid
4753 * other bits &enum iwm_scan_channel_flags_lmac
4754 * @channel_number: channel number 1-13 etc
4755 * @iter_count: scan iteration on this channel
4756 * @iter_interval: interval in seconds between iterations on one channel
4758 struct iwm_scan_channel_cfg_lmac {
4760 uint16_t channel_num;
4761 uint16_t iter_count;
4762 uint32_t iter_interval;
4766 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1
4767 * @offset: offset in the data block
4768 * @len: length of the segment
4770 struct iwm_scan_probe_segment {
4775 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
4776 * @mac_header: first (and common) part of the probe
4777 * @band_data: band specific data
4778 * @common_data: last (and common) part of the probe
4779 * @buf: raw data block
4781 struct iwm_scan_probe_req {
4782 struct iwm_scan_probe_segment mac_header;
4783 struct iwm_scan_probe_segment band_data[2];
4784 struct iwm_scan_probe_segment common_data;
4785 uint8_t buf[IWM_SCAN_OFFLOAD_PROBE_REQ_SIZE];
4788 enum iwm_scan_channel_flags {
4789 IWM_SCAN_CHANNEL_FLAG_EBS = (1 << 0),
4790 IWM_SCAN_CHANNEL_FLAG_EBS_ACCURATE = (1 << 1),
4791 IWM_SCAN_CHANNEL_FLAG_CACHE_ADD = (1 << 2),
4794 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
4795 * @flags: enum iwm_scan_channel_flags
4796 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
4798 * 1 - EBS is disabled.
4799 * 2 - every second scan will be full scan(and so on).
4801 struct iwm_scan_channel_opt {
4803 uint16_t non_ebs_ratio;
4807 * iwm_mvm_lmac_scan_flags
4808 * @IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL: pass all beacons and probe responses
4809 * without filtering.
4810 * @IWM_MVM_LMAC_SCAN_FLAG_PASSIVE: force passive scan on all channels
4811 * @IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION: single channel scan
4812 * @IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE: send iteration complete notification
4813 * @IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS multiple SSID matching
4814 * @IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED: all passive scans will be fragmented
4815 * @IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report
4816 * and DS parameter set IEs into probe requests.
4817 * @IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL: use extended dwell time on channels
4819 * @IWM_MVM_LMAC_SCAN_FLAG_MATCH: Send match found notification on matches
4821 enum iwm_mvm_lmac_scan_flags {
4822 IWM_MVM_LMAC_SCAN_FLAG_PASS_ALL = (1 << 0),
4823 IWM_MVM_LMAC_SCAN_FLAG_PASSIVE = (1 << 1),
4824 IWM_MVM_LMAC_SCAN_FLAG_PRE_CONNECTION = (1 << 2),
4825 IWM_MVM_LMAC_SCAN_FLAG_ITER_COMPLETE = (1 << 3),
4826 IWM_MVM_LMAC_SCAN_FLAG_MULTIPLE_SSIDS = (1 << 4),
4827 IWM_MVM_LMAC_SCAN_FLAG_FRAGMENTED = (1 << 5),
4828 IWM_MVM_LMAC_SCAN_FLAGS_RRM_ENABLED = (1 << 6),
4829 IWM_MVM_LMAC_SCAN_FLAG_EXTENDED_DWELL = (1 << 7),
4830 IWM_MVM_LMAC_SCAN_FLAG_MATCH = (1 << 9),
4833 enum iwm_scan_priority {
4834 IWM_SCAN_PRIORITY_LOW,
4835 IWM_SCAN_PRIORITY_MEDIUM,
4836 IWM_SCAN_PRIORITY_HIGH,
4840 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1
4841 * @reserved1: for alignment and future use
4842 * @channel_num: num of channels to scan
4843 * @active-dwell: dwell time for active channels
4844 * @passive-dwell: dwell time for passive channels
4845 * @fragmented-dwell: dwell time for fragmented passive scan
4846 * @extended_dwell: dwell time for channels 1, 6 and 11 (in certain cases)
4847 * @reserved2: for alignment and future use
4848 * @rx_chain_selct: PHY_RX_CHAIN_* flags
4849 * @scan_flags: &enum iwm_mvm_lmac_scan_flags
4850 * @max_out_time: max time (in TU) to be out of associated channel
4851 * @suspend_time: pause scan this long (TUs) when returning to service channel
4852 * @flags: RXON flags
4853 * @filter_flags: RXON filter
4854 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz
4855 * @direct_scan: list of SSIDs for directed active scan
4856 * @scan_prio: enum iwm_scan_priority
4857 * @iter_num: number of scan iterations
4858 * @delay: delay in seconds before first iteration
4859 * @schedule: two scheduling plans. The first one is finite, the second one can
4861 * @channel_opt: channel optimization options, for full and partial scan
4862 * @data: channel configuration and probe request packet.
4864 struct iwm_scan_req_lmac {
4865 /* SCAN_REQUEST_FIXED_PART_API_S_VER_7 */
4868 uint8_t active_dwell;
4869 uint8_t passive_dwell;
4870 uint8_t fragmented_dwell;
4871 uint8_t extended_dwell;
4873 uint16_t rx_chain_select;
4874 uint32_t scan_flags;
4875 uint32_t max_out_time;
4876 uint32_t suspend_time;
4877 /* RX_ON_FLAGS_API_S_VER_1 */
4879 uint32_t filter_flags;
4880 struct iwm_scan_req_tx_cmd tx_cmd[2];
4881 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
4883 /* SCAN_REQ_PERIODIC_PARAMS_API_S */
4886 struct iwm_scan_schedule_lmac schedule[IWM_MAX_SCHED_SCAN_PLANS];
4887 struct iwm_scan_channel_opt channel_opt[2];
4892 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2
4893 * @last_schedule_line: last schedule line executed (fast or regular)
4894 * @last_schedule_iteration: last scan iteration executed before scan abort
4895 * @status: enum iwm_scan_offload_complete_status
4896 * @ebs_status: EBS success status &enum iwm_scan_ebs_status
4897 * @time_after_last_iter; time in seconds elapsed after last iteration
4899 struct iwm_periodic_scan_complete {
4900 uint8_t last_schedule_line;
4901 uint8_t last_schedule_iteration;
4904 uint32_t time_after_last_iter;
4908 /* How many statistics are gathered for each channel */
4909 #define IWM_SCAN_RESULTS_STATISTICS 1
4912 * enum iwm_scan_complete_status - status codes for scan complete notifications
4913 * @IWM_SCAN_COMP_STATUS_OK: scan completed successfully
4914 * @IWM_SCAN_COMP_STATUS_ABORT: scan was aborted by user
4915 * @IWM_SCAN_COMP_STATUS_ERR_SLEEP: sending null sleep packet failed
4916 * @IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT: timeout before channel is ready
4917 * @IWM_SCAN_COMP_STATUS_ERR_PROBE: sending probe request failed
4918 * @IWM_SCAN_COMP_STATUS_ERR_WAKEUP: sending null wakeup packet failed
4919 * @IWM_SCAN_COMP_STATUS_ERR_ANTENNAS: invalid antennas chosen at scan command
4920 * @IWM_SCAN_COMP_STATUS_ERR_INTERNAL: internal error caused scan abort
4921 * @IWM_SCAN_COMP_STATUS_ERR_COEX: medium was lost ot WiMax
4922 * @IWM_SCAN_COMP_STATUS_P2P_ACTION_OK: P2P public action frame TX was successful
4924 * @IWM_SCAN_COMP_STATUS_ITERATION_END: indicates end of one repeatition the driver
4926 * @IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE: scan could not allocate time events
4928 enum iwm_scan_complete_status {
4929 IWM_SCAN_COMP_STATUS_OK = 0x1,
4930 IWM_SCAN_COMP_STATUS_ABORT = 0x2,
4931 IWM_SCAN_COMP_STATUS_ERR_SLEEP = 0x3,
4932 IWM_SCAN_COMP_STATUS_ERR_CHAN_TIMEOUT = 0x4,
4933 IWM_SCAN_COMP_STATUS_ERR_PROBE = 0x5,
4934 IWM_SCAN_COMP_STATUS_ERR_WAKEUP = 0x6,
4935 IWM_SCAN_COMP_STATUS_ERR_ANTENNAS = 0x7,
4936 IWM_SCAN_COMP_STATUS_ERR_INTERNAL = 0x8,
4937 IWM_SCAN_COMP_STATUS_ERR_COEX = 0x9,
4938 IWM_SCAN_COMP_STATUS_P2P_ACTION_OK = 0xA,
4939 IWM_SCAN_COMP_STATUS_ITERATION_END = 0x0B,
4940 IWM_SCAN_COMP_STATUS_ERR_ALLOC_TE = 0x0C,
4944 * struct iwm_scan_results_notif - scan results for one channel
4945 * ( IWM_SCAN_RESULTS_NOTIFICATION = 0x83 )
4946 * @channel: which channel the results are from
4947 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
4948 * @probe_status: IWM_SCAN_PROBE_STATUS_*, indicates success of probe request
4949 * @num_probe_not_sent: # of request that weren't sent due to not enough time
4950 * @duration: duration spent in channel, in usecs
4951 * @statistics: statistics gathered for this channel
4953 struct iwm_scan_results_notif {
4956 uint8_t probe_status;
4957 uint8_t num_probe_not_sent;
4959 uint32_t statistics[IWM_SCAN_RESULTS_STATISTICS];
4960 } __packed; /* IWM_SCAN_RESULT_NTF_API_S_VER_2 */
4962 enum iwm_scan_framework_client {
4963 IWM_SCAN_CLIENT_SCHED_SCAN = (1 << 0),
4964 IWM_SCAN_CLIENT_NETDETECT = (1 << 1),
4965 IWM_SCAN_CLIENT_ASSET_TRACKING = (1 << 2),
4969 * struct iwm_scan_offload_cmd - IWM_SCAN_REQUEST_FIXED_PART_API_S_VER_6
4970 * @scan_flags: see enum iwm_scan_flags
4971 * @channel_count: channels in channel list
4972 * @quiet_time: dwell time, in milisiconds, on quiet channel
4973 * @quiet_plcp_th: quiet channel num of packets threshold
4974 * @good_CRC_th: passive to active promotion threshold
4975 * @rx_chain: RXON rx chain.
4976 * @max_out_time: max uSec to be out of assoceated channel
4977 * @suspend_time: pause scan this long when returning to service channel
4978 * @flags: RXON flags
4979 * @filter_flags: RXONfilter
4980 * @tx_cmd: tx command for active scan; for 2GHz and for 5GHz.
4981 * @direct_scan: list of SSIDs for directed active scan
4982 * @scan_type: see enum iwm_scan_type.
4983 * @rep_count: repetition count for each scheduled scan iteration.
4985 struct iwm_scan_offload_cmd {
4988 uint8_t channel_count;
4989 uint16_t quiet_time;
4990 uint16_t quiet_plcp_th;
4991 uint16_t good_CRC_th;
4993 uint32_t max_out_time;
4994 uint32_t suspend_time;
4995 /* IWM_RX_ON_FLAGS_API_S_VER_1 */
4997 uint32_t filter_flags;
4998 struct iwm_tx_cmd tx_cmd[2];
4999 /* IWM_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
5000 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5005 enum iwm_scan_offload_channel_flags {
5006 IWM_SCAN_OFFLOAD_CHANNEL_ACTIVE = (1 << 0),
5007 IWM_SCAN_OFFLOAD_CHANNEL_NARROW = (1 << 22),
5008 IWM_SCAN_OFFLOAD_CHANNEL_FULL = (1 << 24),
5009 IWM_SCAN_OFFLOAD_CHANNEL_PARTIAL = (1 << 25),
5013 * iwm_scan_channel_cfg - IWM_SCAN_CHANNEL_CFG_S
5014 * @type: bitmap - see enum iwm_scan_offload_channel_flags.
5015 * 0: passive (0) or active (1) scan.
5016 * 1-20: directed scan to i'th ssid.
5017 * 22: channel width configuation - 1 for narrow.
5020 * @channel_number: channel number 1-13 etc.
5021 * @iter_count: repetition count for the channel.
5022 * @iter_interval: interval between two innteration on one channel.
5023 * @dwell_time: entry 0 - active scan, entry 1 - passive scan.
5025 struct iwm_scan_channel_cfg {
5026 uint32_t type[IWM_MAX_SCAN_CHANNELS];
5027 uint16_t channel_number[IWM_MAX_SCAN_CHANNELS];
5028 uint16_t iter_count[IWM_MAX_SCAN_CHANNELS];
5029 uint32_t iter_interval[IWM_MAX_SCAN_CHANNELS];
5030 uint8_t dwell_time[IWM_MAX_SCAN_CHANNELS][2];
5034 * iwm_scan_offload_cfg - IWM_SCAN_OFFLOAD_CONFIG_API_S
5035 * @scan_cmd: scan command fixed part
5036 * @channel_cfg: scan channel configuration
5037 * @data: probe request frames (one per band)
5039 struct iwm_scan_offload_cfg {
5040 struct iwm_scan_offload_cmd scan_cmd;
5041 struct iwm_scan_channel_cfg channel_cfg;
5046 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
5047 * @ssid: MAC address to filter out
5048 * @reported_rssi: AP rssi reported to the host
5049 * @client_bitmap: clients ignore this entry - enum scan_framework_client
5051 struct iwm_scan_offload_blacklist {
5052 uint8_t ssid[IEEE80211_ADDR_LEN];
5053 uint8_t reported_rssi;
5054 uint8_t client_bitmap;
5057 enum iwm_scan_offload_network_type {
5058 IWM_NETWORK_TYPE_BSS = 1,
5059 IWM_NETWORK_TYPE_IBSS = 2,
5060 IWM_NETWORK_TYPE_ANY = 3,
5063 enum iwm_scan_offload_band_selection {
5064 IWM_SCAN_OFFLOAD_SELECT_2_4 = 0x4,
5065 IWM_SCAN_OFFLOAD_SELECT_5_2 = 0x8,
5066 IWM_SCAN_OFFLOAD_SELECT_ANY = 0xc,
5070 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
5071 * @ssid_index: index to ssid list in fixed part
5072 * @unicast_cipher: encryption olgorithm to match - bitmap
5073 * @aut_alg: authentication olgorithm to match - bitmap
5074 * @network_type: enum iwm_scan_offload_network_type
5075 * @band_selection: enum iwm_scan_offload_band_selection
5076 * @client_bitmap: clients waiting for match - enum scan_framework_client
5078 struct iwm_scan_offload_profile {
5080 uint8_t unicast_cipher;
5082 uint8_t network_type;
5083 uint8_t band_selection;
5084 uint8_t client_bitmap;
5085 uint8_t reserved[2];
5089 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
5090 * @blaclist: AP list to filter off from scan results
5091 * @profiles: profiles to search for match
5092 * @blacklist_len: length of blacklist
5093 * @num_profiles: num of profiles in the list
5094 * @match_notify: clients waiting for match found notification
5095 * @pass_match: clients waiting for the results
5096 * @active_clients: active clients bitmap - enum scan_framework_client
5097 * @any_beacon_notify: clients waiting for match notification without match
5099 struct iwm_scan_offload_profile_cfg {
5100 struct iwm_scan_offload_profile profiles[IWM_SCAN_MAX_PROFILES];
5101 uint8_t blacklist_len;
5102 uint8_t num_profiles;
5103 uint8_t match_notify;
5105 uint8_t active_clients;
5106 uint8_t any_beacon_notify;
5107 uint8_t reserved[2];
5111 * iwm_scan_offload_schedule - schedule of scan offload
5112 * @delay: delay between iterations, in seconds.
5113 * @iterations: num of scan iterations
5114 * @full_scan_mul: number of partial scans before each full scan
5116 struct iwm_scan_offload_schedule {
5119 uint8_t full_scan_mul;
5123 * iwm_scan_offload_flags
5125 * IWM_SCAN_OFFLOAD_FLAG_PASS_ALL: pass all results - no filtering.
5126 * IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL: add cached channels to partial scan.
5127 * IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN: use energy based scan before partial scan
5130 enum iwm_scan_offload_flags {
5131 IWM_SCAN_OFFLOAD_FLAG_PASS_ALL = (1 << 0),
5132 IWM_SCAN_OFFLOAD_FLAG_CACHED_CHANNEL = (1 << 2),
5133 IWM_SCAN_OFFLOAD_FLAG_ENERGY_SCAN = (1 << 3),
5137 * iwm_scan_offload_req - scan offload request command
5138 * @flags: bitmap - enum iwm_scan_offload_flags.
5139 * @watchdog: maximum scan duration in TU.
5140 * @delay: delay in seconds before first iteration.
5141 * @schedule_line: scan offload schedule, for fast and regular scan.
5143 struct iwm_scan_offload_req {
5148 struct iwm_scan_offload_schedule schedule_line[2];
5151 enum iwm_scan_offload_compleate_status {
5152 IWM_SCAN_OFFLOAD_COMPLETED = 1,
5153 IWM_SCAN_OFFLOAD_ABORTED = 2,
5157 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels)
5158 * SCAN_COMPLETE_NTF_API_S_VER_3
5159 * @scanned_channels: number of channels scanned (and number of valid results)
5160 * @status: one of SCAN_COMP_STATUS_*
5161 * @bt_status: BT on/off status
5162 * @last_channel: last channel that was scanned
5163 * @tsf_low: TSF timer (lower half) in usecs
5164 * @tsf_high: TSF timer (higher half) in usecs
5165 * @results: an array of scan results, only "scanned_channels" of them are valid
5167 struct iwm_lmac_scan_complete_notif {
5168 uint8_t scanned_channels;
5171 uint8_t last_channel;
5174 struct iwm_scan_results_notif results[];
5179 * iwm_scan_offload_complete - IWM_SCAN_OFFLOAD_COMPLETE_NTF_API_S_VER_1
5180 * @last_schedule_line: last schedule line executed (fast or regular)
5181 * @last_schedule_iteration: last scan iteration executed before scan abort
5182 * @status: enum iwm_scan_offload_compleate_status
5184 struct iwm_scan_offload_complete {
5185 uint8_t last_schedule_line;
5186 uint8_t last_schedule_iteration;
5192 * iwm_sched_scan_results - IWM_SCAN_OFFLOAD_MATCH_FOUND_NTF_API_S_VER_1
5193 * @ssid_bitmap: SSIDs indexes found in this iteration
5194 * @client_bitmap: clients that are active and wait for this notification
5196 struct iwm_sched_scan_results {
5197 uint16_t ssid_bitmap;
5198 uint8_t client_bitmap;
5204 /* The maximum of either of these cannot exceed 8, because we use an
5205 * 8-bit mask (see IWM_MVM_SCAN_MASK).
5207 #define IWM_MVM_MAX_UMAC_SCANS 8
5208 #define IWM_MVM_MAX_LMAC_SCANS 1
5210 enum iwm_scan_config_flags {
5211 IWM_SCAN_CONFIG_FLAG_ACTIVATE = (1 << 0),
5212 IWM_SCAN_CONFIG_FLAG_DEACTIVATE = (1 << 1),
5213 IWM_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS = (1 << 2),
5214 IWM_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS = (1 << 3),
5215 IWM_SCAN_CONFIG_FLAG_SET_TX_CHAINS = (1 << 8),
5216 IWM_SCAN_CONFIG_FLAG_SET_RX_CHAINS = (1 << 9),
5217 IWM_SCAN_CONFIG_FLAG_SET_AUX_STA_ID = (1 << 10),
5218 IWM_SCAN_CONFIG_FLAG_SET_ALL_TIMES = (1 << 11),
5219 IWM_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES = (1 << 12),
5220 IWM_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS = (1 << 13),
5221 IWM_SCAN_CONFIG_FLAG_SET_LEGACY_RATES = (1 << 14),
5222 IWM_SCAN_CONFIG_FLAG_SET_MAC_ADDR = (1 << 15),
5223 IWM_SCAN_CONFIG_FLAG_SET_FRAGMENTED = (1 << 16),
5224 IWM_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED = (1 << 17),
5225 IWM_SCAN_CONFIG_FLAG_SET_CAM_MODE = (1 << 18),
5226 IWM_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE = (1 << 19),
5227 IWM_SCAN_CONFIG_FLAG_SET_PROMISC_MODE = (1 << 20),
5228 IWM_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE = (1 << 21),
5230 /* Bits 26-31 are for num of channels in channel_array */
5231 #define IWM_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)
5234 enum iwm_scan_config_rates {
5235 /* OFDM basic rates */
5236 IWM_SCAN_CONFIG_RATE_6M = (1 << 0),
5237 IWM_SCAN_CONFIG_RATE_9M = (1 << 1),
5238 IWM_SCAN_CONFIG_RATE_12M = (1 << 2),
5239 IWM_SCAN_CONFIG_RATE_18M = (1 << 3),
5240 IWM_SCAN_CONFIG_RATE_24M = (1 << 4),
5241 IWM_SCAN_CONFIG_RATE_36M = (1 << 5),
5242 IWM_SCAN_CONFIG_RATE_48M = (1 << 6),
5243 IWM_SCAN_CONFIG_RATE_54M = (1 << 7),
5244 /* CCK basic rates */
5245 IWM_SCAN_CONFIG_RATE_1M = (1 << 8),
5246 IWM_SCAN_CONFIG_RATE_2M = (1 << 9),
5247 IWM_SCAN_CONFIG_RATE_5M = (1 << 10),
5248 IWM_SCAN_CONFIG_RATE_11M = (1 << 11),
5250 /* Bits 16-27 are for supported rates */
5251 #define IWM_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)
5254 enum iwm_channel_flags {
5255 IWM_CHANNEL_FLAG_EBS = (1 << 0),
5256 IWM_CHANNEL_FLAG_ACCURATE_EBS = (1 << 1),
5257 IWM_CHANNEL_FLAG_EBS_ADD = (1 << 2),
5258 IWM_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE = (1 << 3),
5262 * struct iwm_scan_config
5263 * @flags: enum scan_config_flags
5264 * @tx_chains: valid_tx antenna - ANT_* definitions
5265 * @rx_chains: valid_rx antenna - ANT_* definitions
5266 * @legacy_rates: default legacy rates - enum scan_config_rates
5267 * @out_of_channel_time: default max out of serving channel time
5268 * @suspend_time: default max suspend time
5269 * @dwell_active: default dwell time for active scan
5270 * @dwell_passive: default dwell time for passive scan
5271 * @dwell_fragmented: default dwell time for fragmented scan
5272 * @dwell_extended: default dwell time for channels 1, 6 and 11
5273 * @mac_addr: default mac address to be used in probes
5274 * @bcast_sta_id: the index of the station in the fw
5275 * @channel_flags: default channel flags - enum iwm_channel_flags
5276 * scan_config_channel_flag
5277 * @channel_array: default supported channels
5279 struct iwm_scan_config {
5283 uint32_t legacy_rates;
5284 uint32_t out_of_channel_time;
5285 uint32_t suspend_time;
5286 uint8_t dwell_active;
5287 uint8_t dwell_passive;
5288 uint8_t dwell_fragmented;
5289 uint8_t dwell_extended;
5290 uint8_t mac_addr[IEEE80211_ADDR_LEN];
5291 uint8_t bcast_sta_id;
5292 uint8_t channel_flags;
5293 uint8_t channel_array[];
5294 } __packed; /* SCAN_CONFIG_DB_CMD_API_S */
5297 * iwm_umac_scan_flags
5298 *@IWM_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
5299 * can be preempted by other scan requests with higher priority.
5300 * The low priority scan will be resumed when the higher proirity scan is
5302 *@IWM_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
5305 enum iwm_umac_scan_flags {
5306 IWM_UMAC_SCAN_FLAG_PREEMPTIVE = (1 << 0),
5307 IWM_UMAC_SCAN_FLAG_START_NOTIF = (1 << 1),
5310 enum iwm_umac_scan_uid_offsets {
5311 IWM_UMAC_SCAN_UID_TYPE_OFFSET = 0,
5312 IWM_UMAC_SCAN_UID_SEQ_OFFSET = 8,
5315 enum iwm_umac_scan_general_flags {
5316 IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC = (1 << 0),
5317 IWM_UMAC_SCAN_GEN_FLAGS_OVER_BT = (1 << 1),
5318 IWM_UMAC_SCAN_GEN_FLAGS_PASS_ALL = (1 << 2),
5319 IWM_UMAC_SCAN_GEN_FLAGS_PASSIVE = (1 << 3),
5320 IWM_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT = (1 << 4),
5321 IWM_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE = (1 << 5),
5322 IWM_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID = (1 << 6),
5323 IWM_UMAC_SCAN_GEN_FLAGS_FRAGMENTED = (1 << 7),
5324 IWM_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED = (1 << 8),
5325 IWM_UMAC_SCAN_GEN_FLAGS_MATCH = (1 << 9),
5326 IWM_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL = (1 << 10),
5330 * struct iwm_scan_channel_cfg_umac
5331 * @flags: bitmap - 0-19: directed scan to i'th ssid.
5332 * @channel_num: channel number 1-13 etc.
5333 * @iter_count: repetition count for the channel.
5334 * @iter_interval: interval between two scan iterations on one channel.
5336 struct iwm_scan_channel_cfg_umac {
5338 uint8_t channel_num;
5340 uint16_t iter_interval;
5341 } __packed; /* SCAN_CHANNEL_CFG_S_VER2 */
5344 * struct iwm_scan_umac_schedule
5345 * @interval: interval in seconds between scan iterations
5346 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
5347 * @reserved: for alignment and future use
5349 struct iwm_scan_umac_schedule {
5353 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */
5356 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5357 * parameters following channels configuration array.
5358 * @schedule: two scheduling plans.
5359 * @delay: delay in TUs before starting the first scan iteration
5360 * @reserved: for future use and alignment
5361 * @preq: probe request with IEs blocks
5362 * @direct_scan: list of SSIDs for directed active scan
5364 struct iwm_scan_req_umac_tail {
5365 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
5366 struct iwm_scan_umac_schedule schedule[IWM_MAX_SCHED_SCAN_PLANS];
5369 /* SCAN_PROBE_PARAMS_API_S_VER_1 */
5370 struct iwm_scan_probe_req preq;
5371 struct iwm_ssid_ie direct_scan[IWM_PROBE_OPTION_MAX];
5375 * struct iwm_scan_req_umac
5376 * @flags: &enum iwm_umac_scan_flags
5377 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5378 * @ooc_priority: out of channel priority - &enum iwm_scan_priority
5379 * @general_flags: &enum iwm_umac_scan_general_flags
5380 * @extended_dwell: dwell time for channels 1, 6 and 11
5381 * @active_dwell: dwell time for active scan
5382 * @passive_dwell: dwell time for passive scan
5383 * @fragmented_dwell: dwell time for fragmented passive scan
5384 * @max_out_time: max out of serving channel time
5385 * @suspend_time: max suspend time
5386 * @scan_priority: scan internal prioritization &enum iwm_scan_priority
5387 * @channel_flags: &enum iwm_scan_channel_flags
5388 * @n_channels: num of channels in scan request
5389 * @reserved: for future use and alignment
5390 * @data: &struct iwm_scan_channel_cfg_umac and
5391 * &struct iwm_scan_req_umac_tail
5393 struct iwm_scan_req_umac {
5396 uint32_t ooc_priority;
5397 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */
5398 uint32_t general_flags;
5399 uint8_t extended_dwell;
5400 uint8_t active_dwell;
5401 uint8_t passive_dwell;
5402 uint8_t fragmented_dwell;
5403 uint32_t max_out_time;
5404 uint32_t suspend_time;
5405 uint32_t scan_priority;
5406 /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */
5407 uint8_t channel_flags;
5411 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */
5414 * struct iwm_umac_scan_abort
5415 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5418 struct iwm_umac_scan_abort {
5421 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */
5424 * struct iwm_umac_scan_complete
5425 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5426 * @last_schedule: last scheduling line
5427 * @last_iter: last scan iteration number
5428 * @scan status: &enum iwm_scan_offload_complete_status
5429 * @ebs_status: &enum iwm_scan_ebs_status
5430 * @time_from_last_iter: time elapsed from last iteration
5431 * @reserved: for future use
5433 struct iwm_umac_scan_complete {
5435 uint8_t last_schedule;
5439 uint32_t time_from_last_iter;
5441 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */
5443 #define IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5
5445 * struct iwm_scan_offload_profile_match - match information
5446 * @bssid: matched bssid
5447 * @channel: channel where the match occurred
5449 * @matching_feature:
5450 * @matching_channels: bitmap of channels that matched, referencing
5451 * the channels passed in tue scan offload request
5453 struct iwm_scan_offload_profile_match {
5454 uint8_t bssid[IEEE80211_ADDR_LEN];
5458 uint8_t matching_feature;
5459 uint8_t matching_channels[IWM_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN];
5460 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */
5463 * struct iwm_scan_offload_profiles_query - match results query response
5464 * @matched_profiles: bitmap of matched profiles, referencing the
5465 * matches passed in the scan offload request
5466 * @last_scan_age: age of the last offloaded scan
5467 * @n_scans_done: number of offloaded scans done
5468 * @gp2_d0u: GP2 when D0U occurred
5469 * @gp2_invoked: GP2 when scan offload was invoked
5470 * @resume_while_scanning: not used
5471 * @self_recovery: obsolete
5472 * @reserved: reserved
5473 * @matches: array of match information, one for each match
5475 struct iwm_scan_offload_profiles_query {
5476 uint32_t matched_profiles;
5477 uint32_t last_scan_age;
5478 uint32_t n_scans_done;
5480 uint32_t gp2_invoked;
5481 uint8_t resume_while_scanning;
5482 uint8_t self_recovery;
5484 struct iwm_scan_offload_profile_match matches[IWM_SCAN_MAX_PROFILES];
5485 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */
5488 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration
5489 * @uid: scan id, &enum iwm_umac_scan_uid_offsets
5490 * @scanned_channels: number of channels scanned and number of valid elements in
5492 * @status: one of SCAN_COMP_STATUS_*
5493 * @bt_status: BT on/off status
5494 * @last_channel: last channel that was scanned
5495 * @tsf_low: TSF timer (lower half) in usecs
5496 * @tsf_high: TSF timer (higher half) in usecs
5497 * @results: array of scan results, only "scanned_channels" of them are valid
5499 struct iwm_umac_scan_iter_complete_notif {
5501 uint8_t scanned_channels;
5504 uint8_t last_channel;
5507 struct iwm_scan_results_notif results[];
5508 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */
5510 /* Please keep this enum *SORTED* by hex value.
5511 * Needed for binary search, otherwise a warning will be triggered.
5513 enum iwm_scan_subcmd_ids {
5514 IWM_GSCAN_START_CMD = 0x0,
5515 IWM_GSCAN_STOP_CMD = 0x1,
5516 IWM_GSCAN_SET_HOTLIST_CMD = 0x2,
5517 IWM_GSCAN_RESET_HOTLIST_CMD = 0x3,
5518 IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD = 0x4,
5519 IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD = 0x5,
5520 IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT = 0xFD,
5521 IWM_GSCAN_HOTLIST_CHANGE_EVENT = 0xFE,
5522 IWM_GSCAN_RESULTS_AVAILABLE_EVENT = 0xFF,
5528 * enum iwm_sta_flags - flags for the ADD_STA host command
5529 * @IWM_STA_FLG_REDUCED_TX_PWR_CTRL:
5530 * @IWM_STA_FLG_REDUCED_TX_PWR_DATA:
5531 * @IWM_STA_FLG_DISABLE_TX: set if TX should be disabled
5532 * @IWM_STA_FLG_PS: set if STA is in Power Save
5533 * @IWM_STA_FLG_INVALID: set if STA is invalid
5534 * @IWM_STA_FLG_DLP_EN: Direct Link Protocol is enabled
5535 * @IWM_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
5536 * @IWM_STA_FLG_DRAIN_FLOW: drain flow
5537 * @IWM_STA_FLG_PAN: STA is for PAN interface
5538 * @IWM_STA_FLG_CLASS_AUTH:
5539 * @IWM_STA_FLG_CLASS_ASSOC:
5540 * @IWM_STA_FLG_CLASS_MIMO_PROT:
5541 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
5542 * @IWM_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
5543 * @IWM_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
5544 * initialised by driver and can be updated by fw upon reception of
5545 * action frames that can change the channel width. When cleared the fw
5546 * will send all the frames in 20MHz even when FAT channel is requested.
5547 * @IWM_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
5548 * driver and can be updated by fw upon reception of action frames.
5549 * @IWM_STA_FLG_MFP_EN: Management Frame Protection
5551 enum iwm_sta_flags {
5552 IWM_STA_FLG_REDUCED_TX_PWR_CTRL = (1 << 3),
5553 IWM_STA_FLG_REDUCED_TX_PWR_DATA = (1 << 6),
5555 IWM_STA_FLG_DISABLE_TX = (1 << 4),
5557 IWM_STA_FLG_PS = (1 << 8),
5558 IWM_STA_FLG_DRAIN_FLOW = (1 << 12),
5559 IWM_STA_FLG_PAN = (1 << 13),
5560 IWM_STA_FLG_CLASS_AUTH = (1 << 14),
5561 IWM_STA_FLG_CLASS_ASSOC = (1 << 15),
5562 IWM_STA_FLG_RTS_MIMO_PROT = (1 << 17),
5564 IWM_STA_FLG_MAX_AGG_SIZE_SHIFT = 19,
5565 IWM_STA_FLG_MAX_AGG_SIZE_8K = (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5566 IWM_STA_FLG_MAX_AGG_SIZE_16K = (1 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5567 IWM_STA_FLG_MAX_AGG_SIZE_32K = (2 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5568 IWM_STA_FLG_MAX_AGG_SIZE_64K = (3 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5569 IWM_STA_FLG_MAX_AGG_SIZE_128K = (4 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5570 IWM_STA_FLG_MAX_AGG_SIZE_256K = (5 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5571 IWM_STA_FLG_MAX_AGG_SIZE_512K = (6 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5572 IWM_STA_FLG_MAX_AGG_SIZE_1024K = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5573 IWM_STA_FLG_MAX_AGG_SIZE_MSK = (7 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT),
5575 IWM_STA_FLG_AGG_MPDU_DENS_SHIFT = 23,
5576 IWM_STA_FLG_AGG_MPDU_DENS_2US = (4 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5577 IWM_STA_FLG_AGG_MPDU_DENS_4US = (5 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5578 IWM_STA_FLG_AGG_MPDU_DENS_8US = (6 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5579 IWM_STA_FLG_AGG_MPDU_DENS_16US = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5580 IWM_STA_FLG_AGG_MPDU_DENS_MSK = (7 << IWM_STA_FLG_AGG_MPDU_DENS_SHIFT),
5582 IWM_STA_FLG_FAT_EN_20MHZ = (0 << 26),
5583 IWM_STA_FLG_FAT_EN_40MHZ = (1 << 26),
5584 IWM_STA_FLG_FAT_EN_80MHZ = (2 << 26),
5585 IWM_STA_FLG_FAT_EN_160MHZ = (3 << 26),
5586 IWM_STA_FLG_FAT_EN_MSK = (3 << 26),
5588 IWM_STA_FLG_MIMO_EN_SISO = (0 << 28),
5589 IWM_STA_FLG_MIMO_EN_MIMO2 = (1 << 28),
5590 IWM_STA_FLG_MIMO_EN_MIMO3 = (2 << 28),
5591 IWM_STA_FLG_MIMO_EN_MSK = (3 << 28),
5595 * enum iwm_sta_key_flag - key flags for the ADD_STA host command
5596 * @IWM_STA_KEY_FLG_NO_ENC: no encryption
5597 * @IWM_STA_KEY_FLG_WEP: WEP encryption algorithm
5598 * @IWM_STA_KEY_FLG_CCM: CCMP encryption algorithm
5599 * @IWM_STA_KEY_FLG_TKIP: TKIP encryption algorithm
5600 * @IWM_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
5601 * @IWM_STA_KEY_FLG_CMAC: CMAC encryption algorithm
5602 * @IWM_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
5603 * @IWM_STA_KEY_FLG_EN_MSK: mask for encryption algorithmi value
5604 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
5605 * station info array (1 - n 1X mode)
5606 * @IWM_STA_KEY_FLG_KEYID_MSK: the index of the key
5607 * @IWM_STA_KEY_NOT_VALID: key is invalid
5608 * @IWM_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
5609 * @IWM_STA_KEY_MULTICAST: set for multical key
5610 * @IWM_STA_KEY_MFP: key is used for Management Frame Protection
5612 enum iwm_sta_key_flag {
5613 IWM_STA_KEY_FLG_NO_ENC = (0 << 0),
5614 IWM_STA_KEY_FLG_WEP = (1 << 0),
5615 IWM_STA_KEY_FLG_CCM = (2 << 0),
5616 IWM_STA_KEY_FLG_TKIP = (3 << 0),
5617 IWM_STA_KEY_FLG_EXT = (4 << 0),
5618 IWM_STA_KEY_FLG_CMAC = (6 << 0),
5619 IWM_STA_KEY_FLG_ENC_UNKNOWN = (7 << 0),
5620 IWM_STA_KEY_FLG_EN_MSK = (7 << 0),
5622 IWM_STA_KEY_FLG_WEP_KEY_MAP = (1 << 3),
5623 IWM_STA_KEY_FLG_KEYID_POS = 8,
5624 IWM_STA_KEY_FLG_KEYID_MSK = (3 << IWM_STA_KEY_FLG_KEYID_POS),
5625 IWM_STA_KEY_NOT_VALID = (1 << 11),
5626 IWM_STA_KEY_FLG_WEP_13BYTES = (1 << 12),
5627 IWM_STA_KEY_MULTICAST = (1 << 14),
5628 IWM_STA_KEY_MFP = (1 << 15),
5632 * enum iwm_sta_modify_flag - indicate to the fw what flag are being changed
5633 * @IWM_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue
5634 * @IWM_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
5635 * @IWM_STA_MODIFY_TX_RATE: unused
5636 * @IWM_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
5637 * @IWM_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
5638 * @IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
5639 * @IWM_STA_MODIFY_PROT_TH:
5640 * @IWM_STA_MODIFY_QUEUES: modify the queues used by this station
5642 enum iwm_sta_modify_flag {
5643 IWM_STA_MODIFY_QUEUE_REMOVAL = (1 << 0),
5644 IWM_STA_MODIFY_TID_DISABLE_TX = (1 << 1),
5645 IWM_STA_MODIFY_TX_RATE = (1 << 2),
5646 IWM_STA_MODIFY_ADD_BA_TID = (1 << 3),
5647 IWM_STA_MODIFY_REMOVE_BA_TID = (1 << 4),
5648 IWM_STA_MODIFY_SLEEPING_STA_TX_COUNT = (1 << 5),
5649 IWM_STA_MODIFY_PROT_TH = (1 << 6),
5650 IWM_STA_MODIFY_QUEUES = (1 << 7),
5653 #define IWM_STA_MODE_MODIFY 1
5656 * enum iwm_sta_sleep_flag - type of sleep of the station
5657 * @IWM_STA_SLEEP_STATE_AWAKE:
5658 * @IWM_STA_SLEEP_STATE_PS_POLL:
5659 * @IWM_STA_SLEEP_STATE_UAPSD:
5660 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on
5661 * (last) released frame
5663 enum iwm_sta_sleep_flag {
5664 IWM_STA_SLEEP_STATE_AWAKE = 0,
5665 IWM_STA_SLEEP_STATE_PS_POLL = (1 << 0),
5666 IWM_STA_SLEEP_STATE_UAPSD = (1 << 1),
5667 IWM_STA_SLEEP_STATE_MOREDATA = (1 << 2),
5670 /* STA ID and color bits definitions */
5671 #define IWM_STA_ID_SEED (0x0f)
5672 #define IWM_STA_ID_POS (0)
5673 #define IWM_STA_ID_MSK (IWM_STA_ID_SEED << IWM_STA_ID_POS)
5675 #define IWM_STA_COLOR_SEED (0x7)
5676 #define IWM_STA_COLOR_POS (4)
5677 #define IWM_STA_COLOR_MSK (IWM_STA_COLOR_SEED << IWM_STA_COLOR_POS)
5679 #define IWM_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
5680 (((id_n_color) & IWM_STA_COLOR_MSK) >> IWM_STA_COLOR_POS)
5681 #define IWM_STA_ID_N_COLOR_GET_ID(id_n_color) \
5682 (((id_n_color) & IWM_STA_ID_MSK) >> IWM_STA_ID_POS)
5684 #define IWM_STA_KEY_MAX_NUM (16)
5685 #define IWM_STA_KEY_IDX_INVALID (0xff)
5686 #define IWM_STA_KEY_MAX_DATA_KEY_NUM (4)
5687 #define IWM_MAX_GLOBAL_KEYS (4)
5688 #define IWM_STA_KEY_LEN_WEP40 (5)
5689 #define IWM_STA_KEY_LEN_WEP104 (13)
5692 * struct iwm_mvm_keyinfo - key information
5693 * @key_flags: type %iwm_sta_key_flag
5694 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5695 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5696 * @key_offset: key offset in the fw's key table
5697 * @key: 16-byte unicast decryption key
5698 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
5699 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
5700 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
5702 struct iwm_mvm_keyinfo {
5704 uint8_t tkip_rx_tsc_byte2;
5706 uint16_t tkip_rx_ttak[5];
5710 uint64_t tx_secur_seq_cnt;
5711 uint64_t hw_tkip_mic_rx_key;
5712 uint64_t hw_tkip_mic_tx_key;
5715 #define IWM_ADD_STA_STATUS_MASK 0xFF
5716 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000
5717 #define IWM_ADD_STA_BAID_MASK 0x7F00
5718 #define IWM_ADD_STA_BAID_SHIFT 8
5721 * struct iwm_mvm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table.
5722 * ( REPLY_ADD_STA = 0x18 )
5723 * @add_modify: 1: modify existing, 0: add new station
5725 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
5726 * AMPDU for tid x. Set %IWM_STA_MODIFY_TID_DISABLE_TX to change this field.
5727 * @mac_id_n_color: the Mac context this station belongs to
5728 * @addr[IEEE80211_ADDR_LEN]: station's MAC address
5729 * @sta_id: index of station in uCode's station table
5730 * @modify_mask: IWM_STA_MODIFY_*, selects which parameters to modify vs. leave
5731 * alone. 1 - modify, 0 - don't change.
5732 * @station_flags: look at %iwm_sta_flags
5733 * @station_flags_msk: what of %station_flags have changed
5734 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
5735 * Set %IWM_STA_MODIFY_ADD_BA_TID to use this field, and also set
5736 * add_immediate_ba_ssn.
5737 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
5738 * Set %IWM_STA_MODIFY_REMOVE_BA_TID to use this field
5739 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
5740 * add_immediate_ba_tid.
5741 * @sleep_tx_count: number of packets to transmit to station even though it is
5742 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
5743 * keeps track of STA sleep state.
5744 * @sleep_state_flags: Look at %iwm_sta_sleep_flag.
5745 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
5747 * @beamform_flags: beam forming controls
5748 * @tfd_queue_msk: tfd queues used by this station
5750 * The device contains an internal table of per-station information, with info
5751 * on security keys, aggregation parameters, and Tx rates for initial Tx
5752 * attempt and any retries (set by IWM_REPLY_TX_LINK_QUALITY_CMD).
5754 * ADD_STA sets up the table entry for one station, either creating a new
5755 * entry, or modifying a pre-existing one.
5757 struct iwm_mvm_add_sta_cmd_v7 {
5760 uint16_t tid_disable_tx;
5761 uint32_t mac_id_n_color;
5762 uint8_t addr[IEEE80211_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
5765 uint8_t modify_mask;
5767 uint32_t station_flags;
5768 uint32_t station_flags_msk;
5769 uint8_t add_immediate_ba_tid;
5770 uint8_t remove_immediate_ba_tid;
5771 uint16_t add_immediate_ba_ssn;
5772 uint16_t sleep_tx_count;
5773 uint16_t sleep_state_flags;
5775 uint16_t beamform_flags;
5776 uint32_t tfd_queue_msk;
5777 } __packed; /* ADD_STA_CMD_API_S_VER_7 */
5780 * struct iwm_mvm_add_sta_key_cmd - add/modify sta key
5781 * ( IWM_REPLY_ADD_STA_KEY = 0x17 )
5782 * @sta_id: index of station in uCode's station table
5783 * @key_offset: key offset in key storage
5784 * @key_flags: type %iwm_sta_key_flag
5785 * @key: key material data
5786 * @key2: key material data
5787 * @rx_secur_seq_cnt: RX security sequence counter for the key
5788 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
5789 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
5791 struct iwm_mvm_add_sta_key_cmd {
5797 uint8_t rx_secur_seq_cnt[16];
5798 uint8_t tkip_rx_tsc_byte2;
5800 uint16_t tkip_rx_ttak[5];
5801 } __packed; /* IWM_ADD_MODIFY_STA_KEY_API_S_VER_1 */
5804 * enum iwm_mvm_add_sta_rsp_status - status in the response to ADD_STA command
5805 * @IWM_ADD_STA_SUCCESS: operation was executed successfully
5806 * @IWM_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
5807 * @IWM_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
5808 * @IWM_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
5809 * that doesn't exist.
5811 enum iwm_mvm_add_sta_rsp_status {
5812 IWM_ADD_STA_SUCCESS = 0x1,
5813 IWM_ADD_STA_STATIONS_OVERLOAD = 0x2,
5814 IWM_ADD_STA_IMMEDIATE_BA_FAILURE = 0x4,
5815 IWM_ADD_STA_MODIFY_NON_EXISTING_STA = 0x8,
5819 * struct iwm_mvm_rm_sta_cmd - Add / modify a station in the fw's station table
5820 * ( IWM_REMOVE_STA = 0x19 )
5821 * @sta_id: the station id of the station to be removed
5823 struct iwm_mvm_rm_sta_cmd {
5825 uint8_t reserved[3];
5826 } __packed; /* IWM_REMOVE_STA_CMD_API_S_VER_2 */
5829 * struct iwm_mvm_mgmt_mcast_key_cmd
5830 * ( IWM_MGMT_MCAST_KEY = 0x1f )
5831 * @ctrl_flags: %iwm_sta_key_flag
5833 * @K1: IGTK master key
5835 * @sta_id: station ID that support IGTK
5837 * @receive_seq_cnt: initial RSC/PN needed for replay check
5839 struct iwm_mvm_mgmt_mcast_key_cmd {
5840 uint32_t ctrl_flags;
5846 uint64_t receive_seq_cnt;
5847 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
5849 struct iwm_mvm_wep_key {
5854 uint8_t reserved2[3];
5858 struct iwm_mvm_wep_key_cmd {
5859 uint32_t mac_id_n_color;
5861 uint8_t decryption_type;
5864 struct iwm_mvm_wep_key wep_key[0];
5865 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
5871 enum iwm_bt_coex_mode {
5872 IWM_BT_COEX_DISABLE = 0x0,
5873 IWM_BT_COEX_NW = 0x1,
5874 IWM_BT_COEX_BT = 0x2,
5875 IWM_BT_COEX_WIFI = 0x3,
5876 }; /* BT_COEX_MODES_E */
5878 enum iwm_bt_coex_enabled_modules {
5879 IWM_BT_COEX_MPLUT_ENABLED = (1 << 0),
5880 IWM_BT_COEX_MPLUT_BOOST_ENABLED = (1 << 1),
5881 IWM_BT_COEX_SYNC2SCO_ENABLED = (1 << 2),
5882 IWM_BT_COEX_CORUN_ENABLED = (1 << 3),
5883 IWM_BT_COEX_HIGH_BAND_RET = (1 << 4),
5884 }; /* BT_COEX_MODULES_ENABLE_E_VER_1 */
5887 * struct iwm_bt_coex_cmd - bt coex configuration command
5888 * @mode: enum %iwm_bt_coex_mode
5889 * @enabled_modules: enum %iwm_bt_coex_enabled_modules
5891 * The structure is used for the BT_COEX command.
5893 struct iwm_bt_coex_cmd {
5895 uint32_t enabled_modules;
5896 } __packed; /* BT_COEX_CMD_API_S_VER_6 */
5900 * Location Aware Regulatory (LAR) API - MCC updates
5904 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic
5905 * regulatory profile according to the given MCC (Mobile Country Code).
5906 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5907 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5908 * MCC in the cmd response will be the relevant MCC in the NVM.
5909 * @mcc: given mobile country code
5910 * @source_id: the source from where we got the MCC, see iwm_mcc_source
5911 * @reserved: reserved for alignment
5913 struct iwm_mcc_update_cmd_v1 {
5917 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_1 */
5920 * struct iwm_mcc_update_cmd - Request the device to update geographic
5921 * regulatory profile according to the given MCC (Mobile Country Code).
5922 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5923 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5924 * MCC in the cmd response will be the relevant MCC in the NVM.
5925 * @mcc: given mobile country code
5926 * @source_id: the source from where we got the MCC, see iwm_mcc_source
5927 * @reserved: reserved for alignment
5928 * @key: integrity key for MCC API OEM testing
5929 * @reserved2: reserved
5931 struct iwm_mcc_update_cmd {
5936 uint32_t reserved2[5];
5937 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */
5940 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD.
5941 * Contains the new channel control profile map, if changed, and the new MCC
5942 * (mobile country code).
5943 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5944 * @status: see &enum iwm_mcc_update_status
5945 * @mcc: the new applied MCC
5946 * @cap: capabilities for all channels which matches the MCC
5947 * @source_id: the MCC source, see iwm_mcc_source
5948 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5949 * channels, depending on platform)
5950 * @channels: channel control data map, DWORD for each channel. Only the first
5953 struct iwm_mcc_update_resp_v1 {
5958 uint32_t n_channels;
5959 uint32_t channels[0];
5960 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_1 */
5963 * iwm_mcc_update_resp - response to MCC_UPDATE_CMD.
5964 * Contains the new channel control profile map, if changed, and the new MCC
5965 * (mobile country code).
5966 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
5967 * @status: see &enum iwm_mcc_update_status
5968 * @mcc: the new applied MCC
5969 * @cap: capabilities for all channels which matches the MCC
5970 * @source_id: the MCC source, see iwm_mcc_source
5971 * @time: time elapsed from the MCC test start (in 30 seconds TU)
5972 * @reserved: reserved.
5973 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
5974 * channels, depending on platform)
5975 * @channels: channel control data map, DWORD for each channel. Only the first
5978 struct iwm_mcc_update_resp {
5985 uint32_t n_channels;
5986 uint32_t channels[0];
5987 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_2 */
5990 * struct iwm_mcc_chub_notif - chub notifies of mcc change
5991 * (MCC_CHUB_UPDATE_CMD = 0xc9)
5992 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
5993 * the cellular and connectivity cores that gets updates of the mcc, and
5994 * notifies the ucode directly of any mcc change.
5995 * The ucode requests the driver to request the device to update geographic
5996 * regulatory profile according to the given MCC (Mobile Country Code).
5997 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
5998 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
5999 * MCC in the cmd response will be the relevant MCC in the NVM.
6000 * @mcc: given mobile country code
6001 * @source_id: identity of the change originator, see iwm_mcc_source
6002 * @reserved1: reserved for alignment
6004 struct iwm_mcc_chub_notif {
6008 } __packed; /* LAR_MCC_NOTIFY_S */
6010 enum iwm_mcc_update_status {
6011 IWM_MCC_RESP_NEW_CHAN_PROFILE,
6012 IWM_MCC_RESP_SAME_CHAN_PROFILE,
6013 IWM_MCC_RESP_INVALID,
6014 IWM_MCC_RESP_NVM_DISABLED,
6015 IWM_MCC_RESP_ILLEGAL,
6016 IWM_MCC_RESP_LOW_PRIORITY,
6017 IWM_MCC_RESP_TEST_MODE_ACTIVE,
6018 IWM_MCC_RESP_TEST_MODE_NOT_ACTIVE,
6019 IWM_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE,
6022 enum iwm_mcc_source {
6023 IWM_MCC_SOURCE_OLD_FW = 0,
6024 IWM_MCC_SOURCE_ME = 1,
6025 IWM_MCC_SOURCE_BIOS = 2,
6026 IWM_MCC_SOURCE_3G_LTE_HOST = 3,
6027 IWM_MCC_SOURCE_3G_LTE_DEVICE = 4,
6028 IWM_MCC_SOURCE_WIFI = 5,
6029 IWM_MCC_SOURCE_RESERVED = 6,
6030 IWM_MCC_SOURCE_DEFAULT = 7,
6031 IWM_MCC_SOURCE_UNINITIALIZED = 8,
6032 IWM_MCC_SOURCE_MCC_API = 9,
6033 IWM_MCC_SOURCE_GET_CURRENT = 0x10,
6034 IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE = 0x11,
6038 * Some cherry-picked definitions
6041 #define IWM_FRAME_LIMIT 64
6044 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811:
6045 * As the firmware is slowly running out of command IDs and grouping of
6046 * commands is desirable anyway, the firmware is extending the command
6047 * header from 4 bytes to 8 bytes to introduce a group (in place of the
6048 * former flags field, since that's always 0 on commands and thus can
6049 * be easily used to distinguish between the two).
6051 * These functions retrieve specific information from the id field in
6052 * the iwm_host_cmd struct which contains the command id, the group id,
6053 * and the version of the command.
6055 static inline uint8_t
6056 iwm_cmd_opcode(uint32_t cmdid)
6058 return cmdid & 0xff;
6061 static inline uint8_t
6062 iwm_cmd_groupid(uint32_t cmdid)
6064 return ((cmdid & 0Xff00) >> 8);
6067 static inline uint8_t
6068 iwm_cmd_version(uint32_t cmdid)
6070 return ((cmdid & 0xff0000) >> 16);
6073 static inline uint32_t
6074 iwm_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version)
6076 return opcode + (groupid << 8) + (version << 16);
6079 /* make uint16_t wide id out of uint8_t group and opcode */
6080 #define IWM_WIDE_ID(grp, opcode) ((grp << 8) | opcode)
6082 /* due to the conversion, this group is special */
6083 #define IWM_ALWAYS_LONG_GROUP 1
6085 struct iwm_cmd_header {
6092 struct iwm_cmd_header_wide {
6102 enum iwm_power_scheme {
6103 IWM_POWER_SCHEME_CAM = 1,
6104 IWM_POWER_SCHEME_BPS,
6108 #define IWM_DEF_CMD_PAYLOAD_SIZE 320
6109 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
6110 #define IWM_CMD_FAILED_MSK 0x40
6113 * struct iwm_device_cmd
6115 * For allocation of the command and tx queues, this establishes the overall
6116 * size of the largest command we send to uCode, except for commands that
6117 * aren't fully copied and use other TFD space.
6119 struct iwm_device_cmd {
6122 struct iwm_cmd_header hdr;
6123 uint8_t data[IWM_DEF_CMD_PAYLOAD_SIZE];
6126 struct iwm_cmd_header_wide hdr_wide;
6127 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE -
6128 sizeof(struct iwm_cmd_header_wide) +
6129 sizeof(struct iwm_cmd_header)];
6134 struct iwm_rx_packet {
6136 * The first 4 bytes of the RX frame header contain both the RX frame
6137 * size and some flags.
6139 * 31: flag flush RB request
6140 * 30: flag ignore TC (terminal counter) request
6141 * 29: flag fast IRQ request
6143 * 13-00: RX frame size
6145 uint32_t len_n_flags;
6146 struct iwm_cmd_header hdr;
6150 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
6152 static inline uint32_t
6153 iwm_rx_packet_len(const struct iwm_rx_packet *pkt)
6156 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
6159 static inline uint32_t
6160 iwm_rx_packet_payload_len(const struct iwm_rx_packet *pkt)
6163 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
6167 #define IWM_MIN_DBM -100
6168 #define IWM_MAX_DBM -33 /* realistic guess */
6170 #define IWM_READ(sc, reg) \
6171 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
6173 #define IWM_WRITE(sc, reg, val) \
6174 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6176 #define IWM_WRITE_1(sc, reg, val) \
6177 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6179 #define IWM_SETBITS(sc, reg, mask) \
6180 IWM_WRITE(sc, reg, IWM_READ(sc, reg) | (mask))
6182 #define IWM_CLRBITS(sc, reg, mask) \
6183 IWM_WRITE(sc, reg, IWM_READ(sc, reg) & ~(mask))
6185 #define IWM_BARRIER_WRITE(sc) \
6186 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6187 BUS_SPACE_BARRIER_WRITE)
6189 #define IWM_BARRIER_READ_WRITE(sc) \
6190 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6191 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
6193 #endif /* __IF_IWM_REG_H__ */