2 * Core definitions and data structures shareable across OS platforms.
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
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13 * without modification.
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15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
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40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.h#79 $
42 * $FreeBSD: src/sys/dev/aic7xxx/aic7xxx.h,v 1.16.2.16 2003/06/10 03:26:08 gibbs Exp $
43 * $DragonFly: src/sys/dev/disk/aic7xxx/aic7xxx.h,v 1.2 2003/06/17 04:28:22 dillon Exp $
49 /* Register Definitions */
50 #include "aic7xxx_reg.h"
52 /************************* Forward Declarations *******************************/
53 struct ahc_platform_data;
54 struct scb_platform_data;
55 struct seeprom_descriptor;
57 /****************************** Useful Macros *********************************/
59 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
63 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
73 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
75 #define ALL_CHANNELS '\0'
76 #define ALL_TARGETS_MASK 0xFFFF
77 #define INITIATOR_WILDCARD (~0)
79 #define SCSIID_TARGET(ahc, scsiid) \
80 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
82 #define SCSIID_OUR_ID(scsiid) \
84 #define SCSIID_CHANNEL(ahc, scsiid) \
85 ((((ahc)->features & AHC_TWIN) != 0) \
86 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \
88 #define SCB_IS_SCSIBUS_B(ahc, scb) \
89 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
90 #define SCB_GET_OUR_ID(scb) \
91 SCSIID_OUR_ID((scb)->hscb->scsiid)
92 #define SCB_GET_TARGET(ahc, scb) \
93 SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
94 #define SCB_GET_CHANNEL(ahc, scb) \
95 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
96 #define SCB_GET_LUN(scb) \
97 ((scb)->hscb->lun & LID)
98 #define SCB_GET_TARGET_OFFSET(ahc, scb) \
99 (SCB_GET_TARGET(ahc, scb) + (SCB_IS_SCSIBUS_B(ahc, scb) ? 8 : 0))
100 #define SCB_GET_TARGET_MASK(ahc, scb) \
101 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
103 #define SCB_IS_SILENT(scb) \
104 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \
105 && (((scb)->flags & SCB_SILENT) != 0))
107 #define SCB_IS_SILENT(scb) \
108 (((scb)->flags & SCB_SILENT) != 0)
110 #define TCL_TARGET_OFFSET(tcl) \
111 ((((tcl) >> 4) & TID) >> 4)
112 #define TCL_LUN(tcl) \
113 (tcl & (AHC_NUM_LUNS - 1))
114 #define BUILD_TCL(scsiid, lun) \
115 ((lun) | (((scsiid) & TID) << 4))
117 #ifndef AHC_TARGET_MODE
118 #undef AHC_TMODE_ENABLE
119 #define AHC_TMODE_ENABLE 0
122 /**************************** Driver Constants ********************************/
124 * The maximum number of supported targets.
126 #define AHC_NUM_TARGETS 16
129 * The maximum number of supported luns.
130 * The identify message only supports 64 luns in SPI3.
131 * You can have 2^64 luns when information unit transfers are enabled,
132 * but it is doubtful this driver will ever support IUTs.
134 #define AHC_NUM_LUNS 64
137 * The maximum transfer per S/G segment.
139 #define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
142 * The maximum amount of SCB storage in hardware on a controller.
143 * This value represents an upper bound. Controllers vary in the number
144 * they actually support.
146 #define AHC_SCB_MAX 255
149 * The maximum number of concurrent transactions supported per driver instance.
150 * Sequencer Control Blocks (SCBs) store per-transaction information. Although
151 * the space for SCBs on the host adapter varies by model, the driver will
152 * page the SCBs between host and controller memory as needed. We are limited
154 * 1) The 8bit nature of the RISC engine holds us to an 8bit value.
155 * 2) We reserve one value, 255, to represent the invalid element.
156 * 3) Our input queue scheme requires one SCB to always be reserved
157 * in advance of queuing any SCBs. This takes us down to 254.
158 * 4) To handle our output queue correctly on machines that only
159 * support 32bit stores, we must clear the array 4 bytes at a
160 * time. To avoid colliding with a DMA write from the sequencer,
161 * we must be sure that 4 slots are empty when we write to clear
162 * the queue. This reduces us to 253 SCBs: 1 that just completed
163 * and the known three additional empty slots in the queue that
166 #define AHC_MAX_QUEUE 253
169 * The maximum amount of SCB storage we allocate in host memory. This
170 * number should reflect the 1 additional SCB we require to handle our
173 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
176 * Ring Buffer of incoming target commands.
177 * We allocate 256 to simplify the logic in the sequencer
178 * by using the natural wrap point of an 8bit counter.
180 #define AHC_TMODE_CMDS 256
182 /* Reset line assertion time in us */
183 #define AHC_BUSRESET_DELAY 25
185 /******************* Chip Characteristics/Operating Settings *****************/
188 * The chip order is from least sophisticated to most sophisticated.
192 AHC_CHIPID_MASK = 0x00FF,
193 AHC_AIC7770 = 0x0001,
194 AHC_AIC7850 = 0x0002,
195 AHC_AIC7855 = 0x0003,
196 AHC_AIC7859 = 0x0004,
197 AHC_AIC7860 = 0x0005,
198 AHC_AIC7870 = 0x0006,
199 AHC_AIC7880 = 0x0007,
200 AHC_AIC7895 = 0x0008,
201 AHC_AIC7895C = 0x0009,
202 AHC_AIC7890 = 0x000a,
203 AHC_AIC7896 = 0x000b,
204 AHC_AIC7892 = 0x000c,
205 AHC_AIC7899 = 0x000d,
206 AHC_VL = 0x0100, /* Bus type VL */
207 AHC_EISA = 0x0200, /* Bus type EISA */
208 AHC_PCI = 0x0400, /* Bus type PCI */
209 AHC_BUS_MASK = 0x0F00
213 * Features available in each chip type.
216 AHC_FENONE = 0x00000,
217 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */
218 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */
219 AHC_WIDE = 0x00004, /* Wide Channel */
220 AHC_TWIN = 0x00008, /* Twin Channel */
221 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */
222 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */
223 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */
224 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */
225 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */
226 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */
227 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */
228 AHC_DT = 0x00800, /* Double Transition transfers */
229 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */
230 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */
231 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */
232 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/
233 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */
234 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */
235 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */
236 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */
237 AHC_AIC7770_FE = AHC_FENONE,
239 * The real 7850 does not support Ultra modes, but there are
240 * several cards that use the generic 7850 PCI ID even though
241 * they are using an Ultra capable chip (7859/7860). We start
242 * out with the AHC_ULTRA feature set and then check the DEVSTATUS
243 * register to determine if the capability is really present.
245 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA,
246 AHC_AIC7860_FE = AHC_AIC7850_FE,
247 AHC_AIC7870_FE = AHC_TARGETMODE,
248 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA,
250 * Although we have space for both the initiator and
251 * target roles on ULTRA2 chips, we currently disable
252 * the initiator role to allow multi-scsi-id target mode
253 * configurations. We can only respond on the same SCSI
254 * ID as our initiator role if we allow initiator operation.
255 * At some point, we should add a configuration knob to
256 * allow both roles to be loaded.
258 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2
259 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID
260 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS
262 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE,
263 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE
264 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS,
265 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
266 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
267 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC
271 * Bugs in the silicon that we work around in software.
276 * On all chips prior to the U2 product line,
277 * the WIDEODD S/G segment feature does not
278 * work during scsi->HostBus transfers.
280 AHC_TMODE_WIDEODD_BUG = 0x01,
282 * On the aic7890/91 Rev 0 chips, the autoflush
283 * feature does not work. A manual flush of
284 * the DMA FIFO is required.
286 AHC_AUTOFLUSH_BUG = 0x02,
288 * On many chips, cacheline streaming does not work.
290 AHC_CACHETHEN_BUG = 0x04,
292 * On the aic7896/97 chips, cacheline
293 * streaming must be enabled.
295 AHC_CACHETHEN_DIS_BUG = 0x08,
297 * PCI 2.1 Retry failure on non-empty data fifo.
299 AHC_PCI_2_1_RETRY_BUG = 0x10,
301 * Controller does not handle cacheline residuals
302 * properly on S/G segments if PCI MWI instructions
305 AHC_PCI_MWI_BUG = 0x20,
307 * An SCB upload using the SCB channel's
308 * auto array entry copy feature may
309 * corrupt data. This appears to only
310 * occur on 66MHz systems.
312 AHC_SCBCHAN_UPLOAD_BUG = 0x40
316 * Configuration specific settings.
317 * The driver determines these settings by probing the
318 * chip/controller's configuration.
322 AHC_PRIMARY_CHANNEL = 0x003, /*
323 * The channel that should
326 AHC_USEDEFAULTS = 0x004, /*
327 * For cards without an seeprom
328 * or a BIOS to initialize the chip's
329 * SRAM, we use the default target
332 AHC_SEQUENCER_DEBUG = 0x008,
333 AHC_SHARED_SRAM = 0x010,
334 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */
335 AHC_RESET_BUS_A = 0x040,
336 AHC_RESET_BUS_B = 0x080,
337 AHC_EXTENDED_TRANS_A = 0x100,
338 AHC_EXTENDED_TRANS_B = 0x200,
339 AHC_TERM_ENB_A = 0x400,
340 AHC_TERM_ENB_B = 0x800,
341 AHC_INITIATORROLE = 0x1000, /*
342 * Allow initiator operations on
345 AHC_TARGETROLE = 0x2000, /*
346 * Allow target operations on this
349 AHC_NEWEEPROM_FMT = 0x4000,
350 AHC_RESOURCE_SHORTAGE = 0x8000,
351 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */
352 AHC_INT50_SPEEDFLEX = 0x20000, /*
353 * Internal 50pin connector
354 * sits behind an aic3860
356 AHC_SCB_BTT = 0x40000, /*
357 * The busy targets table is
358 * stored in SCB space rather
361 AHC_BIOS_ENABLED = 0x80000,
362 AHC_ALL_INTERRUPTS = 0x100000,
363 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */
364 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */
365 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */
366 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */
367 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */
368 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */
369 AHC_DISABLE_PCI_PERR = 0x10000000,
370 AHC_HAS_TERM_LOGIC = 0x20000000
373 /************************* Hardware SCB Definition ***************************/
376 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
377 * consists of a "hardware SCB" mirroring the fields available on the card
378 * and additional information the kernel stores for each transaction.
380 * To minimize space utilization, a portion of the hardware scb stores
381 * different data during different portions of a SCSI transaction.
382 * As initialized by the host driver for the initiator role, this area
383 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
384 * the cdb has been presented to the target, this area serves to store
385 * residual transfer information and the SCSI status byte.
386 * For the target role, the contents of this area do not change, but
387 * still serve a different purpose than for the initiator role. See
388 * struct target_data for details.
392 * Status information embedded in the shared poriton of
393 * an SCB after passing the cdb to the target. The kernel
394 * driver will only read this data for transactions that
395 * complete abnormally (non-zero status byte).
398 uint32_t residual_datacnt; /* Residual in the current S/G seg */
399 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
400 uint8_t scsi_status; /* Standard SCSI status byte */
404 * Target mode version of the shared data SCB segment.
407 uint32_t residual_datacnt; /* Residual in the current S/G seg */
408 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
409 uint8_t scsi_status; /* SCSI status to give to initiator */
410 uint8_t target_phases; /* Bitmap of phases to execute */
411 uint8_t data_phase; /* Data-In or Data-Out */
412 uint8_t initiator_tag; /* Initiator's transaction tag */
415 struct hardware_scb {
418 * If the cdb is 12 bytes or less, we embed it directly
419 * in the SCB. For longer cdbs, we embed the address
420 * of the cdb payload as seen by the chip and a DMA
421 * is used to pull it in.
425 struct status_pkt status;
426 struct target_data tdata;
429 * A word about residuals.
430 * The scb is presented to the sequencer with the dataptr and datacnt
431 * fields initialized to the contents of the first S/G element to
432 * transfer. The sgptr field is initialized to the bus address for
433 * the S/G element that follows the first in the in core S/G array
434 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
435 * S/G entry for this transfer (single S/G element transfer with the
436 * first elements address and length preloaded in the dataptr/datacnt
437 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
438 * The SG_FULL_RESID flag ensures that the residual will be correctly
439 * noted even if no data transfers occur. Once the data phase is entered,
440 * the residual sgptr and datacnt are loaded from the sgptr and the
441 * datacnt fields. After each S/G element's dataptr and length are
442 * loaded into the hardware, the residual sgptr is advanced. After
443 * each S/G element is expired, its datacnt field is checked to see
444 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
445 * residual sg ptr and the transfer is considered complete. If the
446 * sequencer determines that there is a residual in the tranfer, it
447 * will set the SG_RESID_VALID flag in sgptr and dma the scb back into
448 * host memory. To sumarize:
451 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
452 * or residual_sgptr does not have SG_LIST_NULL set.
454 * o We are transfering the last segment if residual_datacnt has
455 * the SG_LAST_SEG flag set.
458 * o A residual has occurred if a completed scb has the
459 * SG_RESID_VALID flag set.
461 * o residual_sgptr and sgptr refer to the "next" sg entry
462 * and so may point beyond the last valid sg entry for the
465 /*12*/ uint32_t dataptr;
466 /*16*/ uint32_t datacnt; /*
467 * Byte 3 (numbered from 0) of
468 * the datacnt is really the
469 * 4th byte in that data address.
471 /*20*/ uint32_t sgptr;
472 #define SG_PTR_MASK 0xFFFFFFF8
473 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */
474 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */
476 /*27*/ uint8_t tag; /*
477 * Index into our kernel SCB array.
478 * Also used as the tag for tagged I/O
480 /*28*/ uint8_t cdb_len;
481 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */
482 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */
483 /*31*/ uint8_t next; /*
484 * Used for threading SCBs in the
485 * "Waiting for Selection" and
486 * "Disconnected SCB" lists down
489 /*32*/ uint8_t cdb32[32]; /*
490 * CDB storage for cdbs of size
491 * 13->32. We store them here
492 * because hardware scbs are
493 * allocated from DMA safe
494 * memory so we are guaranteed
495 * the controller can access
500 /************************ Kernel SCB Definitions ******************************/
502 * Some fields of the SCB are OS dependent. Here we collect the
503 * definitions for elements that all OS platforms need to include
504 * in there SCB definition.
508 * Definition of a scatter/gather element as transfered to the controller.
509 * The aic7xxx chips only support a 24bit length. We use the top byte of
510 * the length to store additional address bits and a flag to indicate
511 * that a given segment terminates the transfer. This gives us an
512 * addressable range of 512GB on machines with 64bit PCI or with chips
513 * that can support dual address cycles on 32bit PCI busses.
518 #define AHC_DMA_LAST_SEG 0x80000000
519 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000
520 #define AHC_SG_LEN_MASK 0x00FFFFFF
524 bus_dmamap_t sg_dmamap;
525 bus_addr_t sg_physaddr;
526 struct ahc_dma_seg* sg_vaddr;
527 SLIST_ENTRY(sg_map_node) links;
531 * The current state of this SCB.
535 SCB_OTHERTCL_TIMEOUT = 0x0002,/*
536 * Another device was active
537 * during the first timeout for
538 * this SCB so we gave ourselves
539 * an additional timeout period
540 * in case it was hogging the
543 SCB_DEVICE_RESET = 0x0004,
545 SCB_CDB32_PTR = 0x0010,
546 SCB_RECOVERY_SCB = 0x0020,
547 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */
548 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */
550 SCB_UNTAGGEDQ = 0x0200,
552 SCB_TARGET_IMMEDIATE = 0x0800,
553 SCB_TRANSMISSION_ERROR = 0x1000,/*
554 * We detected a parity or CRC
555 * error that has effected the
556 * payload of the command. This
557 * flag is checked when normal
558 * status is returned to catch
559 * the case of a target not
560 * responding to our attempt
561 * to report the error.
563 SCB_TARGET_SCB = 0x2000,
564 SCB_SILENT = 0x4000 /*
565 * Be quiet about transmission type
566 * errors. They are expected and we
567 * don't want to upset the user. This
568 * flag is typically used during DV.
573 struct hardware_scb *hscb;
575 SLIST_ENTRY(scb) sle;
576 TAILQ_ENTRY(scb) tqe;
578 LIST_ENTRY(scb) pending_links;
580 struct ahc_softc *ahc_softc;
585 struct scb_platform_data *platform_data;
586 struct sg_map_node *sg_map;
587 struct ahc_dma_seg *sg_list;
588 bus_addr_t sg_list_phys;
589 u_int sg_count;/* How full ahc_dma_seg is */
593 SLIST_HEAD(, scb) free_scbs; /*
594 * Pool of SCBs ready to be assigned
595 * commands to execute.
597 struct scb *scbindex[256]; /*
598 * Mapping from tag to SCB.
599 * As tag identifiers are an
600 * 8bit value, we provide space
601 * for all possible tag values.
602 * Any lookups to entries at or
603 * above AHC_SCB_MAX_ALLOC will
606 struct hardware_scb *hscbs; /* Array of hardware SCBs */
607 struct scb *scbarray; /* Array of kernel SCBs */
608 struct scsi_sense_data *sense; /* Per SCB sense data */
611 * "Bus" addresses of our data structures.
613 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
614 bus_dmamap_t hscb_dmamap;
615 bus_addr_t hscb_busaddr;
616 bus_dma_tag_t sense_dmat;
617 bus_dmamap_t sense_dmamap;
618 bus_addr_t sense_busaddr;
619 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
620 SLIST_HEAD(, sg_map_node) sg_maps;
622 uint8_t maxhscbs; /* Number of SCBs on the card */
623 uint8_t init_level; /*
624 * How far we've initialized
629 /************************ Target Mode Definitions *****************************/
632 * Connection desciptor for select-in requests in target mode.
635 uint8_t scsiid; /* Our ID and the initiator's ID */
636 uint8_t identify; /* Identify message */
637 uint8_t bytes[22]; /*
638 * Bytes contains any additional message
639 * bytes terminated by 0xFF. The remainder
640 * is the cdb to execute.
642 uint8_t cmd_valid; /*
643 * When a command is complete, the firmware
644 * will set cmd_valid to all bits set.
645 * After the host has seen the command,
646 * the bits are cleared. This allows us
647 * to just peek at host memory to determine
648 * if more work is complete. cmd_valid is on
649 * an 8 byte boundary to simplify setting
650 * it on aic7880 hardware which only has
651 * limited direct access to the DMA FIFO.
657 * Number of events we can buffer up if we run out
658 * of immediate notify ccbs.
660 #define AHC_TMODE_EVENT_BUFFER_SIZE 8
661 struct ahc_tmode_event {
662 uint8_t initiator_id;
663 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
664 #define EVENT_TYPE_BUS_RESET 0xFF
669 * Per enabled lun target mode state.
670 * As this state is directly influenced by the host OS'es target mode
671 * environment, we let the OS module define it. Forward declare the
672 * structure here so we can store arrays of them, etc. in OS neutral
675 #ifdef AHC_TARGET_MODE
676 struct ahc_tmode_lstate {
677 struct cam_path *path;
678 struct ccb_hdr_slist accept_tios;
679 struct ccb_hdr_slist immed_notifies;
680 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
685 struct ahc_tmode_lstate;
688 /******************** Transfer Negotiation Datastructures *********************/
689 #define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */
690 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
691 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
692 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
694 #define AHC_WIDTH_UNKNOWN 0xFF
695 #define AHC_PERIOD_UNKNOWN 0xFF
696 #define AHC_OFFSET_UNKNOWN 0xFF
697 #define AHC_PPR_OPTS_UNKNOWN 0xFF
700 * Transfer Negotiation Information.
702 struct ahc_transinfo {
703 uint8_t protocol_version; /* SCSI Revision level */
704 uint8_t transport_version; /* SPI Revision level */
705 uint8_t width; /* Bus width */
706 uint8_t period; /* Sync rate factor */
707 uint8_t offset; /* Sync offset */
708 uint8_t ppr_options; /* Parallel Protocol Request options */
712 * Per-initiator current, goal and user transfer negotiation information. */
713 struct ahc_initiator_tinfo {
714 uint8_t scsirate; /* Computed value for SCSIRATE reg */
715 struct ahc_transinfo curr;
716 struct ahc_transinfo goal;
717 struct ahc_transinfo user;
721 * Per enabled target ID state.
722 * Pointers to lun target state as well as sync/wide negotiation information
723 * for each initiator<->target mapping. For the initiator role we pretend
724 * that we are the target and the targets are the initiators since the
725 * negotiation is the same regardless of role.
727 struct ahc_tmode_tstate {
728 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS];
729 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS];
732 * Per initiator state bitmasks.
734 uint16_t auto_negotiate;/* Auto Negotiation Required */
735 uint16_t ultraenb; /* Using ultra sync rate */
736 uint16_t discenable; /* Disconnection allowed */
737 uint16_t tagenable; /* Tagged Queuing allowed */
741 * Data structure for our table of allowed synchronous transfer rates.
743 struct ahc_syncrate {
744 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */
745 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */
746 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */
747 #define ST_SXFR 0x010 /* Rate Single Transition Only */
748 #define DT_SXFR 0x040 /* Rate Double Transition Only */
749 uint8_t period; /* Period to send to SCSI target */
753 /* Safe and valid period for async negotiations. */
754 #define AHC_ASYNC_XFER_PERIOD 0x45
755 #define AHC_ULTRA2_XFER_PERIOD 0x0a
758 * Indexes into our table of syncronous transfer rates.
760 #define AHC_SYNCRATE_DT 0
761 #define AHC_SYNCRATE_ULTRA2 1
762 #define AHC_SYNCRATE_ULTRA 3
763 #define AHC_SYNCRATE_FAST 6
764 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT
765 #define AHC_SYNCRATE_MIN 13
767 /***************************** Lookup Tables **********************************/
769 * Phase -> name and message out response
770 * to parity errors in each phase table.
772 struct ahc_phase_table_entry {
774 uint8_t mesg_out; /* Message response to parity errors */
778 /************************** Serial EEPROM Format ******************************/
780 struct seeprom_config {
782 * Per SCSI ID Configuration Flags
784 uint16_t device_flags[16]; /* words 0-15 */
785 #define CFXFER 0x0007 /* synchronous transfer rate */
786 #define CFSYNCH 0x0008 /* enable synchronous transfer */
787 #define CFDISC 0x0010 /* enable disconnection */
788 #define CFWIDEB 0x0020 /* wide bus device */
789 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
790 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */
791 #define CFSTART 0x0100 /* send start unit SCSI command */
792 #define CFINCBIOS 0x0200 /* include in BIOS scan */
793 #define CFRNFOUND 0x0400 /* report even if not found */
794 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
795 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */
796 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */
801 uint16_t bios_control; /* word 16 */
802 #define CFSUPREM 0x0001 /* support all removeable drives */
803 #define CFSUPREMB 0x0002 /* support removeable boot drives */
804 #define CFBIOSEN 0x0004 /* BIOS enabled */
805 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */
806 #define CFSM2DRV 0x0010 /* support more than two drives */
807 #define CFSTPWLEVEL 0x0010 /* Termination level control */
808 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
809 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
810 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */
811 #define CFEXTEND 0x0080 /* extended translation enabled */
812 #define CFSCAMEN 0x0100 /* SCAM enable */
813 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
814 #define CFMSG_VERBOSE 0x0000
815 #define CFMSG_SILENT 0x0200
816 #define CFMSG_DIAG 0x0400
817 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */
821 * Host Adapter Control Bits
823 uint16_t adapter_control; /* word 17 */
824 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
825 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
826 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
827 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
828 #define CFSTERM 0x0004 /* SCSI low byte termination */
829 #define CFWSTERM 0x0008 /* SCSI high byte termination */
830 #define CFSPARITY 0x0010 /* SCSI parity */
831 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
832 #define CFMULTILUN 0x0020
833 #define CFRESETB 0x0040 /* reset SCSI bus at boot */
834 #define CFCLUSTERENB 0x0080 /* Cluster Enable */
835 #define CFBOOTCHAN 0x0300 /* probe this channel first */
836 #define CFBOOTCHANSHIFT 8
837 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/
838 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */
839 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */
840 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/
843 * Bus Release Time, Host Adapter ID
845 uint16_t brtime_id; /* word 18 */
846 #define CFSCSIID 0x000f /* host adapter SCSI ID */
848 #define CFBRTIME 0xff00 /* bus release time */
853 uint16_t max_targets; /* word 19 */
854 #define CFMAXTARG 0x00ff /* maximum targets */
855 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
856 #define CFBOOTID 0xf000 /* Target to boot from */
857 uint16_t res_1[10]; /* words 20-29 */
858 uint16_t signature; /* Signature == 0x250 */
859 #define CFSIGNATURE 0x250
860 #define CFSIGNATURE2 0x300
861 uint16_t checksum; /* word 31 */
864 /**************************** Message Buffer *********************************/
866 MSG_TYPE_NONE = 0x00,
867 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
868 MSG_TYPE_INITIATOR_MSGIN = 0x02,
869 MSG_TYPE_TARGET_MSGOUT = 0x03,
870 MSG_TYPE_TARGET_MSGIN = 0x04
879 /*********************** Software Configuration Structure *********************/
880 TAILQ_HEAD(scb_tailq, scb);
882 struct ahc_aic7770_softc {
884 * Saved register state used for chip_init().
890 struct ahc_pci_softc {
892 * Saved register state used for chip_init().
897 uint8_t csize_lattime;
906 union ahc_bus_softc {
907 struct ahc_aic7770_softc aic7770_softc;
908 struct ahc_pci_softc pci_softc;
911 typedef void (*ahc_bus_intr_t)(struct ahc_softc *);
912 typedef int (*ahc_bus_chip_init_t)(struct ahc_softc *);
913 typedef int (*ahc_bus_suspend_t)(struct ahc_softc *);
914 typedef int (*ahc_bus_resume_t)(struct ahc_softc *);
915 typedef void ahc_callback_t (void *);
919 bus_space_handle_t bsh;
921 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
923 struct scb_data *scb_data;
925 struct scb *next_queued_scb;
928 * SCBs that have been sent to the controller
930 LIST_HEAD(, scb) pending_scbs;
933 * Counting lock for deferring the release of additional
934 * untagged transactions from the untagged_queues. When
935 * the lock is decremented to 0, all queues in the
936 * untagged_queues array are run.
938 u_int untagged_queue_lock;
941 * Per-target queue of untagged-transactions. The
942 * transaction at the head of the queue is the
943 * currently pending untagged transaction for the
944 * target. The driver only allows a single untagged
945 * transaction per target.
947 struct scb_tailq untagged_queues[AHC_NUM_TARGETS];
950 * Bus attachment specific data.
952 union ahc_bus_softc bus_softc;
955 * Platform specific data.
957 struct ahc_platform_data *platform_data;
960 * Platform specific device information.
962 ahc_dev_softc_t dev_softc;
965 * Bus specific device information.
967 ahc_bus_intr_t bus_intr;
970 * Bus specific initialization required
971 * after a chip reset.
973 ahc_bus_chip_init_t bus_chip_init;
976 * Bus specific suspend routine.
978 ahc_bus_suspend_t bus_suspend;
981 * Bus specific resume routine.
983 ahc_bus_resume_t bus_resume;
986 * Target mode related state kept on a per enabled lun basis.
987 * Targets that are not enabled will have null entries.
988 * As an initiator, we keep one target entry for our initiator
989 * ID to store our sync/wide transfer settings.
991 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS];
994 * The black hole device responsible for handling requests for
995 * disabled luns on enabled targets.
997 struct ahc_tmode_lstate *black_hole;
1000 * Device instance currently on the bus awaiting a continue TIO
1001 * for a command that was not given the disconnect priveledge.
1003 struct ahc_tmode_lstate *pending_device;
1006 * Card characteristics
1009 ahc_feature features;
1012 struct seeprom_config *seep_config;
1014 /* Values to store in the SEQCTL register for pause and unpause */
1018 /* Command Queues */
1019 uint8_t qoutfifonext;
1020 uint8_t qinfifonext;
1024 /* Critical Section Data */
1025 struct cs *critical_sections;
1026 u_int num_critical_sections;
1028 /* Links for chaining softcs */
1029 TAILQ_ENTRY(ahc_softc) links;
1031 /* Channel Names ('A', 'B', etc.) */
1035 /* Initiator Bus ID */
1040 * PCI error detection.
1042 int unsolicited_ints;
1045 * Target incoming command FIFO.
1047 struct target_cmd *targetcmds;
1048 uint8_t tqinfifonext;
1051 * Cached copy of the sequencer control register.
1056 * Incoming and outgoing message handling.
1058 uint8_t send_msg_perror;
1059 ahc_msg_type msg_type;
1060 uint8_t msgout_buf[12];/* Message we are sending */
1061 uint8_t msgin_buf[12];/* Message we are receiving */
1062 u_int msgout_len; /* Length of message to send */
1063 u_int msgout_index; /* Current index in msgout */
1064 u_int msgin_index; /* Current index in msgin */
1067 * Mapping information for data structures shared
1068 * between the sequencer and kernel.
1070 bus_dma_tag_t parent_dmat;
1071 bus_dma_tag_t shared_data_dmat;
1072 bus_dmamap_t shared_data_dmamap;
1073 bus_addr_t shared_data_busaddr;
1076 * Bus address of the one byte buffer used to
1077 * work-around a DMA bug for chips <= aic7880
1080 bus_addr_t dma_bug_buf;
1082 /* Number of enabled target mode device on this card */
1085 /* Initialization level of this data structure */
1088 /* PCI cacheline size. */
1089 u_int pci_cachesize;
1092 * Count of parity errors we have seen as a target.
1093 * We auto-disable parity error checking after seeing
1094 * AHC_PCI_TARGET_PERR_THRESH number of errors.
1096 u_int pci_target_perr_count;
1097 #define AHC_PCI_TARGET_PERR_THRESH 10
1099 /* Maximum number of sequencer instructions supported. */
1100 u_int instruction_ram_size;
1102 /* Per-Unit descriptive information */
1103 const char *description;
1107 /* Selection Timer settings */
1111 uint16_t user_discenable;/* Disconnection allowed */
1112 uint16_t user_tagenable;/* Tagged Queuing allowed */
1115 TAILQ_HEAD(ahc_softc_tailq, ahc_softc);
1116 extern struct ahc_softc_tailq ahc_tailq;
1118 /************************ Active Device Information ***************************/
1125 struct ahc_devinfo {
1128 uint16_t target_mask;
1133 * Only guaranteed to be correct if not
1134 * in the busfree state.
1138 /****************************** PCI Structures ********************************/
1139 typedef int (ahc_device_setup_t)(struct ahc_softc *);
1141 struct ahc_pci_identity {
1145 ahc_device_setup_t *setup;
1147 extern struct ahc_pci_identity ahc_pci_ident_table[];
1148 extern const u_int ahc_num_pci_devs;
1150 /***************************** VL/EISA Declarations ***************************/
1151 struct aic7770_identity {
1155 ahc_device_setup_t *setup;
1157 extern struct aic7770_identity aic7770_ident_table[];
1158 extern const int ahc_num_aic7770_devs;
1160 #define AHC_EISA_SLOT_OFFSET 0xc00
1161 #define AHC_EISA_IOSIZE 0x100
1163 /*************************** Function Declarations ****************************/
1164 /******************************************************************************/
1165 u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl);
1166 void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl);
1167 void ahc_busy_tcl(struct ahc_softc *ahc,
1168 u_int tcl, u_int busyid);
1170 /***************************** PCI Front End *********************************/
1171 struct ahc_pci_identity *ahc_find_pci_device(ahc_dev_softc_t);
1172 int ahc_pci_config(struct ahc_softc *,
1173 struct ahc_pci_identity *);
1174 int ahc_pci_test_register_access(struct ahc_softc *);
1176 /*************************** EISA/VL Front End ********************************/
1177 struct aic7770_identity *aic7770_find_device(uint32_t);
1178 int aic7770_config(struct ahc_softc *ahc,
1179 struct aic7770_identity *,
1182 /************************** SCB and SCB queue management **********************/
1183 int ahc_probe_scbs(struct ahc_softc *);
1184 void ahc_run_untagged_queues(struct ahc_softc *ahc);
1185 void ahc_run_untagged_queue(struct ahc_softc *ahc,
1186 struct scb_tailq *queue);
1187 void ahc_qinfifo_requeue_tail(struct ahc_softc *ahc,
1189 int ahc_match_scb(struct ahc_softc *ahc, struct scb *scb,
1190 int target, char channel, int lun,
1191 u_int tag, role_t role);
1193 /****************************** Initialization ********************************/
1194 struct ahc_softc *ahc_alloc(void *platform_arg, char *name);
1195 int ahc_softc_init(struct ahc_softc *);
1196 void ahc_controller_info(struct ahc_softc *ahc, char *buf);
1197 int ahc_chip_init(struct ahc_softc *ahc);
1198 int ahc_init(struct ahc_softc *ahc);
1199 void ahc_intr_enable(struct ahc_softc *ahc, int enable);
1200 void ahc_pause_and_flushwork(struct ahc_softc *ahc);
1201 int ahc_suspend(struct ahc_softc *ahc);
1202 int ahc_resume(struct ahc_softc *ahc);
1203 void ahc_softc_insert(struct ahc_softc *);
1204 struct ahc_softc *ahc_find_softc(struct ahc_softc *ahc);
1205 void ahc_set_unit(struct ahc_softc *, int);
1206 void ahc_set_name(struct ahc_softc *, char *);
1207 void ahc_alloc_scbs(struct ahc_softc *ahc);
1208 void ahc_free(struct ahc_softc *ahc);
1209 int ahc_reset(struct ahc_softc *ahc, int reinit);
1210 void ahc_shutdown(void *arg);
1212 /*************************** Interrupt Services *******************************/
1213 void ahc_clear_intstat(struct ahc_softc *ahc);
1214 void ahc_run_qoutfifo(struct ahc_softc *ahc);
1215 #ifdef AHC_TARGET_MODE
1216 void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused);
1218 void ahc_handle_brkadrint(struct ahc_softc *ahc);
1219 void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat);
1220 void ahc_handle_scsiint(struct ahc_softc *ahc,
1222 void ahc_clear_critical_section(struct ahc_softc *ahc);
1224 /***************************** Error Recovery *********************************/
1229 } ahc_search_action;
1230 int ahc_search_qinfifo(struct ahc_softc *ahc, int target,
1231 char channel, int lun, u_int tag,
1232 role_t role, uint32_t status,
1233 ahc_search_action action);
1234 int ahc_search_untagged_queues(struct ahc_softc *ahc,
1236 int target, char channel,
1237 int lun, uint32_t status,
1238 ahc_search_action action);
1239 int ahc_search_disc_list(struct ahc_softc *ahc, int target,
1240 char channel, int lun, u_int tag,
1241 int stop_on_first, int remove,
1243 void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb);
1244 int ahc_reset_channel(struct ahc_softc *ahc, char channel,
1245 int initiate_reset);
1246 int ahc_abort_scbs(struct ahc_softc *ahc, int target,
1247 char channel, int lun, u_int tag,
1248 role_t role, uint32_t status);
1249 void ahc_restart(struct ahc_softc *ahc);
1250 void ahc_calc_residual(struct ahc_softc *ahc,
1252 /*************************** Utility Functions ********************************/
1253 struct ahc_phase_table_entry*
1254 ahc_lookup_phase_entry(int phase);
1255 void ahc_compile_devinfo(struct ahc_devinfo *devinfo,
1256 u_int our_id, u_int target,
1257 u_int lun, char channel,
1259 /************************** Transfer Negotiation ******************************/
1260 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1261 u_int *ppr_options, u_int maxsync);
1262 u_int ahc_find_period(struct ahc_softc *ahc,
1263 u_int scsirate, u_int maxsync);
1264 void ahc_validate_offset(struct ahc_softc *ahc,
1265 struct ahc_initiator_tinfo *tinfo,
1266 struct ahc_syncrate *syncrate,
1267 u_int *offset, int wide,
1269 void ahc_validate_width(struct ahc_softc *ahc,
1270 struct ahc_initiator_tinfo *tinfo,
1274 * Negotiation types. These are used to qualify if we should renegotiate
1275 * even if our goal and current transport parameters are identical.
1278 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1279 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1280 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */
1282 int ahc_update_neg_request(struct ahc_softc*,
1283 struct ahc_devinfo*,
1284 struct ahc_tmode_tstate*,
1285 struct ahc_initiator_tinfo*,
1287 void ahc_set_width(struct ahc_softc *ahc,
1288 struct ahc_devinfo *devinfo,
1289 u_int width, u_int type, int paused);
1290 void ahc_set_syncrate(struct ahc_softc *ahc,
1291 struct ahc_devinfo *devinfo,
1292 struct ahc_syncrate *syncrate,
1293 u_int period, u_int offset,
1295 u_int type, int paused);
1302 void ahc_set_tags(struct ahc_softc *ahc,
1303 struct ahc_devinfo *devinfo,
1306 /**************************** Target Mode *************************************/
1307 #ifdef AHC_TARGET_MODE
1308 void ahc_send_lstate_events(struct ahc_softc *,
1309 struct ahc_tmode_lstate *);
1310 void ahc_handle_en_lun(struct ahc_softc *ahc,
1311 struct cam_sim *sim, union ccb *ccb);
1312 cam_status ahc_find_tmode_devs(struct ahc_softc *ahc,
1313 struct cam_sim *sim, union ccb *ccb,
1314 struct ahc_tmode_tstate **tstate,
1315 struct ahc_tmode_lstate **lstate,
1316 int notfound_failure);
1317 #ifndef AHC_TMODE_ENABLE
1318 #define AHC_TMODE_ENABLE 0
1321 /******************************* Debug ***************************************/
1323 extern uint32_t ahc_debug;
1324 #define AHC_SHOW_MISC 0x0001
1325 #define AHC_SHOW_SENSE 0x0002
1326 #define AHC_DUMP_SEEPROM 0x0004
1327 #define AHC_SHOW_TERMCTL 0x0008
1328 #define AHC_SHOW_MEMORY 0x0010
1329 #define AHC_SHOW_MESSAGES 0x0020
1330 #define AHC_SHOW_DV 0x0040
1331 #define AHC_SHOW_SELTO 0x0080
1332 #define AHC_SHOW_QFULL 0x0200
1333 #define AHC_SHOW_QUEUE 0x0400
1334 #define AHC_SHOW_TQIN 0x0800
1335 #define AHC_SHOW_MASKED_ERRORS 0x1000
1336 #define AHC_DEBUG_SEQUENCER 0x2000
1338 void ahc_print_scb(struct scb *scb);
1339 void ahc_print_devinfo(struct ahc_softc *ahc,
1340 struct ahc_devinfo *dev);
1341 void ahc_dump_card_state(struct ahc_softc *ahc);
1342 int ahc_print_register(ahc_reg_parse_entry_t *table,
1349 /******************************* SEEPROM *************************************/
1350 int ahc_acquire_seeprom(struct ahc_softc *ahc,
1351 struct seeprom_descriptor *sd);
1352 void ahc_release_seeprom(struct seeprom_descriptor *sd);
1353 #endif /* _AIC7XXX_H_ */