2 * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * $FreeBSD: src/sys/i386/isa/if_le.c,v 1.56.2.4 2002/06/05 23:24:10 paul Exp $
25 * $DragonFly: src/sys/dev/netif/le/if_le.c,v 1.3 2003/07/26 19:07:48 rob Exp $
29 * DEC EtherWORKS 2 Ethernet Controllers
30 * DEC EtherWORKS 3 Ethernet Controllers
32 * Written by Matt Thomas
33 * BPF support code stolen directly from if_ec.c
35 * This driver supports the DEPCA, DE100, DE101, DE200, DE201,
36 * DE2002, DE203, DE204, DE205, and DE422 cards.
43 #include <sys/param.h>
44 #include <sys/systm.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/malloc.h>
51 #include <net/ethernet.h>
53 #include <net/if_types.h>
54 #include <net/if_dl.h>
56 #include <netinet/in.h>
57 #include <netinet/if_ether.h>
60 #include <machine/clock.h>
62 #include <i386/isa/isa_device.h>
63 #include <i386/isa/icu.h>
70 /* Forward declarations */
71 typedef struct le_softc le_softc_t;
72 typedef struct le_board le_board_t;
74 typedef u_short le_mcbits_t;
75 #define LE_MC_NBPW_LOG2 4
76 #define LE_MC_NBPW (1 << LE_MC_NBPW_LOG2)
78 #if !defined(LE_NOLEMAC)
80 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
82 * Start of DEC EtherWORKS III (LEMAC) dependent structures
85 #include <i386/isa/ic/lemac.h> /* Include LEMAC definitions */
87 static int lemac_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
89 struct le_lemac_info {
90 u_int lemac__lastpage; /* last 2K page */
91 u_int lemac__memmode; /* Are we in 2K, 32K, or 64K mode */
92 u_int lemac__membase; /* Physical address of start of RAM */
93 u_int lemac__txctl; /* Transmit Control Byte */
94 u_int lemac__txmax; /* Maximum # of outstanding transmits */
95 le_mcbits_t lemac__mctbl[LEMAC_MCTBL_SIZE/sizeof(le_mcbits_t)];
96 /* local copy of multicast table */
97 u_char lemac__eeprom[LEMAC_EEP_SIZE]; /* local copy eeprom */
98 char lemac__prodname[LEMAC_EEP_PRDNMSZ+1]; /* prodname name */
99 #define lemac_lastpage le_un.un_lemac.lemac__lastpage
100 #define lemac_memmode le_un.un_lemac.lemac__memmode
101 #define lemac_membase le_un.un_lemac.lemac__membase
102 #define lemac_txctl le_un.un_lemac.lemac__txctl
103 #define lemac_txmax le_un.un_lemac.lemac__txmax
104 #define lemac_mctbl le_un.un_lemac.lemac__mctbl
105 #define lemac_eeprom le_un.un_lemac.lemac__eeprom
106 #define lemac_prodname le_un.un_lemac.lemac__prodname
108 #endif /* !defined(LE_NOLEMAC) */
110 #if !defined(LE_NOLANCE)
112 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
114 * Start of DEC EtherWORKS II (LANCE) dependent structures
118 #include <i386/isa/ic/am7990.h>
124 static int depca_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
126 typedef struct lance_descinfo lance_descinfo_t;
127 typedef struct lance_ring lance_ring_t;
129 typedef unsigned lance_addr_t;
131 struct lance_descinfo {
132 caddr_t di_addr; /* address of descriptor */
133 lance_addr_t di_bufaddr; /* LANCE address of buffer owned by descriptor */
134 unsigned di_buflen; /* size of buffer owned by descriptor */
135 struct mbuf *di_mbuf; /* mbuf being transmitted/received */
139 lance_descinfo_t *ri_first; /* Pointer to first descriptor in ring */
140 lance_descinfo_t *ri_last; /* Pointer to last + 1 descriptor in ring */
141 lance_descinfo_t *ri_nextin; /* Pointer to next one to be given to HOST */
142 lance_descinfo_t *ri_nextout; /* Pointer to next one to be given to LANCE */
143 unsigned ri_max; /* Size of Ring - 1 */
144 unsigned ri_free; /* Number of free rings entires (owned by HOST) */
145 lance_addr_t ri_heap; /* Start of RAM for this ring */
146 lance_addr_t ri_heapend; /* End + 1 of RAM for this ring */
147 lance_addr_t ri_outptr; /* Pointer to first output byte */
148 unsigned ri_outsize; /* Space remaining for output */
151 struct le_lance_info {
152 unsigned lance__csr1; /* LANCE Address of init block (low 16) */
153 unsigned lance__csr2; /* LANCE Address of init block (high 8) */
154 unsigned lance__csr3; /* Copy of CSR3 */
155 unsigned lance__rap; /* IO Port Offset of RAP */
156 unsigned lance__rdp; /* IO Port Offset of RDP */
157 unsigned lance__ramoffset; /* Offset to valid LANCE RAM */
158 unsigned lance__ramsize; /* Amount of RAM shared by LANCE */
159 unsigned lance__rxbufsize; /* Size of a receive buffer */
160 ln_initb_t lance__initb; /* local copy of LANCE initblock */
161 ln_initb_t *lance__raminitb; /* copy to board's LANCE initblock (debugging) */
162 ln_desc_t *lance__ramdesc; /* copy to board's LANCE descriptors (debugging) */
163 lance_ring_t lance__rxinfo; /* Receive ring information */
164 lance_ring_t lance__txinfo; /* Transmit ring information */
165 #define lance_csr1 le_un.un_lance.lance__csr1
166 #define lance_csr2 le_un.un_lance.lance__csr2
167 #define lance_csr3 le_un.un_lance.lance__csr3
168 #define lance_rap le_un.un_lance.lance__rap
169 #define lance_rdp le_un.un_lance.lance__rdp
170 #define lance_ramoffset le_un.un_lance.lance__ramoffset
171 #define lance_ramsize le_un.un_lance.lance__ramsize
172 #define lance_rxbufsize le_un.un_lance.lance__rxbufsize
173 #define lance_initb le_un.un_lance.lance__initb
174 #define lance_raminitb le_un.un_lance.lance__raminitb
175 #define lance_ramdesc le_un.un_lance.lance__ramdesc
176 #define lance_rxinfo le_un.un_lance.lance__rxinfo
177 #define lance_txinfo le_un.un_lance.lance__txinfo
179 #endif /* !defined(LE_NOLANCE) */
182 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
184 * Start of Common Code
188 static void (*le_intrvec[NLE])(le_softc_t *sc);
191 * Ethernet status, per interface.
194 struct arpcom le_ac; /* Common Ethernet/ARP Structure */
195 void (*if_init) __P((void *));/* Interface init routine */
196 void (*if_reset) __P((le_softc_t *));/* Interface reset routine */
197 caddr_t le_membase; /* Starting memory address (virtual) */
198 unsigned le_iobase; /* Starting I/O base address */
199 unsigned le_irq; /* Interrupt Request Value */
200 unsigned le_flags; /* local copy of if_flags */
201 #define LE_BRDCSTONLY 0x01000000 /* If only broadcast is enabled */
202 u_int le_mcmask; /* bit mask for CRC-32 for multicast hash */
203 le_mcbits_t *le_mctbl; /* pointer to multicast table */
204 const char *le_prodname; /* product name DE20x-xx */
205 u_char le_hwaddr[6]; /* local copy of hwaddr */
207 #if !defined(LE_NOLEMAC)
208 struct le_lemac_info un_lemac; /* LEMAC specific information */
210 #if !defined(LE_NOLANCE)
211 struct le_lance_info un_lance; /* Am7990 specific information */
215 #define le_if le_ac.ac_if
218 static int le_probe(struct isa_device *dvp);
219 static int le_attach(struct isa_device *dvp);
220 static ointhand2_t le_intr;
221 static int le_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
222 static void le_input(le_softc_t *sc, caddr_t seg1, size_t total_len,
223 size_t len2, caddr_t seg2);
224 static void le_multi_filter(le_softc_t *sc);
225 static void le_multi_op(le_softc_t *sc, const u_char *mca, int oper_flg);
226 static int le_read_macaddr(le_softc_t *sc, int ioreg, int skippat);
228 #define LE_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian */
231 int (*bd_probe)(le_softc_t *sc, const le_board_t *bd, int *msize);
235 static le_softc_t le_softc[NLE];
237 static const le_board_t le_boards[] = {
238 #if !defined(LE_NOLEMAC)
239 { lemac_probe }, /* DE20[345] */
241 #if !defined(LE_NOLANCE)
242 { depca_probe }, /* DE{20[012],422} */
244 { NULL } /* Must Be Last! */
248 * This tells the autoconf code how to set us up.
250 struct isa_driver ledriver = {
251 le_probe, le_attach, "le",
254 static unsigned le_intrs[NLE];
256 #define LE_ADDREQUAL(a1, a2) \
257 (((u_short *)a1)[0] == ((u_short *)a2)[0] \
258 || ((u_short *)a1)[1] == ((u_short *)a2)[1] \
259 || ((u_short *)a1)[2] == ((u_short *)a2)[2])
260 #define LE_ADDRBRDCST(a1) \
261 (((u_short *)a1)[0] == 0xFFFFU \
262 || ((u_short *)a1)[1] == 0xFFFFU \
263 || ((u_short *)a1)[2] == 0xFFFFU)
265 #define LE_INL(sc, reg) \
267 __asm __volatile("inl %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
271 #define LE_OUTL(sc, reg, data) \
272 ({__asm __volatile("outl %0, %1"::"a" ((u_int)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
274 #define LE_INW(sc, reg) \
276 __asm __volatile("inw %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
280 #define LE_OUTW(sc, reg, data) \
281 ({__asm __volatile("outw %0, %1"::"a" ((u_short)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
283 #define LE_INB(sc, reg) \
285 __asm __volatile("inb %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
289 #define LE_OUTB(sc, reg, data) \
290 ({__asm __volatile("outb %0, %1"::"a" ((u_char)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
292 #define MEMCPY(to, from, len) bcopy(from, to, len)
293 #define MEMSET(where, what, howmuch) bzero(where, howmuch)
294 #define MEMCMP(l, r, len) bcmp(l, r, len)
299 struct isa_device *dvp)
301 le_softc_t *sc = &le_softc[dvp->id_unit];
302 const le_board_t *bd;
305 if (dvp->id_unit >= NLE) {
306 printf("%s%d not configured -- too many devices\n",
307 ledriver.name, dvp->id_unit);
311 sc->le_iobase = dvp->id_iobase;
312 sc->le_membase = (u_char *) dvp->id_maddr;
313 sc->le_irq = dvp->id_irq;
314 sc->le_if.if_name = ledriver.name;
315 sc->le_if.if_unit = dvp->id_unit;
318 * Find and Initialize board..
321 sc->le_flags &= ~(IFF_UP|IFF_ALLMULTI);
323 for (bd = le_boards; bd->bd_probe != NULL; bd++) {
324 if ((iospace = (*bd->bd_probe)(sc, bd, &dvp->id_msize)) != 0) {
334 struct isa_device *dvp)
336 le_softc_t *sc = &le_softc[dvp->id_unit];
337 struct ifnet *ifp = &sc->le_if;
339 dvp->id_ointr = le_intr;
341 ifp->if_mtu = ETHERMTU;
342 printf("%s%d: %s ethernet address %6D\n",
343 ifp->if_name, ifp->if_unit,
345 sc->le_ac.ac_enaddr, ":");
347 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
348 ifp->if_output = ether_output;
349 ifp->if_ioctl = le_ioctl;
350 ifp->if_type = IFT_ETHER;
353 ifp->if_init = sc->if_init;
355 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
367 (*le_intrvec[unit])(&le_softc[unit]);
382 struct ether_header eh;
385 if (total_len - sizeof(eh) > ETHERMTU
386 || total_len - sizeof(eh) < ETHERMIN) {
387 sc->le_if.if_ierrors++;
390 MEMCPY(&eh, seg1, sizeof(eh));
392 seg1 += sizeof(eh); total_len -= sizeof(eh); len1 -= sizeof(eh);
394 MGETHDR(m, M_DONTWAIT, MT_DATA);
396 sc->le_if.if_ierrors++;
399 m->m_pkthdr.len = total_len;
400 m->m_pkthdr.rcvif = &sc->le_if;
401 if (total_len + LE_XTRA > MHLEN /* >= MINCLSIZE */) {
402 MCLGET(m, M_DONTWAIT);
403 if ((m->m_flags & M_EXT) == 0) {
405 sc->le_if.if_ierrors++;
408 } else if (total_len + LE_XTRA > MHLEN && MINCLSIZE == (MHLEN+MLEN)) {
409 MGET(m->m_next, M_DONTWAIT, MT_DATA);
410 if (m->m_next == NULL) {
412 sc->le_if.if_ierrors++;
415 m->m_next->m_len = total_len - MHLEN - LE_XTRA;
416 len1 = total_len = MHLEN - LE_XTRA;
417 MEMCPY(mtod(m->m_next, caddr_t), &seg1[MHLEN-LE_XTRA], m->m_next->m_len);
418 } else if (total_len + LE_XTRA > MHLEN) {
419 panic("le_input: pkt of unknown length");
421 m->m_data += LE_XTRA;
422 m->m_len = total_len;
423 MEMCPY(mtod(m, caddr_t), seg1, len1);
425 MEMCPY(mtod(m, caddr_t) + len1, seg2, total_len - len1);
426 ether_input(&sc->le_if, &eh, m);
435 le_softc_t *sc = ifp->if_softc;
438 if ((sc->le_flags & IFF_UP) == 0)
447 error = ether_ioctl(ifp, cmd, data);
458 * Update multicast listeners
474 * This is the standard method of reading the DEC Address ROMS.
475 * I don't understand it but it does work.
483 int cksum, rom_cksum;
486 int idx, idx2, found, octet;
487 static u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
490 for (idx = 0; idx < 32; idx++) {
491 octet = LE_INB(sc, ioreg);
493 if (octet == testpat[idx2]) {
494 if (++idx2 == sizeof testpat) {
508 sc->le_hwaddr[0] = LE_INB(sc, ioreg);
509 sc->le_hwaddr[1] = LE_INB(sc, ioreg);
511 cksum = *(u_short *) &sc->le_hwaddr[0];
513 sc->le_hwaddr[2] = LE_INB(sc, ioreg);
514 sc->le_hwaddr[3] = LE_INB(sc, ioreg);
516 if (cksum > 65535) cksum -= 65535;
517 cksum += *(u_short *) &sc->le_hwaddr[2];
518 if (cksum > 65535) cksum -= 65535;
520 sc->le_hwaddr[4] = LE_INB(sc, ioreg);
521 sc->le_hwaddr[5] = LE_INB(sc, ioreg);
523 if (cksum > 65535) cksum -= 65535;
524 cksum += *(u_short *) &sc->le_hwaddr[4];
525 if (cksum >= 65535) cksum -= 65535;
527 rom_cksum = LE_INB(sc, ioreg);
528 rom_cksum |= LE_INB(sc, ioreg) << 8;
530 if (cksum != rom_cksum)
539 struct ifmultiaddr *ifma;
541 MEMSET(sc->le_mctbl, 0, (sc->le_mcmask + 1) / 8);
543 if (sc->le_if.if_flags & IFF_ALLMULTI) {
544 sc->le_flags |= IFF_MULTICAST|IFF_ALLMULTI;
547 sc->le_flags &= ~IFF_MULTICAST;
548 /* if (interface has had an address assigned) { */
549 le_multi_op(sc, etherbroadcastaddr, TRUE);
550 sc->le_flags |= LE_BRDCSTONLY|IFF_MULTICAST;
553 sc->le_flags |= IFF_MULTICAST;
555 for (ifma = sc->le_ac.ac_if.if_multiaddrs.lh_first; ifma;
556 ifma = ifma->ifma_link.le_next) {
557 if (ifma->ifma_addr->sa_family != AF_LINK)
560 le_multi_op(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1);
561 sc->le_flags &= ~LE_BRDCSTONLY;
571 u_int idx, bit, data, crc = 0xFFFFFFFFUL;
574 for (data = *(__unaligned u_long *) mca, bit = 0; bit < 48; bit++, data >>=
576 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
578 for (idx = 0; idx < 6; idx++)
579 for (data = *mca++, bit = 0; bit < 8; bit++, data >>= 1)
580 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
583 * The following two line convert the N bit index into a longword index
584 * and a longword mask.
586 crc &= sc->le_mcmask;
587 bit = 1 << (crc & (LE_MC_NBPW -1));
588 idx = crc >> (LE_MC_NBPW_LOG2);
591 * Set or clear hash filter bit in our table.
594 sc->le_mctbl[idx] |= bit; /* Set Bit */
596 sc->le_mctbl[idx] &= ~bit; /* Clear Bit */
600 #if !defined(LE_NOLEMAC)
602 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
604 * Start of DEC EtherWORKS III (LEMAC) dependent code
608 #define LEMAC_INTR_ENABLE(sc) \
609 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_ALL)
611 #define LEMAC_INTR_DISABLE(sc) \
612 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ~LEMAC_IC_ALL)
614 #define LEMAC_64K_MODE(mbase) (((mbase) >= 0x0A) && ((mbase) <= 0x0F))
615 #define LEMAC_32K_MODE(mbase) (((mbase) >= 0x14) && ((mbase) <= 0x1F))
616 #define LEMAC_2K_MODE(mbase) ( (mbase) >= 0x40)
618 static void lemac_init(void *xsc);
619 static void lemac_start(struct ifnet *ifp);
620 static void lemac_reset(le_softc_t *sc);
621 static void lemac_intr(le_softc_t *sc);
622 static void lemac_rne_intr(le_softc_t *sc);
623 static void lemac_tne_intr(le_softc_t *sc);
624 static void lemac_txd_intr(le_softc_t *sc, unsigned cs_value);
625 static void lemac_rxd_intr(le_softc_t *sc, unsigned cs_value);
626 static int lemac_read_eeprom(le_softc_t *sc);
627 static void lemac_init_adapmem(le_softc_t *sc);
629 #define LE_MCBITS_ALL_1S ((le_mcbits_t)~(le_mcbits_t)0)
631 static const le_mcbits_t lemac_allmulti_mctbl[16] = {
632 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
633 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
634 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
635 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
638 * An IRQ mapping table. Less space than switch statement.
640 static const int lemac_irqs[] = { IRQ5, IRQ10, IRQ11, IRQ15 };
643 * Some tuning/monitoring variables.
645 static unsigned lemac_deftxmax = 16; /* see lemac_max above */
646 static unsigned lemac_txnospc = 0; /* total # of tranmit starvations */
648 static unsigned lemac_tne_intrs = 0; /* total # of tranmit done intrs */
649 static unsigned lemac_rne_intrs = 0; /* total # of receive done intrs */
650 static unsigned lemac_txd_intrs = 0; /* total # of tranmit error intrs */
651 static unsigned lemac_rxd_intrs = 0; /* total # of receive error intrs */
657 const le_board_t *bd,
662 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
663 DELAY(LEMAC_EEP_DELAY);
666 * Read Ethernet address if card is present.
668 if (le_read_macaddr(sc, LEMAC_REG_APD, 0) < 0)
671 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
673 * Clear interrupts and set IRQ.
676 portval = LE_INB(sc, LEMAC_REG_IC) & LEMAC_IC_IRQMSK;
677 irq = lemac_irqs[portval >> 5];
678 LE_OUTB(sc, LEMAC_REG_IC, portval);
681 * Make sure settings match.
684 if (irq != sc->le_irq) {
685 printf("%s%d: lemac configuration error: expected IRQ 0x%x actual 0x%x\n",
686 sc->le_if.if_name, sc->le_if.if_unit, sc->le_irq, irq);
691 * Try to reset the unit
693 sc->if_init = lemac_init;
694 sc->le_if.if_start = lemac_start;
695 sc->if_reset = lemac_reset;
696 sc->lemac_memmode = 2;
698 if ((sc->le_flags & IFF_UP) == 0)
702 * Check for correct memory base configuration.
704 if (vtophys(sc->le_membase) != sc->lemac_membase) {
705 printf("%s%d: lemac configuration error: expected iomem 0x%x actual 0x%x\n",
706 sc->le_if.if_name, sc->le_if.if_unit,
707 vtophys(sc->le_membase), sc->lemac_membase);
711 sc->le_prodname = sc->lemac_prodname;
712 sc->le_mctbl = sc->lemac_mctbl;
713 sc->le_mcmask = (1 << LEMAC_MCTBL_BITS) - 1;
714 sc->lemac_txmax = lemac_deftxmax;
716 le_intrvec[sc->le_if.if_unit] = lemac_intr;
718 return LEMAC_IOSPACE;
722 * Do a hard reset of the board;
734 sc->le_flags &= IFF_UP;
735 sc->le_if.if_flags &= ~IFF_OACTIVE;
736 LEMAC_INTR_DISABLE(sc);
738 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
739 DELAY(LEMAC_EEP_DELAY);
741 /* Disable Interrupts */
742 /* LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ICR_IRQ_SEL); */
745 * Read EEPROM information. NOTE - the placement of this function
746 * is important because functions hereafter may rely on information
747 * read from the EEPROM.
749 if ((cksum = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
750 printf("%s%d: reset: EEPROM checksum failed (0x%x)\n",
751 sc->le_if.if_name, sc->le_if.if_unit, cksum);
756 * Force to 2K mode if not already configured.
759 portval = LE_INB(sc, LEMAC_REG_MBR);
760 if (!LEMAC_2K_MODE(portval)) {
761 if (LEMAC_64K_MODE(portval)) {
762 portval = (((portval * 2) & 0xF) << 4);
763 sc->lemac_memmode = 64;
764 } else if (LEMAC_32K_MODE(portval)) {
765 portval = ((portval & 0xF) << 4);
766 sc->lemac_memmode = 32;
768 LE_OUTB(sc, LEMAC_REG_MBR, portval);
770 sc->lemac_membase = portval * (2 * 1024) + (512 * 1024);
773 * Initialize Free Memory Queue, Init mcast table with broadcast.
776 lemac_init_adapmem(sc);
777 sc->le_flags |= IFF_UP;
785 le_softc_t *sc = (le_softc_t *)xsc;
788 if ((sc->le_flags & IFF_UP) == 0)
794 * If the interface has the up flag
796 if (sc->le_if.if_flags & IFF_UP) {
797 int saved_cs = LE_INB(sc, LEMAC_REG_CS);
798 LE_OUTB(sc, LEMAC_REG_CS, saved_cs | (LEMAC_CS_TXD | LEMAC_CS_RXD));
799 LE_OUTB(sc, LEMAC_REG_PA0, sc->le_ac.ac_enaddr[0]);
800 LE_OUTB(sc, LEMAC_REG_PA1, sc->le_ac.ac_enaddr[1]);
801 LE_OUTB(sc, LEMAC_REG_PA2, sc->le_ac.ac_enaddr[2]);
802 LE_OUTB(sc, LEMAC_REG_PA3, sc->le_ac.ac_enaddr[3]);
803 LE_OUTB(sc, LEMAC_REG_PA4, sc->le_ac.ac_enaddr[4]);
804 LE_OUTB(sc, LEMAC_REG_PA5, sc->le_ac.ac_enaddr[5]);
806 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_IE);
808 if (sc->le_if.if_flags & IFF_PROMISC) {
809 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE | LEMAC_CS_PME);
811 LEMAC_INTR_DISABLE(sc);
813 LE_OUTB(sc, LEMAC_REG_MPN, 0);
814 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
815 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], lemac_allmulti_mctbl, sizeof(lemac_allmulti_mctbl));
817 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], sc->lemac_mctbl, sizeof(sc->lemac_mctbl));
819 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE);
822 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
824 LEMAC_INTR_ENABLE(sc);
825 sc->le_if.if_flags |= IFF_RUNNING;
827 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_RXD|LEMAC_CS_TXD);
829 LEMAC_INTR_DISABLE(sc);
830 sc->le_if.if_flags &= ~IFF_RUNNING;
836 * What to do upon receipt of an interrupt.
844 LEMAC_INTR_DISABLE(sc); /* Mask interrupts */
847 * Determine cause of interrupt. Receive events take
848 * priority over Transmit.
851 cs_value = LE_INB(sc, LEMAC_REG_CS);
854 * Check for Receive Queue not being empty.
855 * Check for Transmit Done Queue not being empty.
858 if (cs_value & LEMAC_CS_RNE)
860 if (cs_value & LEMAC_CS_TNE)
864 * Check for Transmitter Disabled.
865 * Check for Receiver Disabled.
868 if (cs_value & LEMAC_CS_TXD)
869 lemac_txd_intr(sc, cs_value);
870 if (cs_value & LEMAC_CS_RXD)
871 lemac_rxd_intr(sc, cs_value);
874 * Toggle LED and unmask interrupts.
877 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
878 LEMAC_INTR_ENABLE(sc); /* Unmask interrupts */
885 int rxcount, rxlen, rxpg;
889 rxcount = LE_INB(sc, LEMAC_REG_RQC);
891 rxpg = LE_INB(sc, LEMAC_REG_RQ);
892 LE_OUTB(sc, LEMAC_REG_MPN, rxpg);
894 rxptr = sc->le_membase;
895 sc->le_if.if_ipackets++;
896 if (*rxptr & LEMAC_RX_OK) {
899 * Get receive length - subtract out checksum.
902 rxlen = ((*(u_int *)rxptr >> 8) & 0x7FF) - 4;
903 le_input(sc, rxptr + sizeof(u_int), rxlen, rxlen, NULL);
904 } else { /* end if (*rxptr & LEMAC_RX_OK) */
905 sc->le_if.if_ierrors++;
907 LE_OUTB(sc, LEMAC_REG_FMQ, rxpg); /* Return this page to Free Memory Queue */
908 } /* end while (recv_count--) */
919 * Handle CS_RXD (Receiver disabled) here.
921 * Check Free Memory Queue Count. If not equal to zero
922 * then just turn Receiver back on. If it is equal to
923 * zero then check to see if transmitter is disabled.
924 * Process transmit TXD loop once more. If all else
925 * fails then do software init (0xC0 to EEPROM Init)
926 * and rebuild Free Memory Queue.
932 * Re-enable Receiver.
935 cs_value &= ~LEMAC_CS_RXD;
936 LE_OUTB(sc, LEMAC_REG_CS, cs_value);
938 if (LE_INB(sc, LEMAC_REG_FMC) > 0)
941 if (cs_value & LEMAC_CS_TXD)
942 lemac_txd_intr(sc, cs_value);
944 if ((LE_INB(sc, LEMAC_REG_CS) & LEMAC_CS_RXD) == 0)
947 printf("%s%d: fatal RXD error, attempting recovery\n",
948 sc->le_if.if_name, sc->le_if.if_unit);
951 if (sc->le_flags & IFF_UP) {
957 * Error during initializion. Mark card as disabled.
959 printf("%s%d: recovery failed -- board disabled\n",
960 sc->le_if.if_name, sc->le_if.if_unit);
968 le_softc_t *sc = (le_softc_t *) ifp;
969 struct ifqueue *ifq = &ifp->if_snd;
971 if ((ifp->if_flags & IFF_RUNNING) == 0)
974 LEMAC_INTR_DISABLE(sc);
976 while (ifq->ifq_head != NULL) {
981 if (LE_INB(sc, LEMAC_REG_TQC) >= sc->lemac_txmax) {
982 ifp->if_flags |= IFF_OACTIVE;
986 tx_pg = LE_INB(sc, LEMAC_REG_FMQ); /* get free memory page */
988 * Check for good transmit page.
990 if (tx_pg == 0 || tx_pg > sc->lemac_lastpage) {
992 ifp->if_flags |= IFF_OACTIVE;
997 LE_OUTB(sc, LEMAC_REG_MPN, tx_pg); /* Shift 2K window. */
1000 * The first four bytes of each transmit buffer are for
1001 * control information. The first byte is the control
1002 * byte, then the length (why not word aligned?), then
1003 * the off to the buffer.
1006 txoff = (mtod(m, u_int) & (sizeof(u_long) - 1)) + LEMAC_TX_HDRSZ;
1007 txhdr = sc->lemac_txctl | (m->m_pkthdr.len << 8) | (txoff << 24);
1008 *(u_int *) sc->le_membase = txhdr;
1011 * Copy the packet to the board
1014 m_copydata(m, 0, m->m_pkthdr.len, sc->le_membase + txoff);
1016 LE_OUTB(sc, LEMAC_REG_TQ, tx_pg); /* tell chip to transmit this packet */
1018 if (sc->le_if.if_bpf)
1019 bpf_mtap(&sc->le_if, m);
1021 m_freem(m); /* free the mbuf */
1023 LEMAC_INTR_ENABLE(sc);
1030 int txsts, txcount = LE_INB(sc, LEMAC_REG_TDC);
1034 txsts = LE_INB(sc, LEMAC_REG_TDQ);
1035 sc->le_if.if_opackets++; /* another one done */
1036 if ((txsts & LEMAC_TDQ_COL) != LEMAC_TDQ_NOCOL)
1037 sc->le_if.if_collisions++;
1039 sc->le_if.if_flags &= ~IFF_OACTIVE;
1040 lemac_start(&sc->le_if);
1049 * Read transmit status, remove transmit buffer from
1050 * transmit queue and place on free memory queue,
1051 * then reset transmitter.
1052 * Increment appropriate counters.
1056 sc->le_if.if_oerrors++;
1057 if (LE_INB(sc, LEMAC_REG_TS) & LEMAC_TS_ECL)
1058 sc->le_if.if_collisions++;
1059 sc->le_if.if_flags &= ~IFF_OACTIVE;
1061 LE_OUTB(sc, LEMAC_REG_FMQ, LE_INB(sc, LEMAC_REG_TQ));
1062 /* Get Page number and write it back out */
1064 LE_OUTB(sc, LEMAC_REG_CS, cs_value & ~LEMAC_CS_TXD);
1065 /* Turn back on transmitter */
1073 int word_off, cksum;
1078 ep = sc->lemac_eeprom;
1079 for (word_off = 0; word_off < LEMAC_EEP_SIZE / 2; word_off++) {
1080 LE_OUTB(sc, LEMAC_REG_PI1, word_off);
1081 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEREAD);
1083 DELAY(LEMAC_EEP_DELAY);
1085 *ep = LE_INB(sc, LEMAC_REG_EE1); cksum += *ep++;
1086 *ep = LE_INB(sc, LEMAC_REG_EE2); cksum += *ep++;
1090 * Set up Transmit Control Byte for use later during transmit.
1093 sc->lemac_txctl |= LEMAC_TX_FLAGS;
1095 if ((sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_SQE) == 0)
1096 sc->lemac_txctl &= ~LEMAC_TX_SQE;
1098 if (sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_LAB)
1099 sc->lemac_txctl |= LEMAC_TX_LAB;
1101 MEMCPY(sc->lemac_prodname, &sc->lemac_eeprom[LEMAC_EEP_PRDNM], LEMAC_EEP_PRDNMSZ);
1102 sc->lemac_prodname[LEMAC_EEP_PRDNMSZ] = '\0';
1113 conf = LE_INB(sc, LEMAC_REG_CNF);
1115 if ((sc->lemac_eeprom[LEMAC_EEP_SETUP] & LEMAC_EEP_ST_DRAM) == 0) {
1116 sc->lemac_lastpage = 63;
1117 conf &= ~LEMAC_CNF_DRAM;
1119 sc->lemac_lastpage = 127;
1120 conf |= LEMAC_CNF_DRAM;
1123 LE_OUTB(sc, LEMAC_REG_CNF, conf);
1125 for (pg = 1; pg <= sc->lemac_lastpage; pg++)
1126 LE_OUTB(sc, LEMAC_REG_FMQ, pg);
1130 #endif /* !defined(LE_NOLEMAC) */
1132 #if !defined(LE_NOLANCE)
1134 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1136 * Start of DEPCA (DE200/DE201/DE202/DE422 etal) support.
1139 static void depca_intr(le_softc_t *sc);
1140 static int lance_init_adapmem(le_softc_t *sc);
1141 static int lance_init_ring(le_softc_t *sc, ln_ring_t *rp, lance_ring_t *ri,
1142 unsigned ndescs, unsigned bufoffset,
1143 unsigned descoffset);
1144 static void lance_init(void *xsc);
1145 static void lance_reset(le_softc_t *sc);
1146 static void lance_intr(le_softc_t *sc);
1147 static int lance_rx_intr(le_softc_t *sc);
1148 static void lance_start(struct ifnet *ifp);
1149 static int lance_tx_intr(le_softc_t *sc);
1151 #define LN_BUFSIZE /* 380 */ 304 /* 1520 / 4 */
1152 #define LN_TXDESC_RATIO 2048
1153 #define LN_DESC_MAX 128
1157 unsigned lance_rx_misses;
1158 unsigned lance_rx_badcrc;
1159 unsigned lance_rx_badalign;
1160 unsigned lance_rx_badframe;
1161 unsigned lance_rx_buferror;
1162 unsigned lance_tx_deferred;
1163 unsigned lance_tx_single_collisions;
1164 unsigned lance_tx_multiple_collisions;
1165 unsigned lance_tx_excessive_collisions;
1166 unsigned lance_tx_late_collisions;
1168 unsigned lance_memory_errors;
1169 unsigned lance_inits;
1170 unsigned lance_tx_intrs;
1171 unsigned lance_tx_nospc[2];
1172 unsigned lance_tx_drains[2];
1173 unsigned lance_tx_orphaned;
1174 unsigned lance_tx_adoptions;
1175 unsigned lance_tx_emptied;
1176 unsigned lance_tx_deftxint;
1177 unsigned lance_tx_buferror;
1178 unsigned lance_high_txoutptr;
1179 unsigned lance_low_txheapsize;
1180 unsigned lance_low_txfree;
1181 unsigned lance_tx_intr_hidescs;
1182 /* unsigned lance_tx_intr_descs[LN_DESC_MAX]; */
1184 unsigned lance_rx_intrs;
1185 unsigned lance_rx_badsop;
1186 unsigned lance_rx_contig;
1187 unsigned lance_rx_noncontig;
1188 unsigned lance_rx_intr_hidescs;
1189 unsigned lance_rx_ndescs[4096 / LN_BUFSIZE];
1190 /* unsigned lance_rx_intr_descs[LN_DESC_MAX]; */
1193 #define LN_STAT(stat) (lance_stats.lance_ ## stat)
1194 #define LN_MINSTAT(stat, val) (LN_STAT(stat > (val)) ? LN_STAT(stat = (val)) : 0)
1195 #define LN_MAXSTAT(stat, val) (LN_STAT(stat < (val)) ? LN_STAT(stat = (val)) : 0)
1198 #define LN_STAT(stat) 0
1199 #define LN_MINSTAT(stat, val) 0
1200 #define LN_MAXSTAT(stat, val) 0
1203 #define LN_SELCSR(sc, csrno) (LE_OUTW(sc, sc->lance_rap, csrno))
1204 #define LN_INQCSR(sc) (LE_INW(sc, sc->lance_rap))
1206 #define LN_WRCSR(sc, val) (LE_OUTW(sc, sc->lance_rdp, val))
1207 #define LN_RDCSR(sc) (LE_INW(sc, sc->lance_rdp))
1210 #define LN_ZERO(sc, vaddr, len) bzero(vaddr, len)
1211 #define LN_COPYTO(sc, from, to, len) bcopy(from, to, len)
1213 #define LN_SETFLAG(sc, vaddr, val) \
1214 (((volatile u_char *) vaddr)[3] = (val))
1216 #define LN_PUTDESC(sc, desc, vaddr) \
1217 (((volatile u_short *) vaddr)[0] = ((u_short *) desc)[0], \
1218 ((volatile u_short *) vaddr)[2] = ((u_short *) desc)[2], \
1219 ((volatile u_short *) vaddr)[1] = ((u_short *) desc)[1])
1222 * Only get the descriptor flags and length/status. All else
1225 #define LN_GETDESC(sc, desc, vaddr) \
1226 (((u_short *) desc)[1] = ((volatile u_short *) vaddr)[1], \
1227 ((u_short *) desc)[3] = ((volatile u_short *) vaddr)[3])
1231 * These definitions are specific to the DEC "DEPCA-style" NICs.
1232 * (DEPCA, DE10x, DE20[012], DE422)
1235 #define DEPCA_REG_NICSR 0 /* (RW;16) NI Control / Status */
1236 #define DEPCA_REG_RDP 4 /* (RW:16) LANCE RDP (data) register */
1237 #define DEPCA_REG_RAP 6 /* (RW:16) LANCE RAP (address) register */
1238 #define DEPCA_REG_ADDRROM 12 /* (R : 8) DEPCA Ethernet Address ROM */
1239 #define DEPCA_IOSPACE 16 /* DEPCAs use 16 bytes of IO space */
1241 #define DEPCA_NICSR_LED 0x0001 /* Light the LED on the back of the DEPCA */
1242 #define DEPCA_NICSR_ENABINTR 0x0002 /* Enable Interrupts */
1243 #define DEPCA_NICSR_MASKINTR 0x0004 /* Mask Interrupts */
1244 #define DEPCA_NICSR_AAC 0x0008 /* Address Counter Clear */
1245 #define DEPCA_NICSR_REMOTEBOOT 0x0010 /* Remote Boot Enabled (ignored) */
1246 #define DEPCA_NICSR_32KRAM 0x0020 /* DEPCA LANCE RAM size 64K (C) / 32K (S) */
1247 #define DEPCA_NICSR_LOW32K 0x0040 /* Bank Select (A15 = !This Bit) */
1248 #define DEPCA_NICSR_SHE 0x0080 /* Shared RAM Enabled (ie hide ROM) */
1249 #define DEPCA_NICSR_BOOTTMO 0x0100 /* Remote Boot Timeout (ignored) */
1251 #define DEPCA_RDNICSR(sc) (LE_INW(sc, DEPCA_REG_NICSR))
1252 #define DEPCA_WRNICSR(sc, val) (LE_OUTW(sc, DEPCA_REG_NICSR, val))
1254 #define DEPCA_IDSTR_OFFSET 0xC006 /* ID String Offset */
1256 #define DEPCA_REG_EISAID 0x80
1257 #define DEPCA_EISAID_MASK 0xf0ffffff
1258 #define DEPCA_EISAID_DE422 0x2042A310
1262 DEPCA_DE100, DEPCA_DE101,
1264 DEPCA_DE200, DEPCA_DE201, DEPCA_DE202,
1269 static const char *depca_signatures[] = {
1273 "DE200", "DE201", "DE202",
1281 const le_board_t *bd,
1284 unsigned nicsr, idx, idstr_offset = DEPCA_IDSTR_OFFSET;
1287 * Find out how memory we are dealing with. Adjust
1288 * the ID string offset approriately if we are at
1289 * 32K. Make sure the ROM is enabled.
1291 nicsr = DEPCA_RDNICSR(sc);
1292 nicsr &= ~(DEPCA_NICSR_SHE|DEPCA_NICSR_LED|DEPCA_NICSR_ENABINTR);
1294 if (nicsr & DEPCA_NICSR_32KRAM) {
1296 * Make we are going to read the upper
1297 * 32K so we do read the ROM.
1299 sc->lance_ramsize = 32 * 1024;
1300 nicsr &= ~DEPCA_NICSR_LOW32K;
1301 sc->lance_ramoffset = 32 * 1024;
1302 idstr_offset -= sc->lance_ramsize;
1304 sc->lance_ramsize = 64 * 1024;
1305 sc->lance_ramoffset = 0;
1307 DEPCA_WRNICSR(sc, nicsr);
1309 sc->le_prodname = NULL;
1310 for (idx = 0; depca_signatures[idx] != NULL; idx++) {
1311 if (bcmp(depca_signatures[idx], sc->le_membase + idstr_offset, 5) == 0) {
1312 sc->le_prodname = depca_signatures[idx];
1317 if (sc->le_prodname == NULL) {
1319 * Try to get the EISA device if it's a DE422.
1321 if (sc->le_iobase > 0x1000 && (sc->le_iobase & 0x0F00) == 0x0C00
1322 && (LE_INL(sc, DEPCA_REG_EISAID) & DEPCA_EISAID_MASK)
1323 == DEPCA_EISAID_DE422) {
1324 sc->le_prodname = "DE422";
1329 if (idx == DEPCA_CLASSIC)
1330 sc->lance_ramsize -= 16384; /* Can't use the ROM area on a DEPCA */
1333 * Try to read the address ROM.
1334 * Stop the LANCE, reset the Address ROM Counter (AAC),
1335 * read the NICSR to "clock" in the reset, and then
1336 * re-enable the Address ROM Counter. Now read the
1339 sc->lance_rdp = DEPCA_REG_RDP;
1340 sc->lance_rap = DEPCA_REG_RAP;
1341 sc->lance_csr3 = LN_CSR3_ALE;
1342 sc->le_mctbl = sc->lance_initb.ln_multi_mask;
1343 sc->le_mcmask = LN_MC_MASK;
1344 LN_SELCSR(sc, LN_CSR0);
1345 LN_WRCSR(sc, LN_CSR0_STOP);
1347 if (idx < DEPCA_DE200) {
1348 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) & ~DEPCA_NICSR_AAC);
1349 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_AAC);
1352 if (le_read_macaddr(sc, DEPCA_REG_ADDRROM, idx == DEPCA_CLASSIC) < 0)
1355 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
1357 * Renable shared RAM.
1359 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_SHE);
1361 le_intrvec[sc->le_if.if_unit] = depca_intr;
1362 if (!lance_init_adapmem(sc))
1365 sc->if_reset = lance_reset;
1366 sc->if_init = lance_init;
1367 sc->le_if.if_start = lance_start;
1368 DEPCA_WRNICSR(sc, DEPCA_NICSR_SHE | DEPCA_NICSR_ENABINTR);
1371 LN_STAT(low_txfree = sc->lance_txinfo.ri_max);
1372 LN_STAT(low_txheapsize = 0xFFFFFFFF);
1373 *msize = sc->lance_ramsize;
1374 return DEPCA_IOSPACE;
1381 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) ^ DEPCA_NICSR_LED);
1386 * Here's as good a place to describe our paritioning of the
1387 * LANCE shared RAM space. (NOTE: this driver does not yet support
1388 * the concept of a LANCE being able to DMA).
1390 * First is the 24 (00:23) bytes for LANCE Initialization Block
1391 * Next are the recieve descriptors. The number is calculated from
1392 * how many LN_BUFSIZE buffers we can allocate (this number must
1393 * be a power of 2). Next are the transmit descriptors. The amount
1394 * of transmit descriptors is derived from the size of the RAM
1395 * divided by 1K. Now come the receive buffers (one for each receive
1396 * descriptor). Finally is the transmit heap. (no fixed buffers are
1397 * allocated so as to make the most use of the limited space).
1403 lance_addr_t rxbufoffset;
1404 lance_addr_t rxdescoffset, txdescoffset;
1405 unsigned rxdescs, txdescs;
1408 * First calculate how many descriptors we heap.
1409 * Note this assumes the ramsize is a power of two.
1411 sc->lance_rxbufsize = LN_BUFSIZE;
1413 while (rxdescs * sc->lance_rxbufsize < sc->lance_ramsize)
1416 if (rxdescs > LN_DESC_MAX) {
1417 sc->lance_rxbufsize *= rxdescs / LN_DESC_MAX;
1418 rxdescs = LN_DESC_MAX;
1420 txdescs = sc->lance_ramsize / LN_TXDESC_RATIO;
1421 if (txdescs > LN_DESC_MAX)
1422 txdescs = LN_DESC_MAX;
1425 * Now calculate where everything goes in memory
1427 rxdescoffset = sizeof(ln_initb_t);
1428 txdescoffset = rxdescoffset + sizeof(ln_desc_t) * rxdescs;
1429 rxbufoffset = txdescoffset + sizeof(ln_desc_t) * txdescs;
1431 sc->le_mctbl = (le_mcbits_t *) sc->lance_initb.ln_multi_mask;
1433 * Remember these for debugging.
1435 sc->lance_raminitb = (ln_initb_t *) sc->le_membase;
1436 sc->lance_ramdesc = (ln_desc_t *) (sc->le_membase + rxdescoffset);
1439 * Initialize the rings.
1441 if (!lance_init_ring(sc, &sc->lance_initb.ln_rxring, &sc->lance_rxinfo,
1442 rxdescs, rxbufoffset, rxdescoffset))
1444 sc->lance_rxinfo.ri_heap = rxbufoffset;
1445 sc->lance_rxinfo.ri_heapend = rxbufoffset + sc->lance_rxbufsize * rxdescs;
1447 if (!lance_init_ring(sc, &sc->lance_initb.ln_txring, &sc->lance_txinfo,
1448 txdescs, 0, txdescoffset))
1450 sc->lance_txinfo.ri_heap = sc->lance_rxinfo.ri_heapend;
1451 sc->lance_txinfo.ri_heapend = sc->lance_ramsize;
1454 * Set CSR1 and CSR2 to the address of the init block (which
1455 * for us is always 0.
1457 sc->lance_csr1 = LN_ADDR_LO(0 + sc->lance_ramoffset);
1458 sc->lance_csr2 = LN_ADDR_HI(0 + sc->lance_ramoffset);
1468 lance_addr_t bufoffset,
1469 lance_addr_t descoffset)
1471 lance_descinfo_t *di;
1474 * Initialize the ring pointer in the LANCE InitBlock
1476 rp->r_addr_lo = LN_ADDR_LO(descoffset + sc->lance_ramoffset);
1477 rp->r_addr_hi = LN_ADDR_HI(descoffset + sc->lance_ramoffset);
1478 rp->r_log2_size = ffs(ndescs) - 1;
1481 * Allocate the ring entry descriptors and initialize
1482 * our ring information data structure. All these are
1483 * our copies and do not live in the LANCE RAM.
1485 ri->ri_first = (lance_descinfo_t *) malloc(ndescs * sizeof(*di), M_DEVBUF, M_NOWAIT);
1486 if (ri->ri_first == NULL) {
1487 printf("lance_init_ring: malloc(%d) failed\n", ndescs * sizeof(*di));
1490 ri->ri_free = ri->ri_max = ndescs;
1491 ri->ri_last = ri->ri_first + ri->ri_max;
1492 for (di = ri->ri_first; di < ri->ri_last; di++) {
1493 di->di_addr = sc->le_membase + descoffset;
1496 di->di_bufaddr = bufoffset;
1497 di->di_buflen = sc->lance_rxbufsize;
1498 bufoffset += sc->lance_rxbufsize;
1500 descoffset += sizeof(ln_desc_t);
1510 printf("%s%d: %s: nicsr=%04x",
1511 sc->le_if.if_name, sc->le_if.if_unit,
1512 id, DEPCA_RDNICSR(sc));
1513 LN_SELCSR(sc, LN_CSR0); printf(" csr0=%04x", LN_RDCSR(sc));
1514 LN_SELCSR(sc, LN_CSR1); printf(" csr1=%04x", LN_RDCSR(sc));
1515 LN_SELCSR(sc, LN_CSR2); printf(" csr2=%04x", LN_RDCSR(sc));
1516 LN_SELCSR(sc, LN_CSR3); printf(" csr3=%04x\n", LN_RDCSR(sc));
1517 LN_SELCSR(sc, LN_CSR0);
1526 /* lance_dumpcsrs(sc, "lance_reset: start"); */
1528 LN_WRCSR(sc, LN_RDCSR(sc) & ~LN_CSR0_ENABINTR);
1529 LN_WRCSR(sc, LN_CSR0_STOP);
1532 sc->le_flags &= ~IFF_UP;
1533 sc->le_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
1535 le_multi_filter(sc); /* initialize the multicast table */
1536 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
1537 sc->lance_initb.ln_multi_mask[0] = 0xFFFFU;
1538 sc->lance_initb.ln_multi_mask[1] = 0xFFFFU;
1539 sc->lance_initb.ln_multi_mask[2] = 0xFFFFU;
1540 sc->lance_initb.ln_multi_mask[3] = 0xFFFFU;
1542 sc->lance_initb.ln_physaddr[0] = ((u_short *) sc->le_ac.ac_enaddr)[0];
1543 sc->lance_initb.ln_physaddr[1] = ((u_short *) sc->le_ac.ac_enaddr)[1];
1544 sc->lance_initb.ln_physaddr[2] = ((u_short *) sc->le_ac.ac_enaddr)[2];
1545 if (sc->le_if.if_flags & IFF_PROMISC) {
1546 sc->lance_initb.ln_mode |= LN_MODE_PROMISC;
1548 sc->lance_initb.ln_mode &= ~LN_MODE_PROMISC;
1551 * We force the init block to be at the start
1552 * of the LANCE's RAM buffer.
1554 LN_COPYTO(sc, &sc->lance_initb, sc->le_membase, sizeof(sc->lance_initb));
1555 LN_SELCSR(sc, LN_CSR1); LN_WRCSR(sc, sc->lance_csr1);
1556 LN_SELCSR(sc, LN_CSR2); LN_WRCSR(sc, sc->lance_csr2);
1557 LN_SELCSR(sc, LN_CSR3); LN_WRCSR(sc, sc->lance_csr3);
1559 /* lance_dumpcsrs(sc, "lance_reset: preinit"); */
1562 * clear INITDONE and INIT the chip
1564 LN_SELCSR(sc, LN_CSR0);
1565 LN_WRCSR(sc, LN_CSR0_INIT|LN_CSR0_INITDONE);
1570 if (((csr = LN_RDCSR(sc)) & LN_CSR0_INITDONE) != 0)
1575 if ((csr & LN_CSR0_INITDONE) == 0) { /* make sure we got out okay */
1576 lance_dumpcsrs(sc, "lance_reset: reset failure");
1578 /* lance_dumpcsrs(sc, "lance_reset: end"); */
1579 sc->le_if.if_flags |= IFF_UP;
1580 sc->le_flags |= IFF_UP;
1588 le_softc_t *sc = (le_softc_t *)xsc;
1590 lance_descinfo_t *di;
1594 if (sc->le_if.if_flags & IFF_RUNNING) {
1598 * If we were running, requeue any pending transmits.
1600 ri = &sc->lance_txinfo;
1601 di = ri->ri_nextout;
1602 while (ri->ri_free < ri->ri_max) {
1603 if (--di == ri->ri_first)
1604 di = ri->ri_nextout - 1;
1605 if (di->di_mbuf == NULL)
1607 IF_PREPEND(&sc->le_if.if_snd, di->di_mbuf);
1616 * Reset the transmit ring. Make sure we own all the buffers.
1617 * Also reset the transmit heap.
1619 sc->le_if.if_flags &= ~IFF_OACTIVE;
1620 ri = &sc->lance_txinfo;
1621 for (di = ri->ri_first; di < ri->ri_last; di++) {
1622 if (di->di_mbuf != NULL) {
1623 m_freem(di->di_mbuf);
1627 desc.d_addr_lo = LN_ADDR_LO(ri->ri_heap + sc->lance_ramoffset);
1628 desc.d_addr_hi = LN_ADDR_HI(ri->ri_heap + sc->lance_ramoffset);
1630 LN_PUTDESC(sc, &desc, di->di_addr);
1632 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1633 ri->ri_free = ri->ri_max;
1634 ri->ri_outptr = ri->ri_heap;
1635 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1637 ri = &sc->lance_rxinfo;
1638 desc.d_flag = LN_DFLAG_OWNER;
1639 desc.d_buflen = 0 - sc->lance_rxbufsize;
1640 for (di = ri->ri_first; di < ri->ri_last; di++) {
1641 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1642 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1643 LN_PUTDESC(sc, &desc, di->di_addr);
1645 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1646 ri->ri_outptr = ri->ri_heap;
1647 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1650 if (sc->le_if.if_flags & IFF_UP) {
1651 sc->le_if.if_flags |= IFF_RUNNING;
1652 LN_WRCSR(sc, LN_CSR0_START|LN_CSR0_INITDONE|LN_CSR0_ENABINTR);
1653 /* lance_dumpcsrs(sc, "lance_init: up"); */
1654 lance_start(&sc->le_if);
1656 /* lance_dumpcsrs(sc, "lance_init: down"); */
1657 sc->le_if.if_flags &= ~IFF_RUNNING;
1667 oldcsr = LN_RDCSR(sc);
1668 oldcsr &= ~LN_CSR0_ENABINTR;
1669 LN_WRCSR(sc, oldcsr);
1670 LN_WRCSR(sc, LN_CSR0_ENABINTR);
1672 if (oldcsr & LN_CSR0_ERRSUM) {
1673 if (oldcsr & LN_CSR0_MISS) {
1675 * LN_CSR0_MISS is signaled when the LANCE receiver
1676 * loses a packet because it doesn't own a receive
1677 * descriptor. Rev. D LANCE chips, which are no
1678 * longer used, require a chip reset as described
1681 LN_STAT(rx_misses++);
1683 if (oldcsr & LN_CSR0_MEMERROR) {
1684 LN_STAT(memory_errors++);
1685 if (oldcsr & (LN_CSR0_RXON|LN_CSR0_TXON)) {
1692 if ((oldcsr & LN_CSR0_RXINT) && lance_rx_intr(sc)) {
1697 if (oldcsr & LN_CSR0_TXINT) {
1698 if (lance_tx_intr(sc))
1699 lance_start(&sc->le_if);
1702 if (oldcsr == (LN_CSR0_PENDINTR|LN_CSR0_RXON|LN_CSR0_TXON))
1703 printf("%s%d: lance_intr: stray interrupt\n",
1704 sc->le_if.if_name, sc->le_if.if_unit);
1711 lance_ring_t *ri = &sc->lance_rxinfo;
1712 lance_descinfo_t *eop;
1714 int ndescs, total_len, rxdescs;
1716 LN_STAT(rx_intrs++);
1718 for (rxdescs = 0;;) {
1720 * Now to try to find the end of this packet chain.
1722 for (ndescs = 1, eop = ri->ri_nextin;; ndescs++) {
1724 * If we don't own this descriptor, the packet ain't
1725 * all here so return because we are done.
1727 LN_GETDESC(sc, &desc, eop->di_addr);
1728 if (desc.d_flag & LN_DFLAG_OWNER)
1731 * In case we have missed a packet and gotten the
1732 * LANCE confused, make sure we are pointing at the
1733 * start of a packet. If we aren't, something is really
1734 * strange so reinit the LANCE.
1736 if (desc.d_flag & LN_DFLAG_RxBUFERROR) {
1737 LN_STAT(rx_buferror++);
1740 if ((desc.d_flag & LN_DFLAG_SOP) && eop != ri->ri_nextin) {
1741 LN_STAT(rx_badsop++);
1744 if (desc.d_flag & LN_DFLAG_EOP)
1746 if (++eop == ri->ri_last)
1750 total_len = (desc.d_status & LN_DSTS_RxLENMASK) - 4;
1751 if ((desc.d_flag & LN_DFLAG_RxERRSUM) == 0) {
1753 * Valid Packet -- If the SOP is less than or equal to the EOP
1754 * or the length is less than the receive buffer size, then the
1755 * packet is contiguous in memory and can be copied in one shot.
1756 * Otherwise we need to copy two segments to get the entire
1759 if (ri->ri_nextin <= eop || total_len <= ri->ri_heapend - ri->ri_nextin->di_bufaddr) {
1760 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1761 total_len, total_len, NULL);
1762 LN_STAT(rx_contig++);
1764 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1766 ri->ri_heapend - ri->ri_nextin->di_bufaddr,
1767 sc->le_membase + ri->ri_first->di_bufaddr);
1768 LN_STAT(rx_noncontig++);
1772 * If the packet is bad, increment the
1775 sc->le_if.if_ierrors++;
1776 if (desc.d_flag & LN_DFLAG_RxBADCRC)
1777 LN_STAT(rx_badcrc++);
1778 if (desc.d_flag & LN_DFLAG_RxOVERFLOW)
1779 LN_STAT(rx_badalign++);
1780 if (desc.d_flag & LN_DFLAG_RxFRAMING)
1781 LN_STAT(rx_badframe++);
1783 sc->le_if.if_ipackets++;
1784 LN_STAT(rx_ndescs[ndescs-1]++);
1786 while (ndescs-- > 0) {
1787 LN_SETFLAG(sc, ri->ri_nextin->di_addr, LN_DFLAG_OWNER);
1788 if (++ri->ri_nextin == ri->ri_last)
1789 ri->ri_nextin = ri->ri_first;
1792 /* LN_STAT(rx_intr_descs[rxdescs]++); */
1793 LN_MAXSTAT(rx_intr_hidescs, rxdescs);
1802 le_softc_t *sc = (le_softc_t *) ifp;
1803 struct ifqueue *ifq = &ifp->if_snd;
1804 lance_ring_t *ri = &sc->lance_txinfo;
1805 lance_descinfo_t *di;
1808 struct mbuf *m, *m0;
1811 if ((ifp->if_flags & IFF_RUNNING) == 0)
1820 * Make the packet meets the minimum size for Ethernet.
1821 * The slop is so that we also use an even number of longwards.
1823 len = ETHERMIN + sizeof(struct ether_header);
1824 if (m->m_pkthdr.len > len)
1825 len = m->m_pkthdr.len;
1827 slop = (8 - len) & 3;
1829 * If there are no free ring entries (there must be always
1830 * one owned by the host), or there's not enough space for
1831 * this packet, or this packet would wrap around the end
1832 * of LANCE RAM then wait for the transmits to empty for
1833 * space and ring entries to become available.
1835 if (ri->ri_free == 1 || len + slop > ri->ri_outsize) {
1837 * Try to see if we can free up anything off the transit ring.
1839 if (lance_tx_intr(sc) > 0) {
1840 LN_STAT(tx_drains[0]++);
1844 LN_STAT(tx_nospc[0]++);
1848 if (len + slop > ri->ri_heapend - ri->ri_outptr) {
1850 * Since the packet won't fit in the end of the transmit
1851 * heap, see if there is space at the beginning of the transmit
1852 * heap. If not, try again when there is space.
1854 LN_STAT(tx_orphaned++);
1855 slop += ri->ri_heapend - ri->ri_outptr;
1856 if (len + slop > ri->ri_outsize) {
1857 LN_STAT(tx_nospc[1]++);
1861 * Point to the beginning of the heap
1863 ri->ri_outptr = ri->ri_heap;
1864 LN_STAT(tx_adoptions++);
1868 * Initialize the descriptor (saving the buffer address,
1869 * buffer length, and mbuf) and write the packet out
1872 di = ri->ri_nextout;
1873 di->di_bufaddr = ri->ri_outptr;
1874 di->di_buflen = len + slop;
1876 bp = sc->le_membase + di->di_bufaddr;
1877 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1878 LN_COPYTO(sc, mtod(m0, caddr_t), bp, m0->m_len);
1882 * Zero out the remainder if needed (< ETHERMIN).
1884 if (m->m_pkthdr.len < len)
1885 LN_ZERO(sc, bp, len - m->m_pkthdr.len);
1888 * Finally, copy out the descriptor and tell the
1889 * LANCE to transmit!.
1891 desc.d_buflen = 0 - len;
1892 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1893 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1894 desc.d_flag = LN_DFLAG_SOP|LN_DFLAG_EOP|LN_DFLAG_OWNER;
1895 LN_PUTDESC(sc, &desc, di->di_addr);
1896 LN_WRCSR(sc, LN_CSR0_TXDEMAND|LN_CSR0_ENABINTR);
1899 * Do our bookkeeping with our transmit heap.
1900 * (if we wrap, point back to the beginning).
1902 ri->ri_outptr += di->di_buflen;
1903 ri->ri_outsize -= di->di_buflen;
1904 LN_MAXSTAT(high_txoutptr, ri->ri_outptr);
1905 LN_MINSTAT(low_txheapsize, ri->ri_outsize);
1907 if (ri->ri_outptr == ri->ri_heapend)
1908 ri->ri_outptr = ri->ri_heap;
1911 if (++ri->ri_nextout == ri->ri_last)
1912 ri->ri_nextout = ri->ri_first;
1913 LN_MINSTAT(low_txfree, ri->ri_free);
1916 ifp->if_flags |= IFF_OACTIVE;
1925 lance_ring_t *ri = &sc->lance_txinfo;
1928 LN_STAT(tx_intrs++);
1929 for (xmits = 0; ri->ri_free < ri->ri_max; ) {
1932 LN_GETDESC(sc, &desc, ri->ri_nextin->di_addr);
1933 if (desc.d_flag & LN_DFLAG_OWNER)
1936 if (desc.d_flag & (LN_DFLAG_TxONECOLL|LN_DFLAG_TxMULTCOLL))
1937 sc->le_if.if_collisions++;
1938 if (desc.d_flag & LN_DFLAG_TxDEFERRED)
1939 LN_STAT(tx_deferred++);
1940 if (desc.d_flag & LN_DFLAG_TxONECOLL)
1941 LN_STAT(tx_single_collisions++);
1942 if (desc.d_flag & LN_DFLAG_TxMULTCOLL)
1943 LN_STAT(tx_multiple_collisions++);
1945 if (desc.d_flag & LN_DFLAG_TxERRSUM) {
1946 if (desc.d_status & (LN_DSTS_TxUNDERFLOW|LN_DSTS_TxBUFERROR|
1947 LN_DSTS_TxEXCCOLL|LN_DSTS_TxLATECOLL)) {
1948 if (desc.d_status & LN_DSTS_TxEXCCOLL) {
1950 LN_STAT(tx_excessive_collisions++);
1951 if ((tdr = (desc.d_status & LN_DSTS_TxTDRMASK)) > 0) {
1953 printf("%s%d: lance: warning: excessive collisions: TDR %dns (%d-%dm)\n",
1954 sc->le_if.if_name, sc->le_if.if_unit,
1955 tdr, (tdr*99)/1000, (tdr*117)/1000);
1958 if (desc.d_status & LN_DSTS_TxBUFERROR)
1959 LN_STAT(tx_buferror++);
1960 sc->le_if.if_oerrors++;
1961 if ((desc.d_status & LN_DSTS_TxLATECOLL) == 0) {
1965 LN_STAT(tx_late_collisions++);
1969 m_freem(ri->ri_nextin->di_mbuf);
1970 ri->ri_nextin->di_mbuf = NULL;
1971 sc->le_if.if_opackets++;
1973 ri->ri_outsize += ri->ri_nextin->di_buflen;
1974 if (++ri->ri_nextin == ri->ri_last)
1975 ri->ri_nextin = ri->ri_first;
1976 sc->le_if.if_flags &= ~IFF_OACTIVE;
1979 if (ri->ri_free == ri->ri_max)
1980 LN_STAT(tx_emptied++);
1981 /* LN_STAT(tx_intr_descs[xmits]++); */
1982 LN_MAXSTAT(tx_intr_hidescs, xmits);
1985 #endif /* !defined(LE_NOLANCE) */