2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
41 * Routines to handle clock hardware.
45 * inittodr, settodr and support routines written
46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
52 #include "opt_clock.h"
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/eventhandler.h>
58 #include <sys/kernel.h>
63 #include <sys/sysctl.h>
65 #include <sys/systimer.h>
66 #include <sys/globaldata.h>
67 #include <sys/thread2.h>
68 #include <sys/systimer.h>
69 #include <sys/machintr.h>
70 #include <sys/interrupt.h>
72 #include <machine/clock.h>
73 #ifdef CLK_CALIBRATION_LOOP
75 #include <machine/cputypes.h>
76 #include <machine/frame.h>
77 #include <machine/ipl.h>
78 #include <machine/limits.h>
79 #include <machine/md_var.h>
80 #include <machine/psl.h>
81 #include <machine/segments.h>
82 #include <machine/smp.h>
83 #include <machine/specialreg.h>
85 #include <machine_base/apic/ioapic.h>
86 #include <machine_base/apic/ioapic_abi.h>
87 #include <machine_base/icu/icu.h>
88 #include <bus/isa/isa.h>
89 #include <bus/isa/rtc.h>
90 #include <machine_base/isa/timerreg.h>
92 #include <machine/intr_machdep.h>
94 static void i8254_restore(void);
95 static void resettodr_on_shutdown(void *arg __unused);
98 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
99 * can use a simple formula for leap years.
101 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
102 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
105 #define TIMER_FREQ 1193182
108 static uint8_t i8254_walltimer_sel;
109 static uint16_t i8254_walltimer_cntr;
111 int adjkerntz; /* local offset from GMT in seconds */
112 int disable_rtc_set; /* disable resettodr() if != 0 */
114 int64_t tsc_frequency;
116 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
118 enum tstate { RELEASED, ACQUIRED };
119 enum tstate timer0_state;
120 enum tstate timer1_state;
121 enum tstate timer2_state;
123 static int beeping = 0;
124 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
125 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
126 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
127 static int rtc_loaded;
129 static int i8254_cputimer_div;
131 static int i8254_nointr;
132 static int i8254_intr_disable = 1;
133 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
135 static struct callout sysbeepstop_ch;
137 static sysclock_t i8254_cputimer_count(void);
138 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
139 static void i8254_cputimer_destruct(struct cputimer *cputimer);
141 static struct cputimer i8254_cputimer = {
142 SLIST_ENTRY_INITIALIZER,
146 i8254_cputimer_count,
147 cputimer_default_fromhz,
148 cputimer_default_fromus,
149 i8254_cputimer_construct,
150 i8254_cputimer_destruct,
155 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
156 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
157 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
159 static struct cputimer_intr i8254_cputimer_intr = {
161 .reload = i8254_intr_reload,
162 .enable = cputimer_intr_default_enable,
163 .config = i8254_intr_config,
164 .restart = cputimer_intr_default_restart,
165 .pmfixup = cputimer_intr_default_pmfixup,
166 .initclock = i8254_intr_initclock,
167 .next = SLIST_ENTRY_INITIALIZER,
169 .type = CPUTIMER_INTR_8254,
170 .prio = CPUTIMER_INTR_PRIO_8254,
171 .caps = CPUTIMER_INTR_CAP_PS
175 * timer0 clock interrupt. Timer0 is in one-shot mode and has stopped
176 * counting as of this interrupt. We use timer1 in free-running mode (not
177 * generating any interrupts) as our main counter. Each cpu has timeouts
180 * This code is INTR_MPSAFE and may be called without the BGL held.
183 clkintr(void *dummy, void *frame_arg)
185 static sysclock_t sysclock_count; /* NOTE! Must be static */
186 struct globaldata *gd = mycpu;
188 struct globaldata *gscan;
193 * SWSTROBE mode is a one-shot, the timer is no longer running
198 * XXX the dispatcher needs work. right now we call systimer_intr()
199 * directly or via IPI for any cpu with systimers queued, which is
200 * usually *ALL* of them. We need to use the LAPIC timer for this.
202 sysclock_count = sys_cputimer->count();
204 for (n = 0; n < ncpus; ++n) {
205 gscan = globaldata_find(n);
206 if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
209 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
212 systimer_intr(&sysclock_count, 0, frame_arg);
216 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
217 systimer_intr(&sysclock_count, 0, frame_arg);
226 acquire_timer2(int mode)
228 if (timer2_state != RELEASED)
230 timer2_state = ACQUIRED;
233 * This access to the timer registers is as atomic as possible
234 * because it is a single instruction. We could do better if we
237 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
244 if (timer2_state != ACQUIRED)
246 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
247 timer2_state = RELEASED;
255 DB_SHOW_COMMAND(rtc, rtc)
257 kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
258 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
259 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
260 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
265 * Return the current cpu timer count as a 32 bit integer.
269 i8254_cputimer_count(void)
271 static __uint16_t cputimer_last;
276 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
277 count = (__uint8_t)inb(i8254_walltimer_cntr); /* get countdown */
278 count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
279 count = -count; /* -> countup */
280 if (count < cputimer_last) /* rollover */
281 i8254_cputimer.base += 0x00010000;
282 ret = i8254_cputimer.base | count;
283 cputimer_last = count;
289 * This function is called whenever the system timebase changes, allowing
290 * us to calculate what is needed to convert a system timebase tick
291 * into an 8254 tick for the interrupt timer. If we can convert to a
292 * simple shift, multiplication, or division, we do so. Otherwise 64
293 * bit arithmatic is required every time the interrupt timer is reloaded.
296 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
302 * Will a simple divide do the trick?
304 div = (timer->freq + (cti->freq / 2)) / cti->freq;
305 freq = cti->freq * div;
307 if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
308 i8254_cputimer_div = div;
310 i8254_cputimer_div = 0;
314 * Reload for the next timeout. It is possible for the reload value
315 * to be 0 or negative, indicating that an immediate timer interrupt
316 * is desired. For now make the minimum 2 ticks.
318 * We may have to convert from the system timebase to the 8254 timebase.
321 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
325 if (i8254_cputimer_div)
326 reload /= i8254_cputimer_div;
328 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
334 if (timer0_running) {
335 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); /* count-down timer */
336 count = (__uint8_t)inb(TIMER_CNTR0); /* lsb */
337 count |= ((__uint8_t)inb(TIMER_CNTR0) << 8); /* msb */
338 if (reload < count) {
339 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
340 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
341 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
346 reload = 0; /* full count */
347 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
348 outb(TIMER_CNTR0, (__uint8_t)reload); /* lsb */
349 outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
355 * DELAY(usec) - Spin for the specified number of microseconds.
356 * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
357 * but do a thread switch in the loop
359 * Relies on timer 1 counting down from (cputimer_freq / hz)
360 * Note: timer had better have been programmed before this is first used!
363 DODELAY(int n, int doswitch)
365 int delta, prev_tick, tick, ticks_left;
370 static int state = 0;
374 for (n1 = 1; n1 <= 10000000; n1 *= 10)
379 kprintf("DELAY(%d)...", n);
382 * Guard against the timer being uninitialized if we are called
383 * early for console i/o.
385 if (timer0_state == RELEASED)
389 * Read the counter first, so that the rest of the setup overhead is
390 * counted. Then calculate the number of hardware timer ticks
391 * required, rounding up to be sure we delay at least the requested
392 * number of microseconds.
394 prev_tick = sys_cputimer->count();
395 ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
401 while (ticks_left > 0) {
402 tick = sys_cputimer->count();
406 delta = tick - prev_tick;
411 if (doswitch && ticks_left > 0)
417 kprintf(" %d calls to getit() at %d usec each\n",
418 getit_calls, (n + 5) / getit_calls);
423 * DELAY() never switches
432 CHECKTIMEOUT(TOTALDELAY *tdd)
437 if (tdd->started == 0) {
438 if (timer0_state == RELEASED)
440 tdd->last_clock = sys_cputimer->count();
444 delta = sys_cputimer->count() - tdd->last_clock;
445 us = (u_int64_t)delta * (u_int64_t)1000000 /
446 (u_int64_t)sys_cputimer->freq;
447 tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
450 return (tdd->us < 0);
454 * DRIVERSLEEP() does not switch if called with a spinlock held or
455 * from a hard interrupt.
458 DRIVERSLEEP(int usec)
460 globaldata_t gd = mycpu;
462 if (gd->gd_intr_nesting_level || gd->gd_spinlocks_wr) {
470 sysbeepstop(void *chan)
472 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
478 sysbeep(int pitch, int period)
480 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
482 if (sysbeep_enable == 0)
485 * Nobody else is using timer2, we do not need the clock lock
487 outb(TIMER_CNTR2, pitch);
488 outb(TIMER_CNTR2, (pitch>>8));
490 /* enable counter2 output to speaker */
491 outb(IO_PPI, inb(IO_PPI) | 3);
493 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
499 * RTC support routines
510 val = inb(IO_RTC + 1);
517 writertc(u_char reg, u_char val)
523 outb(IO_RTC + 1, val);
524 inb(0x84); /* XXX work around wrong order in rtcin() */
531 return(bcd2bin(rtcin(port)));
535 calibrate_clocks(void)
538 u_int count, prev_count, tot_count;
539 int sec, start_sec, timeout;
542 kprintf("Calibrating clock(s) ... ");
543 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
547 /* Read the mc146818A seconds counter. */
549 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
550 sec = rtcin(RTC_SEC);
557 /* Wait for the mC146818A seconds counter to change. */
560 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
561 sec = rtcin(RTC_SEC);
562 if (sec != start_sec)
569 /* Start keeping track of the i8254 counter. */
570 prev_count = sys_cputimer->count();
576 old_tsc = 0; /* shut up gcc */
579 * Wait for the mc146818A seconds counter to change. Read the i8254
580 * counter for each iteration since this is convenient and only
581 * costs a few usec of inaccuracy. The timing of the final reads
582 * of the counters almost matches the timing of the initial reads,
583 * so the main cause of inaccuracy is the varying latency from
584 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
585 * rtcin(RTC_SEC) that returns a changed seconds count. The
586 * maximum inaccuracy from this cause is < 10 usec on 486's.
590 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
591 sec = rtcin(RTC_SEC);
592 count = sys_cputimer->count();
593 tot_count += (int)(count - prev_count);
595 if (sec != start_sec)
602 * Read the cpu cycle counter. The timing considerations are
603 * similar to those for the i8254 clock.
606 tsc_frequency = rdtsc() - old_tsc;
610 kprintf("TSC clock: %llu Hz, ", tsc_frequency);
611 kprintf("i8254 clock: %u Hz\n", tot_count);
615 kprintf("failed, using default i8254 clock of %u Hz\n",
616 i8254_cputimer.freq);
617 return (i8254_cputimer.freq);
623 timer0_state = ACQUIRED;
628 * Timer0 is our fine-grained variable clock interrupt
630 outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
631 outb(TIMER_CNTR0, 2); /* lsb */
632 outb(TIMER_CNTR0, 0); /* msb */
636 cputimer_intr_register(&i8254_cputimer_intr);
637 cputimer_intr_select(&i8254_cputimer_intr, 0);
641 * Timer1 or timer2 is our free-running clock, but only if another
642 * has not been selected.
644 cputimer_register(&i8254_cputimer);
645 cputimer_select(&i8254_cputimer, 0);
649 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
654 * Should we use timer 1 or timer 2 ?
657 TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
658 if (which != 1 && which != 2)
663 timer->name = "i8254_timer1";
664 timer->type = CPUTIMER_8254_SEL1;
665 i8254_walltimer_sel = TIMER_SEL1;
666 i8254_walltimer_cntr = TIMER_CNTR1;
667 timer1_state = ACQUIRED;
670 timer->name = "i8254_timer2";
671 timer->type = CPUTIMER_8254_SEL2;
672 i8254_walltimer_sel = TIMER_SEL2;
673 i8254_walltimer_cntr = TIMER_CNTR2;
674 timer2_state = ACQUIRED;
678 timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
681 outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
682 outb(i8254_walltimer_cntr, 0); /* lsb */
683 outb(i8254_walltimer_cntr, 0); /* msb */
684 outb(IO_PPI, inb(IO_PPI) | 1); /* bit 0: enable gate, bit 1: spkr */
689 i8254_cputimer_destruct(struct cputimer *timer)
691 switch(timer->type) {
692 case CPUTIMER_8254_SEL1:
693 timer1_state = RELEASED;
695 case CPUTIMER_8254_SEL2:
696 timer2_state = RELEASED;
707 /* Restore all of the RTC's "status" (actually, control) registers. */
708 writertc(RTC_STATUSB, RTCSB_24HR);
709 writertc(RTC_STATUSA, rtc_statusa);
710 writertc(RTC_STATUSB, rtc_statusb);
714 * Restore all the timers.
716 * This function is called to resynchronize our core timekeeping after a
717 * long halt, e.g. from apm_default_resume() and friends. It is also
718 * called if after a BIOS call we have detected munging of the 8254.
719 * It is necessary because cputimer_count() counter's delta may have grown
720 * too large for nanouptime() and friends to handle, or (in the case of 8254
721 * munging) might cause the SYSTIMER code to prematurely trigger.
727 i8254_restore(); /* restore timer_freq and hz */
728 rtc_restore(); /* reenable RTC interrupts */
733 * Initialize 8254 timer 0 early so that it can be used in DELAY().
741 * Can we use the TSC?
743 if (cpu_feature & CPUID_TSC)
749 * Initial RTC state, don't do anything unexpected
751 writertc(RTC_STATUSA, rtc_statusa);
752 writertc(RTC_STATUSB, RTCSB_24HR);
755 * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
756 * generate an interrupt, which we will ignore for now.
758 * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
759 * (so it counts a full 2^16 and repeats). We will use this timer
763 freq = calibrate_clocks();
764 #ifdef CLK_CALIBRATION_LOOP
767 "Press a key on the console to abort clock calibration\n");
768 while (cncheckc() == -1)
774 * Use the calibrated i8254 frequency if it seems reasonable.
775 * Otherwise use the default, and don't use the calibrated i586
778 delta = freq > i8254_cputimer.freq ?
779 freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
780 if (delta < i8254_cputimer.freq / 100) {
781 #ifndef CLK_USE_I8254_CALIBRATION
784 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
785 freq = i8254_cputimer.freq;
789 * Interrupt timer's freq must be adjusted
790 * before we change the cuptimer's frequency.
792 i8254_cputimer_intr.freq = freq;
793 cputimer_set_frequency(&i8254_cputimer, freq);
797 "%d Hz differs from default of %d Hz by more than 1%%\n",
798 freq, i8254_cputimer.freq);
802 #ifndef CLK_USE_TSC_CALIBRATION
803 if (tsc_frequency != 0) {
806 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
810 if (tsc_present && tsc_frequency == 0) {
812 * Calibration of the i586 clock relative to the mc146818A
813 * clock failed. Do a less accurate calibration relative
814 * to the i8254 clock.
816 u_int64_t old_tsc = rdtsc();
819 tsc_frequency = rdtsc() - old_tsc;
820 #ifdef CLK_USE_TSC_CALIBRATION
822 kprintf("TSC clock: %llu Hz (Method B)\n",
828 EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
832 * We can not use the TSC in SMP mode, until we figure out a
833 * cheap (impossible), reliable and precise (yeah right!) way
834 * to synchronize the TSCs of all the CPUs.
835 * Curse Intel for leaving the counter out of the I/O APIC.
840 * We can not use the TSC if we support APM. Precise timekeeping
841 * on an APM'ed machine is at best a fools pursuit, since
842 * any and all of the time spent in various SMM code can't
843 * be reliably accounted for. Reading the RTC is your only
844 * source of reliable time info. The i8254 looses too of course
845 * but we need to have some kind of time...
846 * We don't know at this point whether APM is going to be used
847 * or not, nor when it might be activated. Play it safe.
850 #endif /* NAPM > 0 */
852 #endif /* !defined(SMP) */
856 * Sync the time of day back to the RTC on shutdown, but only if
857 * we have already loaded it and have not crashed.
860 resettodr_on_shutdown(void *arg __unused)
862 if (rtc_loaded && panicstr == NULL) {
868 * Initialize the time of day register, based on the time base which is, e.g.
872 inittodr(time_t base)
874 unsigned long sec, days;
885 /* Look if we have a RTC present and the time is valid */
886 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
889 /* wait for time update to complete */
890 /* If RTCSA_TUP is zero, we have at least 244us before next update */
892 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
898 #ifdef USE_RTC_CENTURY
899 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
901 year = readrtc(RTC_YEAR) + 1900;
909 month = readrtc(RTC_MONTH);
910 for (m = 1; m < month; m++)
911 days += daysinmonth[m-1];
912 if ((month > 2) && LEAPYEAR(year))
914 days += readrtc(RTC_DAY) - 1;
915 for (y = 1970; y < year; y++)
916 days += DAYSPERYEAR + LEAPYEAR(y);
917 sec = ((( days * 24 +
918 readrtc(RTC_HRS)) * 60 +
919 readrtc(RTC_MIN)) * 60 +
921 /* sec now contains the number of seconds, since Jan 1 1970,
922 in the local time zone */
924 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
926 y = time_second - sec;
927 if (y <= -2 || y >= 2) {
928 /* badly off, adjust it */
938 kprintf("Invalid time in real time clock.\n");
939 kprintf("Check and reset the date immediately!\n");
943 * Write system time back to RTC
960 /* Disable RTC updates and interrupts. */
961 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
963 /* Calculate local time to put in RTC */
965 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
967 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
968 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
969 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
971 /* We have now the days since 01-01-1970 in tm */
972 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
973 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
975 y++, m = DAYSPERYEAR + LEAPYEAR(y))
978 /* Now we have the years in y and the day-of-the-year in tm */
979 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
980 #ifdef USE_RTC_CENTURY
981 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
987 if (m == 1 && LEAPYEAR(y))
994 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
995 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
997 /* Reenable RTC updates and interrupts. */
998 writertc(RTC_STATUSB, rtc_statusb);
1003 i8254_ioapic_trial(int irq, struct cputimer_intr *cti)
1009 * Following code assumes the 8254 is the cpu timer,
1010 * so make sure it is.
1012 KKASSERT(sys_cputimer == &i8254_cputimer);
1013 KKASSERT(cti == &i8254_cputimer_intr);
1015 lastcnt = get_interrupt_counter(irq);
1018 * Force an 8254 Timer0 interrupt and wait 1/100s for
1019 * it to happen, then see if we got it.
1021 kprintf("IOAPIC: testing 8254 interrupt delivery\n");
1023 i8254_intr_reload(cti, 2);
1024 base = sys_cputimer->count();
1025 while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1028 if (get_interrupt_counter(irq) - lastcnt == 0)
1034 * Start both clocks running. DragonFly note: the stat clock is no longer
1035 * used. Instead, 8254 based systimers are used for all major clock
1039 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1041 void *clkdesc = NULL;
1042 int irq = 0, mixed_mode = 0, error;
1044 callout_init(&sysbeepstop_ch);
1046 if (!selected && i8254_intr_disable)
1050 * The stat interrupt mask is different without the
1051 * statistics clock. Also, don't set the interrupt
1052 * flag which would normally cause the RTC to generate
1055 rtc_statusb = RTCSB_24HR;
1057 /* Finish initializing 8253 timer 0. */
1058 if (ioapic_enable) {
1059 irq = ioapic_abi_find_irq(0, INTR_TRIGGER_EDGE,
1060 INTR_POLARITY_HIGH);
1063 error = ioapic_abi_extint_irqmap(0);
1065 irq = ioapic_abi_find_irq(0, INTR_TRIGGER_EDGE,
1066 INTR_POLARITY_HIGH);
1073 kprintf("IOAPIC: setup mixed mode for "
1074 "irq 0 failed: %d\n", error);
1077 panic("IOAPIC: setup mixed mode for "
1078 "irq 0 failed: %d\n", error);
1083 clkdesc = register_int(irq, clkintr, NULL, "clk",
1085 INTR_EXCL | INTR_CLOCK |
1086 INTR_NOPOLL | INTR_MPSAFE |
1089 register_int(0, clkintr, NULL, "clk", NULL,
1090 INTR_EXCL | INTR_CLOCK |
1091 INTR_NOPOLL | INTR_MPSAFE |
1095 /* Initialize RTC. */
1096 writertc(RTC_STATUSA, rtc_statusa);
1097 writertc(RTC_STATUSB, RTCSB_24HR);
1099 if (ioapic_enable) {
1100 error = i8254_ioapic_trial(irq, cti);
1104 kprintf("IOAPIC: mixed mode for irq %d "
1105 "trial failed: %d\n",
1109 panic("IOAPIC: mixed mode for irq %d "
1110 "trial failed: %d\n", irq, error);
1113 kprintf("IOAPIC: warning 8254 is not connected "
1114 "to the correct pin, try mixed mode\n");
1115 unregister_int(clkdesc);
1116 goto mixed_mode_setup;
1123 i8254_nointr = 1; /* don't try to register again */
1124 cputimer_intr_deregister(cti);
1128 setstatclockrate(int newhz)
1130 if (newhz == RTC_PROFRATE)
1131 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1133 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1134 writertc(RTC_STATUSA, rtc_statusa);
1139 tsc_get_timecount(struct timecounter *tc)
1145 #ifdef KERN_TIMESTAMP
1146 #define KERN_TIMESTAMP_SIZE 16384
1147 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1148 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1149 sizeof(tsc), "LU", "Kernel timestamps");
1155 tsc[i] = (u_int32_t)rdtsc();
1158 if (i >= KERN_TIMESTAMP_SIZE)
1160 tsc[i] = 0; /* mark last entry */
1162 #endif /* KERN_TIMESTAMP */
1169 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1176 if (sys_cputimer == &i8254_cputimer)
1177 count = sys_cputimer->count();
1185 ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1186 return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1189 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1190 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1192 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1193 0, 0, hw_i8254_timestamp, "A", "");
1195 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1196 &tsc_present, 0, "TSC Available");
1197 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1198 &tsc_frequency, 0, "TSC Frequency");