sys/dev/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <drm/drmP.h>
  28 #include <drm/i915_drm.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31
  32 #include <linux/highmem.h>
  33
  34 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv);
  35 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv);
  36
  37 bool intel_enable_ppgtt(struct drm_device *dev, bool full)
  38 {
  39         if (i915.enable_ppgtt == 0)
  40                 return false;
  41
  42         if (i915.enable_ppgtt == 1 && full)
  43                 return false;
  44
  45         return true;
  46 }
  47
  48 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
  49 {
  50         if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev))
  51                 return 0;
  52
  53         if (enable_ppgtt == 1)
  54                 return 1;
  55
  56         if (enable_ppgtt == 2 && HAS_PPGTT(dev))
  57                 return 2;
  58
  59 #ifdef CONFIG_INTEL_IOMMU
  60         /* Disable ppgtt on SNB if VT-d is on. */
  61         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
  62                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
  63                 return 0;
  64         }
  65 #endif
  66
  67         /* Early VLV doesn't have this */
  68         int revision = pci_read_config(dev->dev, PCIR_REVID, 1);
  69         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
  70             revision < 0xb) {
  71                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
  72                 return 0;
  73         }
  74
  75         return HAS_ALIASING_PPGTT(dev) ? 1 : 0;
  76 }
  77
  78 static void ppgtt_bind_vma(struct i915_vma *vma,
  79                            enum i915_cache_level cache_level,
  80                            u32 flags);
  81 static void ppgtt_unbind_vma(struct i915_vma *vma);
  82 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt);
  83
  84 static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr,
  85                                              enum i915_cache_level level,
  86                                              bool valid)
  87 {
  88         gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
  89         pte |= addr;
  90
  91         switch (level) {
  92         case I915_CACHE_NONE:
  93                 pte |= PPAT_UNCACHED_INDEX;
  94                 break;
  95         case I915_CACHE_WT:
  96                 pte |= PPAT_DISPLAY_ELLC_INDEX;
  97                 break;
  98         default:
  99                 pte |= PPAT_CACHED_INDEX;
 100                 break;
 101         }
 102
 103         return pte;
 104 }
 105
 106 static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev,
 107                                              dma_addr_t addr,
 108                                              enum i915_cache_level level)
 109 {
 110         gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 111         pde |= addr;
 112         if (level != I915_CACHE_NONE)
 113                 pde |= PPAT_CACHED_PDE_INDEX;
 114         else
 115                 pde |= PPAT_UNCACHED_INDEX;
 116         return pde;
 117 }
 118
 119 static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
 120                                      enum i915_cache_level level,
 121                                      bool valid, u32 unused)
 122 {
 123         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 124         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 125
 126         switch (level) {
 127         case I915_CACHE_L3_LLC:
 128         case I915_CACHE_LLC:
 129                 pte |= GEN6_PTE_CACHE_LLC;
 130                 break;
 131         case I915_CACHE_NONE:
 132                 pte |= GEN6_PTE_UNCACHED;
 133                 break;
 134         default:
 135                 WARN_ON(1);
 136         }
 137
 138         return pte;
 139 }
 140
 141 static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
 142                                      enum i915_cache_level level,
 143                                      bool valid, u32 unused)
 144 {
 145         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 146         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 147
 148         switch (level) {
 149         case I915_CACHE_L3_LLC:
 150                 pte |= GEN7_PTE_CACHE_L3_LLC;
 151                 break;
 152         case I915_CACHE_LLC:
 153                 pte |= GEN6_PTE_CACHE_LLC;
 154                 break;
 155         case I915_CACHE_NONE:
 156                 pte |= GEN6_PTE_UNCACHED;
 157                 break;
 158         default:
 159                 WARN_ON(1);
 160         }
 161
 162         return pte;
 163 }
 164
 165 static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
 166                                      enum i915_cache_level level,
 167                                      bool valid, u32 flags)
 168 {
 169         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 170         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 171
 172         /* Mark the page as writeable.  Other platforms don't have a
 173          * setting for read-only/writable, so this matches that behavior.
 174          */
 175         if (!(flags & PTE_READ_ONLY))
 176                 pte |= BYT_PTE_WRITEABLE;
 177
 178         if (level != I915_CACHE_NONE)
 179                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 180
 181         return pte;
 182 }
 183
 184 static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
 185                                      enum i915_cache_level level,
 186                                      bool valid, u32 unused)
 187 {
 188         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 189         pte |= HSW_PTE_ADDR_ENCODE(addr);
 190
 191         if (level != I915_CACHE_NONE)
 192                 pte |= HSW_WB_LLC_AGE3;
 193
 194         return pte;
 195 }
 196
 197 static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
 198                                       enum i915_cache_level level,
 199                                       bool valid, u32 unused)
 200 {
 201         gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 202         pte |= HSW_PTE_ADDR_ENCODE(addr);
 203
 204         switch (level) {
 205         case I915_CACHE_NONE:
 206                 break;
 207         case I915_CACHE_WT:
 208                 pte |= HSW_WT_ELLC_LLC_AGE3;
 209                 break;
 210         default:
 211                 pte |= HSW_WB_ELLC_LLC_AGE3;
 212                 break;
 213         }
 214
 215         return pte;
 216 }
 217
 218 /* Broadwell Page Directory Pointer Descriptors */
 219 static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry,
 220                            uint64_t val, bool synchronous)
 221 {
 222         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 223         int ret;
 224
 225         BUG_ON(entry >= 4);
 226
 227         if (synchronous) {
 228                 I915_WRITE(GEN8_RING_PDP_UDW(ring, entry), val >> 32);
 229                 I915_WRITE(GEN8_RING_PDP_LDW(ring, entry), (u32)val);
 230                 return 0;
 231         }
 232
 233         ret = intel_ring_begin(ring, 6);
 234         if (ret)
 235                 return ret;
 236
 237         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 238         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 239         intel_ring_emit(ring, (u32)(val >> 32));
 240         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 241         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 242         intel_ring_emit(ring, (u32)(val));
 243         intel_ring_advance(ring);
 244
 245         return 0;
 246 }
 247
 248 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
 249                           struct intel_engine_cs *ring,
 250                           bool synchronous)
 251 {
 252         int i, ret;
 253
 254         /* bit of a hack to find the actual last used pd */
 255         int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE;
 256
 257         for (i = used_pd - 1; i >= 0; i--) {
 258                 dma_addr_t addr = ppgtt->pd_dma_addr[i];
 259                 ret = gen8_write_pdp(ring, i, addr, synchronous);
 260                 if (ret)
 261                         return ret;
 262         }
 263
 264         return 0;
 265 }
 266
 267 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 268                                    uint64_t start,
 269                                    uint64_t length,
 270                                    bool use_scratch)
 271 {
 272         struct i915_hw_ppgtt *ppgtt =
 273                 container_of(vm, struct i915_hw_ppgtt, base);
 274         gen8_gtt_pte_t *pt_vaddr, scratch_pte;
 275         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 276         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 277         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 278         unsigned num_entries = length >> PAGE_SHIFT;
 279         unsigned last_pte, i;
 280
 281         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 282                                       I915_CACHE_LLC, use_scratch);
 283
 284         while (num_entries) {
 285                 struct vm_page *page_table = ppgtt->gen8_pt_pages[pdpe][pde];
 286
 287                 last_pte = pte + num_entries;
 288                 if (last_pte > GEN8_PTES_PER_PAGE)
 289                         last_pte = GEN8_PTES_PER_PAGE;
 290
 291                 pt_vaddr = kmap_atomic(page_table);
 292
 293                 for (i = pte; i < last_pte; i++) {
 294                         pt_vaddr[i] = scratch_pte;
 295                         num_entries--;
 296                 }
 297
 298                 if (!HAS_LLC(ppgtt->base.dev))
 299                         drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 300                 kunmap_atomic(pt_vaddr);
 301
 302                 pte = 0;
 303                 if (++pde == GEN8_PDES_PER_PAGE) {
 304                         pdpe++;
 305                         pde = 0;
 306                 }
 307         }
 308 }
 309
 310 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 311                                       vm_page_t *pages,
 312                                       uint64_t start,
 313                                       unsigned int num_entries,
 314                                       enum i915_cache_level cache_level, u32 unused)
 315 {
 316         struct i915_hw_ppgtt *ppgtt =
 317                 container_of(vm, struct i915_hw_ppgtt, base);
 318         gen8_gtt_pte_t *pt_vaddr;
 319         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 320         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 321         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 322         int i;
 323
 324         pt_vaddr = NULL;
 325
 326         for (i=0;i<num_entries;i++) {
 327                 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPS))
 328                         break;
 329
 330                 if (pt_vaddr == NULL)
 331                         pt_vaddr = kmap_atomic(ppgtt->gen8_pt_pages[pdpe][pde]);
 332
 333                 pt_vaddr[pte] =
 334                         gen8_pte_encode(VM_PAGE_TO_PHYS(pages[i]),
 335                                         cache_level, true);
 336                 if (++pte == GEN8_PTES_PER_PAGE) {
 337                         if (!HAS_LLC(ppgtt->base.dev))
 338                                 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 339                         kunmap_atomic(pt_vaddr);
 340                         pt_vaddr = NULL;
 341                         if (++pde == GEN8_PDES_PER_PAGE) {
 342                                 pdpe++;
 343                                 pde = 0;
 344                         }
 345                         pte = 0;
 346                 }
 347         }
 348         if (pt_vaddr) {
 349                 if (!HAS_LLC(ppgtt->base.dev))
 350                         drm_clflush_virt_range(pt_vaddr, PAGE_SIZE);
 351                 kunmap_atomic(pt_vaddr);
 352         }
 353 }
 354
 355 static void gen8_free_page_tables(struct vm_page **pt_pages)
 356 {
 357         int i;
 358
 359         if (pt_pages == NULL)
 360                 return;
 361
 362         for (i = 0; i < GEN8_PDES_PER_PAGE; i++)
 363                 if (pt_pages[i])
 364                         __free_pages(pt_pages[i], 0);
 365 }
 366
 367 static void gen8_ppgtt_free(const struct i915_hw_ppgtt *ppgtt)
 368 {
 369         int i;
 370
 371         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 372                 gen8_free_page_tables(ppgtt->gen8_pt_pages[i]);
 373                 kfree(ppgtt->gen8_pt_pages[i]);
 374                 kfree(ppgtt->gen8_pt_dma_addr[i]);
 375         }
 376
 377         __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
 378 }
 379
 380 static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
 381 {
 382         struct pci_dev *hwdev = ppgtt->base.dev->pdev;
 383         int i, j;
 384
 385         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 386                 /* TODO: In the future we'll support sparse mappings, so this
 387                  * will have to change. */
 388                 if (!ppgtt->pd_dma_addr[i])
 389                         continue;
 390
 391                 pci_unmap_page(hwdev, ppgtt->pd_dma_addr[i], PAGE_SIZE,
 392                                PCI_DMA_BIDIRECTIONAL);
 393
 394                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 395                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 396                         if (addr)
 397                                 pci_unmap_page(hwdev, addr, PAGE_SIZE,
 398                                                PCI_DMA_BIDIRECTIONAL);
 399                 }
 400         }
 401 }
 402
 403 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 404 {
 405         struct i915_hw_ppgtt *ppgtt =
 406                 container_of(vm, struct i915_hw_ppgtt, base);
 407
 408         list_del(&vm->global_link);
 409         drm_mm_takedown(&vm->mm);
 410
 411         gen8_ppgtt_unmap_pages(ppgtt);
 412         gen8_ppgtt_free(ppgtt);
 413 }
 414
 415 static struct vm_page **__gen8_alloc_page_tables(void)
 416 {
 417         struct vm_page **pt_pages;
 418         int i;
 419
 420         pt_pages = kcalloc(GEN8_PDES_PER_PAGE, sizeof(struct vm_page *), GFP_KERNEL);
 421         if (!pt_pages)
 422                 return ERR_PTR(-ENOMEM);
 423
 424         for (i = 0; i < GEN8_PDES_PER_PAGE; i++) {
 425                 pt_pages[i] = alloc_page(GFP_KERNEL);
 426                 if (!pt_pages[i])
 427                         goto bail;
 428         }
 429
 430         return pt_pages;
 431
 432 bail:
 433         gen8_free_page_tables(pt_pages);
 434         kfree(pt_pages);
 435         return ERR_PTR(-ENOMEM);
 436 }
 437
 438 static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt,
 439                                            const int max_pdp)
 440 {
 441         struct vm_page **pt_pages[GEN8_LEGACY_PDPS];
 442         int i, ret;
 443
 444         for (i = 0; i < max_pdp; i++) {
 445                 pt_pages[i] = __gen8_alloc_page_tables();
 446                 if (IS_ERR(pt_pages[i])) {
 447                         ret = PTR_ERR(pt_pages[i]);
 448                         goto unwind_out;
 449                 }
 450         }
 451
 452         /* NB: Avoid touching gen8_pt_pages until last to keep the allocation,
 453          * "atomic" - for cleanup purposes.
 454          */
 455         for (i = 0; i < max_pdp; i++)
 456                 ppgtt->gen8_pt_pages[i] = pt_pages[i];
 457
 458         return 0;
 459
 460 unwind_out:
 461         while (i--) {
 462                 gen8_free_page_tables(pt_pages[i]);
 463                 kfree(pt_pages[i]);
 464         }
 465
 466         return ret;
 467 }
 468
 469 static int gen8_ppgtt_allocate_dma(struct i915_hw_ppgtt *ppgtt)
 470 {
 471         int i;
 472
 473         for (i = 0; i < ppgtt->num_pd_pages; i++) {
 474                 ppgtt->gen8_pt_dma_addr[i] = kcalloc(GEN8_PDES_PER_PAGE,
 475                                                      sizeof(dma_addr_t),
 476                                                      GFP_KERNEL);
 477                 if (!ppgtt->gen8_pt_dma_addr[i])
 478                         return -ENOMEM;
 479         }
 480
 481         return 0;
 482 }
 483
 484 static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt,
 485                                                 const int max_pdp)
 486 {
 487         ppgtt->pd_pages = alloc_pages(GFP_KERNEL, get_order(max_pdp << PAGE_SHIFT));
 488         if (!ppgtt->pd_pages)
 489                 return -ENOMEM;
 490
 491         ppgtt->num_pd_pages = 1 << get_order(max_pdp << PAGE_SHIFT);
 492         BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
 493
 494         return 0;
 495 }
 496
 497 static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt,
 498                             const int max_pdp)
 499 {
 500         int ret;
 501
 502         ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp);
 503         if (ret)
 504                 return ret;
 505
 506         ret = gen8_ppgtt_allocate_page_tables(ppgtt, max_pdp);
 507         if (ret) {
 508                 __free_pages(ppgtt->pd_pages, get_order(max_pdp << PAGE_SHIFT));
 509                 return ret;
 510         }
 511
 512         ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE;
 513
 514         ret = gen8_ppgtt_allocate_dma(ppgtt);
 515         if (ret)
 516                 gen8_ppgtt_free(ppgtt);
 517
 518         return ret;
 519 }
 520
 521 static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt,
 522                                              const int pd)
 523 {
 524         dma_addr_t pd_addr;
 525         int ret;
 526
 527         pd_addr = pci_map_page(ppgtt->base.dev->pdev,
 528                                &ppgtt->pd_pages[pd], 0,
 529                                PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 530
 531         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr);
 532         if (ret)
 533                 return ret;
 534
 535         ppgtt->pd_dma_addr[pd] = pd_addr;
 536
 537         return 0;
 538 }
 539
 540 static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt,
 541                                         const int pd,
 542                                         const int pt)
 543 {
 544         dma_addr_t pt_addr;
 545         struct vm_page *p;
 546         int ret;
 547
 548         p = ppgtt->gen8_pt_pages[pd][pt];
 549         pt_addr = pci_map_page(ppgtt->base.dev->pdev,
 550                                p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 551         ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr);
 552         if (ret)
 553                 return ret;
 554
 555         ppgtt->gen8_pt_dma_addr[pd][pt] = pt_addr;
 556
 557         return 0;
 558 }
 559
 560 /**
 561  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
 562  * with a net effect resembling a 2-level page table in normal x86 terms. Each
 563  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
 564  * space.
 565  *
 566  * FIXME: split allocation into smaller pieces. For now we only ever do this
 567  * once, but with full PPGTT, the multiple contiguous allocations will be bad.
 568  * TODO: Do something with the size parameter
 569  */
 570 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
 571 {
 572         const int max_pdp = DIV_ROUND_UP(size, 1 << 30);
 573         const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp;
 574         int i, j, ret;
 575
 576         if (size % (1<<30))
 577                 DRM_INFO("Pages will be wasted unless GTT size (%lu) is divisible by 1GB\n", size);
 578
 579         /* 1. Do all our allocations for page directories and page tables. */
 580         ret = gen8_ppgtt_alloc(ppgtt, max_pdp);
 581         if (ret)
 582                 return ret;
 583
 584         /*
 585          * 2. Create DMA mappings for the page directories and page tables.
 586          */
 587         for (i = 0; i < max_pdp; i++) {
 588                 ret = gen8_ppgtt_setup_page_directories(ppgtt, i);
 589                 if (ret)
 590                         goto bail;
 591
 592                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 593                         ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j);
 594                         if (ret)
 595                                 goto bail;
 596                 }
 597         }
 598
 599         /*
 600          * 3. Map all the page directory entires to point to the page tables
 601          * we've allocated.
 602          *
 603          * For now, the PPGTT helper functions all require that the PDEs are
 604          * plugged in correctly. So we do that now/here. For aliasing PPGTT, we
 605          * will never need to touch the PDEs again.
 606          */
 607         for (i = 0; i < max_pdp; i++) {
 608                 gen8_ppgtt_pde_t *pd_vaddr;
 609                 pd_vaddr = kmap_atomic(&ppgtt->pd_pages[i]);
 610                 for (j = 0; j < GEN8_PDES_PER_PAGE; j++) {
 611                         dma_addr_t addr = ppgtt->gen8_pt_dma_addr[i][j];
 612                         pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr,
 613                                                       I915_CACHE_LLC);
 614                 }
 615                 if (!HAS_LLC(ppgtt->base.dev))
 616                         drm_clflush_virt_range(pd_vaddr, PAGE_SIZE);
 617                 kunmap_atomic(pd_vaddr);
 618         }
 619
 620         ppgtt->enable = gen8_ppgtt_enable;
 621         ppgtt->switch_mm = gen8_mm_switch;
 622         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 623         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 624         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 625         ppgtt->base.start = 0;
 626         ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE;
 627
 628         ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
 629
 630         DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n",
 631                          ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp);
 632         DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%ld wasted)\n",
 633                          ppgtt->num_pd_entries,
 634                          (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30));
 635         return 0;
 636
 637 bail:
 638         gen8_ppgtt_unmap_pages(ppgtt);
 639         gen8_ppgtt_free(ppgtt);
 640         return ret;
 641 }
 642
 643 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
 644 {
 645         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 646         struct i915_address_space *vm = &ppgtt->base;
 647         gen6_gtt_pte_t __iomem *pd_addr;
 648         gen6_gtt_pte_t scratch_pte;
 649         uint32_t pd_entry;
 650         int pte, pde;
 651
 652         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
 653
 654         pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm +
 655                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 656
 657         seq_printf(m, "  VM %p (pd_offset %x-%x):\n", vm,
 658                    ppgtt->pd_offset, ppgtt->pd_offset + ppgtt->num_pd_entries);
 659         for (pde = 0; pde < ppgtt->num_pd_entries; pde++) {
 660                 u32 expected;
 661                 gen6_gtt_pte_t *pt_vaddr;
 662                 dma_addr_t pt_addr = ppgtt->pt_dma_addr[pde];
 663                 pd_entry = readl(pd_addr + pde);
 664                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
 665
 666                 if (pd_entry != expected)
 667                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
 668                                    pde,
 669                                    pd_entry,
 670                                    expected);
 671                 seq_printf(m, "\tPDE: %x\n", pd_entry);
 672
 673                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[pde]);
 674                 for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) {
 675                         unsigned long va =
 676                                 (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) +
 677                                 (pte * PAGE_SIZE);
 678                         int i;
 679                         bool found = false;
 680                         for (i = 0; i < 4; i++)
 681                                 if (pt_vaddr[pte + i] != scratch_pte)
 682                                         found = true;
 683                         if (!found)
 684                                 continue;
 685
 686                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
 687                         for (i = 0; i < 4; i++) {
 688                                 if (pt_vaddr[pte + i] != scratch_pte)
 689                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
 690                                 else
 691                                         seq_printf(m, "  SCRATCH ");
 692                         }
 693                         seq_printf(m, "\n");
 694                 }
 695                 kunmap_atomic(pt_vaddr);
 696         }
 697 }
 698
 699 static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
 700 {
 701         struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
 702         gen6_gtt_pte_t __iomem *pd_addr;
 703         uint32_t pd_entry;
 704         int i;
 705
 706         WARN_ON(ppgtt->pd_offset & 0x3f);
 707         pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
 708                 ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
 709         for (i = 0; i < ppgtt->num_pd_entries; i++) {
 710                 dma_addr_t pt_addr;
 711
 712                 pt_addr = ppgtt->pt_dma_addr[i];
 713                 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
 714                 pd_entry |= GEN6_PDE_VALID;
 715
 716                 writel(pd_entry, pd_addr + i);
 717         }
 718         readl(pd_addr);
 719 }
 720
 721 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
 722 {
 723         BUG_ON(ppgtt->pd_offset & 0x3f);
 724
 725         return (ppgtt->pd_offset / 64) << 16;
 726 }
 727
 728 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
 729                          struct intel_engine_cs *ring,
 730                          bool synchronous)
 731 {
 732         struct drm_device *dev = ppgtt->base.dev;
 733         struct drm_i915_private *dev_priv = dev->dev_private;
 734         int ret;
 735
 736         /* If we're in reset, we can assume the GPU is sufficiently idle to
 737          * manually frob these bits. Ideally we could use the ring functions,
 738          * except our error handling makes it quite difficult (can't use
 739          * intel_ring_begin, ring->flush, or intel_ring_advance)
 740          *
 741          * FIXME: We should try not to special case reset
 742          */
 743         if (synchronous ||
 744             i915_reset_in_progress(&dev_priv->gpu_error)) {
 745                 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
 746                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 747                 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 748                 POSTING_READ(RING_PP_DIR_BASE(ring));
 749                 return 0;
 750         }
 751
 752         /* NB: TLBs must be flushed and invalidated before a switch */
 753         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 754         if (ret)
 755                 return ret;
 756
 757         ret = intel_ring_begin(ring, 6);
 758         if (ret)
 759                 return ret;
 760
 761         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 762         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 763         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 764         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 765         intel_ring_emit(ring, get_pd_offset(ppgtt));
 766         intel_ring_emit(ring, MI_NOOP);
 767         intel_ring_advance(ring);
 768
 769         return 0;
 770 }
 771
 772 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
 773                           struct intel_engine_cs *ring,
 774                           bool synchronous)
 775 {
 776         struct drm_device *dev = ppgtt->base.dev;
 777         struct drm_i915_private *dev_priv = dev->dev_private;
 778         int ret;
 779
 780         /* If we're in reset, we can assume the GPU is sufficiently idle to
 781          * manually frob these bits. Ideally we could use the ring functions,
 782          * except our error handling makes it quite difficult (can't use
 783          * intel_ring_begin, ring->flush, or intel_ring_advance)
 784          *
 785          * FIXME: We should try not to special case reset
 786          */
 787         if (synchronous ||
 788             i915_reset_in_progress(&dev_priv->gpu_error)) {
 789                 WARN_ON(ppgtt != dev_priv->mm.aliasing_ppgtt);
 790                 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 791                 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 792                 POSTING_READ(RING_PP_DIR_BASE(ring));
 793                 return 0;
 794         }
 795
 796         /* NB: TLBs must be flushed and invalidated before a switch */
 797         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 798         if (ret)
 799                 return ret;
 800
 801         ret = intel_ring_begin(ring, 6);
 802         if (ret)
 803                 return ret;
 804
 805         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
 806         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
 807         intel_ring_emit(ring, PP_DIR_DCLV_2G);
 808         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
 809         intel_ring_emit(ring, get_pd_offset(ppgtt));
 810         intel_ring_emit(ring, MI_NOOP);
 811         intel_ring_advance(ring);
 812
 813         /* XXX: RCS is the only one to auto invalidate the TLBs? */
 814         if (ring->id != RCS) {
 815                 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
 816                 if (ret)
 817                         return ret;
 818         }
 819
 820         return 0;
 821 }
 822
 823 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
 824                           struct intel_engine_cs *ring,
 825                           bool synchronous)
 826 {
 827         struct drm_device *dev = ppgtt->base.dev;
 828         struct drm_i915_private *dev_priv = dev->dev_private;
 829
 830         if (!synchronous)
 831                 return 0;
 832
 833         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
 834         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
 835
 836         POSTING_READ(RING_PP_DIR_DCLV(ring));
 837
 838         return 0;
 839 }
 840
 841 static int gen8_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 842 {
 843         struct drm_device *dev = ppgtt->base.dev;
 844         struct drm_i915_private *dev_priv = dev->dev_private;
 845         struct intel_engine_cs *ring;
 846         int j, ret;
 847
 848         for_each_ring(ring, dev_priv, j) {
 849                 I915_WRITE(RING_MODE_GEN7(ring),
 850                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 851
 852                 /* We promise to do a switch later with FULL PPGTT. If this is
 853                  * aliasing, this is the one and only switch we'll do */
 854                 if (USES_FULL_PPGTT(dev))
 855                         continue;
 856
 857                 ret = ppgtt->switch_mm(ppgtt, ring, true);
 858                 if (ret)
 859                         goto err_out;
 860         }
 861
 862         return 0;
 863
 864 err_out:
 865         for_each_ring(ring, dev_priv, j)
 866                 I915_WRITE(RING_MODE_GEN7(ring),
 867                            _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
 868         return ret;
 869 }
 870
 871 static int gen7_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 872 {
 873         struct drm_device *dev = ppgtt->base.dev;
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         struct intel_engine_cs *ring;
 876         uint32_t ecochk, ecobits;
 877         int i;
 878
 879         ecobits = I915_READ(GAC_ECO_BITS);
 880         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
 881
 882         ecochk = I915_READ(GAM_ECOCHK);
 883         if (IS_HASWELL(dev)) {
 884                 ecochk |= ECOCHK_PPGTT_WB_HSW;
 885         } else {
 886                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
 887                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
 888         }
 889         I915_WRITE(GAM_ECOCHK, ecochk);
 890
 891         for_each_ring(ring, dev_priv, i) {
 892                 int ret;
 893                 /* GFX_MODE is per-ring on gen7+ */
 894                 I915_WRITE(RING_MODE_GEN7(ring),
 895                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 896
 897                 /* We promise to do a switch later with FULL PPGTT. If this is
 898                  * aliasing, this is the one and only switch we'll do */
 899                 if (USES_FULL_PPGTT(dev))
 900                         continue;
 901
 902                 ret = ppgtt->switch_mm(ppgtt, ring, true);
 903                 if (ret)
 904                         return ret;
 905         }
 906
 907         return 0;
 908 }
 909
 910 static int gen6_ppgtt_enable(struct i915_hw_ppgtt *ppgtt)
 911 {
 912         struct drm_device *dev = ppgtt->base.dev;
 913         struct drm_i915_private *dev_priv = dev->dev_private;
 914         struct intel_engine_cs *ring;
 915         uint32_t ecochk, gab_ctl, ecobits;
 916         int i;
 917
 918         ecobits = I915_READ(GAC_ECO_BITS);
 919         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
 920                    ECOBITS_PPGTT_CACHE64B);
 921
 922         gab_ctl = I915_READ(GAB_CTL);
 923         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
 924
 925         ecochk = I915_READ(GAM_ECOCHK);
 926         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
 927
 928         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
 929
 930         for_each_ring(ring, dev_priv, i) {
 931                 int ret = ppgtt->switch_mm(ppgtt, ring, true);
 932                 if (ret)
 933                         return ret;
 934         }
 935
 936         return 0;
 937 }
 938
 939 /* PPGTT support for Sandybdrige/Gen6 and later */
 940 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
 941                                    uint64_t start,
 942                                    uint64_t length,
 943                                    bool use_scratch)
 944 {
 945         struct i915_hw_ppgtt *ppgtt =
 946                 container_of(vm, struct i915_hw_ppgtt, base);
 947         gen6_gtt_pte_t *pt_vaddr, scratch_pte;
 948         unsigned first_entry = start >> PAGE_SHIFT;
 949         unsigned num_entries = length >> PAGE_SHIFT;
 950         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 951         unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 952         unsigned last_pte, i;
 953
 954         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
 955
 956         while (num_entries) {
 957                 last_pte = first_pte + num_entries;
 958                 if (last_pte > I915_PPGTT_PT_ENTRIES)
 959                         last_pte = I915_PPGTT_PT_ENTRIES;
 960
 961                 pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 962
 963                 for (i = first_pte; i < last_pte; i++)
 964                         pt_vaddr[i] = scratch_pte;
 965
 966                 kunmap_atomic(pt_vaddr);
 967
 968                 num_entries -= last_pte - first_pte;
 969                 first_pte = 0;
 970                 act_pt++;
 971         }
 972 }
 973
 974 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
 975                                       vm_page_t *pages,
 976                                       uint64_t start,
 977                                       unsigned num_entries,
 978                                       enum i915_cache_level cache_level, u32 flags)
 979 {
 980         struct i915_hw_ppgtt *ppgtt =
 981                 container_of(vm, struct i915_hw_ppgtt, base);
 982         gen6_gtt_pte_t *pt_vaddr;
 983         unsigned first_entry = start >> PAGE_SHIFT;
 984         unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES;
 985         unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES;
 986
 987         pt_vaddr = NULL;
 988         for (int i=0;i<num_entries;i++) {
 989                 if (pt_vaddr == NULL)
 990                         pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]);
 991
 992                 pt_vaddr[act_pte] =
 993                         vm->pte_encode(VM_PAGE_TO_PHYS(pages[i]),
 994                                        cache_level, true, flags);
 995                 if (++act_pte == I915_PPGTT_PT_ENTRIES) {
 996                         kunmap_atomic(pt_vaddr);
 997                         pt_vaddr = NULL;
 998                         act_pt++;
 999                         act_pte = 0;
1000                 }
1001         }
1002         if (pt_vaddr)
1003                 kunmap_atomic(pt_vaddr);
1004 }
1005
1006 static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt)
1007 {
1008         int i;
1009
1010         if (ppgtt->pt_dma_addr) {
1011                 for (i = 0; i < ppgtt->num_pd_entries; i++)
1012                         pci_unmap_page(ppgtt->base.dev->pdev,
1013                                        ppgtt->pt_dma_addr[i],
1014                                        4096, PCI_DMA_BIDIRECTIONAL);
1015         }
1016 }
1017
1018 static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt)
1019 {
1020         int i;
1021
1022         kfree(ppgtt->pt_dma_addr);
1023         for (i = 0; i < ppgtt->num_pd_entries; i++)
1024                 __free_page(ppgtt->pt_pages[i]);
1025         kfree(ppgtt->pt_pages);
1026 }
1027
1028 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1029 {
1030         struct i915_hw_ppgtt *ppgtt =
1031                 container_of(vm, struct i915_hw_ppgtt, base);
1032
1033         list_del(&vm->global_link);
1034         drm_mm_takedown(&ppgtt->base.mm);
1035         drm_mm_remove_node(&ppgtt->node);
1036
1037         gen6_ppgtt_unmap_pages(ppgtt);
1038         gen6_ppgtt_free(ppgtt);
1039 }
1040
1041 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1042 {
1043         struct drm_device *dev = ppgtt->base.dev;
1044         struct drm_i915_private *dev_priv = dev->dev_private;
1045         bool retried = false;
1046         int ret;
1047
1048         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1049          * allocator works in address space sizes, so it's multiplied by page
1050          * size. We allocate at the top of the GTT to avoid fragmentation.
1051          */
1052         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1053 alloc:
1054         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1055                                                   &ppgtt->node, GEN6_PD_SIZE,
1056                                                   GEN6_PD_ALIGN, 0,
1057                                                   0, dev_priv->gtt.base.total,
1058                                                   DRM_MM_TOPDOWN);
1059         if (ret == -ENOSPC && !retried) {
1060                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1061                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
1062                                                I915_CACHE_NONE,
1063                                                0, dev_priv->gtt.base.total,
1064                                                0);
1065                 if (ret)
1066                         return ret;
1067
1068                 retried = true;
1069                 goto alloc;
1070         }
1071
1072         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1073                 DRM_DEBUG("Forced to use aperture for PDEs\n");
1074
1075         ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES;
1076         return ret;
1077 }
1078
1079 static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt)
1080 {
1081         int i;
1082
1083         ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct vm_page *),
1084                                   GFP_KERNEL);
1085
1086         if (!ppgtt->pt_pages)
1087                 return -ENOMEM;
1088
1089         for (i = 0; i < ppgtt->num_pd_entries; i++) {
1090                 ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL);
1091                 if (!ppgtt->pt_pages[i]) {
1092                         gen6_ppgtt_free(ppgtt);
1093                         return -ENOMEM;
1094                 }
1095         }
1096
1097         return 0;
1098 }
1099
1100 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1101 {
1102         int ret;
1103
1104         ret = gen6_ppgtt_allocate_page_directories(ppgtt);
1105         if (ret)
1106                 return ret;
1107
1108         ret = gen6_ppgtt_allocate_page_tables(ppgtt);
1109         if (ret) {
1110                 drm_mm_remove_node(&ppgtt->node);
1111                 return ret;
1112         }
1113
1114         ppgtt->pt_dma_addr = kcalloc(ppgtt->num_pd_entries, sizeof(dma_addr_t),
1115                                      GFP_KERNEL);
1116         if (!ppgtt->pt_dma_addr) {
1117                 drm_mm_remove_node(&ppgtt->node);
1118                 gen6_ppgtt_free(ppgtt);
1119                 return -ENOMEM;
1120         }
1121
1122         return 0;
1123 }
1124
1125 static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt)
1126 {
1127         struct drm_device *dev = ppgtt->base.dev;
1128         int i;
1129
1130         for (i = 0; i < ppgtt->num_pd_entries; i++) {
1131                 dma_addr_t pt_addr;
1132
1133                 pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096,
1134                                        PCI_DMA_BIDIRECTIONAL);
1135
1136                 if (pci_dma_mapping_error(dev->pdev, pt_addr)) {
1137                         gen6_ppgtt_unmap_pages(ppgtt);
1138                         return -EIO;
1139                 }
1140
1141                 ppgtt->pt_dma_addr[i] = pt_addr;
1142         }
1143
1144         return 0;
1145 }
1146
1147 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1148 {
1149         struct drm_device *dev = ppgtt->base.dev;
1150         struct drm_i915_private *dev_priv = dev->dev_private;
1151         int ret;
1152
1153         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1154         if (IS_GEN6(dev)) {
1155                 ppgtt->enable = gen6_ppgtt_enable;
1156                 ppgtt->switch_mm = gen6_mm_switch;
1157         } else if (IS_HASWELL(dev)) {
1158                 ppgtt->enable = gen7_ppgtt_enable;
1159                 ppgtt->switch_mm = hsw_mm_switch;
1160         } else if (IS_GEN7(dev)) {
1161                 ppgtt->enable = gen7_ppgtt_enable;
1162                 ppgtt->switch_mm = gen7_mm_switch;
1163         } else
1164                 BUG();
1165
1166         ret = gen6_ppgtt_alloc(ppgtt);
1167         if (ret)
1168                 return ret;
1169
1170         ret = gen6_ppgtt_setup_page_tables(ppgtt);
1171         if (ret) {
1172                 gen6_ppgtt_free(ppgtt);
1173                 return ret;
1174         }
1175
1176         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1177         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1178         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1179         ppgtt->base.start = 0;
1180         ppgtt->base.total =  ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
1181         ppgtt->debug_dump = gen6_dump_ppgtt;
1182
1183         ppgtt->pd_offset =
1184                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
1185
1186         ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
1187
1188         DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n",
1189                          ppgtt->node.size >> 20,
1190                          ppgtt->node.start / PAGE_SIZE);
1191
1192         return 0;
1193 }
1194
1195 int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1196 {
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         int ret = 0;
1199
1200         ppgtt->base.dev = dev;
1201         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1202
1203         if (INTEL_INFO(dev)->gen < 8)
1204                 ret = gen6_ppgtt_init(ppgtt);
1205         else if (IS_GEN8(dev))
1206                 ret = gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total);
1207         else
1208                 BUG();
1209
1210         if (!ret) {
1211                 struct drm_i915_private *dev_priv = dev->dev_private;
1212                 kref_init(&ppgtt->ref);
1213                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1214                             ppgtt->base.total);
1215                 i915_init_vm(dev_priv, &ppgtt->base);
1216                 if (INTEL_INFO(dev)->gen < 8) {
1217                         gen6_write_pdes(ppgtt);
1218                         DRM_DEBUG("Adding PPGTT at offset %x\n",
1219                                   ppgtt->pd_offset << 10);
1220                 }
1221         }
1222
1223         return ret;
1224 }
1225
1226 static void
1227 ppgtt_bind_vma(struct i915_vma *vma,
1228                enum i915_cache_level cache_level,
1229                u32 flags)
1230 {
1231         const unsigned int num_entries = vma->obj->base.size >> PAGE_SHIFT;
1232
1233         /* Currently applicable only to VLV */
1234         if (vma->obj->gt_ro)
1235                 flags |= PTE_READ_ONLY;
1236
1237         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
1238                                 num_entries,
1239                                 cache_level, flags);
1240 }
1241
1242 static void ppgtt_unbind_vma(struct i915_vma *vma)
1243 {
1244         vma->vm->clear_range(vma->vm,
1245                              vma->node.start,
1246                              vma->obj->base.size,
1247                              true);
1248 }
1249
1250 extern int intel_iommu_gfx_mapped;
1251 /* Certain Gen5 chipsets require require idling the GPU before
1252  * unmapping anything from the GTT when VT-d is enabled.
1253  */
1254 static inline bool needs_idle_maps(struct drm_device *dev)
1255 {
1256 #ifdef CONFIG_INTEL_IOMMU
1257         /* Query intel_iommu to see if we need the workaround. Presumably that
1258          * was loaded first.
1259          */
1260         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1261                 return true;
1262 #endif
1263         return false;
1264 }
1265
1266 static bool do_idling(struct drm_i915_private *dev_priv)
1267 {
1268         bool ret = dev_priv->mm.interruptible;
1269
1270         if (unlikely(dev_priv->gtt.do_idle_maps)) {
1271                 dev_priv->mm.interruptible = false;
1272                 if (i915_gpu_idle(dev_priv->dev)) {
1273                         DRM_ERROR("Couldn't idle GPU\n");
1274                         /* Wait a bit, in hopes it avoids the hang */
1275                         udelay(10);
1276                 }
1277         }
1278
1279         return ret;
1280 }
1281
1282 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1283 {
1284         if (unlikely(dev_priv->gtt.do_idle_maps))
1285                 dev_priv->mm.interruptible = interruptible;
1286 }
1287
1288 void i915_check_and_clear_faults(struct drm_device *dev)
1289 {
1290         struct drm_i915_private *dev_priv = dev->dev_private;
1291         struct intel_engine_cs *ring;
1292         int i;
1293
1294         if (INTEL_INFO(dev)->gen < 6)
1295                 return;
1296
1297         for_each_ring(ring, dev_priv, i) {
1298                 u32 fault_reg;
1299                 fault_reg = I915_READ(RING_FAULT_REG(ring));
1300                 if (fault_reg & RING_FAULT_VALID) {
1301 #if 0
1302                         DRM_DEBUG_DRIVER("Unexpected fault\n"
1303                                          "\tAddr: 0x%08lx\\n"
1304                                          "\tAddress space: %s\n"
1305                                          "\tSource ID: %d\n"
1306                                          "\tType: %d\n",
1307                                          fault_reg & PAGE_MASK,
1308                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1309                                          RING_FAULT_SRCID(fault_reg),
1310                                          RING_FAULT_FAULT_TYPE(fault_reg));
1311 #endif
1312                         I915_WRITE(RING_FAULT_REG(ring),
1313                                    fault_reg & ~RING_FAULT_VALID);
1314                 }
1315         }
1316         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1317 }
1318
1319 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1320 {
1321         if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1322                 intel_gtt_chipset_flush();
1323         } else {
1324                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1325                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1326         }
1327 }
1328
1329 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1330 {
1331         struct drm_i915_private *dev_priv = dev->dev_private;
1332
1333         /* Don't bother messing with faults pre GEN6 as we have little
1334          * documentation supporting that it's a good idea.
1335          */
1336         if (INTEL_INFO(dev)->gen < 6)
1337                 return;
1338
1339         i915_check_and_clear_faults(dev);
1340
1341         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1342                                        dev_priv->gtt.base.start,
1343                                        dev_priv->gtt.base.total,
1344                                        true);
1345
1346         i915_ggtt_flush(dev_priv);
1347 }
1348
1349 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
1350 {
1351         struct drm_i915_private *dev_priv = dev->dev_private;
1352         struct drm_i915_gem_object *obj;
1353         struct i915_address_space *vm;
1354
1355         i915_check_and_clear_faults(dev);
1356
1357         /* First fill our portion of the GTT with scratch pages */
1358         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1359                                        dev_priv->gtt.base.start,
1360                                        dev_priv->gtt.base.total,
1361                                        true);
1362
1363         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1364                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
1365                                                            &dev_priv->gtt.base);
1366                 if (!vma)
1367                         continue;
1368
1369                 i915_gem_clflush_object(obj, obj->pin_display);
1370                 /* The bind_vma code tries to be smart about tracking mappings.
1371                  * Unfortunately above, we've just wiped out the mappings
1372                  * without telling our object about it. So we need to fake it.
1373                  */
1374                 obj->has_global_gtt_mapping = 0;
1375                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
1376         }
1377
1378
1379         if (INTEL_INFO(dev)->gen >= 8) {
1380                 if (IS_CHERRYVIEW(dev))
1381                         chv_setup_private_ppat(dev_priv);
1382                 else
1383                         bdw_setup_private_ppat(dev_priv);
1384
1385                 return;
1386         }
1387
1388         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
1389                 /* TODO: Perhaps it shouldn't be gen6 specific */
1390                 if (i915_is_ggtt(vm)) {
1391                         if (dev_priv->mm.aliasing_ppgtt)
1392                                 gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
1393                         continue;
1394                 }
1395
1396                 gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
1397         }
1398
1399         i915_ggtt_flush(dev_priv);
1400 }
1401
1402 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1403 {
1404         if (obj->has_dma_mapping)
1405                 return 0;
1406
1407 #if 0
1408         if (!dma_map_sg(&obj->base.dev->pdev->dev,
1409                         obj->pages->sgl, obj->pages->nents,
1410                         PCI_DMA_BIDIRECTIONAL))
1411                 return -ENOSPC;
1412 #endif
1413
1414         return 0;
1415 }
1416
1417 static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte)
1418 {
1419 #if 0
1420         writeq(pte, addr);
1421 #else
1422         iowrite32((u32)pte, addr);
1423         iowrite32(pte >> 32, addr + 4);
1424 #endif
1425 }
1426
1427 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1428                                      vm_page_t *pages,
1429                                      uint64_t start,
1430                                      unsigned int num_entries,
1431                                      enum i915_cache_level level, u32 unused)
1432 {
1433         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1434         unsigned first_entry = start >> PAGE_SHIFT;
1435         gen8_gtt_pte_t __iomem *gtt_entries =
1436                 (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1437         int i = 0;
1438         dma_addr_t addr = 0;
1439
1440         for (i=0;i<num_entries;i++) {
1441                 addr = VM_PAGE_TO_PHYS(pages[i]);
1442                 gen8_set_pte(&gtt_entries[i],
1443                              gen8_pte_encode(addr, level, true));
1444         }
1445
1446         /*
1447          * XXX: This serves as a posting read to make sure that the PTE has
1448          * actually been updated. There is some concern that even though
1449          * registers and PTEs are within the same BAR that they are potentially
1450          * of NUMA access patterns. Therefore, even with the way we assume
1451          * hardware should work, we must keep this posting read for paranoia.
1452          */
1453         if (i != 0)
1454                 WARN_ON(readq(&gtt_entries[i-1])
1455                         != gen8_pte_encode(addr, level, true));
1456
1457         /* This next bit makes the above posting read even more important. We
1458          * want to flush the TLBs only after we're certain all the PTE updates
1459          * have finished.
1460          */
1461         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1462         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1463 }
1464
1465 /*
1466  * Binds an object into the global gtt with the specified cache level. The object
1467  * will be accessible to the GPU via commands whose operands reference offsets
1468  * within the global GTT as well as accessible by the GPU through the GMADR
1469  * mapped BAR (dev_priv->mm.gtt->gtt).
1470  */
1471 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1472                                      vm_page_t *pages,
1473                                      uint64_t start,
1474                                      unsigned int num_entries,
1475                                      enum i915_cache_level level, u32 flags)
1476 {
1477         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1478         unsigned first_entry = start >> PAGE_SHIFT;
1479         gen6_gtt_pte_t __iomem *gtt_entries =
1480                 (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1481         int i = 0;
1482         dma_addr_t addr = 0; /* shut up gcc */
1483
1484         for (i = 0; i < num_entries; i++) {
1485                 addr = VM_PAGE_TO_PHYS(pages[i]);
1486                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1487         }
1488
1489         /* XXX: This serves as a posting read to make sure that the PTE has
1490          * actually been updated. There is some concern that even though
1491          * registers and PTEs are within the same BAR that they are potentially
1492          * of NUMA access patterns. Therefore, even with the way we assume
1493          * hardware should work, we must keep this posting read for paranoia.
1494          */
1495         if (i != 0) {
1496                 unsigned long gtt = readl(&gtt_entries[i-1]);
1497                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1498         }
1499
1500         /* This next bit makes the above posting read even more important. We
1501          * want to flush the TLBs only after we're certain all the PTE updates
1502          * have finished.
1503          */
1504         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1505         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1506 }
1507
1508 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1509                                   uint64_t start,
1510                                   uint64_t length,
1511                                   bool use_scratch)
1512 {
1513         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1514         unsigned first_entry = start >> PAGE_SHIFT;
1515         unsigned num_entries = length >> PAGE_SHIFT;
1516         gen8_gtt_pte_t scratch_pte, __iomem *gtt_base =
1517                 (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1518         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1519         int i;
1520
1521         if (WARN(num_entries > max_entries,
1522                  "First entry = %d; Num entries = %d (max=%d)\n",
1523                  first_entry, num_entries, max_entries))
1524                 num_entries = max_entries;
1525
1526         scratch_pte = gen8_pte_encode(vm->scratch.addr,
1527                                       I915_CACHE_LLC,
1528                                       use_scratch);
1529         for (i = 0; i < num_entries; i++)
1530                 gen8_set_pte(&gtt_base[i], scratch_pte);
1531         readl(gtt_base);
1532 }
1533
1534 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1535                                   uint64_t start,
1536                                   uint64_t length,
1537                                   bool use_scratch)
1538 {
1539         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1540         unsigned first_entry = start >> PAGE_SHIFT;
1541         unsigned num_entries = length >> PAGE_SHIFT;
1542         gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
1543                 (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1544         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1545         int i;
1546
1547         if (WARN(num_entries > max_entries,
1548                  "First entry = %d; Num entries = %d (max=%d)\n",
1549                  first_entry, num_entries, max_entries))
1550                 num_entries = max_entries;
1551
1552         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1553
1554         for (i = 0; i < num_entries; i++)
1555                 iowrite32(scratch_pte, &gtt_base[i]);
1556         readl(gtt_base);
1557 }
1558
1559 static void i915_ggtt_bind_vma(struct i915_vma *vma,
1560                                enum i915_cache_level cache_level,
1561                                u32 unused)
1562 {
1563         const unsigned long entry = vma->node.start >> PAGE_SHIFT;
1564         const unsigned int num_entries = vma->obj->base.size >> PAGE_SHIFT;
1565         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1566                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1567
1568         BUG_ON(!i915_is_ggtt(vma->vm));
1569         intel_gtt_insert_pages(entry, num_entries, vma->obj->pages, flags);
1570         vma->obj->has_global_gtt_mapping = 1;
1571 }
1572
1573 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1574                                   uint64_t start,
1575                                   uint64_t length,
1576                                   bool unused)
1577 {
1578         unsigned first_entry = start >> PAGE_SHIFT;
1579         unsigned num_entries = length >> PAGE_SHIFT;
1580         intel_gtt_clear_range(first_entry, num_entries);
1581 }
1582
1583 static void i915_ggtt_unbind_vma(struct i915_vma *vma)
1584 {
1585         const unsigned int first = vma->node.start >> PAGE_SHIFT;
1586         const unsigned int size = vma->obj->base.size >> PAGE_SHIFT;
1587
1588         BUG_ON(!i915_is_ggtt(vma->vm));
1589         vma->obj->has_global_gtt_mapping = 0;
1590         intel_gtt_clear_range(first, size);
1591 }
1592
1593 static void ggtt_bind_vma(struct i915_vma *vma,
1594                           enum i915_cache_level cache_level,
1595                           u32 flags)
1596 {
1597         struct drm_device *dev = vma->vm->dev;
1598         struct drm_i915_private *dev_priv = dev->dev_private;
1599         struct drm_i915_gem_object *obj = vma->obj;
1600
1601         /* Currently applicable only to VLV */
1602         if (obj->gt_ro)
1603                 flags |= PTE_READ_ONLY;
1604
1605         /* If there is no aliasing PPGTT, or the caller needs a global mapping,
1606          * or we have a global mapping already but the cacheability flags have
1607          * changed, set the global PTEs.
1608          *
1609          * If there is an aliasing PPGTT it is anecdotally faster, so use that
1610          * instead if none of the above hold true.
1611          *
1612          * NB: A global mapping should only be needed for special regions like
1613          * "gtt mappable", SNB errata, or if specified via special execbuf
1614          * flags. At all other times, the GPU will use the aliasing PPGTT.
1615          */
1616         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1617                 if (!obj->has_global_gtt_mapping ||
1618                     (cache_level != obj->cache_level)) {
1619                         vma->vm->insert_entries(vma->vm, obj->pages,
1620                                                 vma->node.start,
1621                                                 obj->base.size >> PAGE_SHIFT,
1622                                                 cache_level, flags);
1623                         obj->has_global_gtt_mapping = 1;
1624                 }
1625         }
1626
1627         if (dev_priv->mm.aliasing_ppgtt &&
1628             (!obj->has_aliasing_ppgtt_mapping ||
1629              (cache_level != obj->cache_level))) {
1630                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1631                 appgtt->base.insert_entries(&appgtt->base,
1632                                             vma->obj->pages,
1633                                             vma->node.start,
1634                                             obj->base.size >> PAGE_SHIFT,
1635                                             cache_level, flags);
1636                 vma->obj->has_aliasing_ppgtt_mapping = 1;
1637         }
1638 }
1639
1640 static void ggtt_unbind_vma(struct i915_vma *vma)
1641 {
1642         struct drm_device *dev = vma->vm->dev;
1643         struct drm_i915_private *dev_priv = dev->dev_private;
1644         struct drm_i915_gem_object *obj = vma->obj;
1645
1646         if (obj->has_global_gtt_mapping) {
1647                 vma->vm->clear_range(vma->vm,
1648                                      vma->node.start,
1649                                      obj->base.size,
1650                                      true);
1651                 obj->has_global_gtt_mapping = 0;
1652         }
1653
1654         if (obj->has_aliasing_ppgtt_mapping) {
1655                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1656                 appgtt->base.clear_range(&appgtt->base,
1657                                          vma->node.start,
1658                                          obj->base.size,
1659                                          true);
1660                 obj->has_aliasing_ppgtt_mapping = 0;
1661         }
1662 }
1663
1664 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1665 {
1666         struct drm_device *dev = obj->base.dev;
1667         struct drm_i915_private *dev_priv = dev->dev_private;
1668         bool interruptible;
1669
1670         interruptible = do_idling(dev_priv);
1671
1672 #if 0
1673         if (!obj->has_dma_mapping)
1674                 dma_unmap_sg(&dev->pdev->dev,
1675                              obj->pages->sgl, obj->pages->nents,
1676                              PCI_DMA_BIDIRECTIONAL);
1677 #endif
1678
1679         undo_idling(dev_priv, interruptible);
1680 }
1681
1682 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1683                                   unsigned long color,
1684                                   unsigned long *start,
1685                                   unsigned long *end)
1686 {
1687         if (node->color != color)
1688                 *start += 4096;
1689
1690         if (!list_empty(&node->node_list)) {
1691                 node = list_entry(node->node_list.next,
1692                                   struct drm_mm_node,
1693                                   node_list);
1694                 if (node->allocated && node->color != color)
1695                         *end -= 4096;
1696         }
1697 }
1698
1699 void i915_gem_setup_global_gtt(struct drm_device *dev,
1700                                unsigned long start,
1701                                unsigned long mappable_end,
1702                                unsigned long end)
1703 {
1704         /* Let GEM Manage all of the aperture.
1705          *
1706          * However, leave one page at the end still bound to the scratch page.
1707          * There are a number of places where the hardware apparently prefetches
1708          * past the end of the object, and we've seen multiple hangs with the
1709          * GPU head pointer stuck in a batchbuffer bound at the last page of the
1710          * aperture.  One page should be enough to keep any prefetching inside
1711          * of the aperture.
1712          */
1713         struct drm_i915_private *dev_priv = dev->dev_private;
1714         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
1715         unsigned long mappable;
1716         int error;
1717         struct drm_mm_node *entry;
1718         struct drm_i915_gem_object *obj;
1719         unsigned long hole_start, hole_end;
1720
1721         kprintf("MAPPABLE_END VS END %016jx %016jx\n", mappable_end, end);
1722         tsleep(&mappable_end, 0, "DELAY", hz); /* for kprintf */
1723         /*BUG_ON(mappable_end > end);*/
1724
1725         mappable = min(end, mappable_end) - start;
1726
1727         /* Subtract the guard page ... */
1728         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
1729         if (!HAS_LLC(dev))
1730                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
1731
1732         /* Mark any preallocated objects as occupied */
1733         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
1734                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
1735                 int ret;
1736                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
1737                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
1738
1739                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
1740                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
1741                 if (ret)
1742                         DRM_DEBUG_KMS("Reservation failed\n");
1743                 obj->has_global_gtt_mapping = 1;
1744         }
1745
1746         dev_priv->gtt.base.start = start;
1747         dev_priv->gtt.base.total = end - start;
1748
1749         /* Clear any non-preallocated blocks */
1750         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
1751                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
1752                               hole_start, hole_end);
1753                 ggtt_vm->clear_range(ggtt_vm, hole_start,
1754                                      hole_end - hole_start, true);
1755         }
1756
1757         /* XXX: DragonFly-specific */
1758         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
1759         device_printf(dev->dev,
1760             "taking over the fictitious range 0x%lx-0x%lx\n",
1761             dev_priv->gtt.mappable_base + start, dev_priv->gtt.mappable_base + start + mappable);
1762         error = -vm_phys_fictitious_reg_range(dev_priv->gtt.mappable_base + start,
1763             dev_priv->gtt.mappable_base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
1764
1765         /* And finally clear the reserved guard page */
1766         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
1767 }
1768
1769 void i915_gem_init_global_gtt(struct drm_device *dev)
1770 {
1771         struct drm_i915_private *dev_priv = dev->dev_private;
1772         unsigned long gtt_size, mappable_size;
1773
1774         gtt_size = dev_priv->gtt.base.total;
1775         mappable_size = dev_priv->gtt.mappable_end;
1776
1777         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
1778 }
1779
1780 static int setup_scratch_page(struct drm_device *dev)
1781 {
1782         struct drm_i915_private *dev_priv = dev->dev_private;
1783         struct vm_page *page;
1784         dma_addr_t dma_addr;
1785
1786         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
1787         if (page == NULL)
1788                 return -ENOMEM;
1789         get_page(page);
1790         set_pages_uc(page, 1);
1791
1792 #ifdef CONFIG_INTEL_IOMMU
1793         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
1794                                 PCI_DMA_BIDIRECTIONAL);
1795         if (pci_dma_mapping_error(dev->pdev, dma_addr))
1796                 return -EINVAL;
1797 #else
1798         dma_addr = page_to_phys(page);
1799 #endif
1800         dev_priv->gtt.base.scratch.page = page;
1801         dev_priv->gtt.base.scratch.addr = dma_addr;
1802
1803         return 0;
1804 }
1805
1806 #if 0
1807 static void teardown_scratch_page(struct drm_device *dev)
1808 {
1809         struct drm_i915_private *dev_priv = dev->dev_private;
1810         struct vm_page *page = dev_priv->gtt.base.scratch.page;
1811
1812         set_pages_wb(page, 1);
1813         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
1814                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1815         put_page(page);
1816         __free_page(page);
1817 }
1818 #endif
1819
1820 static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
1821 {
1822         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
1823         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
1824         return snb_gmch_ctl << 20;
1825 }
1826
1827 static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1828 {
1829         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
1830         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1831         if (bdw_gmch_ctl)
1832                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1833
1834 #ifdef CONFIG_X86_32
1835         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
1836         if (bdw_gmch_ctl > 4)
1837                 bdw_gmch_ctl = 4;
1838 #endif
1839
1840         return bdw_gmch_ctl << 20;
1841 }
1842
1843 static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
1844 {
1845         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
1846         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
1847
1848         if (gmch_ctrl)
1849                 return 1 << (20 + gmch_ctrl);
1850
1851         return 0;
1852 }
1853
1854 static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
1855 {
1856         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
1857         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
1858         return snb_gmch_ctl << 25; /* 32 MB units */
1859 }
1860
1861 static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
1862 {
1863         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
1864         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
1865         return bdw_gmch_ctl << 25; /* 32 MB units */
1866 }
1867
1868 static size_t chv_get_stolen_size(u16 gmch_ctrl)
1869 {
1870         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
1871         gmch_ctrl &= SNB_GMCH_GMS_MASK;
1872
1873         /*
1874          * 0x0  to 0x10: 32MB increments starting at 0MB
1875          * 0x11 to 0x16: 4MB increments starting at 8MB
1876          * 0x17 to 0x1d: 4MB increments start at 36MB
1877          */
1878         if (gmch_ctrl < 0x11)
1879                 return gmch_ctrl << 25;
1880         else if (gmch_ctrl < 0x17)
1881                 return (gmch_ctrl - 0x11 + 2) << 22;
1882         else
1883                 return (gmch_ctrl - 0x17 + 9) << 22;
1884 }
1885
1886 static int ggtt_probe_common(struct drm_device *dev,
1887                              size_t gtt_size)
1888 {
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         phys_addr_t gtt_phys_addr;
1891         int ret;
1892
1893         /* For Modern GENs the PTEs and register space are split in the BAR */
1894         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
1895                 (pci_resource_len(dev->pdev, 0) / 2);
1896
1897         kprintf("gtt_probe_common: gtt_phys_addr=0x%lx\n", gtt_phys_addr);
1898         dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
1899         if (!dev_priv->gtt.gsm) {
1900                 DRM_ERROR("Failed to map the gtt page table\n");
1901                 return -ENOMEM;
1902         }
1903
1904         ret = setup_scratch_page(dev);
1905         if (ret) {
1906                 DRM_ERROR("Scratch setup failed\n");
1907                 /* iounmap will also get called at remove, but meh */
1908 #if 0
1909                 iounmap(dev_priv->gtt.gsm);
1910 #endif
1911         }
1912
1913         return ret;
1914 }
1915
1916 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
1917  * bits. When using advanced contexts each context stores its own PAT, but
1918  * writing this data shouldn't be harmful even in those cases. */
1919 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
1920 {
1921         uint64_t pat;
1922
1923         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
1924               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
1925               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
1926               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
1927               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
1928               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
1929               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
1930               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
1931
1932         if (!USES_PPGTT(dev_priv->dev))
1933                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
1934                  * so RTL will always use the value corresponding to
1935                  * pat_sel = 000".
1936                  * So let's disable cache for GGTT to avoid screen corruptions.
1937                  * MOCS still can be used though.
1938                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
1939                  * before this patch, i.e. the same uncached + snooping access
1940                  * like on gen6/7 seems to be in effect.
1941                  * - So this just fixes blitter/render access. Again it looks
1942                  * like it's not just uncached access, but uncached + snooping.
1943                  * So we can still hold onto all our assumptions wrt cpu
1944                  * clflushing on LLC machines.
1945                  */
1946                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
1947
1948         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
1949          * write would work. */
1950         I915_WRITE(GEN8_PRIVATE_PAT, pat);
1951         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1952 }
1953
1954 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
1955 {
1956         uint64_t pat;
1957
1958         /*
1959          * Map WB on BDW to snooped on CHV.
1960          *
1961          * Only the snoop bit has meaning for CHV, the rest is
1962          * ignored.
1963          *
1964          * Note that the harware enforces snooping for all page
1965          * table accesses. The snoop bit is actually ignored for
1966          * PDEs.
1967          */
1968         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
1969               GEN8_PPAT(1, 0) |
1970               GEN8_PPAT(2, 0) |
1971               GEN8_PPAT(3, 0) |
1972               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
1973               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
1974               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
1975               GEN8_PPAT(7, CHV_PPAT_SNOOP);
1976
1977         I915_WRITE(GEN8_PRIVATE_PAT, pat);
1978         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
1979 }
1980
1981 static int gen8_gmch_probe(struct drm_device *dev,
1982                            size_t *gtt_total,
1983                            size_t *stolen,
1984                            phys_addr_t *mappable_base,
1985                            unsigned long *mappable_end)
1986 {
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         unsigned int gtt_size;
1989         u16 snb_gmch_ctl;
1990         int ret;
1991
1992         /* TODO: We're not aware of mappable constraints on gen8 yet */
1993         *mappable_base = pci_resource_start(dev->pdev, 2);
1994         *mappable_end = pci_resource_len(dev->pdev, 2);
1995
1996 #if 0
1997         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
1998                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
1999 #endif
2000
2001         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2002
2003         if (IS_CHERRYVIEW(dev)) {
2004                 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2005                 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2006         } else {
2007                 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2008                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2009         }
2010
2011         *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT;
2012
2013         if (IS_CHERRYVIEW(dev))
2014                 chv_setup_private_ppat(dev_priv);
2015         else
2016                 bdw_setup_private_ppat(dev_priv);
2017
2018         ret = ggtt_probe_common(dev, gtt_size);
2019
2020         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2021         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2022
2023         return ret;
2024 }
2025
2026 static int gen6_gmch_probe(struct drm_device *dev,
2027                            size_t *gtt_total,
2028                            size_t *stolen,
2029                            phys_addr_t *mappable_base,
2030                            unsigned long *mappable_end)
2031 {
2032         struct drm_i915_private *dev_priv = dev->dev_private;
2033         unsigned int gtt_size;
2034         u16 snb_gmch_ctl;
2035         int ret;
2036
2037         *mappable_base = pci_resource_start(dev->pdev, 2);
2038         *mappable_end = pci_resource_len(dev->pdev, 2);
2039
2040         /* 64/512MB is the current min/max we actually know of, but this is just
2041          * a coarse sanity check.
2042          */
2043         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2044                 DRM_ERROR("Unknown GMADR size (%lx)\n",
2045                           dev_priv->gtt.mappable_end);
2046                 return -ENXIO;
2047         }
2048
2049 #if 0
2050         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2051                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2052 #endif
2053         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2054
2055         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2056
2057         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2058         *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT;
2059
2060         ret = ggtt_probe_common(dev, gtt_size);
2061
2062         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2063         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2064
2065         return ret;
2066 }
2067
2068 static void gen6_gmch_remove(struct i915_address_space *vm)
2069 {
2070 #if 0
2071         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2072
2073         if (drm_mm_initialized(&vm->mm)) {
2074                 drm_mm_takedown(&vm->mm);
2075                 list_del(&vm->global_link);
2076         }
2077         iounmap(gtt->gsm);
2078         teardown_scratch_page(vm->dev);
2079 #endif
2080 }
2081
2082 static int i915_gmch_probe(struct drm_device *dev,
2083                            size_t *gtt_total,
2084                            size_t *stolen,
2085                            phys_addr_t *mappable_base,
2086                            unsigned long *mappable_end)
2087 {
2088         struct drm_i915_private *dev_priv = dev->dev_private;
2089 #if 0
2090         int ret;
2091
2092         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2093         if (!ret) {
2094                 DRM_ERROR("failed to set up gmch\n");
2095                 return -EIO;
2096         }
2097 #endif
2098
2099         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2100
2101         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2102         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2103
2104         if (unlikely(dev_priv->gtt.do_idle_maps))
2105                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2106
2107         return 0;
2108 }
2109
2110 static void i915_gmch_remove(struct i915_address_space *vm)
2111 {
2112         if (drm_mm_initialized(&vm->mm)) {
2113                 drm_mm_takedown(&vm->mm);
2114                 list_del(&vm->global_link);
2115         }
2116 #if 0
2117         intel_gmch_remove();
2118 #endif
2119 }
2120
2121 int i915_gem_gtt_init(struct drm_device *dev)
2122 {
2123         struct drm_i915_private *dev_priv = dev->dev_private;
2124         struct i915_gtt *gtt = &dev_priv->gtt;
2125         int ret;
2126
2127         if (INTEL_INFO(dev)->gen <= 5) {
2128                 gtt->gtt_probe = i915_gmch_probe;
2129                 gtt->base.cleanup = i915_gmch_remove;
2130         } else if (INTEL_INFO(dev)->gen < 8) {
2131                 gtt->gtt_probe = gen6_gmch_probe;
2132                 gtt->base.cleanup = gen6_gmch_remove;
2133                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2134                         gtt->base.pte_encode = iris_pte_encode;
2135                 else if (IS_HASWELL(dev))
2136                         gtt->base.pte_encode = hsw_pte_encode;
2137                 else if (IS_VALLEYVIEW(dev))
2138                         gtt->base.pte_encode = byt_pte_encode;
2139                 else if (INTEL_INFO(dev)->gen >= 7)
2140                         gtt->base.pte_encode = ivb_pte_encode;
2141                 else
2142                         gtt->base.pte_encode = snb_pte_encode;
2143         } else {
2144                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2145                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2146         }
2147
2148         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2149                              &gtt->mappable_base, &gtt->mappable_end);
2150         if (ret)
2151                 return ret;
2152
2153         gtt->base.dev = dev;
2154
2155         /* GMADR is the PCI mmio aperture into the global GTT. */
2156         DRM_INFO("Memory usable by graphics device = %zdM\n",
2157                  gtt->base.total >> 20);
2158         DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20);
2159         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2160 #ifdef CONFIG_INTEL_IOMMU
2161         if (intel_iommu_gfx_mapped)
2162                 DRM_INFO("VT-d active for gfx access\n");
2163 #endif
2164         /*
2165          * i915.enable_ppgtt is read-only, so do an early pass to validate the
2166          * user's requested state against the hardware/driver capabilities.  We
2167          * do this now so that we can print out any log messages once rather
2168          * than every time we check intel_enable_ppgtt().
2169          */
2170         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2171         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2172
2173         return 0;
2174 }
2175
2176 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2177                                               struct i915_address_space *vm)
2178 {
2179         struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
2180         if (vma == NULL)
2181                 return ERR_PTR(-ENOMEM);
2182
2183         INIT_LIST_HEAD(&vma->vma_link);
2184         INIT_LIST_HEAD(&vma->mm_list);
2185         INIT_LIST_HEAD(&vma->exec_list);
2186         vma->vm = vm;
2187         vma->obj = obj;
2188
2189         switch (INTEL_INFO(vm->dev)->gen) {
2190         case 8:
2191         case 7:
2192         case 6:
2193                 if (i915_is_ggtt(vm)) {
2194                         vma->unbind_vma = ggtt_unbind_vma;
2195                         vma->bind_vma = ggtt_bind_vma;
2196                 } else {
2197                         vma->unbind_vma = ppgtt_unbind_vma;
2198                         vma->bind_vma = ppgtt_bind_vma;
2199                 }
2200                 break;
2201         case 5:
2202         case 4:
2203         case 3:
2204         case 2:
2205                 BUG_ON(!i915_is_ggtt(vm));
2206                 vma->unbind_vma = i915_ggtt_unbind_vma;
2207                 vma->bind_vma = i915_ggtt_bind_vma;
2208                 break;
2209         default:
2210                 BUG();
2211         }
2212
2213         /* Keep GGTT vmas first to make debug easier */
2214         if (i915_is_ggtt(vm))
2215                 list_add(&vma->vma_link, &obj->vma_list);
2216         else
2217                 list_add_tail(&vma->vma_link, &obj->vma_list);
2218
2219         return vma;
2220 }
2221
2222 struct i915_vma *
2223 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2224                                   struct i915_address_space *vm)
2225 {
2226         struct i915_vma *vma;
2227
2228         vma = i915_gem_obj_to_vma(obj, vm);
2229         if (!vma)
2230                 vma = __i915_gem_vma_create(obj, vm);
2231
2232         return vma;
2233 }