1 /* $OpenBSD: if_skreg.h,v 1.10 2003/08/12 05:23:06 nate Exp $ */
4 * Copyright (c) 1997, 1998, 1999, 2000
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/pci/if_skreg.h,v 1.8.2.1 2000/04/27 14:48:07 wpaul Exp $
35 * $DragonFly: src/sys/dev/netif/sk/if_skreg.h,v 1.11 2006/10/16 14:12:34 sephe Exp $
39 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
41 * Permission to use, copy, modify, and distribute this software for any
42 * purpose with or without fee is hereby granted, provided that the above
43 * copyright notice and this permission notice appear in all copies.
45 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
46 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
47 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
48 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
49 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
50 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
51 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
54 /* Values to keep the different chip revisions apart */
59 * SysKonnect PCI vendor ID
61 #define VENDORID_SK 0x1148
64 * Marvell PCI vendor ID
66 #define VENDORID_MARVELL 0x11AB
69 * SK-NET gigabit ethernet device IDs
71 #define DEVICEID_SK_V1 0x4300
72 #define DEVICEID_SK_V2 0x4320
77 #define VENDORID_3COM 0x10b7
80 * 3Com gigabit ethernet device ID
82 #define DEVICEID_3COM_3C940 0x1700
85 * Linksys PCI vendor ID
87 #define VENDORID_LINKSYS 0x1737
90 * Linksys gigabit ethernet device ID
92 #define DEVICEID_LINKSYS_EG1032 0x1032
95 * Linksys gigabit ethernet rev 2 sub-device ID
97 #define SUBDEVICEID_LINKSYS_EG1032_REV2 0x0015
100 * D-Link PCI vendor ID
102 #define VENDORID_DLINK 0x1186
105 * D-Link gigabit ethernet device ID
107 #define DEVICEID_DLINK_DGE530T 0x4c00
110 * GEnesis registers. The GEnesis chip has a 256-byte I/O window
111 * but internally it has a 16K register space. This 16K space is
112 * divided into 128-byte blocks. The first 128 bytes of the I/O
113 * window represent the first block, which is permanently mapped
114 * at the start of the window. The other 127 blocks can be mapped
115 * to the second 128 bytes of the I/O window by setting the desired
116 * block value in the RAP register in block 0. Not all of the 127
117 * blocks are actually used. Most registers are 32 bits wide, but
118 * there are a few 16-bit and 8-bit ones as well.
122 /* Start of remappable register window. */
123 #define SK_WIN_BASE 0x0080
125 /* Size of a window */
126 #define SK_WIN_LEN 0x80
128 #define SK_WIN_MASK 0x3F80
129 #define SK_REG_MASK 0x7F
131 /* Compute the window of a given register (for the RAP register) */
132 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN)
134 /* Compute the relative offset of a register within the window */
135 #define SK_REG(reg) ((reg) & SK_REG_MASK)
141 * Compute offset of port-specific register. Since there are two
142 * ports, there are two of some GEnesis modules (e.g. two sets of
143 * DMA queues, two sets of FIFO control registers, etc...). Normally,
144 * the block for port 0 is at offset 0x0 and the block for port 1 is
145 * at offset 0x80 (i.e. the next page over). However for the transmit
146 * BMUs and RAMbuffers, there are two blocks for each port: one for
147 * the sync transmit queue and one for the async queue (which we don't
148 * use). However instead of ordering them like this:
149 * TX sync 1 / TX sync 2 / TX async 1 / TX async 2
150 * SysKonnect has instead ordered them like this:
151 * TX sync 1 / TX async 1 / TX sync 2 / TX async 2
152 * This means that when referencing the TX BMU and RAMbuffer registers,
153 * we have to double the block offset (0x80 * 2) in order to reach the
154 * second queue. This prevents us from using the same formula
155 * (sk_port * 0x80) to compute the offsets for all of the port-specific
156 * blocks: we need an extra offset for the BMU and RAMbuffer registers.
157 * The simplest thing is to provide an extra argument to these macros:
158 * the 'skip' parameter. The 'skip' value is the number of extra pages
159 * for skip when computing the port0/port1 offsets. For most registers,
160 * the skip value is 0; for the BMU and RAMbuffer registers, it's 1.
162 #define SK_IF_READ_4(sc_if, skip, reg) \
163 sk_win_read_4(sc_if->sk_softc, reg + \
164 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
165 #define SK_IF_READ_2(sc_if, skip, reg) \
166 sk_win_read_2(sc_if->sk_softc, reg + \
167 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
168 #define SK_IF_READ_1(sc_if, skip, reg) \
169 sk_win_read_1(sc_if->sk_softc, reg + \
170 ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
172 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \
173 sk_win_write_4(sc_if->sk_softc, \
174 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
175 #define SK_IF_WRITE_2(sc_if, skip, reg, val) \
176 sk_win_write_2(sc_if->sk_softc, \
177 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
178 #define SK_IF_WRITE_1(sc_if, skip, reg, val) \
179 sk_win_write_1(sc_if->sk_softc, \
180 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
182 /* Block 0 registers, permanently mapped at iobase. */
183 #define SK_RAP 0x0000
184 #define SK_CSR 0x0004
185 #define SK_LED 0x0006
186 #define SK_ISR 0x0008 /* interrupt source */
187 #define SK_IMR 0x000C /* interrupt mask */
188 #define SK_IESR 0x0010 /* interrupt hardware error source */
189 #define SK_IEMR 0x0014 /* interrupt hardware error mask */
190 #define SK_ISSR 0x0018 /* special interrupt source */
191 #define SK_XM_IMR0 0x0020
192 #define SK_XM_ISR0 0x0028
193 #define SK_XM_PHYADDR0 0x0030
194 #define SK_XM_PHYDATA0 0x0034
195 #define SK_XM_IMR1 0x0040
196 #define SK_XM_ISR1 0x0048
197 #define SK_XM_PHYADDR1 0x0050
198 #define SK_XM_PHYDATA1 0x0054
199 #define SK_BMU_RX_CSR0 0x0060
200 #define SK_BMU_RX_CSR1 0x0064
201 #define SK_BMU_TXS_CSR0 0x0068
202 #define SK_BMU_TXA_CSR0 0x006C
203 #define SK_BMU_TXS_CSR1 0x0070
204 #define SK_BMU_TXA_CSR1 0x0074
206 /* SK_CSR register */
207 #define SK_CSR_SW_RESET 0x0001
208 #define SK_CSR_SW_UNRESET 0x0002
209 #define SK_CSR_MASTER_RESET 0x0004
210 #define SK_CSR_MASTER_UNRESET 0x0008
211 #define SK_CSR_MASTER_STOP 0x0010
212 #define SK_CSR_MASTER_DONE 0x0020
213 #define SK_CSR_SW_IRQ_CLEAR 0x0040
214 #define SK_CSR_SW_IRQ_SET 0x0080
215 #define SK_CSR_SLOTSIZE 0x0100 /* 1 == 64 bits, 0 == 32 */
216 #define SK_CSR_BUSCLOCK 0x0200 /* 1 == 33/66 Mhz, = 33 */
218 /* SK_LED register */
219 #define SK_LED_GREEN_OFF 0x01
220 #define SK_LED_GREEN_ON 0x02
222 /* SK_ISR register */
223 #define SK_ISR_TX2_AS_CHECK 0x00000001
224 #define SK_ISR_TX2_AS_EOF 0x00000002
225 #define SK_ISR_TX2_AS_EOB 0x00000004
226 #define SK_ISR_TX2_S_CHECK 0x00000008
227 #define SK_ISR_TX2_S_EOF 0x00000010
228 #define SK_ISR_TX2_S_EOB 0x00000020
229 #define SK_ISR_TX1_AS_CHECK 0x00000040
230 #define SK_ISR_TX1_AS_EOF 0x00000080
231 #define SK_ISR_TX1_AS_EOB 0x00000100
232 #define SK_ISR_TX1_S_CHECK 0x00000200
233 #define SK_ISR_TX1_S_EOF 0x00000400
234 #define SK_ISR_TX1_S_EOB 0x00000800
235 #define SK_ISR_RX2_CHECK 0x00001000
236 #define SK_ISR_RX2_EOF 0x00002000
237 #define SK_ISR_RX2_EOB 0x00004000
238 #define SK_ISR_RX1_CHECK 0x00008000
239 #define SK_ISR_RX1_EOF 0x00010000
240 #define SK_ISR_RX1_EOB 0x00020000
241 #define SK_ISR_LINK2_OFLOW 0x00040000
242 #define SK_ISR_MAC2 0x00080000
243 #define SK_ISR_LINK1_OFLOW 0x00100000
244 #define SK_ISR_MAC1 0x00200000
245 #define SK_ISR_TIMER 0x00400000
246 #define SK_ISR_EXTERNAL_REG 0x00800000
247 #define SK_ISR_SW 0x01000000
248 #define SK_ISR_I2C_RDY 0x02000000
249 #define SK_ISR_TX2_TIMEO 0x04000000
250 #define SK_ISR_TX1_TIMEO 0x08000000
251 #define SK_ISR_RX2_TIMEO 0x10000000
252 #define SK_ISR_RX1_TIMEO 0x20000000
253 #define SK_ISR_RSVD 0x40000000
254 #define SK_ISR_HWERR 0x80000000
256 /* SK_IMR register */
257 #define SK_IMR_TX2_AS_CHECK 0x00000001
258 #define SK_IMR_TX2_AS_EOF 0x00000002
259 #define SK_IMR_TX2_AS_EOB 0x00000004
260 #define SK_IMR_TX2_S_CHECK 0x00000008
261 #define SK_IMR_TX2_S_EOF 0x00000010
262 #define SK_IMR_TX2_S_EOB 0x00000020
263 #define SK_IMR_TX1_AS_CHECK 0x00000040
264 #define SK_IMR_TX1_AS_EOF 0x00000080
265 #define SK_IMR_TX1_AS_EOB 0x00000100
266 #define SK_IMR_TX1_S_CHECK 0x00000200
267 #define SK_IMR_TX1_S_EOF 0x00000400
268 #define SK_IMR_TX1_S_EOB 0x00000800
269 #define SK_IMR_RX2_CHECK 0x00001000
270 #define SK_IMR_RX2_EOF 0x00002000
271 #define SK_IMR_RX2_EOB 0x00004000
272 #define SK_IMR_RX1_CHECK 0x00008000
273 #define SK_IMR_RX1_EOF 0x00010000
274 #define SK_IMR_RX1_EOB 0x00020000
275 #define SK_IMR_LINK2_OFLOW 0x00040000
276 #define SK_IMR_MAC2 0x00080000
277 #define SK_IMR_LINK1_OFLOW 0x00100000
278 #define SK_IMR_MAC1 0x00200000
279 #define SK_IMR_TIMER 0x00400000
280 #define SK_IMR_EXTERNAL_REG 0x00800000
281 #define SK_IMR_SW 0x01000000
282 #define SK_IMR_I2C_RDY 0x02000000
283 #define SK_IMR_TX2_TIMEO 0x04000000
284 #define SK_IMR_TX1_TIMEO 0x08000000
285 #define SK_IMR_RX2_TIMEO 0x10000000
286 #define SK_IMR_RX1_TIMEO 0x20000000
287 #define SK_IMR_RSVD 0x40000000
288 #define SK_IMR_HWERR 0x80000000
291 (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1)
294 (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2)
296 /* SK_IESR register */
297 #define SK_IESR_PAR_RX2 0x00000001
298 #define SK_IESR_PAR_RX1 0x00000002
299 #define SK_IESR_PAR_MAC2 0x00000004
300 #define SK_IESR_PAR_MAC1 0x00000008
301 #define SK_IESR_PAR_WR_RAM 0x00000010
302 #define SK_IESR_PAR_RD_RAM 0x00000020
303 #define SK_IESR_NO_TSTAMP_MAC2 0x00000040
304 #define SK_IESR_NO_TSTAMO_MAC1 0x00000080
305 #define SK_IESR_NO_STS_MAC2 0x00000100
306 #define SK_IESR_NO_STS_MAC1 0x00000200
307 #define SK_IESR_IRQ_STS 0x00000400
308 #define SK_IESR_MASTERERR 0x00000800
310 /* SK_IEMR register */
311 #define SK_IEMR_PAR_RX2 0x00000001
312 #define SK_IEMR_PAR_RX1 0x00000002
313 #define SK_IEMR_PAR_MAC2 0x00000004
314 #define SK_IEMR_PAR_MAC1 0x00000008
315 #define SK_IEMR_PAR_WR_RAM 0x00000010
316 #define SK_IEMR_PAR_RD_RAM 0x00000020
317 #define SK_IEMR_NO_TSTAMP_MAC2 0x00000040
318 #define SK_IEMR_NO_TSTAMO_MAC1 0x00000080
319 #define SK_IEMR_NO_STS_MAC2 0x00000100
320 #define SK_IEMR_NO_STS_MAC1 0x00000200
321 #define SK_IEMR_IRQ_STS 0x00000400
322 #define SK_IEMR_MASTERERR 0x00000800
325 #define SK_MAC0_0 0x0100
326 #define SK_MAC0_1 0x0104
327 #define SK_MAC1_0 0x0108
328 #define SK_MAC1_1 0x010C
329 #define SK_MAC2_0 0x0110
330 #define SK_MAC2_1 0x0114
331 #define SK_CONNTYPE 0x0118
332 #define SK_PMDTYPE 0x0119
333 #define SK_CONFIG 0x011A
334 #define SK_CHIPVER 0x011B
335 #define SK_EPROM0 0x011C
336 #define SK_EPROM1 0x011D
337 #define SK_EPROM2 0x011E
338 #define SK_EPROM3 0x011F
339 #define SK_EP_ADDR 0x0120
340 #define SK_EP_DATA 0x0124
341 #define SK_EP_LOADCTL 0x0128
342 #define SK_EP_LOADTST 0x0129
343 #define SK_TIMERINIT 0x0130
344 #define SK_TIMER 0x0134
345 #define SK_TIMERCTL 0x0138
346 #define SK_TIMERTST 0x0139
347 #define SK_IMTIMERINIT 0x0140
348 #define SK_IMTIMER 0x0144
349 #define SK_IMTIMERCTL 0x0148
350 #define SK_IMTIMERTST 0x0149
351 #define SK_IMMR 0x014C
352 #define SK_IHWEMR 0x0150
353 #define SK_TESTCTL1 0x0158
354 #define SK_TESTCTL2 0x0159
355 #define SK_GPIO 0x015C
356 #define SK_I2CHWCTL 0x0160
357 #define SK_I2CHWDATA 0x0164
358 #define SK_I2CHWIRQ 0x0168
359 #define SK_I2CSW 0x016C
360 #define SK_BLNKINIT 0x0170
361 #define SK_BLNKCOUNT 0x0174
362 #define SK_BLNKCTL 0x0178
363 #define SK_BLNKSTS 0x0179
364 #define SK_BLNKTST 0x017A
366 #define SK_IMCTL_STOP 0x02
367 #define SK_IMCTL_START 0x04
369 #define SK_IMTIMER_TICKS 54
370 #define SK_IM_USECS(x) ((x) * SK_IMTIMER_TICKS)
373 * The SK_EPROM0 register contains a byte that describes the
374 * amount of SRAM mounted on the NIC. The value also tells if
375 * the chips are 64K or 128K. This affects the RAMbuffer address
376 * offset that we need to use.
378 #define SK_RAMSIZE_512K_64 0x1
379 #define SK_RAMSIZE_1024K_128 0x2
380 #define SK_RAMSIZE_1024K_64 0x3
381 #define SK_RAMSIZE_2048K_128 0x4
383 #define SK_RBOFF_0 0x0
384 #define SK_RBOFF_80000 0x80000
387 * SK_EEPROM1 contains the PHY type, which may be XMAC for
388 * fiber-based cards or BCOM for 1000baseT cards with a Broadcom
391 #define SK_PHYTYPE_XMAC 0 /* integeated XMAC II PHY */
392 #define SK_PHYTYPE_BCOM 1 /* Broadcom BCM5400 */
393 #define SK_PHYTYPE_LONE 2 /* Level One LXT1000 */
394 #define SK_PHYTYPE_NAT 3 /* National DP83891 */
395 #define SK_PHYTYPE_MARV_COPPER 4 /* Marvell 88E1011S */
396 #define SK_PHYTYPE_MARV_FIBER 5 /* Marvell 88E1011S (fiber) */
401 #define SK_PHYADDR_XMAC 0x0
402 #define SK_PHYADDR_BCOM 0x1
403 #define SK_PHYADDR_LONE 0x3
404 #define SK_PHYADDR_NAT 0x0
405 #define SK_PHYADDR_MARV 0x0
407 #define SK_CONFIG_SINGLEMAC 0x01
408 #define SK_CONFIG_DIS_DSL_CLK 0x02
410 #define SK_PMD_1000BASELX 0x4C
411 #define SK_PMD_1000BASESX 0x53
412 #define SK_PMD_1000BASECX 0x43
413 #define SK_PMD_1000BASETX 0x54
416 #define SK_GPIO_DAT0 0x00000001
417 #define SK_GPIO_DAT1 0x00000002
418 #define SK_GPIO_DAT2 0x00000004
419 #define SK_GPIO_DAT3 0x00000008
420 #define SK_GPIO_DAT4 0x00000010
421 #define SK_GPIO_DAT5 0x00000020
422 #define SK_GPIO_DAT6 0x00000040
423 #define SK_GPIO_DAT7 0x00000080
424 #define SK_GPIO_DAT8 0x00000100
425 #define SK_GPIO_DAT9 0x00000200
426 #define SK_GPIO_DIR0 0x00010000
427 #define SK_GPIO_DIR1 0x00020000
428 #define SK_GPIO_DIR2 0x00040000
429 #define SK_GPIO_DIR3 0x00080000
430 #define SK_GPIO_DIR4 0x00100000
431 #define SK_GPIO_DIR5 0x00200000
432 #define SK_GPIO_DIR6 0x00400000
433 #define SK_GPIO_DIR7 0x00800000
434 #define SK_GPIO_DIR8 0x01000000
435 #define SK_GPIO_DIR9 0x02000000
437 /* Block 3 Ram interface and MAC arbiter registers */
438 #define SK_RAMADDR 0x0180
439 #define SK_RAMDATA0 0x0184
440 #define SK_RAMDATA1 0x0188
441 #define SK_TO0 0x0190
442 #define SK_TO1 0x0191
443 #define SK_TO2 0x0192
444 #define SK_TO3 0x0193
445 #define SK_TO4 0x0194
446 #define SK_TO5 0x0195
447 #define SK_TO6 0x0196
448 #define SK_TO7 0x0197
449 #define SK_TO8 0x0198
450 #define SK_TO9 0x0199
451 #define SK_TO10 0x019A
452 #define SK_TO11 0x019B
453 #define SK_RITIMEO_TMR 0x019C
454 #define SK_RAMCTL 0x01A0
455 #define SK_RITIMER_TST 0x01A2
457 #define SK_RAMCTL_RESET 0x0001
458 #define SK_RAMCTL_UNRESET 0x0002
459 #define SK_RAMCTL_CLR_IRQ_WPAR 0x0100
460 #define SK_RAMCTL_CLR_IRQ_RPAR 0x0200
462 /* Mac arbiter registers */
463 #define SK_MINIT_RX1 0x01B0
464 #define SK_MINIT_RX2 0x01B1
465 #define SK_MINIT_TX1 0x01B2
466 #define SK_MINIT_TX2 0x01B3
467 #define SK_MTIMEO_RX1 0x01B4
468 #define SK_MTIMEO_RX2 0x01B5
469 #define SK_MTIMEO_TX1 0x01B6
470 #define SK_MTIEMO_TX2 0x01B7
471 #define SK_MACARB_CTL 0x01B8
472 #define SK_MTIMER_TST 0x01BA
473 #define SK_RCINIT_RX1 0x01C0
474 #define SK_RCINIT_RX2 0x01C1
475 #define SK_RCINIT_TX1 0x01C2
476 #define SK_RCINIT_TX2 0x01C3
477 #define SK_RCTIMEO_RX1 0x01C4
478 #define SK_RCTIMEO_RX2 0x01C5
479 #define SK_RCTIMEO_TX1 0x01C6
480 #define SK_RCTIMEO_TX2 0x01C7
481 #define SK_RECOVERY_CTL 0x01C8
482 #define SK_RCTIMER_TST 0x01CA
484 /* Packet arbiter registers */
485 #define SK_RXPA1_TINIT 0x01D0
486 #define SK_RXPA2_TINIT 0x01D4
487 #define SK_TXPA1_TINIT 0x01D8
488 #define SK_TXPA2_TINIT 0x01DC
489 #define SK_RXPA1_TIMEO 0x01E0
490 #define SK_RXPA2_TIMEO 0x01E4
491 #define SK_TXPA1_TIMEO 0x01E8
492 #define SK_TXPA2_TIMEO 0x01EC
493 #define SK_PKTARB_CTL 0x01F0
494 #define SK_PKTATB_TST 0x01F2
496 #define SK_PKTARB_TIMEOUT 0x2000
498 #define SK_PKTARBCTL_RESET 0x0001
499 #define SK_PKTARBCTL_UNRESET 0x0002
500 #define SK_PKTARBCTL_RXTO1_OFF 0x0004
501 #define SK_PKTARBCTL_RXTO1_ON 0x0008
502 #define SK_PKTARBCTL_RXTO2_OFF 0x0010
503 #define SK_PKTARBCTL_RXTO2_ON 0x0020
504 #define SK_PKTARBCTL_TXTO1_OFF 0x0040
505 #define SK_PKTARBCTL_TXTO1_ON 0x0080
506 #define SK_PKTARBCTL_TXTO2_OFF 0x0100
507 #define SK_PKTARBCTL_TXTO2_ON 0x0200
508 #define SK_PKTARBCTL_CLR_IRQ_RXTO1 0x0400
509 #define SK_PKTARBCTL_CLR_IRQ_RXTO2 0x0800
510 #define SK_PKTARBCTL_CLR_IRQ_TXTO1 0x1000
511 #define SK_PKTARBCTL_CLR_IRQ_TXTO2 0x2000
513 #define SK_MINIT_XMAC_B2 54
514 #define SK_MINIT_XMAC_C1 63
516 #define SK_MACARBCTL_RESET 0x0001
517 #define SK_MACARBCTL_UNRESET 0x0002
518 #define SK_MACARBCTL_FASTOE_OFF 0x0004
519 #define SK_MACARBCRL_FASTOE_ON 0x0008
521 #define SK_RCINIT_XMAC_B2 54
522 #define SK_RCINIT_XMAC_C1 0
524 #define SK_RECOVERYCTL_RX1_OFF 0x0001
525 #define SK_RECOVERYCTL_RX1_ON 0x0002
526 #define SK_RECOVERYCTL_RX2_OFF 0x0004
527 #define SK_RECOVERYCTL_RX2_ON 0x0008
528 #define SK_RECOVERYCTL_TX1_OFF 0x0010
529 #define SK_RECOVERYCTL_TX1_ON 0x0020
530 #define SK_RECOVERYCTL_TX2_OFF 0x0040
531 #define SK_RECOVERYCTL_TX2_ON 0x0080
533 #define SK_RECOVERY_XMAC_B2 \
534 (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON| \
535 SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON)
537 #define SK_RECOVERY_XMAC_C1 \
538 (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \
539 SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF)
541 /* Block 4 -- TX Arbiter MAC 1 */
542 #define SK_TXAR1_TIMERINIT 0x0200
543 #define SK_TXAR1_TIMERVAL 0x0204
544 #define SK_TXAR1_LIMITINIT 0x0208
545 #define SK_TXAR1_LIMITCNT 0x020C
546 #define SK_TXAR1_COUNTERCTL 0x0210
547 #define SK_TXAR1_COUNTERTST 0x0212
548 #define SK_TXAR1_COUNTERSTS 0x0212
550 /* Block 5 -- TX Arbiter MAC 2 */
551 #define SK_TXAR2_TIMERINIT 0x0280
552 #define SK_TXAR2_TIMERVAL 0x0284
553 #define SK_TXAR2_LIMITINIT 0x0288
554 #define SK_TXAR2_LIMITCNT 0x028C
555 #define SK_TXAR2_COUNTERCTL 0x0290
556 #define SK_TXAR2_COUNTERTST 0x0291
557 #define SK_TXAR2_COUNTERSTS 0x0292
559 #define SK_TXARCTL_OFF 0x01
560 #define SK_TXARCTL_ON 0x02
561 #define SK_TXARCTL_RATECTL_OFF 0x04
562 #define SK_TXARCTL_RATECTL_ON 0x08
563 #define SK_TXARCTL_ALLOC_OFF 0x10
564 #define SK_TXARCTL_ALLOC_ON 0x20
565 #define SK_TXARCTL_FSYNC_OFF 0x40
566 #define SK_TXARCTL_FSYNC_ON 0x80
568 /* Block 6 -- External registers */
569 #define SK_EXTREG_BASE 0x300
570 #define SK_EXTREG_END 0x37C
572 /* Block 7 -- PCI config registers */
573 #define SK_PCI_BASE 0x0380
574 #define SK_PCI_END 0x03FC
576 /* Compute offset of mirrored PCI register */
577 #define SK_PCI_REG(reg) ((reg) + SK_PCI_BASE)
579 /* Block 8 -- RX queue 1 */
580 #define SK_RXQ1_BUFCNT 0x0400
581 #define SK_RXQ1_BUFCTL 0x0402
582 #define SK_RXQ1_NEXTDESC 0x0404
583 #define SK_RXQ1_RXBUF_LO 0x0408
584 #define SK_RXQ1_RXBUF_HI 0x040C
585 #define SK_RXQ1_RXSTAT 0x0410
586 #define SK_RXQ1_TIMESTAMP 0x0414
587 #define SK_RXQ1_CSUM1 0x0418
588 #define SK_RXQ1_CSUM2 0x041A
589 #define SK_RXQ1_CSUM1_START 0x041C
590 #define SK_RXQ1_CSUM2_START 0x041E
591 #define SK_RXQ1_CURADDR_LO 0x0420
592 #define SK_RXQ1_CURADDR_HI 0x0424
593 #define SK_RXQ1_CURCNT_LO 0x0428
594 #define SK_RXQ1_CURCNT_HI 0x042C
595 #define SK_RXQ1_CURBYTES 0x0430
596 #define SK_RXQ1_BMU_CSR 0x0434
597 #define SK_RXQ1_WATERMARK 0x0438
598 #define SK_RXQ1_FLAG 0x043A
599 #define SK_RXQ1_TEST1 0x043C
600 #define SK_RXQ1_TEST2 0x0440
601 #define SK_RXQ1_TEST3 0x0444
603 /* Block 9 -- RX queue 2 */
604 #define SK_RXQ2_BUFCNT 0x0480
605 #define SK_RXQ2_BUFCTL 0x0482
606 #define SK_RXQ2_NEXTDESC 0x0484
607 #define SK_RXQ2_RXBUF_LO 0x0488
608 #define SK_RXQ2_RXBUF_HI 0x048C
609 #define SK_RXQ2_RXSTAT 0x0490
610 #define SK_RXQ2_TIMESTAMP 0x0494
611 #define SK_RXQ2_CSUM1 0x0498
612 #define SK_RXQ2_CSUM2 0x049A
613 #define SK_RXQ2_CSUM1_START 0x049C
614 #define SK_RXQ2_CSUM2_START 0x049E
615 #define SK_RXQ2_CURADDR_LO 0x04A0
616 #define SK_RXQ2_CURADDR_HI 0x04A4
617 #define SK_RXQ2_CURCNT_LO 0x04A8
618 #define SK_RXQ2_CURCNT_HI 0x04AC
619 #define SK_RXQ2_CURBYTES 0x04B0
620 #define SK_RXQ2_BMU_CSR 0x04B4
621 #define SK_RXQ2_WATERMARK 0x04B8
622 #define SK_RXQ2_FLAG 0x04BA
623 #define SK_RXQ2_TEST1 0x04BC
624 #define SK_RXQ2_TEST2 0x04C0
625 #define SK_RXQ2_TEST3 0x04C4
627 #define SK_RXBMU_CLR_IRQ_ERR 0x00000001
628 #define SK_RXBMU_CLR_IRQ_EOF 0x00000002
629 #define SK_RXBMU_CLR_IRQ_EOB 0x00000004
630 #define SK_RXBMU_CLR_IRQ_PAR 0x00000008
631 #define SK_RXBMU_RX_START 0x00000010
632 #define SK_RXBMU_RX_STOP 0x00000020
633 #define SK_RXBMU_POLL_OFF 0x00000040
634 #define SK_RXBMU_POLL_ON 0x00000080
635 #define SK_RXBMU_TRANSFER_SM_RESET 0x00000100
636 #define SK_RXBMU_TRANSFER_SM_UNRESET 0x00000200
637 #define SK_RXBMU_DESCWR_SM_RESET 0x00000400
638 #define SK_RXBMU_DESCWR_SM_UNRESET 0x00000800
639 #define SK_RXBMU_DESCRD_SM_RESET 0x00001000
640 #define SK_RXBMU_DESCRD_SM_UNRESET 0x00002000
641 #define SK_RXBMU_SUPERVISOR_SM_RESET 0x00004000
642 #define SK_RXBMU_SUPERVISOR_SM_UNRESET 0x00008000
643 #define SK_RXBMU_PFI_SM_RESET 0x00010000
644 #define SK_RXBMU_PFI_SM_UNRESET 0x00020000
645 #define SK_RXBMU_FIFO_RESET 0x00040000
646 #define SK_RXBMU_FIFO_UNRESET 0x00080000
647 #define SK_RXBMU_DESC_RESET 0x00100000
648 #define SK_RXBMU_DESC_UNRESET 0x00200000
649 #define SK_RXBMU_SUPERVISOR_IDLE 0x01000000
651 #define SK_RXBMU_ONLINE \
652 (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET| \
653 SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET| \
654 SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET| \
655 SK_RXBMU_DESC_UNRESET)
657 #define SK_RXBMU_OFFLINE \
658 (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET| \
659 SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET| \
660 SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET| \
663 /* Block 12 -- TX sync queue 1 */
664 #define SK_TXQS1_BUFCNT 0x0600
665 #define SK_TXQS1_BUFCTL 0x0602
666 #define SK_TXQS1_NEXTDESC 0x0604
667 #define SK_TXQS1_RXBUF_LO 0x0608
668 #define SK_TXQS1_RXBUF_HI 0x060C
669 #define SK_TXQS1_RXSTAT 0x0610
670 #define SK_TXQS1_CSUM_STARTVAL 0x0614
671 #define SK_TXQS1_CSUM_STARTPOS 0x0618
672 #define SK_TXQS1_CSUM_WRITEPOS 0x061A
673 #define SK_TXQS1_CURADDR_LO 0x0620
674 #define SK_TXQS1_CURADDR_HI 0x0624
675 #define SK_TXQS1_CURCNT_LO 0x0628
676 #define SK_TXQS1_CURCNT_HI 0x062C
677 #define SK_TXQS1_CURBYTES 0x0630
678 #define SK_TXQS1_BMU_CSR 0x0634
679 #define SK_TXQS1_WATERMARK 0x0638
680 #define SK_TXQS1_FLAG 0x063A
681 #define SK_TXQS1_TEST1 0x063C
682 #define SK_TXQS1_TEST2 0x0640
683 #define SK_TXQS1_TEST3 0x0644
685 /* Block 13 -- TX async queue 1 */
686 #define SK_TXQA1_BUFCNT 0x0680
687 #define SK_TXQA1_BUFCTL 0x0682
688 #define SK_TXQA1_NEXTDESC 0x0684
689 #define SK_TXQA1_RXBUF_LO 0x0688
690 #define SK_TXQA1_RXBUF_HI 0x068C
691 #define SK_TXQA1_RXSTAT 0x0690
692 #define SK_TXQA1_CSUM_STARTVAL 0x0694
693 #define SK_TXQA1_CSUM_STARTPOS 0x0698
694 #define SK_TXQA1_CSUM_WRITEPOS 0x069A
695 #define SK_TXQA1_CURADDR_LO 0x06A0
696 #define SK_TXQA1_CURADDR_HI 0x06A4
697 #define SK_TXQA1_CURCNT_LO 0x06A8
698 #define SK_TXQA1_CURCNT_HI 0x06AC
699 #define SK_TXQA1_CURBYTES 0x06B0
700 #define SK_TXQA1_BMU_CSR 0x06B4
701 #define SK_TXQA1_WATERMARK 0x06B8
702 #define SK_TXQA1_FLAG 0x06BA
703 #define SK_TXQA1_TEST1 0x06BC
704 #define SK_TXQA1_TEST2 0x06C0
705 #define SK_TXQA1_TEST3 0x06C4
707 /* Block 14 -- TX sync queue 2 */
708 #define SK_TXQS2_BUFCNT 0x0700
709 #define SK_TXQS2_BUFCTL 0x0702
710 #define SK_TXQS2_NEXTDESC 0x0704
711 #define SK_TXQS2_RXBUF_LO 0x0708
712 #define SK_TXQS2_RXBUF_HI 0x070C
713 #define SK_TXQS2_RXSTAT 0x0710
714 #define SK_TXQS2_CSUM_STARTVAL 0x0714
715 #define SK_TXQS2_CSUM_STARTPOS 0x0718
716 #define SK_TXQS2_CSUM_WRITEPOS 0x071A
717 #define SK_TXQS2_CURADDR_LO 0x0720
718 #define SK_TXQS2_CURADDR_HI 0x0724
719 #define SK_TXQS2_CURCNT_LO 0x0728
720 #define SK_TXQS2_CURCNT_HI 0x072C
721 #define SK_TXQS2_CURBYTES 0x0730
722 #define SK_TXQS2_BMU_CSR 0x0734
723 #define SK_TXQS2_WATERMARK 0x0738
724 #define SK_TXQS2_FLAG 0x073A
725 #define SK_TXQS2_TEST1 0x073C
726 #define SK_TXQS2_TEST2 0x0740
727 #define SK_TXQS2_TEST3 0x0744
729 /* Block 15 -- TX async queue 2 */
730 #define SK_TXQA2_BUFCNT 0x0780
731 #define SK_TXQA2_BUFCTL 0x0782
732 #define SK_TXQA2_NEXTDESC 0x0784
733 #define SK_TXQA2_RXBUF_LO 0x0788
734 #define SK_TXQA2_RXBUF_HI 0x078C
735 #define SK_TXQA2_RXSTAT 0x0790
736 #define SK_TXQA2_CSUM_STARTVAL 0x0794
737 #define SK_TXQA2_CSUM_STARTPOS 0x0798
738 #define SK_TXQA2_CSUM_WRITEPOS 0x079A
739 #define SK_TXQA2_CURADDR_LO 0x07A0
740 #define SK_TXQA2_CURADDR_HI 0x07A4
741 #define SK_TXQA2_CURCNT_LO 0x07A8
742 #define SK_TXQA2_CURCNT_HI 0x07AC
743 #define SK_TXQA2_CURBYTES 0x07B0
744 #define SK_TXQA2_BMU_CSR 0x07B4
745 #define SK_TXQA2_WATERMARK 0x07B8
746 #define SK_TXQA2_FLAG 0x07BA
747 #define SK_TXQA2_TEST1 0x07BC
748 #define SK_TXQA2_TEST2 0x07C0
749 #define SK_TXQA2_TEST3 0x07C4
751 #define SK_TXBMU_CLR_IRQ_ERR 0x00000001
752 #define SK_TXBMU_CLR_IRQ_EOF 0x00000002
753 #define SK_TXBMU_CLR_IRQ_EOB 0x00000004
754 #define SK_TXBMU_TX_START 0x00000010
755 #define SK_TXBMU_TX_STOP 0x00000020
756 #define SK_TXBMU_POLL_OFF 0x00000040
757 #define SK_TXBMU_POLL_ON 0x00000080
758 #define SK_TXBMU_TRANSFER_SM_RESET 0x00000100
759 #define SK_TXBMU_TRANSFER_SM_UNRESET 0x00000200
760 #define SK_TXBMU_DESCWR_SM_RESET 0x00000400
761 #define SK_TXBMU_DESCWR_SM_UNRESET 0x00000800
762 #define SK_TXBMU_DESCRD_SM_RESET 0x00001000
763 #define SK_TXBMU_DESCRD_SM_UNRESET 0x00002000
764 #define SK_TXBMU_SUPERVISOR_SM_RESET 0x00004000
765 #define SK_TXBMU_SUPERVISOR_SM_UNRESET 0x00008000
766 #define SK_TXBMU_PFI_SM_RESET 0x00010000
767 #define SK_TXBMU_PFI_SM_UNRESET 0x00020000
768 #define SK_TXBMU_FIFO_RESET 0x00040000
769 #define SK_TXBMU_FIFO_UNRESET 0x00080000
770 #define SK_TXBMU_DESC_RESET 0x00100000
771 #define SK_TXBMU_DESC_UNRESET 0x00200000
772 #define SK_TXBMU_SUPERVISOR_IDLE 0x01000000
774 #define SK_TXBMU_ONLINE \
775 (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET| \
776 SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET| \
777 SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET| \
778 SK_TXBMU_DESC_UNRESET)
780 #define SK_TXBMU_OFFLINE \
781 (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET| \
782 SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET| \
783 SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET| \
786 /* Block 16 -- Receive RAMbuffer 1 */
787 #define SK_RXRB1_START 0x0800
788 #define SK_RXRB1_END 0x0804
789 #define SK_RXRB1_WR_PTR 0x0808
790 #define SK_RXRB1_RD_PTR 0x080C
791 #define SK_RXRB1_UTHR_PAUSE 0x0810
792 #define SK_RXRB1_LTHR_PAUSE 0x0814
793 #define SK_RXRB1_UTHR_HIPRIO 0x0818
794 #define SK_RXRB1_UTHR_LOPRIO 0x081C
795 #define SK_RXRB1_PKTCNT 0x0820
796 #define SK_RXRB1_LVL 0x0824
797 #define SK_RXRB1_CTLTST 0x0828
799 /* Block 17 -- Receive RAMbuffer 2 */
800 #define SK_RXRB2_START 0x0880
801 #define SK_RXRB2_END 0x0884
802 #define SK_RXRB2_WR_PTR 0x0888
803 #define SK_RXRB2_RD_PTR 0x088C
804 #define SK_RXRB2_UTHR_PAUSE 0x0890
805 #define SK_RXRB2_LTHR_PAUSE 0x0894
806 #define SK_RXRB2_UTHR_HIPRIO 0x0898
807 #define SK_RXRB2_UTHR_LOPRIO 0x089C
808 #define SK_RXRB2_PKTCNT 0x08A0
809 #define SK_RXRB2_LVL 0x08A4
810 #define SK_RXRB2_CTLTST 0x08A8
812 /* Block 20 -- Sync. Transmit RAMbuffer 1 */
813 #define SK_TXRBS1_START 0x0A00
814 #define SK_TXRBS1_END 0x0A04
815 #define SK_TXRBS1_WR_PTR 0x0A08
816 #define SK_TXRBS1_RD_PTR 0x0A0C
817 #define SK_TXRBS1_PKTCNT 0x0A20
818 #define SK_TXRBS1_LVL 0x0A24
819 #define SK_TXRBS1_CTLTST 0x0A28
821 /* Block 21 -- Async. Transmit RAMbuffer 1 */
822 #define SK_TXRBA1_START 0x0A80
823 #define SK_TXRBA1_END 0x0A84
824 #define SK_TXRBA1_WR_PTR 0x0A88
825 #define SK_TXRBA1_RD_PTR 0x0A8C
826 #define SK_TXRBA1_PKTCNT 0x0AA0
827 #define SK_TXRBA1_LVL 0x0AA4
828 #define SK_TXRBA1_CTLTST 0x0AA8
830 /* Block 22 -- Sync. Transmit RAMbuffer 2 */
831 #define SK_TXRBS2_START 0x0B00
832 #define SK_TXRBS2_END 0x0B04
833 #define SK_TXRBS2_WR_PTR 0x0B08
834 #define SK_TXRBS2_RD_PTR 0x0B0C
835 #define SK_TXRBS2_PKTCNT 0x0B20
836 #define SK_TXRBS2_LVL 0x0B24
837 #define SK_TXRBS2_CTLTST 0x0B28
839 /* Block 23 -- Async. Transmit RAMbuffer 2 */
840 #define SK_TXRBA2_START 0x0B80
841 #define SK_TXRBA2_END 0x0B84
842 #define SK_TXRBA2_WR_PTR 0x0B88
843 #define SK_TXRBA2_RD_PTR 0x0B8C
844 #define SK_TXRBA2_PKTCNT 0x0BA0
845 #define SK_TXRBA2_LVL 0x0BA4
846 #define SK_TXRBA2_CTLTST 0x0BA8
848 #define SK_RBCTL_RESET 0x00000001
849 #define SK_RBCTL_UNRESET 0x00000002
850 #define SK_RBCTL_OFF 0x00000004
851 #define SK_RBCTL_ON 0x00000008
852 #define SK_RBCTL_STORENFWD_OFF 0x00000010
853 #define SK_RBCTL_STORENFWD_ON 0x00000020
855 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */
856 #define SK_RXF1_END 0x0C00
857 #define SK_RXF1_WPTR 0x0C04
858 #define SK_RXF1_RPTR 0x0C0C
859 #define SK_RXF1_PKTCNT 0x0C10
860 #define SK_RXF1_LVL 0x0C14
861 #define SK_RXF1_MACCTL 0x0C18
862 #define SK_RXF1_CTL 0x0C1C
863 #define SK_RXLED1_CNTINIT 0x0C20
864 #define SK_RXLED1_COUNTER 0x0C24
865 #define SK_RXLED1_CTL 0x0C28
866 #define SK_RXLED1_TST 0x0C29
867 #define SK_LINK_SYNC1_CINIT 0x0C30
868 #define SK_LINK_SYNC1_COUNTER 0x0C34
869 #define SK_LINK_SYNC1_CTL 0x0C38
870 #define SK_LINK_SYNC1_TST 0x0C39
871 #define SK_LINKLED1_CTL 0x0C3C
873 #define SK_FIFO_END 0x3F
875 /* Receive MAC FIFO 1 (Yukon Only) */
876 #define SK_RXMF1_END 0x0C40
877 #define SK_RXMF1_THRESHOLD 0x0C44
878 #define SK_RXMF1_CTRL_TEST 0x0C48
879 #define SK_RXMF1_WRITE_PTR 0x0C60
880 #define SK_RXMF1_WRITE_LEVEL 0x0C68
881 #define SK_RXMF1_READ_PTR 0x0C70
882 #define SK_RXMF1_READ_LEVEL 0x0C78
884 #define SK_RFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
885 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
886 #define SK_RFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
887 #define SK_RFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */
888 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */
889 #define SK_RFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */
890 #define SK_RFCTL_RX_FIFO_OVER 0x00000040 /* Clear IRQ RX FIFO Overrun */
891 #define SK_RFCTL_FRAME_RX_DONE 0x00000010 /* Clear IRQ Frame RX Done */
892 #define SK_RFCTL_OPERATION_ON 0x00000008 /* Operational mode on */
893 #define SK_RFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */
894 #define SK_RFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */
895 #define SK_RFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */
897 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
898 #define SK_RXF2_END 0x0C80
899 #define SK_RXF2_WPTR 0x0C84
900 #define SK_RXF2_RPTR 0x0C8C
901 #define SK_RXF2_PKTCNT 0x0C90
902 #define SK_RXF2_LVL 0x0C94
903 #define SK_RXF2_MACCTL 0x0C98
904 #define SK_RXF2_CTL 0x0C9C
905 #define SK_RXLED2_CNTINIT 0x0CA0
906 #define SK_RXLED2_COUNTER 0x0CA4
907 #define SK_RXLED2_CTL 0x0CA8
908 #define SK_RXLED2_TST 0x0CA9
909 #define SK_LINK_SYNC2_CINIT 0x0CB0
910 #define SK_LINK_SYNC2_COUNTER 0x0CB4
911 #define SK_LINK_SYNC2_CTL 0x0CB8
912 #define SK_LINK_SYNC2_TST 0x0CB9
913 #define SK_LINKLED2_CTL 0x0CBC
915 #define SK_RXMACCTL_CLR_IRQ_NOSTS 0x00000001
916 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP 0x00000002
917 #define SK_RXMACCTL_TSTAMP_OFF 0x00000004
918 #define SK_RXMACCTL_RSTAMP_ON 0x00000008
919 #define SK_RXMACCTL_FLUSH_OFF 0x00000010
920 #define SK_RXMACCTL_FLUSH_ON 0x00000020
921 #define SK_RXMACCTL_PAUSE_OFF 0x00000040
922 #define SK_RXMACCTL_PAUSE_ON 0x00000080
923 #define SK_RXMACCTL_AFULL_OFF 0x00000100
924 #define SK_RXMACCTL_AFULL_ON 0x00000200
925 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400
926 #define SK_RXMACCTL_VALIDTIME_PATCH_ON 0x00000800
927 #define SK_RXMACCTL_RXRDY_PATCH_OFF 0x00001000
928 #define SK_RXMACCTL_RXRDY_PATCH_ON 0x00002000
929 #define SK_RXMACCTL_STS_TIMEO 0x00FF0000
930 #define SK_RXMACCTL_TSTAMP_TIMEO 0xFF000000
932 #define SK_RXLEDCTL_ENABLE 0x0001
933 #define SK_RXLEDCTL_COUNTER_STOP 0x0002
934 #define SK_RXLEDCTL_COUNTER_START 0x0004
936 #define SK_LINKLED_OFF 0x0001
937 #define SK_LINKLED_ON 0x0002
938 #define SK_LINKLED_LINKSYNC_OFF 0x0004
939 #define SK_LINKLED_LINKSYNC_ON 0x0008
940 #define SK_LINKLED_BLINK_OFF 0x0010
941 #define SK_LINKLED_BLINK_ON 0x0020
943 /* Block 26 -- TX MAC FIFO 1 regisrers */
944 #define SK_TXF1_END 0x0D00
945 #define SK_TXF1_WPTR 0x0D04
946 #define SK_TXF1_RPTR 0x0D0C
947 #define SK_TXF1_PKTCNT 0x0D10
948 #define SK_TXF1_LVL 0x0D14
949 #define SK_TXF1_MACCTL 0x0D18
950 #define SK_TXF1_CTL 0x0D1C
951 #define SK_TXLED1_CNTINIT 0x0D20
952 #define SK_TXLED1_COUNTER 0x0D24
953 #define SK_TXLED1_CTL 0x0D28
954 #define SK_TXLED1_TST 0x0D29
956 /* Receive MAC FIFO 1 (Yukon Only) */
957 #define SK_TXMF1_END 0x0D40
958 #define SK_TXMF1_THRESHOLD 0x0D44
959 #define SK_TXMF1_CTRL_TEST 0x0D48
960 #define SK_TXMF1_WRITE_PTR 0x0D60
961 #define SK_TXMF1_WRITE_SHADOW 0x0D64
962 #define SK_TXMF1_WRITE_LEVEL 0x0D68
963 #define SK_TXMF1_READ_PTR 0x0D70
964 #define SK_TXMF1_RESTART_PTR 0x0D74
965 #define SK_TXMF1_READ_LEVEL 0x0D78
967 #define SK_TFCTL_WR_PTR_TST_ON 0x00004000 /* Write pointer test on*/
968 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000 /* Write pointer test off */
969 #define SK_TFCTL_WR_PTR_STEP 0x00001000 /* Write pointer increment */
970 #define SK_TFCTL_RD_PTR_TST_ON 0x00000400 /* Read pointer test on */
971 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200 /* Read pointer test off */
972 #define SK_TFCTL_RD_PTR_STEP 0x00000100 /* Read pointer increment */
973 #define SK_TFCTL_TX_FIFO_UNDER 0x00000040 /* Clear IRQ TX FIFO Under */
974 #define SK_TFCTL_FRAME_TX_DONE 0x00000020 /* Clear IRQ Frame TX Done */
975 #define SK_TFCTL_IRQ_PARITY_ER 0x00000010 /* Clear IRQ Parity Error */
976 #define SK_TFCTL_OPERATION_ON 0x00000008 /* Operational mode on */
977 #define SK_TFCTL_OPERATION_OFF 0x00000004 /* Operational mode off */
978 #define SK_TFCTL_RESET_CLEAR 0x00000002 /* MAC FIFO Reset Clear */
979 #define SK_TFCTL_RESET_SET 0x00000001 /* MAC FIFO Reset Set */
981 /* Block 27 -- TX MAC FIFO 2 regisrers */
982 #define SK_TXF2_END 0x0D80
983 #define SK_TXF2_WPTR 0x0D84
984 #define SK_TXF2_RPTR 0x0D8C
985 #define SK_TXF2_PKTCNT 0x0D90
986 #define SK_TXF2_LVL 0x0D94
987 #define SK_TXF2_MACCTL 0x0D98
988 #define SK_TXF2_CTL 0x0D9C
989 #define SK_TXLED2_CNTINIT 0x0DA0
990 #define SK_TXLED2_COUNTER 0x0DA4
991 #define SK_TXLED2_CTL 0x0DA8
992 #define SK_TXLED2_TST 0x0DA9
994 #define SK_TXMACCTL_XMAC_RESET 0x00000001
995 #define SK_TXMACCTL_XMAC_UNRESET 0x00000002
996 #define SK_TXMACCTL_LOOP_OFF 0x00000004
997 #define SK_TXMACCTL_LOOP_ON 0x00000008
998 #define SK_TXMACCTL_FLUSH_OFF 0x00000010
999 #define SK_TXMACCTL_FLUSH_ON 0x00000020
1000 #define SK_TXMACCTL_WAITEMPTY_OFF 0x00000040
1001 #define SK_TXMACCTL_WAITEMPTY_ON 0x00000080
1002 #define SK_TXMACCTL_AFULL_OFF 0x00000100
1003 #define SK_TXMACCTL_AFULL_ON 0x00000200
1004 #define SK_TXMACCTL_TXRDY_PATCH_OFF 0x00000400
1005 #define SK_TXMACCTL_RXRDY_PATCH_ON 0x00000800
1006 #define SK_TXMACCTL_PKT_RECOVERY_OFF 0x00001000
1007 #define SK_TXMACCTL_PKT_RECOVERY_ON 0x00002000
1008 #define SK_TXMACCTL_CLR_IRQ_PERR 0x00008000
1009 #define SK_TXMACCTL_WAITAFTERFLUSH 0x00010000
1011 #define SK_TXLEDCTL_ENABLE 0x0001
1012 #define SK_TXLEDCTL_COUNTER_STOP 0x0002
1013 #define SK_TXLEDCTL_COUNTER_START 0x0004
1015 #define SK_FIFO_RESET 0x00000001
1016 #define SK_FIFO_UNRESET 0x00000002
1017 #define SK_FIFO_OFF 0x00000004
1018 #define SK_FIFO_ON 0x00000008
1020 /* Block 28 -- Descriptor Poll Timer */
1021 #define SK_DPT_INIT 0x0e00 /* Initial value 24 bits */
1022 #define SK_DPT_TIMER 0x0e04 /* Mul of 78.12MHz clk (24b) */
1024 #define SK_DPT_TIMER_CTRL 0x0e08 /* Timer Control 16 bits */
1025 #define SK_DPT_TCTL_STOP 0x0001 /* Stop Timer */
1026 #define SK_DPT_TCTL_START 0x0002 /* Start Timer */
1028 #define SK_DPT_TIMER_TEST 0x0e0a /* Timer Test 16 bits */
1029 #define SK_DPT_TTEST_STEP 0x0001 /* Timer Decrement */
1030 #define SK_DPT_TTEST_OFF 0x0002 /* Test Mode Off */
1031 #define SK_DPT_TTEST_ON 0x0004 /* Test Mode On */
1033 /* Block 29 -- reserved */
1035 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/
1036 #define SK_GMAC_CTRL 0x0f00 /* GMAC Control Register */
1037 #define SK_GPHY_CTRL 0x0f04 /* GPHY Control Register */
1038 #define SK_GMAC_ISR 0x0f08 /* GMAC Interrupt Source Register */
1039 #define SK_GMAC_IMR 0x0f08 /* GMAC Interrupt Mask Register */
1040 #define SK_LINK_CTRL 0x0f10 /* Link Control Register (LCR) */
1041 #define SK_WOL_CTRL 0x0f20 /* Wake on LAN Control Register */
1042 #define SK_MAC_ADDR_LOW 0x0f24 /* Mack Address Registers LOW */
1043 #define SK_MAC_ADDR_HIGH 0x0f28 /* Mack Address Registers HIGH */
1044 #define SK_PAT_READ_PTR 0x0f2c /* Pattern Read Pointer Register */
1045 #define SK_PAT_LEN_REG0 0x0f30 /* Pattern Length Register 0 */
1046 #define SK_PAT_LEN0 0x0f30 /* Pattern Length 0 */
1047 #define SK_PAT_LEN1 0x0f31 /* Pattern Length 1 */
1048 #define SK_PAT_LEN2 0x0f32 /* Pattern Length 2 */
1049 #define SK_PAT_LEN3 0x0f33 /* Pattern Length 3 */
1050 #define SK_PAT_LEN_REG1 0x0f34 /* Pattern Length Register 1 */
1051 #define SK_PAT_LEN4 0x0f34 /* Pattern Length 4 */
1052 #define SK_PAT_LEN5 0x0f35 /* Pattern Length 5 */
1053 #define SK_PAT_LEN6 0x0f36 /* Pattern Length 6 */
1054 #define SK_PAT_LEN7 0x0f37 /* Pattern Length 7 */
1055 #define SK_PAT_CTR_REG0 0x0f38 /* Pattern Counter Register 0 */
1056 #define SK_PAT_CTR0 0x0f38 /* Pattern Counter 0 */
1057 #define SK_PAT_CTR1 0x0f39 /* Pattern Counter 1 */
1058 #define SK_PAT_CTR2 0x0f3a /* Pattern Counter 2 */
1059 #define SK_PAT_CTR3 0x0f3b /* Pattern Counter 3 */
1060 #define SK_PAT_CTR_REG1 0x0f3c /* Pattern Counter Register 1 */
1061 #define SK_PAT_CTR4 0x0f3c /* Pattern Counter 4 */
1062 #define SK_PAT_CTR5 0x0f3d /* Pattern Counter 5 */
1063 #define SK_PAT_CTR6 0x0f3e /* Pattern Counter 6 */
1064 #define SK_PAT_CTR7 0x0f3f /* Pattern Counter 7 */
1066 #define SK_GMAC_LOOP_ON 0x00000020 /* Loopback mode for testing */
1067 #define SK_GMAC_LOOP_OFF 0x00000010 /* purposes */
1068 #define SK_GMAC_PAUSE_ON 0x00000008 /* enable forward of pause */
1069 #define SK_GMAC_PAUSE_OFF 0x00000004 /* signal to GMAC */
1070 #define SK_GMAC_RESET_CLEAR 0x00000002 /* Clear GMAC Reset */
1071 #define SK_GMAC_RESET_SET 0x00000001 /* Set GMAC Reset */
1073 #define SK_GPHY_SEL_BDT 0x10000000 /* Select Bidirectional xfer */
1074 #define SK_GPHY_INT_POL_HI 0x08000000 /* IRQ Polarity Active */
1075 #define SK_GPHY_75_OHM 0x04000000 /* Use 75 Ohm Termination */
1076 #define SK_GPHY_DIS_FC 0x02000000 /* Disable Auto Fiber/Copper */
1077 #define SK_GPHY_DIS_SLEEP 0x01000000 /* Disable Energy Detect */
1078 #define SK_GPHY_HWCFG_M_3 0x00800000 /* HWCFG_MODE[3] */
1079 #define SK_GPHY_HWCFG_M_2 0x00400000 /* HWCFG_MODE[2] */
1080 #define SK_GPHY_HWCFG_M_1 0x00200000 /* HWCFG_MODE[1] */
1081 #define SK_GPHY_HWCFG_M_0 0x00100000 /* HWCFG_MODE[0] */
1082 #define SK_GPHY_ANEG_0 0x00080000 /* ANEG[0] */
1083 #define SK_GPHY_ENA_XC 0x00040000 /* Enable MDI Crossover */
1084 #define SK_GPHY_DIS_125 0x00020000 /* Disable 125MHz Clock */
1085 #define SK_GPHY_ANEG_3 0x00010000 /* ANEG[3] */
1086 #define SK_GPHY_ANEG_2 0x00008000 /* ANEG[2] */
1087 #define SK_GPHY_ANEG_1 0x00004000 /* ANEG[1] */
1088 #define SK_GPHY_ENA_PAUSE 0x00002000 /* Enable Pause */
1089 #define SK_GPHY_PHYADDR_4 0x00001000 /* Bit 4 of Phy Addr */
1090 #define SK_GPHY_PHYADDR_3 0x00000800 /* Bit 3 of Phy Addr */
1091 #define SK_GPHY_PHYADDR_2 0x00000400 /* Bit 2 of Phy Addr */
1092 #define SK_GPHY_PHYADDR_1 0x00000200 /* Bit 1 of Phy Addr */
1093 #define SK_GPHY_PHYADDR_0 0x00000100 /* Bit 0 of Phy Addr */
1094 #define SK_GPHY_RESET_CLEAR 0x00000002 /* Clear GPHY Reset */
1095 #define SK_GPHY_RESET_SET 0x00000001 /* Set GPHY Reset */
1097 #define SK_GPHY_COPPER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
1098 SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 )
1099 #define SK_GPHY_FIBER (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
1101 #define SK_GPHY_ANEG_ALL (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \
1102 SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 )
1104 #define SK_GMAC_INT_TX_OFLOW 0x20 /* Transmit Counter Overflow */
1105 #define SK_GMAC_INT_RX_OFLOW 0x10 /* Receiver Overflow */
1106 #define SK_GMAC_INT_TX_UNDER 0x08 /* Transmit FIFO Underrun */
1107 #define SK_GMAC_INT_TX_DONE 0x04 /* Transmit Complete */
1108 #define SK_GMAC_INT_RX_OVER 0x02 /* Receive FIFO Overrun */
1109 #define SK_GMAC_INT_RX_DONE 0x01 /* Receive Complete */
1111 #define SK_LINK_RESET_CLEAR 0x0002 /* Link Reset Clear */
1112 #define SK_LINK_RESET_SET 0x0001 /* Link Reset Set */
1114 /* Block 31 -- reserved */
1116 /* Block 32-33 -- Pattern Ram */
1117 #define SK_WOL_PRAM 0x1000
1119 /* Block 0x22 - 0x3f -- reserved */
1121 /* Block 0x40 to 0x4F -- XMAC 1 registers */
1122 #define SK_XMAC1_BASE 0x2000
1124 /* Block 0x50 to 0x5F -- MARV 1 registers */
1125 #define SK_MARV1_BASE 0x2800
1127 /* Block 0x60 to 0x6F -- XMAC 2 registers */
1128 #define SK_XMAC2_BASE 0x3000
1130 /* Block 0x70 to 0x7F -- MARV 2 registers */
1131 #define SK_MARV2_BASE 0x3800
1133 /* Compute relative offset of an XMAC register in the XMAC window(s). */
1134 #define SK_XMAC_REG(sc, reg) (((reg) * 2) + SK_XMAC1_BASE + \
1135 (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE)))
1138 #define SK_XM_READ_4(sc, reg) \
1139 ((sk_win_read_2(sc->sk_softc, \
1140 SK_XMAC_REG(sc, reg)) & 0xFFFF) | \
1141 ((sk_win_read_2(sc->sk_softc, \
1142 SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16))
1144 #define SK_XM_WRITE_4(sc, reg, val) \
1145 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), \
1146 ((val) & 0xFFFF)); \
1147 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2), \
1148 ((val) >> 16) & 0xFFFF)
1150 #define SK_XM_READ_4(sc, reg) \
1151 sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg))
1153 #define SK_XM_WRITE_4(sc, reg, val) \
1154 sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))
1157 #define SK_XM_READ_2(sc, reg) \
1158 sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg))
1160 #define SK_XM_WRITE_2(sc, reg, val) \
1161 sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)
1163 #define SK_XM_SETBIT_4(sc, reg, x) \
1164 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))
1166 #define SK_XM_CLRBIT_4(sc, reg, x) \
1167 SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))
1169 #define SK_XM_SETBIT_2(sc, reg, x) \
1170 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))
1172 #define SK_XM_CLRBIT_2(sc, reg, x) \
1173 SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))
1175 /* Compute relative offset of an MARV register in the MARV window(s). */
1176 #define SK_YU_REG(sc, reg) \
1177 ((reg) + SK_MARV1_BASE + \
1178 (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE)))
1180 #define SK_YU_READ_4(sc, reg) \
1181 sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg)))
1183 #define SK_YU_READ_2(sc, reg) \
1184 sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg)))
1186 #define SK_YU_WRITE_4(sc, reg, val) \
1187 sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
1189 #define SK_YU_WRITE_2(sc, reg, val) \
1190 sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
1192 #define SK_YU_SETBIT_4(sc, reg, x) \
1193 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x))
1195 #define SK_YU_CLRBIT_4(sc, reg, x) \
1196 SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x))
1198 #define SK_YU_SETBIT_2(sc, reg, x) \
1199 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x))
1201 #define SK_YU_CLRBIT_2(sc, reg, x) \
1202 SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x))
1205 * The default FIFO threshold on the XMAC II is 4 bytes. On
1206 * dual port NICs, this often leads to transmit underruns, so we
1207 * bump the threshold a little.
1209 #define SK_XM_TX_FIFOTHRESH 512
1211 #define SK_PCI_VENDOR_ID 0x0000
1212 #define SK_PCI_DEVICE_ID 0x0002
1213 #define SK_PCI_COMMAND 0x0004
1214 #define SK_PCI_STATUS 0x0006
1215 #define SK_PCI_REVID 0x0008
1216 #define SK_PCI_CLASSCODE 0x0009
1217 #define SK_PCI_CACHELEN 0x000C
1218 #define SK_PCI_LATENCY_TIMER 0x000D
1219 #define SK_PCI_HEADER_TYPE 0x000E
1220 #define SK_PCI_LOMEM 0x0010
1221 #define SK_PCI_LOIO 0x0014
1222 #define SK_PCI_SUBVEN_ID 0x002C
1223 #define SK_PCI_SYBSYS_ID 0x002E
1224 #define SK_PCI_BIOSROM 0x0030
1225 #define SK_PCI_INTLINE 0x003C
1226 #define SK_PCI_INTPIN 0x003D
1227 #define SK_PCI_MINGNT 0x003E
1228 #define SK_PCI_MINLAT 0x003F
1230 /* device specific PCI registers */
1231 #define SK_PCI_OURREG1 0x0040
1232 #define SK_PCI_OURREG2 0x0044
1233 #define SK_PCI_CAPID 0x0048 /* 8 bits */
1234 #define SK_PCI_NEXTPTR 0x0049 /* 8 bits */
1235 #define SK_PCI_PWRMGMTCAP 0x004A /* 16 bits */
1236 #define SK_PCI_PWRMGMTCTRL 0x004C /* 16 bits */
1237 #define SK_PCI_PME_EVENT 0x004F
1238 #define SK_PCI_VPD_CAPID 0x0050
1239 #define SK_PCI_VPD_NEXTPTR 0x0051
1240 #define SK_PCI_VPD_ADDR 0x0052
1241 #define SK_PCI_VPD_DATA 0x0054
1243 #define SK_PSTATE_MASK 0x0003
1244 #define SK_PSTATE_D0 0x0000
1245 #define SK_PSTATE_D1 0x0001
1246 #define SK_PSTATE_D2 0x0002
1247 #define SK_PSTATE_D3 0x0003
1248 #define SK_PME_EN 0x0010
1249 #define SK_PME_STATUS 0x8000
1252 * VPD flag bit. Set to 0 to initiate a read, will become 1 when
1253 * read is complete. Set to 1 to initiate a write, will become 0
1254 * when write is finished.
1256 #define SK_VPD_FLAG 0x8000
1258 /* VPD structures */
1270 #define VPD_RES_ID 0x82 /* ID string */
1271 #define VPD_RES_READ 0x90 /* start of read only area */
1272 #define VPD_RES_WRITE 0x81 /* start of read/write area */
1273 #define VPD_RES_END 0x78 /* end tag */
1275 #define CSR_WRITE_4(sc, reg, val) \
1276 bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
1277 #define CSR_WRITE_2(sc, reg, val) \
1278 bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
1279 #define CSR_WRITE_1(sc, reg, val) \
1280 bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
1282 #define CSR_READ_4(sc, reg) \
1283 bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg))
1284 #define CSR_READ_2(sc, reg) \
1285 bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg))
1286 #define CSR_READ_1(sc, reg) \
1287 bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg))
1295 /* RX queue descriptor data structure */
1299 uint32_t sk_data_lo;
1300 uint32_t sk_data_hi;
1301 uint32_t sk_xmac_rxstat;
1302 uint32_t sk_timestamp;
1305 uint16_t sk_csum2_start;
1306 uint16_t sk_csum1_start;
1309 #define SK_OPCODE_DEFAULT 0x00550000
1310 #define SK_OPCODE_CSUM 0x00560000
1312 #define SK_RXCTL_LEN 0x0000FFFF
1313 #define SK_RXCTL_OPCODE 0x00FF0000
1314 #define SK_RXCTL_TSTAMP_VALID 0x01000000
1315 #define SK_RXCTL_STATUS_VALID 0x02000000
1316 #define SK_RXCTL_DEV0 0x04000000
1317 #define SK_RXCTL_EOF_INTR 0x08000000
1318 #define SK_RXCTL_EOB_INTR 0x10000000
1319 #define SK_RXCTL_LASTFRAG 0x20000000
1320 #define SK_RXCTL_FIRSTFRAG 0x40000000
1321 #define SK_RXCTL_OWN 0x80000000
1324 (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \
1325 SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
1330 uint32_t sk_data_lo;
1331 uint32_t sk_data_hi;
1332 uint32_t sk_xmac_txstat;
1334 uint16_t sk_csum_startval;
1335 uint16_t sk_csum_startpos;
1336 uint16_t sk_csum_writepos;
1340 #define SK_TXCTL_LEN 0x0000FFFF
1341 #define SK_TXCTL_OPCODE 0x00FF0000
1342 #define SK_TXCTL_SW 0x01000000
1343 #define SK_TXCTL_NOCRC 0x02000000
1344 #define SK_TXCTL_STORENFWD 0x04000000
1345 #define SK_TXCTL_EOF_INTR 0x08000000
1346 #define SK_TXCTL_EOB_INTR 0x10000000
1347 #define SK_TXCTL_LASTFRAG 0x20000000
1348 #define SK_TXCTL_FIRSTFRAG 0x40000000
1349 #define SK_TXCTL_OWN 0x80000000
1352 (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN)
1354 #define SK_RXBYTES(x) (x) & 0x0000FFFF;
1355 #define SK_TXBYTES SK_RXBYTES
1357 #define SK_TX_RING_CNT 512
1358 #define SK_RX_RING_CNT 256
1361 * Jumbo buffer stuff. Note that we must allocate more jumbo
1362 * buffers than there are descriptors in the receive ring. This
1363 * is because we don't know how long it will take for a packet
1364 * to be released after we hand it off to the upper protocol
1365 * layers. To be safe, we allocate 1.5 times the number of
1366 * receive descriptors.
1368 #define SK_JUMBO_FRAMELEN 9018
1369 #define SK_JUMBO_MTU (SK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
1370 #define SK_JSLOTS 384
1372 #define SK_JRAWLEN (SK_JUMBO_FRAMELEN + ETHER_ALIGN)
1373 #define SK_JLEN (SK_JRAWLEN + (sizeof(uint64_t) - \
1374 (SK_JRAWLEN % sizeof(uint64_t))))
1375 #define SK_JPAGESZ PAGE_SIZE
1376 #define SK_RESID (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ)
1377 #define SK_JMEM ((SK_JLEN * SK_JSLOTS) + SK_RESID)
1382 struct sk_if_softc *sk_sc;
1386 SLIST_ENTRY(sk_jslot) jslot_link;
1391 struct mbuf *sk_mbuf;
1392 struct sk_chain *sk_next;
1395 struct sk_chain_data {
1396 struct sk_chain sk_tx_chain[SK_TX_RING_CNT];
1397 struct sk_chain sk_rx_chain[SK_RX_RING_CNT];
1404 /* Stick the jumbo mem management stuff here too. */
1405 struct sk_jslot sk_jslots[SK_JSLOTS];
1410 struct sk_ring_data {
1411 struct sk_tx_desc sk_tx_ring[SK_TX_RING_CNT];
1412 struct sk_rx_desc sk_rx_ring[SK_RX_RING_CNT];
1415 struct sk_bcom_hack {
1420 #define SK_INC(x, y) (x) = (x + 1) % y
1425 /* Softc for the GEnesis controller. */
1427 bus_space_handle_t sk_bhandle; /* bus space handle */
1428 bus_space_tag_t sk_btag; /* bus space tag */
1429 void *sk_intrhand; /* irq handler handle */
1430 struct resource *sk_irq; /* IRQ resource handle */
1431 struct resource *sk_res; /* I/O or shared mem handle */
1432 uint8_t sk_unit; /* controller number */
1434 char *sk_vpd_prodname;
1435 char *sk_vpd_readonly;
1436 uint32_t sk_rboff; /* RAMbuffer offset */
1437 uint32_t sk_ramsize; /* amount of RAM on NIC */
1438 uint32_t sk_pmd; /* physical media type */
1439 uint32_t sk_intrmask;
1440 struct sk_if_softc *sk_if[2];
1441 device_t sk_devs[2];
1444 /* Softc for each logical interface */
1445 struct sk_if_softc {
1446 struct arpcom arpcom; /* interface info */
1448 uint8_t sk_unit; /* interface number */
1449 uint8_t sk_port; /* port # on controller */
1450 uint8_t sk_xmac_rev; /* XMAC chip rev (B2 or C1) */
1451 uint32_t sk_rx_ramstart;
1452 uint32_t sk_rx_ramend;
1453 uint32_t sk_tx_ramstart;
1454 uint32_t sk_tx_ramend;
1460 struct callout sk_tick_timer;
1461 struct sk_chain_data sk_cdata;
1462 struct sk_ring_data *sk_rdata;
1463 struct sk_softc *sk_softc; /* parent controller */
1464 int sk_tx_bmu; /* TX BMU register */
1466 SLIST_HEAD(__sk_jfreehead, sk_jslot) sk_jfree_listhead;
1467 struct lwkt_serialize sk_jslot_serializer;
1470 #define SK_MAXUNIT 256
1471 #define SK_TIMEOUT 1000
1472 #define ETHER_ALIGN 2