2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/mpapic.h>
60 #include <machine/psl.h>
61 #include <machine/segments.h>
62 #include <machine/tss.h>
63 #include <machine/specialreg.h>
64 #include <machine/globaldata.h>
65 #include <machine/pmap_inval.h>
67 #include <machine/md_var.h> /* setidt() */
68 #include <machine_base/icu/icu.h> /* IPIs */
69 #include <machine/intr_machdep.h> /* IPIs */
71 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_long cpu_signature;
130 u_long feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 #define MPTABLE_POS_USE_DEFAULT(mpt) \
173 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
177 int mb_type; /* MPTABLE_BUS_ */
178 TAILQ_ENTRY(mptable_bus) mb_link;
181 #define MPTABLE_BUS_ISA 0
182 #define MPTABLE_BUS_PCI 1
184 struct mptable_bus_info {
185 TAILQ_HEAD(, mptable_bus) mbi_list;
188 struct mptable_pci_int {
195 TAILQ_ENTRY(mptable_pci_int) mpci_link;
198 typedef int (*mptable_iter_func)(void *, const void *, int);
201 * this code MUST be enabled here and in mpboot.s.
202 * it follows the very early stages of AP boot by placing values in CMOS ram.
203 * it NORMALLY will never be needed and thus the primitive method for enabling.
206 #if defined(CHECK_POINTS)
207 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
208 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
210 #define CHECK_INIT(D); \
211 CHECK_WRITE(0x34, (D)); \
212 CHECK_WRITE(0x35, (D)); \
213 CHECK_WRITE(0x36, (D)); \
214 CHECK_WRITE(0x37, (D)); \
215 CHECK_WRITE(0x38, (D)); \
216 CHECK_WRITE(0x39, (D));
218 #define CHECK_PRINT(S); \
219 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
228 #else /* CHECK_POINTS */
230 #define CHECK_INIT(D)
231 #define CHECK_PRINT(S)
233 #endif /* CHECK_POINTS */
236 * Values to send to the POST hardware.
238 #define MP_BOOTADDRESS_POST 0x10
239 #define MP_PROBE_POST 0x11
240 #define MPTABLE_PASS1_POST 0x12
242 #define MP_START_POST 0x13
243 #define MP_ENABLE_POST 0x14
244 #define MPTABLE_PASS2_POST 0x15
246 #define START_ALL_APS_POST 0x16
247 #define INSTALL_AP_TRAMP_POST 0x17
248 #define START_AP_POST 0x18
250 #define MP_ANNOUNCE_POST 0x19
252 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
253 int current_postcode;
255 /** XXX FIXME: what system files declare these??? */
256 extern struct region_descriptor r_gdt, r_idt;
258 int mp_naps; /* # of Applications processors */
259 #ifdef SMP /* APIC-IO */
260 static int mp_nbusses; /* # of busses */
261 int mp_napics; /* # of IO APICs */
262 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
263 u_int32_t *io_apic_versions;
267 u_int32_t cpu_apic_versions[MAXCPU];
269 extern int64_t tsc_offsets[];
271 extern u_long ebda_addr;
273 #ifdef SMP /* APIC-IO */
274 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
278 * APIC ID logical/physical mapping structures.
279 * We oversize these to simplify boot-time config.
281 int cpu_num_to_apic_id[NAPICID];
282 #ifdef SMP /* APIC-IO */
283 int io_num_to_apic_id[NAPICID];
285 int apic_id_to_logical[NAPICID];
287 /* AP uses this during bootstrap. Do not staticize. */
291 /* Hotwire a 0->4MB V==P mapping */
292 extern pt_entry_t *KPTphys;
295 * SMP page table page. Setup by locore to point to a page table
296 * page from which we allocate per-cpu privatespace areas io_apics,
300 #define IO_MAPPING_START_INDEX \
301 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
303 extern pt_entry_t *SMPpt;
304 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
306 struct pcb stoppcbs[MAXCPU];
308 static basetable_entry basetable_entry_types[] =
310 {0, 20, "Processor"},
318 * Local data and functions.
321 static u_int boot_address;
322 static u_int base_memory;
323 static int mp_finish;
325 static void mp_enable(u_int boot_addr);
327 static int mptable_iterate_entries(const mpcth_t,
328 mptable_iter_func, void *);
329 static int mptable_search(void);
330 static int mptable_search_sig(u_int32_t target, int count);
331 static int mptable_hyperthread_fixup(cpumask_t, int);
332 #ifdef SMP /* APIC-IO */
333 static void mptable_pass1(struct mptable_pos *);
334 static void mptable_pass2(struct mptable_pos *);
335 static void mptable_default(int type);
336 static void mptable_fix(void);
338 static int mptable_map(struct mptable_pos *);
339 static void mptable_unmap(struct mptable_pos *);
340 static void mptable_imcr(struct mptable_pos *);
341 static void mptable_bus_info_alloc(const mpcth_t,
342 struct mptable_bus_info *);
343 static void mptable_bus_info_free(struct mptable_bus_info *);
345 static int mptable_lapic_probe(struct lapic_enumerator *);
346 static void mptable_lapic_enumerate(struct lapic_enumerator *);
347 static void mptable_lapic_default(void);
349 static int mptable_ioapic_probe(struct ioapic_enumerator *);
350 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
352 #ifdef SMP /* APIC-IO */
353 static void setup_apic_irq_mapping(void);
354 static int apic_int_is_bus_type(int intr, int bus_type);
356 static int start_all_aps(u_int boot_addr);
357 static void install_ap_tramp(u_int boot_addr);
358 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
359 static int smitest(void);
361 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
362 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
363 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
365 static vm_paddr_t mptable_fps_phyaddr;
366 static int mptable_use_default;
367 static TAILQ_HEAD(, mptable_pci_int) mptable_pci_int_list =
368 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
371 * Calculate usable address in base memory for AP trampoline code.
374 mp_bootaddress(u_int basemem)
376 POSTCODE(MP_BOOTADDRESS_POST);
378 base_memory = basemem;
380 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
381 if ((base_memory - boot_address) < bootMP_size)
382 boot_address -= 4096; /* not enough, lower by 4k */
391 struct mptable_pos mpt;
394 KKASSERT(mptable_fps_phyaddr == 0);
396 mptable_fps_phyaddr = mptable_search();
397 if (mptable_fps_phyaddr == 0)
400 error = mptable_map(&mpt);
402 mptable_fps_phyaddr = 0;
406 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
407 kprintf("MPTABLE: use default configuration\n");
408 mptable_use_default = 1;
413 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
416 * Look for an Intel MP spec table (ie, SMP capable hardware).
425 * Make sure our SMPpt[] page table is big enough to hold all the
428 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
430 POSTCODE(MP_PROBE_POST);
432 /* see if EBDA exists */
433 if (ebda_addr != 0) {
434 /* search first 1K of EBDA */
435 target = (u_int32_t)ebda_addr;
436 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
439 /* last 1K of base memory, effective 'top of base' passed in */
440 target = (u_int32_t)(base_memory - 0x400);
441 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
445 /* search the BIOS */
446 target = (u_int32_t)BIOS_BASE;
447 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
450 /* search the extended BIOS */
451 target = (u_int32_t)BIOS_BASE2;
452 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
460 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
462 int count, total_size;
463 const void *position;
465 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
466 total_size = cth->base_table_length - sizeof(struct MPCTH);
467 position = (const uint8_t *)cth + sizeof(struct MPCTH);
468 count = cth->entry_count;
473 KKASSERT(total_size >= 0);
474 if (total_size == 0) {
475 kprintf("invalid base MP table, "
476 "entry count and length mismatch\n");
480 type = *(const uint8_t *)position;
482 case 0: /* processor_entry */
483 case 1: /* bus_entry */
484 case 2: /* io_apic_entry */
485 case 3: /* int_entry */
486 case 4: /* int_entry */
489 kprintf("unknown base MP table entry type %d\n", type);
493 if (total_size < basetable_entry_types[type].length) {
494 kprintf("invalid base MP table length, "
495 "does not contain all entries\n");
498 total_size -= basetable_entry_types[type].length;
500 error = func(arg, position, type);
504 position = (const uint8_t *)position +
505 basetable_entry_types[type].length;
512 * Startup the SMP processors.
517 POSTCODE(MP_START_POST);
518 mp_enable(boot_address);
523 * Print various information about the SMP system hardware and setup.
530 POSTCODE(MP_ANNOUNCE_POST);
532 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
533 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
534 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
535 for (x = 1; x <= mp_naps; ++x) {
536 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
537 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
540 if (apic_io_enable) {
541 for (x = 0; x < mp_napics; ++x) {
542 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
543 kprintf(", version: 0x%08x", io_apic_versions[x]);
544 kprintf(", at 0x%08lx\n", io_apic_address[x]);
547 kprintf(" Warning: APIC I/O disabled\n");
552 * AP cpu's call this to sync up protected mode.
554 * WARNING! We must ensure that the cpu is sufficiently initialized to
555 * be able to use to the FP for our optimized bzero/bcopy code before
556 * we enter more mainstream C code.
558 * WARNING! %fs is not set up on entry. This routine sets up %fs.
564 int x, myid = bootAP;
566 struct mdglobaldata *md;
567 struct privatespace *ps;
569 ps = &CPU_prvspace[myid];
571 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
572 gdt_segs[GPROC0_SEL].ssd_base =
573 (int) &ps->mdglobaldata.gd_common_tss;
574 ps->mdglobaldata.mi.gd_prvspace = ps;
576 for (x = 0; x < NGDT; x++) {
577 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
580 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
581 r_gdt.rd_base = (int) &gdt[myid * NGDT];
582 lgdt(&r_gdt); /* does magic intra-segment return */
587 mdcpu->gd_currentldt = _default_ldt;
589 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
590 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
592 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
594 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
595 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
596 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
597 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
598 md->gd_common_tssd = *md->gd_tss_gdt;
602 * Set to a known state:
603 * Set by mpboot.s: CR0_PG, CR0_PE
604 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
607 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
609 pmap_set_opt(); /* PSE/4MB pages, etc */
611 /* set up CPU registers and state */
614 /* set up FPU state on the AP */
615 npxinit(__INITIAL_NPXCW__);
617 /* set up SSE registers */
621 /*******************************************************************
622 * local functions and data
626 * start the SMP system
629 mp_enable(u_int boot_addr)
633 struct mptable_pos mpt;
635 POSTCODE(MP_ENABLE_POST);
642 if (mptable_fps_phyaddr) {
647 if (apic_io_enable) {
649 if (!mptable_fps_phyaddr)
650 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
655 * Examine the MP table for needed info
662 /* Post scan cleanup */
665 setup_apic_irq_mapping();
667 /* fill the LOGICAL io_apic_versions table */
668 for (apic = 0; apic < mp_napics; ++apic) {
669 ux = ioapic_read(ioapic[apic], IOAPIC_VER);
670 io_apic_versions[apic] = ux;
671 io_apic_set_id(apic, IO_TO_ID(apic));
674 /* program each IO APIC in the system */
675 for (apic = 0; apic < mp_napics; ++apic)
676 if (io_apic_setup(apic) < 0)
677 panic("IO APIC setup failure");
682 * These are required for SMP operation
685 /* install a 'Spurious INTerrupt' vector */
686 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
687 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
689 /* install an inter-CPU IPI for TLB invalidation */
690 setidt(XINVLTLB_OFFSET, Xinvltlb,
691 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
693 /* install an inter-CPU IPI for IPIQ messaging */
694 setidt(XIPIQ_OFFSET, Xipiq,
695 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
697 /* install a timer vector */
698 setidt(XTIMER_OFFSET, Xtimer,
699 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
701 /* install an inter-CPU IPI for CPU stop/restart */
702 setidt(XCPUSTOP_OFFSET, Xcpustop,
703 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
705 /* start each Application Processor */
706 start_all_aps(boot_addr);
711 * look for the MP spec signature
714 /* string defined by the Intel MP Spec as identifying the MP table */
715 #define MP_SIG 0x5f504d5f /* _MP_ */
716 #define NEXT(X) ((X) += 4)
718 mptable_search_sig(u_int32_t target, int count)
724 KKASSERT(target != 0);
726 map_size = count * sizeof(u_int32_t);
727 addr = pmap_mapdev((vm_paddr_t)target, map_size);
730 for (x = 0; x < count; NEXT(x)) {
731 if (addr[x] == MP_SIG) {
732 /* make array index a byte index */
733 ret = target + (x * sizeof(u_int32_t));
738 pmap_unmapdev((vm_offset_t)addr, map_size);
743 typedef struct BUSDATA {
745 enum busTypes bus_type;
748 typedef struct INTDATA {
758 typedef struct BUSTYPENAME {
763 static bus_type_name bus_type_table[] =
769 {UNKNOWN_BUSTYPE, "---"},
772 {UNKNOWN_BUSTYPE, "---"},
773 {UNKNOWN_BUSTYPE, "---"},
774 {UNKNOWN_BUSTYPE, "---"},
775 {UNKNOWN_BUSTYPE, "---"},
776 {UNKNOWN_BUSTYPE, "---"},
778 {UNKNOWN_BUSTYPE, "---"},
779 {UNKNOWN_BUSTYPE, "---"},
780 {UNKNOWN_BUSTYPE, "---"},
781 {UNKNOWN_BUSTYPE, "---"},
783 {UNKNOWN_BUSTYPE, "---"}
785 /* from MP spec v1.4, table 5-1 */
786 static int default_data[7][5] =
788 /* nbus, id0, type0, id1, type1 */
789 {1, 0, ISA, 255, 255},
790 {1, 0, EISA, 255, 255},
791 {1, 0, EISA, 255, 255},
792 {1, 0, MCA, 255, 255},
794 {2, 0, EISA, 1, PCI},
800 static bus_datum *bus_data;
802 /* the IO INT data, one entry per possible APIC INTerrupt */
803 static io_int *io_apic_ints;
806 static int processor_entry (const struct PROCENTRY *entry, int cpu);
807 static int bus_entry (const struct BUSENTRY *entry, int bus);
808 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
809 static int int_entry (const struct INTENTRY *entry, int intr);
810 static int lookup_bus_type (char *name);
813 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
815 const struct IOAPICENTRY *ioapic_ent;
818 case 1: /* bus_entry */
822 case 2: /* io_apic_entry */
824 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
825 io_apic_address[mp_napics++] =
826 (vm_offset_t)ioapic_ent->apic_address;
830 case 3: /* int_entry */
838 * 1st pass on motherboard's Intel MP specification table.
847 mptable_pass1(struct mptable_pos *mpt)
852 POSTCODE(MPTABLE_PASS1_POST);
855 KKASSERT(fps != NULL);
857 /* clear various tables */
858 for (x = 0; x < NAPICID; ++x)
859 io_apic_address[x] = ~0; /* IO APIC address table */
865 /* check for use of 'default' configuration */
866 if (fps->mpfb1 != 0) {
867 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
868 mp_nbusses = default_data[fps->mpfb1 - 1][0];
874 error = mptable_iterate_entries(mpt->mp_cth,
875 mptable_ioapic_pass1_callback, NULL);
877 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
881 struct mptable_ioapic2_cbarg {
888 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
890 struct mptable_ioapic2_cbarg *arg = xarg;
894 if (bus_entry(pos, arg->bus))
899 if (io_apic_entry(pos, arg->apic))
904 if (int_entry(pos, arg->intr))
912 * 2nd pass on motherboard's Intel MP specification table.
915 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
916 * IO_TO_ID(N), logical IO to APIC ID table
921 mptable_pass2(struct mptable_pos *mpt)
923 struct mptable_ioapic2_cbarg arg;
927 POSTCODE(MPTABLE_PASS2_POST);
930 KKASSERT(fps != NULL);
932 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
934 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
935 M_DEVBUF, M_WAITOK | M_ZERO);
936 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
938 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
941 for (x = 0; x < mp_napics; x++)
942 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
944 /* clear various tables */
945 for (x = 0; x < NAPICID; ++x) {
946 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
947 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
950 /* clear bus data table */
951 for (x = 0; x < mp_nbusses; ++x)
952 bus_data[x].bus_id = 0xff;
954 /* clear IO APIC INT table */
955 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
956 io_apic_ints[x].int_type = 0xff;
957 io_apic_ints[x].int_vector = 0xff;
960 /* check for use of 'default' configuration */
961 if (fps->mpfb1 != 0) {
962 mptable_default(fps->mpfb1);
966 bzero(&arg, sizeof(arg));
967 error = mptable_iterate_entries(mpt->mp_cth,
968 mptable_ioapic_pass2_callback, &arg);
970 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
974 * Check if we should perform a hyperthreading "fix-up" to
975 * enumerate any logical CPU's that aren't already listed
978 * XXX: We assume that all of the physical CPUs in the
979 * system have the same number of logical CPUs.
981 * XXX: We assume that APIC ID's are allocated such that
982 * the APIC ID's for a physical processor are aligned
983 * with the number of logical CPU's in the processor.
986 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
988 int i, id, lcpus_max, logical_cpus;
990 if ((cpu_feature & CPUID_HTT) == 0)
993 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
997 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
999 * INSTRUCTION SET REFERENCE, A-M (#253666)
1000 * Page 3-181, Table 3-20
1001 * "The nearest power-of-2 integer that is not smaller
1002 * than EBX[23:16] is the number of unique initial APIC
1003 * IDs reserved for addressing different logical
1004 * processors in a physical package."
1006 for (i = 0; ; ++i) {
1007 if ((1 << i) >= lcpus_max) {
1014 KKASSERT(cpu_count != 0);
1015 if (cpu_count == lcpus_max) {
1016 /* We have nothing to fix */
1018 } else if (cpu_count == 1) {
1019 /* XXX this may be incorrect */
1020 logical_cpus = lcpus_max;
1022 int cur, prev, dist;
1025 * Calculate the distances between two nearest
1026 * APIC IDs. If all such distances are same,
1027 * then it is the number of missing cpus that
1028 * we are going to fill later.
1030 dist = cur = prev = -1;
1031 for (id = 0; id < MAXCPU; ++id) {
1032 if ((id_mask & CPUMASK(id)) == 0)
1037 int new_dist = cur - prev;
1043 * Make sure that all distances
1044 * between two nearest APIC IDs
1047 if (dist != new_dist)
1055 /* Must be power of 2 */
1056 if (dist & (dist - 1))
1059 /* Can't exceed CPU package capacity */
1060 if (dist > lcpus_max)
1061 logical_cpus = lcpus_max;
1063 logical_cpus = dist;
1067 * For each APIC ID of a CPU that is set in the mask,
1068 * scan the other candidate APIC ID's for this
1069 * physical processor. If any of those ID's are
1070 * already in the table, then kill the fixup.
1072 for (id = 0; id < MAXCPU; id++) {
1073 if ((id_mask & CPUMASK(id)) == 0)
1075 /* First, make sure we are on a logical_cpus boundary. */
1076 if (id % logical_cpus != 0)
1078 for (i = id + 1; i < id + logical_cpus; i++)
1079 if ((id_mask & CPUMASK(i)) != 0)
1082 return logical_cpus;
1086 mptable_map(struct mptable_pos *mpt)
1090 vm_size_t cth_mapsz = 0;
1092 KKASSERT(mptable_fps_phyaddr != 0);
1094 bzero(mpt, sizeof(*mpt));
1096 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
1097 if (fps->pap != 0) {
1099 * Map configuration table header to get
1100 * the base table size
1102 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1103 cth_mapsz = cth->base_table_length;
1104 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1106 if (cth_mapsz < sizeof(*cth)) {
1107 kprintf("invalid base MP table length %d\n",
1109 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1114 * Map the base table
1116 cth = pmap_mapdev(fps->pap, cth_mapsz);
1121 mpt->mp_cth_mapsz = cth_mapsz;
1127 mptable_unmap(struct mptable_pos *mpt)
1129 if (mpt->mp_cth != NULL) {
1130 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1132 mpt->mp_cth_mapsz = 0;
1134 if (mpt->mp_fps != NULL) {
1135 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1141 assign_apic_irq(int apic, int intpin, int irq)
1145 if (int_to_apicintpin[irq].ioapic != -1)
1146 panic("assign_apic_irq: inconsistent table");
1148 int_to_apicintpin[irq].ioapic = apic;
1149 int_to_apicintpin[irq].int_pin = intpin;
1150 int_to_apicintpin[irq].apic_address = ioapic[apic];
1151 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1153 for (x = 0; x < nintrs; x++) {
1154 if ((io_apic_ints[x].int_type == 0 ||
1155 io_apic_ints[x].int_type == 3) &&
1156 io_apic_ints[x].int_vector == 0xff &&
1157 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1158 io_apic_ints[x].dst_apic_int == intpin)
1159 io_apic_ints[x].int_vector = irq;
1164 revoke_apic_irq(int irq)
1170 if (int_to_apicintpin[irq].ioapic == -1)
1171 panic("revoke_apic_irq: inconsistent table");
1173 oldapic = int_to_apicintpin[irq].ioapic;
1174 oldintpin = int_to_apicintpin[irq].int_pin;
1176 int_to_apicintpin[irq].ioapic = -1;
1177 int_to_apicintpin[irq].int_pin = 0;
1178 int_to_apicintpin[irq].apic_address = NULL;
1179 int_to_apicintpin[irq].redirindex = 0;
1181 for (x = 0; x < nintrs; x++) {
1182 if ((io_apic_ints[x].int_type == 0 ||
1183 io_apic_ints[x].int_type == 3) &&
1184 io_apic_ints[x].int_vector != 0xff &&
1185 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1186 io_apic_ints[x].dst_apic_int == oldintpin)
1187 io_apic_ints[x].int_vector = 0xff;
1195 allocate_apic_irq(int intr)
1201 if (io_apic_ints[intr].int_vector != 0xff)
1202 return; /* Interrupt handler already assigned */
1204 if (io_apic_ints[intr].int_type != 0 &&
1205 (io_apic_ints[intr].int_type != 3 ||
1206 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1207 io_apic_ints[intr].dst_apic_int == 0)))
1208 return; /* Not INT or ExtInt on != (0, 0) */
1211 while (irq < APIC_INTMAPSIZE &&
1212 int_to_apicintpin[irq].ioapic != -1)
1215 if (irq >= APIC_INTMAPSIZE)
1216 return; /* No free interrupt handlers */
1218 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1219 intpin = io_apic_ints[intr].dst_apic_int;
1221 assign_apic_irq(apic, intpin, irq);
1226 swap_apic_id(int apic, int oldid, int newid)
1233 return; /* Nothing to do */
1235 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1236 apic, oldid, newid);
1238 /* Swap physical APIC IDs in interrupt entries */
1239 for (x = 0; x < nintrs; x++) {
1240 if (io_apic_ints[x].dst_apic_id == oldid)
1241 io_apic_ints[x].dst_apic_id = newid;
1242 else if (io_apic_ints[x].dst_apic_id == newid)
1243 io_apic_ints[x].dst_apic_id = oldid;
1246 /* Swap physical APIC IDs in IO_TO_ID mappings */
1247 for (oapic = 0; oapic < mp_napics; oapic++)
1248 if (IO_TO_ID(oapic) == newid)
1251 if (oapic < mp_napics) {
1252 kprintf("Changing APIC ID for IO APIC #%d from "
1253 "%d to %d in MP table\n",
1254 oapic, newid, oldid);
1255 IO_TO_ID(oapic) = oldid;
1257 IO_TO_ID(apic) = newid;
1262 fix_id_to_io_mapping(void)
1266 for (x = 0; x < NAPICID; x++)
1269 for (x = 0; x <= mp_naps; x++)
1270 if (CPU_TO_ID(x) < NAPICID)
1271 ID_TO_IO(CPU_TO_ID(x)) = x;
1273 for (x = 0; x < mp_napics; x++)
1274 if (IO_TO_ID(x) < NAPICID)
1275 ID_TO_IO(IO_TO_ID(x)) = x;
1280 first_free_apic_id(void)
1284 for (freeid = 0; freeid < NAPICID; freeid++) {
1285 for (x = 0; x <= mp_naps; x++)
1286 if (CPU_TO_ID(x) == freeid)
1290 for (x = 0; x < mp_napics; x++)
1291 if (IO_TO_ID(x) == freeid)
1302 io_apic_id_acceptable(int apic, int id)
1304 int cpu; /* Logical CPU number */
1305 int oapic; /* Logical IO APIC number for other IO APIC */
1308 return 0; /* Out of range */
1310 for (cpu = 0; cpu <= mp_naps; cpu++)
1311 if (CPU_TO_ID(cpu) == id)
1312 return 0; /* Conflict with CPU */
1314 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1315 if (IO_TO_ID(oapic) == id)
1316 return 0; /* Conflict with other APIC */
1318 return 1; /* ID is acceptable for IO APIC */
1323 io_apic_find_int_entry(int apic, int pin)
1327 /* search each of the possible INTerrupt sources */
1328 for (x = 0; x < nintrs; ++x) {
1329 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1330 (pin == io_apic_ints[x].dst_apic_int))
1331 return (&io_apic_ints[x]);
1337 * parse an Intel MP specification table
1344 int apic; /* IO APIC unit number */
1345 int freeid; /* Free physical APIC ID */
1346 int physid; /* Current physical IO APIC ID */
1348 int bus_0 = 0; /* Stop GCC warning */
1349 int bus_pci = 0; /* Stop GCC warning */
1353 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1354 * did it wrong. The MP spec says that when more than 1 PCI bus
1355 * exists the BIOS must begin with bus entries for the PCI bus and use
1356 * actual PCI bus numbering. This implies that when only 1 PCI bus
1357 * exists the BIOS can choose to ignore this ordering, and indeed many
1358 * MP motherboards do ignore it. This causes a problem when the PCI
1359 * sub-system makes requests of the MP sub-system based on PCI bus
1360 * numbers. So here we look for the situation and renumber the
1361 * busses and associated INTs in an effort to "make it right".
1364 /* find bus 0, PCI bus, count the number of PCI busses */
1365 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1366 if (bus_data[x].bus_id == 0) {
1369 if (bus_data[x].bus_type == PCI) {
1375 * bus_0 == slot of bus with ID of 0
1376 * bus_pci == slot of last PCI bus encountered
1379 /* check the 1 PCI bus case for sanity */
1380 /* if it is number 0 all is well */
1381 if (num_pci_bus == 1 &&
1382 bus_data[bus_pci].bus_id != 0) {
1384 /* mis-numbered, swap with whichever bus uses slot 0 */
1386 /* swap the bus entry types */
1387 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1388 bus_data[bus_0].bus_type = PCI;
1390 /* swap each relavant INTerrupt entry */
1391 id = bus_data[bus_pci].bus_id;
1392 for (x = 0; x < nintrs; ++x) {
1393 if (io_apic_ints[x].src_bus_id == id) {
1394 io_apic_ints[x].src_bus_id = 0;
1396 else if (io_apic_ints[x].src_bus_id == 0) {
1397 io_apic_ints[x].src_bus_id = id;
1402 /* Assign IO APIC IDs.
1404 * First try the existing ID. If a conflict is detected, try
1405 * the ID in the MP table. If a conflict is still detected, find
1408 * We cannot use the ID_TO_IO table before all conflicts has been
1409 * resolved and the table has been corrected.
1411 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1413 /* First try to use the value set by the BIOS */
1414 physid = io_apic_get_id(apic);
1415 if (io_apic_id_acceptable(apic, physid)) {
1416 if (IO_TO_ID(apic) != physid)
1417 swap_apic_id(apic, IO_TO_ID(apic), physid);
1421 /* Then check if the value in the MP table is acceptable */
1422 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1425 /* Last resort, find a free APIC ID and use it */
1426 freeid = first_free_apic_id();
1427 if (freeid >= NAPICID)
1428 panic("No free physical APIC IDs found");
1430 if (io_apic_id_acceptable(apic, freeid)) {
1431 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1434 panic("Free physical APIC ID not usable");
1436 fix_id_to_io_mapping();
1438 /* detect and fix broken Compaq MP table */
1439 if (apic_int_type(0, 0) == -1) {
1440 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1441 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1442 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1443 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1444 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1445 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1447 } else if (apic_int_type(0, 0) == 0) {
1448 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1449 for (x = 0; x < nintrs; ++x)
1450 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1451 (0 == io_apic_ints[x].dst_apic_int)) {
1452 io_apic_ints[x].int_type = 3;
1453 io_apic_ints[x].int_vector = 0xff;
1459 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1460 * controllers universally come in pairs. If IRQ 14 is specified
1461 * as an ISA interrupt, then IRQ 15 had better be too.
1463 * [ Shuttle XPC / AMD Athlon X2 ]
1464 * The MPTable is missing an entry for IRQ 15. Note that the
1465 * ACPI table has an entry for both 14 and 15.
1467 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1468 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1469 io14 = io_apic_find_int_entry(0, 14);
1470 io_apic_ints[nintrs] = *io14;
1471 io_apic_ints[nintrs].src_bus_irq = 15;
1472 io_apic_ints[nintrs].dst_apic_int = 15;
1477 /* Assign low level interrupt handlers */
1479 setup_apic_irq_mapping(void)
1485 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1486 int_to_apicintpin[x].ioapic = -1;
1487 int_to_apicintpin[x].int_pin = 0;
1488 int_to_apicintpin[x].apic_address = NULL;
1489 int_to_apicintpin[x].redirindex = 0;
1491 /* Default to masked */
1492 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1495 /* First assign ISA/EISA interrupts */
1496 for (x = 0; x < nintrs; x++) {
1497 int_vector = io_apic_ints[x].src_bus_irq;
1498 if (int_vector < APIC_INTMAPSIZE &&
1499 io_apic_ints[x].int_vector == 0xff &&
1500 int_to_apicintpin[int_vector].ioapic == -1 &&
1501 (apic_int_is_bus_type(x, ISA) ||
1502 apic_int_is_bus_type(x, EISA)) &&
1503 io_apic_ints[x].int_type == 0) {
1504 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1505 io_apic_ints[x].dst_apic_int,
1510 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1511 for (x = 0; x < nintrs; x++) {
1512 if (io_apic_ints[x].dst_apic_int == 0 &&
1513 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1514 io_apic_ints[x].int_vector == 0xff &&
1515 int_to_apicintpin[0].ioapic == -1 &&
1516 io_apic_ints[x].int_type == 3) {
1517 assign_apic_irq(0, 0, 0);
1522 /* Assign PCI interrupts */
1523 for (x = 0; x < nintrs; ++x) {
1524 if (io_apic_ints[x].int_type == 0 &&
1525 io_apic_ints[x].int_vector == 0xff &&
1526 apic_int_is_bus_type(x, PCI))
1527 allocate_apic_irq(x);
1532 mp_set_cpuids(int cpu_id, int apic_id)
1534 CPU_TO_ID(cpu_id) = apic_id;
1535 ID_TO_CPU(apic_id) = cpu_id;
1539 processor_entry(const struct PROCENTRY *entry, int cpu)
1543 /* check for usability */
1544 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1547 /* check for BSP flag */
1548 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1549 mp_set_cpuids(0, entry->apic_id);
1550 return 0; /* its already been counted */
1553 /* add another AP to list, if less than max number of CPUs */
1554 else if (cpu < MAXCPU) {
1555 mp_set_cpuids(cpu, entry->apic_id);
1563 bus_entry(const struct BUSENTRY *entry, int bus)
1568 /* encode the name into an index */
1569 for (x = 0; x < 6; ++x) {
1570 if ((c = entry->bus_type[x]) == ' ')
1576 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1577 panic("unknown bus type: '%s'", name);
1579 bus_data[bus].bus_id = entry->bus_id;
1580 bus_data[bus].bus_type = x;
1586 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1588 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1591 IO_TO_ID(apic) = entry->apic_id;
1592 ID_TO_IO(entry->apic_id) = apic;
1598 lookup_bus_type(char *name)
1602 for (x = 0; x < MAX_BUSTYPE; ++x)
1603 if (strcmp(bus_type_table[x].name, name) == 0)
1604 return bus_type_table[x].type;
1606 return UNKNOWN_BUSTYPE;
1610 int_entry(const struct INTENTRY *entry, int intr)
1614 io_apic_ints[intr].int_type = entry->int_type;
1615 io_apic_ints[intr].int_flags = entry->int_flags;
1616 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1617 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1618 if (entry->dst_apic_id == 255) {
1619 /* This signal goes to all IO APICS. Select an IO APIC
1620 with sufficient number of interrupt pins */
1621 for (apic = 0; apic < mp_napics; apic++)
1622 if (((ioapic_read(ioapic[apic], IOAPIC_VER) &
1623 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1624 entry->dst_apic_int)
1626 if (apic < mp_napics)
1627 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1629 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1631 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1632 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1638 apic_int_is_bus_type(int intr, int bus_type)
1642 for (bus = 0; bus < mp_nbusses; ++bus)
1643 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1644 && ((int) bus_data[bus].bus_type == bus_type))
1651 * Given a traditional ISA INT mask, return an APIC mask.
1654 isa_apic_mask(u_int isa_mask)
1659 #if defined(SKIP_IRQ15_REDIRECT)
1660 if (isa_mask == (1 << 15)) {
1661 kprintf("skipping ISA IRQ15 redirect\n");
1664 #endif /* SKIP_IRQ15_REDIRECT */
1666 isa_irq = ffs(isa_mask); /* find its bit position */
1667 if (isa_irq == 0) /* doesn't exist */
1669 --isa_irq; /* make it zero based */
1671 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1675 return (1 << apic_pin); /* convert pin# to a mask */
1679 * Determine which APIC pin an ISA/EISA INT is attached to.
1681 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1682 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1683 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1684 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1686 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1688 isa_apic_irq(int isa_irq)
1692 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1693 if (INTTYPE(intr) == 0) { /* standard INT */
1694 if (SRCBUSIRQ(intr) == isa_irq) {
1695 if (apic_int_is_bus_type(intr, ISA) ||
1696 apic_int_is_bus_type(intr, EISA)) {
1697 if (INTIRQ(intr) == 0xff)
1698 return -1; /* unassigned */
1699 return INTIRQ(intr); /* found */
1704 return -1; /* NOT found */
1709 * Determine which APIC pin a PCI INT is attached to.
1711 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1712 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1713 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1715 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1719 --pciInt; /* zero based */
1721 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1722 if ((INTTYPE(intr) == 0) /* standard INT */
1723 && (SRCBUSID(intr) == pciBus)
1724 && (SRCBUSDEVICE(intr) == pciDevice)
1725 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1726 if (apic_int_is_bus_type(intr, PCI)) {
1727 if (INTIRQ(intr) == 0xff) {
1728 kprintf("IOAPIC: pci_apic_irq() "
1730 return -1; /* unassigned */
1732 return INTIRQ(intr); /* exact match */
1737 return -1; /* NOT found */
1741 next_apic_irq(int irq)
1748 for (intr = 0; intr < nintrs; intr++) {
1749 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1751 bus = SRCBUSID(intr);
1752 bustype = apic_bus_type(bus);
1753 if (bustype != ISA &&
1759 if (intr >= nintrs) {
1762 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1763 if (INTTYPE(ointr) != 0)
1765 if (bus != SRCBUSID(ointr))
1767 if (bustype == PCI) {
1768 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1770 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1773 if (bustype == ISA || bustype == EISA) {
1774 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1777 if (INTPIN(intr) == INTPIN(ointr))
1781 if (ointr >= nintrs) {
1784 return INTIRQ(ointr);
1797 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1800 * Exactly what this means is unclear at this point. It is a solution
1801 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1802 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1803 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1807 undirect_isa_irq(int rirq)
1811 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1812 /** FIXME: tickle the MB redirector chip */
1816 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1823 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1826 undirect_pci_irq(int rirq)
1830 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1832 /** FIXME: tickle the MB redirector chip */
1836 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1844 * given a bus ID, return:
1845 * the bus type if found
1849 apic_bus_type(int id)
1853 for (x = 0; x < mp_nbusses; ++x)
1854 if (bus_data[x].bus_id == id)
1855 return bus_data[x].bus_type;
1861 * given a LOGICAL APIC# and pin#, return:
1862 * the associated src bus ID if found
1866 apic_src_bus_id(int apic, int pin)
1870 /* search each of the possible INTerrupt sources */
1871 for (x = 0; x < nintrs; ++x)
1872 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1873 (pin == io_apic_ints[x].dst_apic_int))
1874 return (io_apic_ints[x].src_bus_id);
1876 return -1; /* NOT found */
1880 * given a LOGICAL APIC# and pin#, return:
1881 * the associated src bus IRQ if found
1885 apic_src_bus_irq(int apic, int pin)
1889 for (x = 0; x < nintrs; x++)
1890 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1891 (pin == io_apic_ints[x].dst_apic_int))
1892 return (io_apic_ints[x].src_bus_irq);
1894 return -1; /* NOT found */
1899 * given a LOGICAL APIC# and pin#, return:
1900 * the associated INTerrupt type if found
1904 apic_int_type(int apic, int pin)
1908 /* search each of the possible INTerrupt sources */
1909 for (x = 0; x < nintrs; ++x) {
1910 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1911 (pin == io_apic_ints[x].dst_apic_int))
1912 return (io_apic_ints[x].int_type);
1914 return -1; /* NOT found */
1918 * Return the IRQ associated with an APIC pin
1921 apic_irq(int apic, int pin)
1926 for (x = 0; x < nintrs; ++x) {
1927 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1928 (pin == io_apic_ints[x].dst_apic_int)) {
1929 res = io_apic_ints[x].int_vector;
1932 if (apic != int_to_apicintpin[res].ioapic)
1933 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1934 if (pin != int_to_apicintpin[res].int_pin)
1935 panic("apic_irq inconsistent table (2)");
1944 * given a LOGICAL APIC# and pin#, return:
1945 * the associated trigger mode if found
1949 apic_trigger(int apic, int pin)
1953 /* search each of the possible INTerrupt sources */
1954 for (x = 0; x < nintrs; ++x)
1955 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1956 (pin == io_apic_ints[x].dst_apic_int))
1957 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1959 return -1; /* NOT found */
1964 * given a LOGICAL APIC# and pin#, return:
1965 * the associated 'active' level if found
1969 apic_polarity(int apic, int pin)
1973 /* search each of the possible INTerrupt sources */
1974 for (x = 0; x < nintrs; ++x)
1975 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1976 (pin == io_apic_ints[x].dst_apic_int))
1977 return (io_apic_ints[x].int_flags & 0x03);
1979 return -1; /* NOT found */
1983 * set data according to MP defaults
1984 * FIXME: probably not complete yet...
1987 mptable_default(int type)
1993 kprintf(" MP default config type: %d\n", type);
1996 kprintf(" bus: ISA, APIC: 82489DX\n");
1999 kprintf(" bus: EISA, APIC: 82489DX\n");
2002 kprintf(" bus: EISA, APIC: 82489DX\n");
2005 kprintf(" bus: MCA, APIC: 82489DX\n");
2008 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2011 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2014 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2017 kprintf(" future type\n");
2023 /* one and only IO APIC */
2024 io_apic_id = (ioapic_read(ioapic[0], IOAPIC_ID) & APIC_ID_MASK) >> 24;
2027 * sanity check, refer to MP spec section 3.6.6, last paragraph
2028 * necessary as some hardware isn't properly setting up the IO APIC
2030 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2031 if (io_apic_id != 2) {
2033 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2034 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2035 io_apic_set_id(0, 2);
2038 IO_TO_ID(0) = io_apic_id;
2039 ID_TO_IO(io_apic_id) = 0;
2041 /* fill out bus entries */
2050 bus_data[0].bus_id = default_data[type - 1][1];
2051 bus_data[0].bus_type = default_data[type - 1][2];
2052 bus_data[1].bus_id = default_data[type - 1][3];
2053 bus_data[1].bus_type = default_data[type - 1][4];
2056 /* case 4: case 7: MCA NOT supported */
2057 default: /* illegal/reserved */
2058 panic("BAD default MP config: %d", type);
2062 /* general cases from MP v1.4, table 5-2 */
2063 for (pin = 0; pin < 16; ++pin) {
2064 io_apic_ints[pin].int_type = 0;
2065 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2066 io_apic_ints[pin].src_bus_id = 0;
2067 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2068 io_apic_ints[pin].dst_apic_id = io_apic_id;
2069 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2072 /* special cases from MP v1.4, table 5-2 */
2074 io_apic_ints[2].int_type = 0xff; /* N/C */
2075 io_apic_ints[13].int_type = 0xff; /* N/C */
2076 #if !defined(APIC_MIXED_MODE)
2078 panic("sorry, can't support type 2 default yet");
2079 #endif /* APIC_MIXED_MODE */
2082 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2085 io_apic_ints[0].int_type = 0xff; /* N/C */
2087 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2091 * Map a physical memory address representing I/O into KVA. The I/O
2092 * block is assumed not to cross a page boundary.
2095 permanent_io_mapping(vm_paddr_t pa)
2101 KKASSERT(pa < 0x100000000LL);
2103 pgeflag = 0; /* not used for SMP yet */
2106 * If the requested physical address has already been incidently
2107 * mapped, just use the existing mapping. Otherwise create a new
2110 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2111 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2112 ((vm_offset_t)pa & PG_FRAME)) {
2116 if (i == SMPpt_alloc_index) {
2117 if (i == NPTEPG - 2) {
2118 panic("permanent_io_mapping: We ran out of space"
2121 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2122 ((vm_offset_t)pa & PG_FRAME));
2123 ++SMPpt_alloc_index;
2125 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2126 ((vm_offset_t)pa & PAGE_MASK);
2127 return ((void *)vaddr);
2131 * start each AP in our list
2134 start_all_aps(u_int boot_addr)
2141 u_char mpbiosreason;
2142 u_long mpbioswarmvec;
2143 struct mdglobaldata *gd;
2144 struct privatespace *ps;
2148 POSTCODE(START_ALL_APS_POST);
2150 /* Initialize BSP's local APIC */
2151 apic_initialize(TRUE);
2154 MachIntrABI.finalize();
2156 /* install the AP 1st level boot code */
2157 install_ap_tramp(boot_addr);
2160 /* save the current value of the warm-start vector */
2161 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2162 outb(CMOS_REG, BIOS_RESET);
2163 mpbiosreason = inb(CMOS_DATA);
2165 /* setup a vector to our boot code */
2166 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2167 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2168 outb(CMOS_REG, BIOS_RESET);
2169 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2172 * If we have a TSC we can figure out the SMI interrupt rate.
2173 * The SMI does not necessarily use a constant rate. Spend
2174 * up to 250ms trying to figure it out.
2177 if (cpu_feature & CPUID_TSC) {
2178 set_apic_timer(275000);
2179 smilast = read_apic_timer();
2180 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2181 smicount = smitest();
2182 if (smibest == 0 || smilast - smicount < smibest)
2183 smibest = smilast - smicount;
2186 if (smibest > 250000)
2189 smibest = smibest * (int64_t)1000000 /
2190 get_apic_timer_frequency();
2194 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2195 1000000 / smibest, smibest);
2198 /* set up temporary P==V mapping for AP boot */
2199 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2200 kptbase = (uintptr_t)(void *)KPTphys;
2201 for (x = 0; x < NKPT; x++) {
2202 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2203 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2208 for (x = 1; x <= mp_naps; ++x) {
2210 /* This is a bit verbose, it will go away soon. */
2212 /* first page of AP's private space */
2213 pg = x * i386_btop(sizeof(struct privatespace));
2215 /* allocate new private data page(s) */
2216 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2217 MDGLOBALDATA_BASEALLOC_SIZE);
2218 /* wire it into the private page table page */
2219 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2220 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2221 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2223 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2225 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2226 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2227 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2228 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2230 /* allocate and set up an idle stack data page */
2231 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2232 for (i = 0; i < UPAGES; i++) {
2233 SMPpt[pg + 4 + i] = (pt_entry_t)
2234 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2237 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2238 bzero(gd, sizeof(*gd));
2239 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2241 /* prime data page for it to use */
2242 mi_gdinit(&gd->mi, x);
2244 gd->gd_CMAP1 = &SMPpt[pg + 0];
2245 gd->gd_CMAP2 = &SMPpt[pg + 1];
2246 gd->gd_CMAP3 = &SMPpt[pg + 2];
2247 gd->gd_PMAP1 = &SMPpt[pg + 3];
2248 gd->gd_CADDR1 = ps->CPAGE1;
2249 gd->gd_CADDR2 = ps->CPAGE2;
2250 gd->gd_CADDR3 = ps->CPAGE3;
2251 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2254 * Per-cpu pmap for get_ptbase().
2256 gd->gd_GDADDR1= (unsigned *)
2257 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2258 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2260 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2261 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2264 * Setup the AP boot stack
2266 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2269 /* attempt to start the Application Processor */
2270 CHECK_INIT(99); /* setup checkpoints */
2271 if (!start_ap(gd, boot_addr, smibest)) {
2272 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2273 CHECK_PRINT("trace"); /* show checkpoints */
2274 /* better panic as the AP may be running loose */
2275 kprintf("panic y/n? [y] ");
2276 if (cngetc() != 'n')
2279 CHECK_PRINT("trace"); /* show checkpoints */
2281 /* record its version info */
2282 cpu_apic_versions[x] = cpu_apic_versions[0];
2285 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2288 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2289 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2292 ncpus2_shift = shift;
2293 ncpus2 = 1 << shift;
2294 ncpus2_mask = ncpus2 - 1;
2296 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2297 if ((1 << shift) < ncpus)
2299 ncpus_fit = 1 << shift;
2300 ncpus_fit_mask = ncpus_fit - 1;
2302 /* build our map of 'other' CPUs */
2303 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2304 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2305 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2307 /* fill in our (BSP) APIC version */
2308 cpu_apic_versions[0] = lapic.version;
2310 /* restore the warmstart vector */
2311 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2312 outb(CMOS_REG, BIOS_RESET);
2313 outb(CMOS_DATA, mpbiosreason);
2316 * NOTE! The idlestack for the BSP was setup by locore. Finish
2317 * up, clean out the P==V mapping we did earlier.
2319 for (x = 0; x < NKPT; x++)
2323 /* number of APs actually started */
2328 * load the 1st level AP boot code into base memory.
2331 /* targets for relocation */
2332 extern void bigJump(void);
2333 extern void bootCodeSeg(void);
2334 extern void bootDataSeg(void);
2335 extern void MPentry(void);
2336 extern u_int MP_GDT;
2337 extern u_int mp_gdtbase;
2340 install_ap_tramp(u_int boot_addr)
2343 int size = *(int *) ((u_long) & bootMP_size);
2344 u_char *src = (u_char *) ((u_long) bootMP);
2345 u_char *dst = (u_char *) boot_addr + KERNBASE;
2346 u_int boot_base = (u_int) bootMP;
2351 POSTCODE(INSTALL_AP_TRAMP_POST);
2353 for (x = 0; x < size; ++x)
2357 * modify addresses in code we just moved to basemem. unfortunately we
2358 * need fairly detailed info about mpboot.s for this to work. changes
2359 * to mpboot.s might require changes here.
2362 /* boot code is located in KERNEL space */
2363 dst = (u_char *) boot_addr + KERNBASE;
2365 /* modify the lgdt arg */
2366 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2367 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2369 /* modify the ljmp target for MPentry() */
2370 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2371 *dst32 = ((u_int) MPentry - KERNBASE);
2373 /* modify the target for boot code segment */
2374 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2375 dst8 = (u_int8_t *) (dst16 + 1);
2376 *dst16 = (u_int) boot_addr & 0xffff;
2377 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2379 /* modify the target for boot data segment */
2380 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2381 dst8 = (u_int8_t *) (dst16 + 1);
2382 *dst16 = (u_int) boot_addr & 0xffff;
2383 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2388 * This function starts the AP (application processor) identified
2389 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2390 * to accomplish this. This is necessary because of the nuances
2391 * of the different hardware we might encounter. It ain't pretty,
2392 * but it seems to work.
2394 * NOTE: eventually an AP gets to ap_init(), which is called just
2395 * before the AP goes into the LWKT scheduler's idle loop.
2398 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2402 u_long icr_lo, icr_hi;
2404 POSTCODE(START_AP_POST);
2406 /* get the PHYSICAL APIC ID# */
2407 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2409 /* calculate the vector */
2410 vector = (boot_addr >> 12) & 0xff;
2412 /* We don't want anything interfering */
2415 /* Make sure the target cpu sees everything */
2419 * Try to detect when a SMI has occurred, wait up to 200ms.
2421 * If a SMI occurs during an AP reset but before we issue
2422 * the STARTUP command, the AP may brick. To work around
2423 * this problem we hold off doing the AP startup until
2424 * after we have detected the SMI. Hopefully another SMI
2425 * will not occur before we finish the AP startup.
2427 * Retries don't seem to help. SMIs have a window of opportunity
2428 * and if USB->legacy keyboard emulation is enabled in the BIOS
2429 * the interrupt rate can be quite high.
2431 * NOTE: Don't worry about the L1 cache load, it might bloat
2432 * ldelta a little but ndelta will be so huge when the SMI
2433 * occurs the detection logic will still work fine.
2436 set_apic_timer(200000);
2441 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2442 * and running the target CPU. OR this INIT IPI might be latched (P5
2443 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2446 * see apic/apicreg.h for icr bit definitions.
2448 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2452 * Setup the address for the target AP. We can setup
2453 * icr_hi once and then just trigger operations with
2456 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2457 icr_hi |= (physical_cpu << 24);
2458 icr_lo = lapic.icr_lo & 0xfff00000;
2459 lapic.icr_hi = icr_hi;
2462 * Do an INIT IPI: assert RESET
2464 * Use edge triggered mode to assert INIT
2466 lapic.icr_lo = icr_lo | 0x0000c500;
2467 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2471 * The spec calls for a 10ms delay but we may have to use a
2472 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2473 * interrupt. We have other loops here too and dividing by 2
2474 * doesn't seem to be enough even after subtracting 350us,
2475 * so we divide by 4.
2477 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2478 * interrupt was detected we use the full 10ms.
2482 else if (smibest < 150 * 4 + 350)
2484 else if ((smibest - 350) / 4 < 10000)
2485 u_sleep((smibest - 350) / 4);
2490 * Do an INIT IPI: deassert RESET
2492 * Use level triggered mode to deassert. It is unclear
2493 * why we need to do this.
2495 lapic.icr_lo = icr_lo | 0x00008500;
2496 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2498 u_sleep(150); /* wait 150us */
2501 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2502 * latched, (P5 bug) this 1st STARTUP would then terminate
2503 * immediately, and the previously started INIT IPI would continue. OR
2504 * the previous INIT IPI has already run. and this STARTUP IPI will
2505 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2508 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2509 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2511 u_sleep(200); /* wait ~200uS */
2514 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2515 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2516 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2517 * recognized after hardware RESET or INIT IPI.
2519 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2520 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2523 /* Resume normal operation */
2526 /* wait for it to start, see ap_init() */
2527 set_apic_timer(5000000);/* == 5 seconds */
2528 while (read_apic_timer()) {
2529 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2530 return 1; /* return SUCCESS */
2533 return 0; /* return FAILURE */
2548 while (read_apic_timer()) {
2550 for (count = 0; count < 100; ++count)
2551 ntsc = rdtsc(); /* force loop to occur */
2553 ndelta = ntsc - ltsc;
2554 if (ldelta > ndelta)
2556 if (ndelta > ldelta * 2)
2559 ldelta = ntsc - ltsc;
2562 return(read_apic_timer());
2566 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2568 * If for some reason we were unable to start all cpus we cannot safely
2569 * use broadcast IPIs.
2572 static cpumask_t smp_invltlb_req;
2573 #define SMP_INVLTLB_DEBUG
2579 struct mdglobaldata *md = mdcpu;
2580 #ifdef SMP_INVLTLB_DEBUG
2585 crit_enter_gd(&md->mi);
2586 md->gd_invltlb_ret = 0;
2587 ++md->mi.gd_cnt.v_smpinvltlb;
2588 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2589 #ifdef SMP_INVLTLB_DEBUG
2592 if (smp_startup_mask == smp_active_mask) {
2593 all_but_self_ipi(XINVLTLB_OFFSET);
2595 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2596 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2599 #ifdef SMP_INVLTLB_DEBUG
2601 kprintf("smp_invltlb: ipi sent\n");
2603 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2604 (smp_active_mask & ~md->mi.gd_cpumask)) {
2607 #ifdef SMP_INVLTLB_DEBUG
2609 if (++count == 400000000) {
2610 print_backtrace(-1);
2611 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2612 "rflags %016lx retry",
2613 (long)md->gd_invltlb_ret,
2614 (long)smp_invltlb_req,
2615 (long)read_eflags());
2616 __asm __volatile ("sti");
2619 lwkt_process_ipiq();
2621 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2622 ~md->mi.gd_cpumask &
2625 kprintf("bcpu %d\n", bcpu);
2626 xgd = globaldata_find(bcpu);
2627 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2636 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2637 crit_exit_gd(&md->mi);
2644 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2645 * bother to bump the critical section count or nested interrupt count
2646 * so only do very low level operations here.
2649 smp_invltlb_intr(void)
2651 struct mdglobaldata *md = mdcpu;
2652 struct mdglobaldata *omd;
2656 mask = smp_invltlb_req;
2660 cpu = BSFCPUMASK(mask);
2661 mask &= ~CPUMASK(cpu);
2662 omd = (struct mdglobaldata *)globaldata_find(cpu);
2663 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2670 * When called the executing CPU will send an IPI to all other CPUs
2671 * requesting that they halt execution.
2673 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2675 * - Signals all CPUs in map to stop.
2676 * - Waits for each to stop.
2683 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2684 * from executing at same time.
2687 stop_cpus(cpumask_t map)
2689 map &= smp_active_mask;
2691 /* send the Xcpustop IPI to all CPUs in map */
2692 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2694 while ((stopped_cpus & map) != map)
2702 * Called by a CPU to restart stopped CPUs.
2704 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2706 * - Signals all CPUs in map to restart.
2707 * - Waits for each to restart.
2715 restart_cpus(cpumask_t map)
2717 /* signal other cpus to restart */
2718 started_cpus = map & smp_active_mask;
2720 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2727 * This is called once the mpboot code has gotten us properly relocated
2728 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2729 * and when it returns the scheduler will call the real cpu_idle() main
2730 * loop for the idlethread. Interrupts are disabled on entry and should
2731 * remain disabled at return.
2739 * Adjust smp_startup_mask to signal the BSP that we have started
2740 * up successfully. Note that we do not yet hold the BGL. The BSP
2741 * is waiting for our signal.
2743 * We can't set our bit in smp_active_mask yet because we are holding
2744 * interrupts physically disabled and remote cpus could deadlock
2745 * trying to send us an IPI.
2747 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2751 * Interlock for finalization. Wait until mp_finish is non-zero,
2752 * then get the MP lock.
2754 * Note: We are in a critical section.
2756 * Note: we are the idle thread, we can only spin.
2758 * Note: The load fence is memory volatile and prevents the compiler
2759 * from improperly caching mp_finish, and the cpu from improperly
2762 while (mp_finish == 0)
2764 while (try_mplock() == 0)
2767 if (cpu_feature & CPUID_TSC) {
2769 * The BSP is constantly updating tsc0_offset, figure out
2770 * the relative difference to synchronize ktrdump.
2772 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2775 /* BSP may have changed PTD while we're waiting for the lock */
2778 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2782 /* Build our map of 'other' CPUs. */
2783 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2785 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2787 /* A quick check from sanity claus */
2788 apic_id = (apic_id_to_logical[(lapic.id & 0xff000000) >> 24]);
2789 if (mycpu->gd_cpuid != apic_id) {
2790 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2791 kprintf("SMP: apic_id = %d\n", apic_id);
2792 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2793 panic("cpuid mismatch! boom!!");
2796 /* Initialize AP's local APIC for irq's */
2797 apic_initialize(FALSE);
2799 /* Set memory range attributes for this CPU to match the BSP */
2800 mem_range_AP_init();
2803 * Once we go active we must process any IPIQ messages that may
2804 * have been queued, because no actual IPI will occur until we
2805 * set our bit in the smp_active_mask. If we don't the IPI
2806 * message interlock could be left set which would also prevent
2809 * The idle loop doesn't expect the BGL to be held and while
2810 * lwkt_switch() normally cleans things up this is a special case
2811 * because we returning almost directly into the idle loop.
2813 * The idle thread is never placed on the runq, make sure
2814 * nothing we've done put it there.
2816 KKASSERT(get_mplock_count(curthread) == 1);
2817 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2820 * Enable interrupts here. idle_restore will also do it, but
2821 * doing it here lets us clean up any strays that got posted to
2822 * the CPU during the AP boot while we are still in a critical
2825 __asm __volatile("sti; pause; pause"::);
2826 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2828 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2829 lwkt_process_ipiq();
2832 * Releasing the mp lock lets the BSP finish up the SMP init
2835 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2839 * Get SMP fully working before we start initializing devices.
2847 kprintf("Finish MP startup\n");
2848 if (cpu_feature & CPUID_TSC)
2849 tsc0_offset = rdtsc();
2852 while (smp_active_mask != smp_startup_mask) {
2854 if (cpu_feature & CPUID_TSC)
2855 tsc0_offset = rdtsc();
2857 while (try_mplock() == 0)
2860 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2863 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2866 cpu_send_ipiq(int dcpu)
2868 if (CPUMASK(dcpu) & smp_active_mask)
2869 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2872 #if 0 /* single_apic_ipi_passive() not working yet */
2874 * Returns 0 on failure, 1 on success
2877 cpu_send_ipiq_passive(int dcpu)
2880 if (CPUMASK(dcpu) & smp_active_mask) {
2881 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2882 APIC_DELMODE_FIXED);
2889 mptable_bus_info_callback(void *xarg, const void *pos, int type)
2891 struct mptable_bus_info *bus_info = xarg;
2892 const struct BUSENTRY *ent;
2893 struct mptable_bus *bus;
2900 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
2901 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2902 bus->mb_type = MPTABLE_BUS_PCI;
2903 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
2904 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2905 bus->mb_type = MPTABLE_BUS_ISA;
2909 const struct mptable_bus *bus1;
2911 TAILQ_FOREACH(bus1, &bus_info->mbi_list, mb_link) {
2912 if (bus1->mb_id == ent->bus_id) {
2913 kprintf("mptable_bus_info_alloc: "
2914 "duplicated bus id (%d)\n", bus1->mb_id);
2920 bus->mb_id = ent->bus_id;
2921 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
2931 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
2935 bzero(bus_info, sizeof(*bus_info));
2936 TAILQ_INIT(&bus_info->mbi_list);
2938 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
2940 mptable_bus_info_free(bus_info);
2944 mptable_bus_info_free(struct mptable_bus_info *bus_info)
2946 struct mptable_bus *bus;
2948 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
2949 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
2954 struct mptable_lapic_cbarg1 {
2957 u_int ht_apicid_mask;
2961 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2963 const struct PROCENTRY *ent;
2964 struct mptable_lapic_cbarg1 *arg = xarg;
2970 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2974 if (ent->apic_id < 32) {
2975 arg->ht_apicid_mask |= 1 << ent->apic_id;
2976 } else if (arg->ht_fixup) {
2977 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2983 struct mptable_lapic_cbarg2 {
2990 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2992 const struct PROCENTRY *ent;
2993 struct mptable_lapic_cbarg2 *arg = xarg;
2999 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3000 KKASSERT(!arg->found_bsp);
3004 if (processor_entry(ent, arg->cpu))
3007 if (arg->logical_cpus) {
3008 struct PROCENTRY proc;
3012 * Create fake mptable processor entries
3013 * and feed them to processor_entry() to
3014 * enumerate the logical CPUs.
3016 bzero(&proc, sizeof(proc));
3018 proc.cpu_flags = PROCENTRY_FLAG_EN;
3019 proc.apic_id = ent->apic_id;
3021 for (i = 1; i < arg->logical_cpus; i++) {
3023 processor_entry(&proc, arg->cpu);
3031 mptable_imcr(struct mptable_pos *mpt)
3033 /* record whether PIC or virtual-wire mode */
3034 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
3035 mpt->mp_fps->mpfb2 & 0x80);
3039 mptable_lapic_default(void)
3041 int ap_apicid, bsp_apicid;
3043 mp_naps = 1; /* exclude BSP */
3045 /* Map local apic before the id field is accessed */
3046 lapic_map(DEFAULT_APIC_BASE);
3048 bsp_apicid = APIC_ID(lapic.id);
3049 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3052 mp_set_cpuids(0, bsp_apicid);
3053 /* one and only AP */
3054 mp_set_cpuids(1, ap_apicid);
3060 * ID_TO_CPU(N), APIC ID to logical CPU table
3061 * CPU_TO_ID(N), logical CPU to APIC ID table
3064 mptable_lapic_enumerate(struct lapic_enumerator *e)
3066 struct mptable_pos mpt;
3067 struct mptable_lapic_cbarg1 arg1;
3068 struct mptable_lapic_cbarg2 arg2;
3070 int error, logical_cpus = 0;
3071 vm_offset_t lapic_addr;
3073 if (mptable_use_default) {
3074 mptable_lapic_default();
3078 error = mptable_map(&mpt);
3080 panic("mptable_lapic_enumerate mptable_map failed\n");
3081 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3085 /* Save local apic address */
3086 lapic_addr = (vm_offset_t)cth->apic_address;
3087 KKASSERT(lapic_addr != 0);
3090 * Find out how many CPUs do we have
3092 bzero(&arg1, sizeof(arg1));
3093 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3095 error = mptable_iterate_entries(cth,
3096 mptable_lapic_pass1_callback, &arg1);
3098 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3099 KKASSERT(arg1.cpu_count != 0);
3101 /* See if we need to fixup HT logical CPUs. */
3102 if (arg1.ht_fixup) {
3103 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3105 if (logical_cpus != 0)
3106 arg1.cpu_count *= logical_cpus;
3108 mp_naps = arg1.cpu_count;
3110 /* Qualify the numbers again, after possible HT fixup */
3111 if (mp_naps > MAXCPU) {
3112 kprintf("Warning: only using %d of %d available CPUs!\n",
3117 --mp_naps; /* subtract the BSP */
3120 * Link logical CPU id to local apic id
3122 bzero(&arg2, sizeof(arg2));
3124 arg2.logical_cpus = logical_cpus;
3126 error = mptable_iterate_entries(cth,
3127 mptable_lapic_pass2_callback, &arg2);
3129 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3130 KKASSERT(arg2.found_bsp);
3132 /* Map local apic */
3133 lapic_map(lapic_addr);
3135 mptable_unmap(&mpt);
3138 struct mptable_lapic_probe_cbarg {
3144 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
3146 const struct PROCENTRY *ent;
3147 struct mptable_lapic_probe_cbarg *arg = xarg;
3153 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3157 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3158 if (arg->found_bsp) {
3159 kprintf("more than one BSP in base MP table\n");
3168 mptable_lapic_probe(struct lapic_enumerator *e)
3170 struct mptable_pos mpt;
3171 struct mptable_lapic_probe_cbarg arg;
3175 if (mptable_fps_phyaddr == 0)
3178 if (mptable_use_default)
3181 error = mptable_map(&mpt);
3184 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3189 if (cth->apic_address == 0)
3192 bzero(&arg, sizeof(arg));
3193 error = mptable_iterate_entries(cth,
3194 mptable_lapic_probe_callback, &arg);
3196 if (arg.cpu_count == 0) {
3197 kprintf("MP table contains no processor entries\n");
3199 } else if (!arg.found_bsp) {
3200 kprintf("MP table does not contains BSP entry\n");
3205 mptable_unmap(&mpt);
3209 static struct lapic_enumerator mptable_lapic_enumerator = {
3210 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3211 .lapic_probe = mptable_lapic_probe,
3212 .lapic_enumerate = mptable_lapic_enumerate
3216 mptable_lapic_enum_register(void)
3218 lapic_enumerator_register(&mptable_lapic_enumerator);
3220 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3221 mptable_lapic_enum_register, 0);
3224 mptable_pci_int_callback(void *xarg, const void *pos, int type)
3226 const struct mptable_bus_info *bus_info = xarg;
3227 const struct mptable_bus *bus;
3228 struct mptable_pci_int *pci_int;
3229 const struct INTENTRY *ent;
3230 int pci_pin, pci_dev;
3236 if (ent->int_type != 0)
3239 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
3240 if (bus->mb_type == MPTABLE_BUS_PCI &&
3241 bus->mb_id == ent->src_bus_id)
3247 pci_pin = ent->src_bus_irq & 0x3;
3248 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
3250 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
3251 if (pci_int->mpci_bus == ent->src_bus_id &&
3252 pci_int->mpci_dev == pci_dev &&
3253 pci_int->mpci_pin == pci_pin) {
3254 if (pci_int->mpci_ioapic == ent->dst_apic_id &&
3255 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
3256 kprintf("MPTABLE: warning duplicated "
3257 "PCI int entry for "
3258 "bus %d, dev %d, pin %d\n",
3264 kprintf("mptable_pci_int_register: "
3265 "conflict PCI int entry for "
3266 "bus %d, dev %d, pin %d, "
3267 "IOAPIC %d.%d -> %d.%d\n",
3271 pci_int->mpci_ioapic,
3272 pci_int->mpci_ioapic_pin,
3280 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
3282 pci_int->mpci_bus = ent->src_bus_id;
3283 pci_int->mpci_dev = pci_dev;
3284 pci_int->mpci_pin = pci_pin;
3285 pci_int->mpci_ioapic = ent->dst_apic_id;
3286 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
3288 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
3294 mptable_pci_int_register(void)
3296 struct mptable_bus_info bus_info;
3297 const struct mptable_bus *bus;
3298 struct mptable_pci_int *pci_int;
3299 struct mptable_pos mpt;
3300 int error, force_pci0, npcibus;
3303 if (mptable_fps_phyaddr == 0)
3306 if (mptable_use_default)
3309 error = mptable_map(&mpt);
3311 panic("mptable_pci_int_register: mptable_map failed\n");
3312 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3316 mptable_bus_info_alloc(cth, &bus_info);
3317 if (TAILQ_EMPTY(&bus_info.mbi_list))
3321 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
3322 if (bus->mb_type == MPTABLE_BUS_PCI)
3326 mptable_bus_info_free(&bus_info);
3328 } else if (npcibus == 1) {
3332 error = mptable_iterate_entries(cth,
3333 mptable_pci_int_callback, &bus_info);
3335 mptable_bus_info_free(&bus_info);
3338 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
3339 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
3340 kfree(pci_int, M_DEVBUF);
3346 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
3347 pci_int->mpci_bus = 0;
3350 mptable_unmap(&mpt);
3352 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3353 mptable_pci_int_register, 0);
3355 struct mptable_ioapic_probe_cbarg {
3356 const struct mptable_bus_info *bus_info;
3361 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
3363 struct mptable_ioapic_probe_cbarg *arg = xarg;
3366 const struct INTENTRY *ent = pos;
3367 const struct mptable_bus *bus;
3369 if (ent->int_type != 0)
3372 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3373 if (bus->mb_type == MPTABLE_BUS_ISA &&
3374 bus->mb_id == ent->src_bus_id)
3380 /* XXX magic number */
3381 if (ent->src_bus_irq >= 16) {
3382 kprintf("mptable_ioapic_probe: invalid ISA irq "
3383 "(%d)\n", ent->src_bus_irq);
3386 } else if (type == 2) {
3387 const struct IOAPICENTRY *ent = pos;
3389 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
3392 if (ent->apic_address == 0) {
3393 kprintf("mptable_ioapic_probe: zero IOAPIC address\n");
3402 mptable_ioapic_probe(struct ioapic_enumerator *e)
3404 struct mptable_ioapic_probe_cbarg arg;
3405 struct mptable_bus_info bus_info;
3406 struct mptable_pos mpt;
3410 if (mptable_fps_phyaddr == 0)
3413 if (mptable_use_default)
3416 error = mptable_map(&mpt);
3418 panic("mptable_ioapic_probe: mptable_map failed\n");
3419 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3423 mptable_bus_info_alloc(cth, &bus_info);
3425 bzero(&arg, sizeof(arg));
3426 arg.bus_info = &bus_info;
3428 error = mptable_iterate_entries(cth,
3429 mptable_ioapic_probe_callback, &arg);
3431 if (arg.ioapic_cnt == 0) {
3432 kprintf("mptable_ioapic_probe: no IOAPIC\n");
3437 mptable_bus_info_free(&bus_info);
3438 mptable_unmap(&mpt);
3444 mptable_ioapic_enum_callback(void *xarg, const void *pos, int type)
3446 const struct IOAPICENTRY *ent;
3453 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
3457 kprintf("MPTABLE: IOAPIC addr 0x%08x, apic id %d\n",
3458 (unsigned int)ent->apic_address, ent->apic_id);
3463 struct mptable_ioapic_int_cbarg {
3464 const struct mptable_bus_info *bus_info;
3469 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
3471 struct mptable_ioapic_int_cbarg *arg = xarg;
3472 const struct mptable_bus *bus;
3473 const struct INTENTRY *ent;
3481 if (ent->int_type != 0)
3484 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3485 if (bus->mb_type == MPTABLE_BUS_ISA &&
3486 bus->mb_id == ent->src_bus_id)
3492 /* XXX rough estimation */
3493 if (ent->src_bus_irq != ent->dst_apic_int) {
3495 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3496 ent->src_bus_irq, ent->dst_apic_int);
3503 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
3505 struct mptable_bus_info bus_info;
3506 struct mptable_pos mpt;
3510 KKASSERT(mptable_fps_phyaddr != 0);
3512 if (mptable_use_default) {
3514 kprintf("MPTABLE: IOAPIC address 0xfec00000 "
3516 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
3518 /* TODO default ioapic and intsrc */
3522 error = mptable_map(&mpt);
3524 panic("mptable_ioapic_probe: mptable_map failed\n");
3525 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3529 error = mptable_iterate_entries(cth,
3530 mptable_ioapic_enum_callback, NULL);
3532 panic("mptable_ioapic_enum failed\n");
3534 mptable_bus_info_alloc(cth, &bus_info);
3536 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
3538 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
3539 /* TODO default intsrc */
3541 struct mptable_ioapic_int_cbarg arg;
3543 bzero(&arg, sizeof(arg));
3544 arg.bus_info = &bus_info;
3546 error = mptable_iterate_entries(cth,
3547 mptable_ioapic_int_callback, &arg);
3549 panic("mptable_ioapic_int failed\n");
3551 if (arg.ioapic_nint == 0) {
3553 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
3556 /* TODO default intsrc */
3560 mptable_bus_info_free(&bus_info);
3562 mptable_unmap(&mpt);
3565 static struct ioapic_enumerator mptable_ioapic_enumerator = {
3566 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
3567 .ioapic_probe = mptable_ioapic_probe,
3568 .ioapic_enumerate = mptable_ioapic_enumerate
3572 mptable_ioapic_enum_register(void)
3574 ioapic_enumerator_register(&mptable_ioapic_enumerator);
3576 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3577 mptable_ioapic_enum_register, 0);