2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/lge/if_lgereg.h,v 1.2.2.1 2001/06/19 19:42:38 wpaul Exp $
34 * $DragonFly: src/sys/dev/netif/lge/if_lgereg.h,v 1.9 2005/11/29 19:56:51 dillon Exp $
38 #define LGE_MODE1 0x00 /* CSR00 */
39 #define LGE_MODE2 0x04 /* CSR01 */
40 #define LGE_PPTXBUF_IDX 0x08 /* CSR02 */
41 #define LGE_PRODID 0x0C /* CSR03 */
42 #define LGE_PPTXBUF_ADDR_LO 0x10 /* CSR04 */
43 #define LGE_PPTXBUF_ADDR_HI 0x14 /* CSR05 */
44 #define LGE_RSVD0 0x18 /* CSR06 */
45 #define LGE_PPRXBUF_IDX 0x1C /* CSR07 */
46 #define LGE_PPRXBUF_ADDR_LO 0x20 /* CSR08 */
47 #define LGE_PPRXBUF_ADDR_HI 0x24 /* CSR09 */
48 #define LGE_EECTL 0x28 /* CSR10 */
49 #define LGE_CHIPSTS 0x2C /* CSR11 */
50 #define LGE_TXDESC_ADDR_LO 0x30 /* CSR12 */
51 #define LGE_TXDESC_ADDR_HI 0x34 /* CSR13 */
52 #define LGE_RXDESC_ADDR_LO 0x38 /* CSR14 */
53 #define LGE_RXDESC_ADDR_HI 0x3C /* CSR15 */
54 #define LGE_PPTXCTL 0x40 /* CSR16 */
55 #define LGE_PPRXCTL 0x44 /* CSR17 */
56 #define LGE_INTR_PERIOD 0x48 /* CSR18 */
57 #define LGE_TXFIFO_PKTCNT 0x4C /* CSR19 */
58 #define LGE_TXFIFO_LOWAT 0x50 /* CSR20 */
59 #define LGE_TXFIFO_FREEDWORDS 0x54 /* CSR21 */
60 #define LGE_TXFIFO_WRITE 0x58 /* CSR22 */
61 #define LGE_RSVD1 0x5C /* CSR23 */
62 #define LGE_RXFIFO_READ 0x60 /* CSR24 */
63 #define LGE_RSVD2 0x64 /* CSR25 */
64 #define LGE_RXFIFO_DWORDCNT 0x68 /* CSR26 */
65 #define LGE_RXFIFO_HIWAT 0x6C /* CSR27 */
66 #define LGE_RXFIFO_PKTCNT 0x70 /* CSR28 */
67 #define LGE_CMD 0x74 /* CSR29 */
68 #define LGE_IMR 0x78 /* CSR30 */
69 #define LGE_RSVD3 0x7C /* CSR31 */
70 #define LGE_ISR 0x80 /* CSR32 */
71 #define LGE_RSVD4 0x84 /* CSR33 */
72 #define LGE_MAR0 0x88 /* CSR34 */
73 #define LGE_MAR1 0x8C /* CSR35 */
74 #define LGE_LEDCFG0 0x90 /* CSR36 */
75 #define LGE_LEDCFG1 0x84 /* CSR37 */
76 #define LGE_LEDCFG2 0x98 /* CSR38 */
77 #define LGE_LEDCFG3 0x9C /* CSR39 */
78 #define LGE_RSVD5 0xA0 /* CSR40 */
79 #define LGE_EEDATA 0xA4 /* CSR41 */
80 #define LGE_PAR0 0xA8 /* CSR42 */
81 #define LGE_PAR1 0xAC /* CSR43 */
82 #define LGE_GMIICTL 0xB0 /* CSR44 */
83 #define LGE_GMIIMODE 0xB4 /* CSR45 */
84 #define LGE_STATSIDX 0xB8 /* CSR46 */
85 #define LGE_STATSVAL 0xBC /* CSR47 */
86 #define LGE_VLANCTL 0xC0 /* CSR48 */
87 #define LGE_RSVD6 0xC4 /* CSR49 */
88 #define LGE_RSVD7 0xC8 /* CSR50 */
89 #define LGE_CMDSTS 0xCC /* CSR51 */
90 #define LGE_FLOWCTL_WAT 0xD0 /* CSR52 */
91 #define LGE_RSVD8 0xD4 /* CSR53 */
92 #define LGE_RSVD9 0xD8 /* CSR54 */
93 #define LGE_RSVD10 0xDC /* CSR55 */
94 #define LGE_RSVD11 0xE0 /* CSR56 */
95 #define LGE_RSVD12 0xE4 /* CSR57 */
96 #define LGE_TIMER0_CNT 0xE8 /* CSR58 */
97 #define LGE_TIMER0_INT 0xEC /* CSR59 */
98 #define LGE_TIMER1_CNT 0xF0 /* CSR60 */
99 #define LGE_TIMER1_INT 0xF4 /* CSR61 */
100 #define LGE_DBG_CMD 0xF8 /* CSR62 */
101 #define LGE_DBG_DATA 0xFC /* CSR63 */
104 /* Mode register 1 */
105 #define LGE_MODE1_SETRST_CTL0 0x00000001
106 #define LGE_MODE1_SOFTRST 0x00000002
107 #define LGE_MODE1_DEBTOD 0x00000004 /* Not documented? */
108 #define LGE_MODE1_TX_FLOWCTL 0x00000008 /* Not documented? */
109 #define LGE_MODE1_RXTXRIO 0x00000010
110 #define LGE_MODE1_GMIIPOLL 0x00000020
111 #define LGE_MODE1_TXPAD 0x00000040
112 #define LGE_MODE1_RMVPAD 0x00000080 /* Not documented? */
113 #define LGE_MODE1_SETRST_CTL1 0x00000100
114 #define LGE_MODE1_TX_ENB 0x00000200
115 #define LGE_MODE1_RX_ENB 0x00000400
116 #define LGE_MODE1_RX_MCAST 0x00000800
117 #define LGE_MODE1_RX_BCAST 0x00001000
118 #define LGE_MODE1_RX_PROMISC 0x00002000
119 #define LGE_MODE1_RX_UCAST 0x00004000
120 #define LGE_MODE1_RX_GIANTS 0x00008000
121 #define LGE_MODE1_SETRST_CTL2 0x00010000
122 #define LGE_MODE1_RX_CRC 0x00020000
123 #define LGE_MODE1_RX_ERRPKTS 0x00040000
124 #define LGE_MODE1_TX_CRC 0x00080000
125 #define LGE_MODE1_DEMDEN 0x00100000 /* Not documented? */
126 #define LGE_MODE1_MPACK_ENB 0x00200000
127 #define LGE_MODE1_MPACK_BCAST 0x00400000
128 #define LGE_MODE1_RX_FLOWCTL 0x00800000
129 #define LGE_MODE1_SETRST_CTL3 0x01000000
130 #define LGE_MODE1_VLAN_RX 0x02000000
131 #define LGE_MODE1_VLAN_TX 0x04000000
132 #define LGE_MODE1_VLAN_STRIP 0x08000000
133 #define LGE_MODE1_VLAN_INSERT 0x10000000
134 #define LGE_MODE1_GPIO_CTL0 0x20000000
135 #define LGE_MODE1_GPIO_CTL1 0x40000000
136 #define LGE_MODE1_RX_LENCHK 0x80000000
139 /* Mode register 2 */
140 #define LGE_MODE2_LOOPBACK 0x000000E0
141 #define LGE_MODE2_RX_IPCSUM 0x00001000
142 #define LGE_MODE2_RX_TCPCSUM 0x00002000
143 #define LGE_MODE2_RX_UDPCSUM 0x00004000
144 #define LGE_MODE2_RX_ERRCSUM 0x00008000
147 /* EEPROM register */
148 #define LGE_EECTL_HAVE_EEPROM 0x00000001
149 #define LGE_EECTL_CMD_READ 0x00000002
150 #define LGE_EECTL_CMD_WRITE 0x00000004
151 #define LGE_EECTL_CSUMERR 0x00000010
152 #define LGE_EECTL_MULTIACCESS 0x00000020
153 #define LGE_EECTL_SINGLEACCESS 0x00000040
154 #define LGE_EECTL_ADDR 0x00001F00
155 #define LGE_EECTL_ROM_TIMING 0x000F0000
156 #define LGE_EECTL_HAVE_FLASH 0x00100000
157 #define LGE_EECTL_WRITEFLASH 0x00200000
159 #define LGE_EE_NODEADDR_0 0x12
160 #define LGE_EE_NODEADDR_1 0x13
161 #define LGE_EE_NODEADDR_2 0x10
164 /* Chip status register */
165 #define LGE_CHIPSTS_HAVETXSPC 0x00000001 /* have room in TX FIFO for pkt */
166 #define LGE_CHIPSTS_HAVERXPKT 0x00000002 /* RX FIFO holds complete pkt */
167 #define LGE_CHIPSTS_FLOWCTL_STS 0x00000004
168 #define LGE_CHIPSTS_GPIO_STS0 0x00000008
169 #define LGE_CHIPSTS_GPIO_STS1 0x00000010
170 #define LGE_CHIPSTS_TXIDLE 0x00000020
171 #define LGE_CHIPSTS_RXIDLE 0x00000040
174 /* TX PacketPropulsion control register */
175 #define LGE_PPTXCTL_BUFLEN 0x0000FFFF
176 #define LGE_PPTXCTL_BUFID 0x003F0000
177 #define LGE_PPTXCTL_WANTINTR 0x01000000
180 /* RX PacketPropulsion control register */
181 #define LGE_PPRXCTL_BUFLEN 0x0000FFFF
182 #define LGE_PPRXCTL_BUFID 0x003F0000
183 #define LGE_PPRXCTL_WANTINTR 0x10000000
186 /* Command register */
187 #define LGE_CMD_SETRST_CTL0 0x00000001
188 #define LGE_CMD_STARTTX 0x00000002
189 #define LGE_CMD_SKIP_RXPKT 0x00000004
190 #define LGE_CMD_DEL_INTREQ 0x00000008
191 #define LGE_CMD_PER_INTREQ 0x00000010
192 #define LGE_CMD_TIMER0 0x00000020
193 #define LGE_CMD_TIMER1 0x00000040
196 /* Interrupt mask register */
197 #define LGE_IMR_SETRST_CTL0 0x00000001
198 #define LGE_IMR_TXCMDFIFO_EMPTY 0x00000002
199 #define LGE_IMR_TXFIFO_WAT 0x00000004
200 #define LGE_IMR_TXDMA_DONE 0x00000008
201 #define LGE_IMR_DELAYEDINTR 0x00000040
202 #define LGE_IMR_INTR_ENB 0x00000080
203 #define LGE_IMR_SETRST_CTL1 0x00000100
204 #define LGE_IMR_RXCMDFIFO_EMPTY 0x00000200
205 #define LGE_IMR_RXFIFO_WAT 0x00000400
206 #define LGE_IMR_RX_DONE 0x00000800
207 #define LGE_IMR_RXDMA_DONE 0x00001000
208 #define LGE_IMR_PHY_INTR 0x00002000
209 #define LGE_IMR_MAGICPKT 0x00004000
210 #define LGE_IMR_SETRST_CTL2 0x00010000
211 #define LGE_IMR_GPIO0 0x00020000
212 #define LGE_IMR_GPIO1 0x00040000
213 #define LGE_IMR_TIMER0 0x00080000
214 #define LGE_IMR_TIMER1 0x00100000
218 (LGE_IMR_TXCMDFIFO_EMPTY|LGE_IMR_TXDMA_DONE|LGE_IMR_RX_DONE| \
219 LGE_IMR_RXCMDFIFO_EMPTY|LGE_IMR_RXDMA_DONE|LGE_IMR_PHY_INTR)
222 /* Interrupt status register */
223 #define LGE_ISR_TXCMDFIFO_EMPTY 0x00000002
224 #define LGE_ISR_TXFIFO_WAT 0x00000004
225 #define LGE_ISR_TXDMA_DONE 0x00000008
226 #define LGE_ISR_DELAYEDINTR 0x00000040
227 #define LGE_ISR_INTR_ENB 0x00000080
228 #define LGE_ISR_RXCMDFIFO_EMPTY 0x00000200
229 #define LGE_ISR_RXFIFO_WAT 0x00000400
230 #define LGE_ISR_RX_DONE 0x00000800
231 #define LGE_ISR_RXDMA_DONE 0x00001000
232 #define LGE_ISR_PHY_INTR 0x00002000
233 #define LGE_ISR_MAGICPKT 0x00004000
234 #define LGE_ISR_GPIO0 0x00020000
235 #define LGE_ISR_GPIO1 0x00040000
236 #define LGE_ISR_TIMER0 0x00080000
237 #define LGE_ISR_TIMER1 0x00100000
238 #define LGE_ISR_RXDMADONE_CNT 0xFF000000
239 #define LGE_RX_DMACNT(x) ((x & LGE_ISR_RXDMADONE_CNT) >> 24)
241 /* LED0 config register */
242 #define LGE_LED0CFG_ENABLE 0x00000002
243 #define LGE_LED0CFG_INPUT_POL 0x00000004
244 #define LGE_LED0CFG_PULSE_EXP 0x00000008
245 #define LGE_LED0CFG_10MBPS 0x00000010
246 #define LGE_LED0CFG_100MBPS 0x00000100
247 #define LGE_LED0CFG_1000MBPS 0x00000200
248 #define LGE_LED0CFG_FDX 0x00000400
249 #define LGE_LED0CFG_ANEG 0x00000800
250 #define LGE_LED0CFG_LINKSTS 0x00001000
251 #define LGE_LED0CFG_RXMATCH 0x00002000
252 #define LGE_LED0CFG_TX 0x00004000
253 #define LGE_LED0CFG_RX 0x00008000
254 #define LGE_LED0CFG_JABBER 0x00010000
255 #define LGE_LED0CFG_COLLISION 0x00020000
256 #define LGE_LED0CFG_CARRIER 0x00040000
257 #define LGE_LED0CFG_LEDOUT 0x10000000
260 /* LED1 config register */
261 #define LGE_LED1CFG_ENABLE 0x00000002
262 #define LGE_LED1CFG_INPUT_POL 0x00000004
263 #define LGE_LED1CFG_PULSE_EXP 0x00000008
264 #define LGE_LED1CFG_10MBPS 0x00000010
265 #define LGE_LED1CFG_100MBPS 0x00000100
266 #define LGE_LED1CFG_1000MBPS 0x00000200
267 #define LGE_LED1CFG_FDX 0x00000400
268 #define LGE_LED1CFG_ANEG 0x00000800
269 #define LGE_LED1CFG_LINKSTS 0x00001000
270 #define LGE_LED1CFG_RXMATCH 0x00002000
271 #define LGE_LED1CFG_TX 0x00004000
272 #define LGE_LED1CFG_RX 0x00008000
273 #define LGE_LED1CFG_JABBER 0x00010000
274 #define LGE_LED1CFG_COLLISION 0x00020000
275 #define LGE_LED1CFG_CARRIER 0x00040000
276 #define LGE_LED1CFG_LEDOUT 0x10000000
279 /* LED2 config register */
280 #define LGE_LED2CFG_ENABLE 0x00000002
281 #define LGE_LED2CFG_INPUT_POL 0x00000004
282 #define LGE_LED2CFG_PULSE_EXP 0x00000008
283 #define LGE_LED2CFG_10MBPS 0x00000010
284 #define LGE_LED2CFG_100MBPS 0x00000100
285 #define LGE_LED2CFG_1000MBPS 0x00000200
286 #define LGE_LED2CFG_FDX 0x00000400
287 #define LGE_LED2CFG_ANEG 0x00000800
288 #define LGE_LED2CFG_LINKSTS 0x00001000
289 #define LGE_LED2CFG_RXMATCH 0x00002000
290 #define LGE_LED2CFG_TX 0x00004000
291 #define LGE_LED2CFG_RX 0x00008000
292 #define LGE_LED2CFG_JABBER 0x00010000
293 #define LGE_LED2CFG_COLLISION 0x00020000
294 #define LGE_LED2CFG_CARRIER 0x00040000
295 #define LGE_LED2CFG_LEDOUT 0x10000000
298 /* GMII PHY access register */
299 #define LGE_GMIICTL_PHYREG 0x0000001F
300 #define LGE_GMIICTL_CMD 0x00000080
301 #define LGE_GMIICTL_PHYADDR 0x00001F00
302 #define LGE_GMIICTL_CMDBUSY 0x00008000
303 #define LGE_GMIICTL_DATA 0xFFFF0000
305 #define LGE_GMIICMD_READ 0x00000000
306 #define LGE_GMIICMD_WRITE 0x00000080
308 /* GMII PHY mode register */
309 #define LGE_GMIIMODE_SPEED 0x00000003
310 #define LGE_GMIIMODE_FDX 0x00000004
311 #define LGE_GMIIMODE_PROTSEL 0x00000100 /* 0 == GMII, 1 == TBI */
312 #define LGE_GMIIMODE_PCSENH 0x00000200
314 #define LGE_SPEED_10 0x00000000
315 #define LGE_SPEED_100 0x00000001
316 #define LGE_SPEED_1000 0x00000002
319 /* VLAN tag control register */
320 #define LGE_VLANCTL_VLID 0x00000FFF
321 #define LGE_VLANCTL_USERPRIO 0x0000E000
322 #define LGE_VLANCTL_TCI_IDX 0x000D0000
323 #define LGE_VLANCTL_TBLCMD 0x00200000
326 /* Command status register */
327 #define LGE_CMDSTS_TXDMADONE 0x000000FF
328 #define LGE_CMDSTS_RXDMADONE 0x0000FF00
329 #define LGE_CMDSTS_TXCMDFREE 0x003F0000
330 #define LGE_CMDSTS_RXCMDFREE 0x3F000000
332 #define LGE_TXDMADONE_8BIT LGE_CMDSTS
333 #define LGE_RXDMADONE_8BIT (LGE_CMDSTS + 1)
334 #define LGE_TXCMDFREE_8BIT (LGE_CMDSTS + 2)
335 #define LGE_RXCMDFREE_8BIT (LGE_CMDSTS + 3)
337 #define LGE_MAXCMDS 31
340 /* Index for statistics counters. */
341 #define LGE_STATS_TX_PKTS_OK 0x00
342 #define LGE_STATS_SINGLE_COLL_PKTS 0x01
343 #define LGE_STATS_MULTI_COLL_PKTS 0x02
344 #define LGE_STATS_RX_PKTS_OK 0x03
345 #define LGE_STATS_FCS_ERRS 0x04
346 #define LGE_STATS_ALIGN_ERRS 0x05
347 #define LGE_STATS_DROPPED_PKTS 0x06
348 #define LGE_STATS_RX_ERR_PKTS 0x07
349 #define LGE_STATS_TX_ERR_PKTS 0x08
350 #define LGE_STATS_LATE_COLLS 0x09
351 #define LGE_STATS_RX_RUNTS 0x0A
352 #define LGE_STATS_RX_GIANTS 0x0B
353 #define LGE_STATS_VLAN_PKTS_ACCEPT 0x0C
354 #define LGE_STATS_VLAN_PKTS_REJECT 0x0D
355 #define LGE_STATS_IP_CSUM_ERR 0x0E
356 #define LGE_STATS_UDP_CSUM_ERR 0x0F
357 #define LGE_STATS_RANGELEN_ERRS 0x10
358 #define LGE_STATS_TCP_CSUM_ERR 0x11
359 #define LGE_STATS_RSVD0 0x12
360 #define LGE_STATS_TX_EXCESS_COLLS 0x13
361 #define LGE_STATS_RX_UCASTS 0x14
362 #define LGE_STATS_RX_MCASTS 0x15
363 #define LGE_STATS_RX_BCASTS 0x16
364 #define LGE_STATS_RX_PAUSE_PKTS 0x17
365 #define LGE_STATS_TX_PAUSE_PKTS 0x18
366 #define LGE_STATS_TX_PKTS_DEFERRED 0x19
367 #define LGE_STATS_TX_EXCESS_DEFER 0x1A
368 #define LGE_STATS_CARRIER_SENSE_ERR 0x1B
371 * RX and TX DMA descriptor structures for scatter/gather.
372 * Each descriptor can have up to 31 fragments in it, however for
373 * RX we only need one fragment, and for transmit we only allocate
374 * 10 in order to reduce the amount of space we need for the
376 * Note: descriptor structures must be 64-bit aligned.
380 /* Hardware descriptor section */
383 uint32_t lge_fragptr_lo;
384 uint32_t lge_fragptr_hi;
385 uint16_t lge_fraglen;
388 /* Driver software section */
390 struct mbuf *lge_mbuf;
397 uint32_t lge_fragptr_lo;
398 uint32_t lge_fragptr_hi;
399 uint16_t lge_fraglen;
404 /* Hardware descriptor section */
406 struct lge_frag lge_frags[10];
409 struct mbuf *lge_mbuf;
414 #define lge_mbuf lge_u.lge_mbuf
416 #define LGE_RXCTL_BUFLEN 0x0000FFFF
417 #define LGE_RXCTL_FRAGCNT 0x001F0000
418 #define LGE_RXCTL_LENERR 0x00400000
419 #define LGE_RXCTL_UCAST 0x00800000
420 #define LGR_RXCTL_BCAST 0x01000000
421 #define LGE_RXCTL_MCAST 0x02000000
422 #define LGE_RXCTL_GIANT 0x04000000
423 #define LGE_RXCTL_OFLOW 0x08000000
424 #define LGE_RXCTL_CRCERR 0x10000000
425 #define LGE_RXCTL_RUNT 0x20000000
426 #define LGE_RXCTL_ALGNERR 0x40000000
427 #define LGE_RXCTL_WANTINTR 0x80000000
429 #define LGE_RXCTL_ERRMASK \
430 (LGE_RXCTL_LENERR|LGE_RXCTL_OFLOW| \
431 LGE_RXCTL_CRCERR|LGE_RXCTL_RUNT| \
434 #define LGE_RXSTS_VLTBIDX 0x0000000F
435 #define LGE_RXSTS_VLTBLHIT 0x00000010
436 #define LGE_RXSTS_IPCSUMERR 0x00000100
437 #define LGE_RXSTS_TCPCSUMERR 0x00000200
438 #define LGE_RXSTS_UDPCSUMERR 0x00000400
439 #define LGE_RXSTS_ISIP 0x00000800
440 #define LGE_RXSTS_ISTCP 0x00001000
441 #define LGE_RXSTS_ISUDP 0x00002000
443 #define LGE_TXCTL_BUFLEN 0x0000FFFF
444 #define LGE_TXCTL_FRAGCNT 0x001F0000
445 #define LGE_TXCTL_VLTBIDX 0x0F000000
446 #define LGE_TXCTL_VLIS 0x10000000
447 #define LGE_TXCTL_WANTINTR 0x80000000
449 #define LGE_INC(x, y) (x) = (x + 1) % y
450 #define LGE_FRAGCNT_1 (1<<16)
451 #define LGE_FRAGCNT_10 (10<<16)
452 #define LGE_FRAGCNT(x) (x<<16)
453 #define LGE_RXBYTES(x) (x->lge_ctl & 0xFFFF)
454 #define LGE_RXTAIL(x) \
455 (x->lge_ldata->lge_rx_list[x->lge_cdata.lge_rx_prod])
457 #define LGE_RX_LIST_CNT 64
458 #define LGE_TX_LIST_CNT 128
460 struct lge_list_data {
461 struct lge_rx_desc lge_rx_list[LGE_RX_LIST_CNT];
462 struct lge_tx_desc lge_tx_list[LGE_TX_LIST_CNT];
467 * Level 1 PCI vendor ID.
469 #define LGE_VENDORID 0x1394
472 * LXT 1001 PCI device IDs
474 #define LGE_DEVICEID 0x0001
482 struct lge_mii_frame {
487 uint8_t mii_turnaround;
494 #define LGE_MII_STARTDELIM 0x01
495 #define LGE_MII_READOP 0x02
496 #define LGE_MII_WRITEOP 0x01
497 #define LGE_MII_TURNAROUND 0x02
499 #define LGE_JUMBO_FRAMELEN 9018
500 #define LGE_JUMBO_MTU (LGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
501 #define LGE_JSLOTS 384
503 #define LGE_JRAWLEN (LGE_JUMBO_FRAMELEN + ETHER_ALIGN)
504 #define LGE_JLEN (LGE_JRAWLEN + \
505 (sizeof(uint64_t) - LGE_JRAWLEN % sizeof(uint64_t)))
506 #define LGE_JPAGESZ PAGE_SIZE
507 #define LGE_RESID (LGE_JPAGESZ - (LGE_JLEN * LGE_JSLOTS) % LGE_JPAGESZ)
508 #define LGE_JMEM ((LGE_JLEN * LGE_JSLOTS) + LGE_RESID)
513 struct lge_softc *lge_sc;
517 SLIST_ENTRY(lge_jslot) jslot_link;
520 struct lge_ring_data {
525 /* Stick the jumbo mem management stuff here too. */
526 struct lge_jslot lge_jslots[LGE_JSLOTS];
531 struct arpcom arpcom; /* interface info */
532 bus_space_handle_t lge_bhandle;
533 bus_space_tag_t lge_btag;
534 struct resource *lge_res;
535 struct resource *lge_irq;
543 struct lge_list_data *lge_ldata;
544 struct lge_ring_data lge_cdata;
545 struct callout lge_stat_timer;
546 SLIST_HEAD(__lge_jfreehead, lge_jslot) lge_jfree_listhead;
547 struct lwkt_serialize lge_jslot_serializer;
551 * register space access macros
553 #define CSR_WRITE_4(sc, reg, val) \
554 bus_space_write_4(sc->lge_btag, sc->lge_bhandle, reg, val)
556 #define CSR_READ_2(sc, reg) \
557 bus_space_read_2(sc->lge_btag, sc->lge_bhandle, reg)
559 #define CSR_WRITE_2(sc, reg, val) \
560 bus_space_write_2(sc->lge_btag, sc->lge_bhandle, reg, val)
562 #define CSR_READ_4(sc, reg) \
563 bus_space_read_4(sc->lge_btag, sc->lge_bhandle, reg)
565 #define CSR_WRITE_1(sc, reg, val) \
566 bus_space_write_1(sc->lge_btag, sc->lge_bhandle, reg, val)
568 #define CSR_READ_1(sc, reg) \
569 bus_space_read_1(sc->lge_btag, sc->lge_bhandle, reg)
571 #define LGE_TIMEOUT 1000
572 #define ETHER_ALIGN 2
573 #define LGE_RXLEN 1536
574 #define LGE_MIN_FRAMELEN 60
577 * PCI low memory base and low I/O base register, and
578 * other PCI registers.
581 #define LGE_PCI_VENDOR_ID 0x00
582 #define LGE_PCI_DEVICE_ID 0x02
583 #define LGE_PCI_COMMAND 0x04
584 #define LGE_PCI_STATUS 0x06
585 #define LGE_PCI_REVID 0x08
586 #define LGE_PCI_CLASSCODE 0x09
587 #define LGE_PCI_CACHELEN 0x0C
588 #define LGE_PCI_LATENCY_TIMER 0x0D
589 #define LGE_PCI_HEADER_TYPE 0x0E
590 #define LGE_PCI_LOIO 0x10
591 #define LGE_PCI_LOMEM 0x14
592 #define LGE_PCI_BIOSROM 0x30
593 #define LGE_PCI_INTLINE 0x3C
594 #define LGE_PCI_INTPIN 0x3D
595 #define LGE_PCI_MINGNT 0x3E
596 #define LGE_PCI_MINLAT 0x0F
597 #define LGE_PCI_RESETOPT 0x48
598 #define LGE_PCI_EEPROM_DATA 0x4C