sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  */
  32
  33 /*
  34  * The following controllers are supported by this driver:
  35  *   BCM5706C A2, A3
  36  *   BCM5706S A2, A3
  37  *   BCM5708C B1, B2
  38  *   BCM5708S B1, B2
  39  *   BCM5709C A1, C0
  40  *   BCM5716  C0
  41  *
  42  * The following controllers are not supported by this driver:
  43  *   BCM5706C A0, A1
  44  *   BCM5706S A0, A1
  45  *   BCM5708C A0, B0
  46  *   BCM5708S A0, B0
  47  *   BCM5709C A0, B0, B1
  48  *   BCM5709S A0, A1, B0, B1, B2, C0
  49  */
  50
  51 #include "opt_bce.h"
  52 #include "opt_polling.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/bus.h>
  56 #include <sys/endian.h>
  57 #include <sys/kernel.h>
  58 #include <sys/interrupt.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/queue.h>
  62 #ifdef BCE_DEBUG
  63 #include <sys/random.h>
  64 #endif
  65 #include <sys/rman.h>
  66 #include <sys/serialize.h>
  67 #include <sys/socket.h>
  68 #include <sys/sockio.h>
  69 #include <sys/sysctl.h>
  70
  71 #include <net/bpf.h>
  72 #include <net/ethernet.h>
  73 #include <net/if.h>
  74 #include <net/if_arp.h>
  75 #include <net/if_dl.h>
  76 #include <net/if_media.h>
  77 #include <net/if_types.h>
  78 #include <net/ifq_var.h>
  79 #include <net/vlan/if_vlan_var.h>
  80 #include <net/vlan/if_vlan_ether.h>
  81
  82 #include <dev/netif/mii_layer/mii.h>
  83 #include <dev/netif/mii_layer/miivar.h>
  84
  85 #include <bus/pci/pcireg.h>
  86 #include <bus/pci/pcivar.h>
  87
  88 #include "miibus_if.h"
  89
  90 #include <dev/netif/bce/if_bcereg.h>
  91 #include <dev/netif/bce/if_bcefw.h>
  92
  93 /****************************************************************************/
  94 /* BCE Debug Options                                                        */
  95 /****************************************************************************/
  96 #ifdef BCE_DEBUG
  97
  98 static uint32_t bce_debug = BCE_WARN;
  99
 100 /*
 101  *          0 = Never
 102  *          1 = 1 in 2,147,483,648
 103  *        256 = 1 in     8,388,608
 104  *       2048 = 1 in     1,048,576
 105  *      65536 = 1 in        32,768
 106  *    1048576 = 1 in         2,048
 107  *  268435456 = 1 in             8
 108  *  536870912 = 1 in             4
 109  * 1073741824 = 1 in             2
 110  *
 111  * bce_debug_l2fhdr_status_check:
 112  *     How often the l2_fhdr frame error check will fail.
 113  *
 114  * bce_debug_unexpected_attention:
 115  *     How often the unexpected attention check will fail.
 116  *
 117  * bce_debug_mbuf_allocation_failure:
 118  *     How often to simulate an mbuf allocation failure.
 119  *
 120  * bce_debug_dma_map_addr_failure:
 121  *     How often to simulate a DMA mapping failure.
 122  *
 123  * bce_debug_bootcode_running_failure:
 124  *     How often to simulate a bootcode failure.
 125  */
 126 static int      bce_debug_l2fhdr_status_check = 0;
 127 static int      bce_debug_unexpected_attention = 0;
 128 static int      bce_debug_mbuf_allocation_failure = 0;
 129 static int      bce_debug_dma_map_addr_failure = 0;
 130 static int      bce_debug_bootcode_running_failure = 0;
 131
 132 #endif  /* BCE_DEBUG */
 133
 134
 135 /****************************************************************************/
 136 /* PCI Device ID Table                                                      */
 137 /*                                                                          */
 138 /* Used by bce_probe() to identify the devices supported by this driver.    */
 139 /****************************************************************************/
 140 #define BCE_DEVDESC_MAX         64
 141
 142 static struct bce_type bce_devs[] = {
 143         /* BCM5706C Controllers and OEM boards. */
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 145                 "HP NC370T Multifunction Gigabit Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 147                 "HP NC370i Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 149                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 150
 151         /* BCM5706S controllers and OEM boards. */
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 153                 "HP NC370F Multifunction Gigabit Server Adapter" },
 154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 155                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 156
 157         /* BCM5708C controllers and OEM boards. */
 158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 159                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 160
 161         /* BCM5708S controllers and OEM boards. */
 162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 163                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 164
 165         /* BCM5709C controllers and OEM boards. */
 166         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 167                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 168
 169         /* BCM5709S controllers and OEM boards. */
 170         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 171                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 172
 173         /* BCM5716 controllers and OEM boards. */
 174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
 175                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 176
 177         { 0, 0, 0, 0, NULL }
 178 };
 179
 180
 181 /****************************************************************************/
 182 /* Supported Flash NVRAM device data.                                       */
 183 /****************************************************************************/
 184 static const struct flash_spec flash_table[] =
 185 {
 186 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 187 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 188
 189         /* Slow EEPROM */
 190         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 191          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 192          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 193          "EEPROM - slow"},
 194         /* Expansion entry 0001 */
 195         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 196          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 197          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 198          "Entry 0001"},
 199         /* Saifun SA25F010 (non-buffered flash) */
 200         /* strap, cfg1, & write1 need updates */
 201         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 202          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 203          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 204          "Non-buffered flash (128kB)"},
 205         /* Saifun SA25F020 (non-buffered flash) */
 206         /* strap, cfg1, & write1 need updates */
 207         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 208          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 209          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 210          "Non-buffered flash (256kB)"},
 211         /* Expansion entry 0100 */
 212         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 213          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 214          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 215          "Entry 0100"},
 216         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 217         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 218          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 219          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 220          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 221         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 222         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 223          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 224          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 225          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 226         /* Saifun SA25F005 (non-buffered flash) */
 227         /* strap, cfg1, & write1 need updates */
 228         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 229          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 230          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 231          "Non-buffered flash (64kB)"},
 232         /* Fast EEPROM */
 233         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 234          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 235          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 236          "EEPROM - fast"},
 237         /* Expansion entry 1001 */
 238         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 239          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 240          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 241          "Entry 1001"},
 242         /* Expansion entry 1010 */
 243         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 244          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 245          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 246          "Entry 1010"},
 247         /* ATMEL AT45DB011B (buffered flash) */
 248         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 249          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 250          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 251          "Buffered flash (128kB)"},
 252         /* Expansion entry 1100 */
 253         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 254          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 255          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 256          "Entry 1100"},
 257         /* Expansion entry 1101 */
 258         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 259          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 260          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 261          "Entry 1101"},
 262         /* Ateml Expansion entry 1110 */
 263         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 264          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 265          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 266          "Entry 1110 (Atmel)"},
 267         /* ATMEL AT45DB021B (buffered flash) */
 268         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 269          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 270          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 271          "Buffered flash (256kB)"},
 272 };
 273
 274 /*
 275  * The BCM5709 controllers transparently handle the
 276  * differences between Atmel 264 byte pages and all
 277  * flash devices which use 256 byte pages, so no
 278  * logical-to-physical mapping is required in the
 279  * driver.
 280  */
 281 static struct flash_spec flash_5709 = {
 282         .flags          = BCE_NV_BUFFERED,
 283         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 284         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 285         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 286         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 287         .name           = "5709/5716 buffered flash (256kB)",
 288 };
 289
 290
 291 /****************************************************************************/
 292 /* DragonFly device entry points.                                           */
 293 /****************************************************************************/
 294 static int      bce_probe(device_t);
 295 static int      bce_attach(device_t);
 296 static int      bce_detach(device_t);
 297 static void     bce_shutdown(device_t);
 298
 299 /****************************************************************************/
 300 /* BCE Debug Data Structure Dump Routines                                   */
 301 /****************************************************************************/
 302 #ifdef BCE_DEBUG
 303 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 304 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
 305 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 306 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 307 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 308 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 309                                 struct l2_fhdr *) __unused;
 310 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 311 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 312 static void     bce_dump_status_block(struct bce_softc *);
 313 static void     bce_dump_driver_state(struct bce_softc *);
 314 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 315 static void     bce_dump_hw_state(struct bce_softc *);
 316 static void     bce_dump_txp_state(struct bce_softc *);
 317 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 318 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 319 static void     bce_freeze_controller(struct bce_softc *) __unused;
 320 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 321 static void     bce_breakpoint(struct bce_softc *);
 322 #endif  /* BCE_DEBUG */
 323
 324
 325 /****************************************************************************/
 326 /* BCE Register/Memory Access Routines                                      */
 327 /****************************************************************************/
 328 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 329 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 330 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 331 static int      bce_miibus_read_reg(device_t, int, int);
 332 static int      bce_miibus_write_reg(device_t, int, int, int);
 333 static void     bce_miibus_statchg(device_t);
 334
 335
 336 /****************************************************************************/
 337 /* BCE NVRAM Access Routines                                                */
 338 /****************************************************************************/
 339 static int      bce_acquire_nvram_lock(struct bce_softc *);
 340 static int      bce_release_nvram_lock(struct bce_softc *);
 341 static void     bce_enable_nvram_access(struct bce_softc *);
 342 static void     bce_disable_nvram_access(struct bce_softc *);
 343 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 344                                      uint32_t);
 345 static int      bce_init_nvram(struct bce_softc *);
 346 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 347 static int      bce_nvram_test(struct bce_softc *);
 348
 349 /****************************************************************************/
 350 /* BCE DMA Allocate/Free Routines                                           */
 351 /****************************************************************************/
 352 static int      bce_dma_alloc(struct bce_softc *);
 353 static void     bce_dma_free(struct bce_softc *);
 354 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 355
 356 /****************************************************************************/
 357 /* BCE Firmware Synchronization and Load                                    */
 358 /****************************************************************************/
 359 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 360 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 361                                  uint32_t, uint32_t);
 362 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 363                                 struct fw_info *);
 364 static void     bce_init_rxp_cpu(struct bce_softc *);
 365 static void     bce_init_txp_cpu(struct bce_softc *);
 366 static void     bce_init_tpat_cpu(struct bce_softc *);
 367 static void     bce_init_cp_cpu(struct bce_softc *);
 368 static void     bce_init_com_cpu(struct bce_softc *);
 369 static void     bce_init_cpus(struct bce_softc *);
 370
 371 static void     bce_stop(struct bce_softc *);
 372 static int      bce_reset(struct bce_softc *, uint32_t);
 373 static int      bce_chipinit(struct bce_softc *);
 374 static int      bce_blockinit(struct bce_softc *);
 375 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
 376                                uint32_t *, int);
 377 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
 378 static void     bce_probe_pci_caps(struct bce_softc *);
 379 static void     bce_print_adapter_info(struct bce_softc *);
 380 static void     bce_get_media(struct bce_softc *);
 381
 382 static void     bce_init_tx_context(struct bce_softc *);
 383 static int      bce_init_tx_chain(struct bce_softc *);
 384 static void     bce_init_rx_context(struct bce_softc *);
 385 static int      bce_init_rx_chain(struct bce_softc *);
 386 static void     bce_free_rx_chain(struct bce_softc *);
 387 static void     bce_free_tx_chain(struct bce_softc *);
 388
 389 static int      bce_encap(struct bce_softc *, struct mbuf **);
 390 static void     bce_start(struct ifnet *);
 391 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 392 static void     bce_watchdog(struct ifnet *);
 393 static int      bce_ifmedia_upd(struct ifnet *);
 394 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 395 static void     bce_init(void *);
 396 static void     bce_mgmt_init(struct bce_softc *);
 397
 398 static void     bce_init_ctx(struct bce_softc *);
 399 static void     bce_get_mac_addr(struct bce_softc *);
 400 static void     bce_set_mac_addr(struct bce_softc *);
 401 static void     bce_phy_intr(struct bce_softc *);
 402 static void     bce_rx_intr(struct bce_softc *, int);
 403 static void     bce_tx_intr(struct bce_softc *);
 404 static void     bce_disable_intr(struct bce_softc *);
 405 static void     bce_enable_intr(struct bce_softc *, int);
 406
 407 #ifdef DEVICE_POLLING
 408 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 409 #endif
 410 static void     bce_intr(void *);
 411 static void     bce_set_rx_mode(struct bce_softc *);
 412 static void     bce_stats_update(struct bce_softc *);
 413 static void     bce_tick(void *);
 414 static void     bce_tick_serialized(struct bce_softc *);
 415 static void     bce_pulse(void *);
 416 static void     bce_add_sysctls(struct bce_softc *);
 417
 418 static void     bce_coal_change(struct bce_softc *);
 419 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 420 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 421 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 422 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 423 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 424 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 425 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 426 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 427 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 428                                        uint32_t *, uint32_t);
 429
 430 /*
 431  * NOTE:
 432  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 433  * takes 1023 as the TX ticks limit.  However, using 1023 will
 434  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 435  * there is _no_ network activity on the NIC.
 436  */
 437 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 438 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 439 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 440 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 441 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 442 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
 443 static uint32_t bce_rx_ticks_int = 125;         /* bcm: 18 */
 444 static uint32_t bce_rx_ticks = 125;             /* bcm: 18 */
 445
 446 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 447 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 448 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 449 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 450 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 451 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 452 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 453 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 454
 455 /****************************************************************************/
 456 /* DragonFly device dispatch table.                                         */
 457 /****************************************************************************/
 458 static device_method_t bce_methods[] = {
 459         /* Device interface */
 460         DEVMETHOD(device_probe,         bce_probe),
 461         DEVMETHOD(device_attach,        bce_attach),
 462         DEVMETHOD(device_detach,        bce_detach),
 463         DEVMETHOD(device_shutdown,      bce_shutdown),
 464
 465         /* bus interface */
 466         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 467         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 468
 469         /* MII interface */
 470         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 471         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 472         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 473
 474         { 0, 0 }
 475 };
 476
 477 static driver_t bce_driver = {
 478         "bce",
 479         bce_methods,
 480         sizeof(struct bce_softc)
 481 };
 482
 483 static devclass_t bce_devclass;
 484
 485
 486 DECLARE_DUMMY_MODULE(if_bce);
 487 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 488 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
 489 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 490
 491
 492 /****************************************************************************/
 493 /* Device probe function.                                                   */
 494 /*                                                                          */
 495 /* Compares the device to the driver's list of supported devices and        */
 496 /* reports back to the OS whether this is the right driver for the device.  */
 497 /*                                                                          */
 498 /* Returns:                                                                 */
 499 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 500 /****************************************************************************/
 501 static int
 502 bce_probe(device_t dev)
 503 {
 504         struct bce_type *t;
 505         uint16_t vid, did, svid, sdid;
 506
 507         /* Get the data for the device to be probed. */
 508         vid  = pci_get_vendor(dev);
 509         did  = pci_get_device(dev);
 510         svid = pci_get_subvendor(dev);
 511         sdid = pci_get_subdevice(dev);
 512
 513         /* Look through the list of known devices for a match. */
 514         for (t = bce_devs; t->bce_name != NULL; ++t) {
 515                 if (vid == t->bce_vid && did == t->bce_did &&
 516                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 517                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 518                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 519                         char *descbuf;
 520
 521                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 522
 523                         /* Print out the device identity. */
 524                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 525                                   t->bce_name,
 526                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 527
 528                         device_set_desc_copy(dev, descbuf);
 529                         kfree(descbuf, M_TEMP);
 530                         return 0;
 531                 }
 532         }
 533         return ENXIO;
 534 }
 535
 536
 537 /****************************************************************************/
 538 /* PCI Capabilities Probe Function.                                         */
 539 /*                                                                          */
 540 /* Walks the PCI capabiites list for the device to find what features are   */
 541 /* supported.                                                               */
 542 /*                                                                          */
 543 /* Returns:                                                                 */
 544 /*   None.                                                                  */
 545 /****************************************************************************/
 546 static void
 547 bce_print_adapter_info(struct bce_softc *sc)
 548 {
 549         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
 550
 551         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 552                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 553
 554         /* Bus info. */
 555         if (sc->bce_flags & BCE_PCIE_FLAG) {
 556                 kprintf("Bus (PCIe x%d, ", sc->link_width);
 557                 switch (sc->link_speed) {
 558                 case 1:
 559                         kprintf("2.5Gbps); ");
 560                         break;
 561                 case 2:
 562                         kprintf("5Gbps); ");
 563                         break;
 564                 default:
 565                         kprintf("Unknown link speed); ");
 566                         break;
 567                 }
 568         } else {
 569                 kprintf("Bus (PCI%s, %s, %dMHz); ",
 570                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 571                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
 572                     sc->bus_speed_mhz);
 573         }
 574
 575         /* Firmware version and device features. */
 576         kprintf("F/W (0x%08X); Flags( ", sc->bce_fw_ver);
 577
 578         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
 579                 kprintf("MFW ");
 580         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 581                 kprintf("2.5G ");
 582         kprintf(")\n");
 583 }
 584
 585
 586 /****************************************************************************/
 587 /* PCI Capabilities Probe Function.                                         */
 588 /*                                                                          */
 589 /* Walks the PCI capabiites list for the device to find what features are   */
 590 /* supported.                                                               */
 591 /*                                                                          */
 592 /* Returns:                                                                 */
 593 /*   None.                                                                  */
 594 /****************************************************************************/
 595 static void
 596 bce_probe_pci_caps(struct bce_softc *sc)
 597 {
 598         device_t dev = sc->bce_dev;
 599         uint8_t ptr;
 600
 601         if (pci_is_pcix(dev))
 602                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 603
 604         ptr = pci_get_pciecap_ptr(dev);
 605         if (ptr) {
 606                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
 607
 608                 sc->link_speed = link_status & 0xf;
 609                 sc->link_width = (link_status >> 4) & 0x3f;
 610                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 611                 sc->bce_flags |= BCE_PCIE_FLAG;
 612         }
 613 }
 614
 615
 616 /****************************************************************************/
 617 /* Device attach function.                                                  */
 618 /*                                                                          */
 619 /* Allocates device resources, performs secondary chip identification,      */
 620 /* resets and initializes the hardware, and initializes driver instance     */
 621 /* variables.                                                               */
 622 /*                                                                          */
 623 /* Returns:                                                                 */
 624 /*   0 on success, positive value on failure.                               */
 625 /****************************************************************************/
 626 static int
 627 bce_attach(device_t dev)
 628 {
 629         struct bce_softc *sc = device_get_softc(dev);
 630         struct ifnet *ifp = &sc->arpcom.ac_if;
 631         uint32_t val;
 632         int rid, rc = 0;
 633 #ifdef notyet
 634         int count;
 635 #endif
 636
 637         sc->bce_dev = dev;
 638         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 639
 640         pci_enable_busmaster(dev);
 641
 642         bce_probe_pci_caps(sc);
 643
 644         /* Allocate PCI memory resources. */
 645         rid = PCIR_BAR(0);
 646         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 647                                                  RF_ACTIVE | PCI_RF_DENSE);
 648         if (sc->bce_res_mem == NULL) {
 649                 device_printf(dev, "PCI memory allocation failed\n");
 650                 return ENXIO;
 651         }
 652         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 653         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 654
 655         /* Allocate PCI IRQ resources. */
 656 #ifdef notyet
 657         count = pci_msi_count(dev);
 658         if (count == 1 && pci_alloc_msi(dev, &count) == 0) {
 659                 rid = 1;
 660                 sc->bce_flags |= BCE_USING_MSI_FLAG;
 661         } else
 662 #endif
 663         rid = 0;
 664         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 665                                                  RF_SHAREABLE | RF_ACTIVE);
 666         if (sc->bce_res_irq == NULL) {
 667                 device_printf(dev, "PCI map interrupt failed\n");
 668                 rc = ENXIO;
 669                 goto fail;
 670         }
 671
 672         /*
 673          * Configure byte swap and enable indirect register access.
 674          * Rely on CPU to do target byte swapping on big endian systems.
 675          * Access to registers outside of PCI configurtion space are not
 676          * valid until this is done.
 677          */
 678         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 679                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 680                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 681
 682         /* Save ASIC revsion info. */
 683         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 684
 685         /* Weed out any non-production controller revisions. */
 686         switch(BCE_CHIP_ID(sc)) {
 687         case BCE_CHIP_ID_5706_A0:
 688         case BCE_CHIP_ID_5706_A1:
 689         case BCE_CHIP_ID_5708_A0:
 690         case BCE_CHIP_ID_5708_B0:
 691         case BCE_CHIP_ID_5709_A0:
 692         case BCE_CHIP_ID_5709_B0:
 693         case BCE_CHIP_ID_5709_B1:
 694 #ifdef foo
 695         /* 5709C B2 seems to work fine */
 696         case BCE_CHIP_ID_5709_B2:
 697 #endif
 698                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 699                               BCE_CHIP_ID(sc));
 700                 rc = ENODEV;
 701                 goto fail;
 702         }
 703
 704         /*
 705          * Find the base address for shared memory access.
 706          * Newer versions of bootcode use a signature and offset
 707          * while older versions use a fixed address.
 708          */
 709         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 710         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
 711             BCE_SHM_HDR_SIGNATURE_SIG) {
 712                 /* Multi-port devices use different offsets in shared memory. */
 713                 sc->bce_shmem_base = REG_RD_IND(sc,
 714                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
 715         } else {
 716                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 717         }
 718         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 719
 720         /* Fetch the bootcode revision. */
 721         sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base +
 722                 BCE_DEV_INFO_BC_REV);
 723
 724         /* Check if any management firmware is running. */
 725         val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
 726         if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED))
 727                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 728
 729         /* Get PCI bus information (speed and type). */
 730         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 731         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 732                 uint32_t clkreg;
 733
 734                 sc->bce_flags |= BCE_PCIX_FLAG;
 735
 736                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 737                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 738                 switch (clkreg) {
 739                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 740                         sc->bus_speed_mhz = 133;
 741                         break;
 742
 743                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 744                         sc->bus_speed_mhz = 100;
 745                         break;
 746
 747                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 748                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 749                         sc->bus_speed_mhz = 66;
 750                         break;
 751
 752                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 753                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 754                         sc->bus_speed_mhz = 50;
 755                         break;
 756
 757                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 758                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 759                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 760                         sc->bus_speed_mhz = 33;
 761                         break;
 762                 }
 763         } else {
 764                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 765                         sc->bus_speed_mhz = 66;
 766                 else
 767                         sc->bus_speed_mhz = 33;
 768         }
 769
 770         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 771                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 772
 773         /* Reset the controller. */
 774         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 775         if (rc != 0)
 776                 goto fail;
 777
 778         /* Initialize the controller. */
 779         rc = bce_chipinit(sc);
 780         if (rc != 0) {
 781                 device_printf(dev, "Controller initialization failed!\n");
 782                 goto fail;
 783         }
 784
 785         /* Perform NVRAM test. */
 786         rc = bce_nvram_test(sc);
 787         if (rc != 0) {
 788                 device_printf(dev, "NVRAM test failed!\n");
 789                 goto fail;
 790         }
 791
 792         /* Fetch the permanent Ethernet MAC address. */
 793         bce_get_mac_addr(sc);
 794
 795         /*
 796          * Trip points control how many BDs
 797          * should be ready before generating an
 798          * interrupt while ticks control how long
 799          * a BD can sit in the chain before
 800          * generating an interrupt.  Set the default
 801          * values for the RX and TX rings.
 802          */
 803
 804 #ifdef BCE_DRBUG
 805         /* Force more frequent interrupts. */
 806         sc->bce_tx_quick_cons_trip_int = 1;
 807         sc->bce_tx_quick_cons_trip     = 1;
 808         sc->bce_tx_ticks_int           = 0;
 809         sc->bce_tx_ticks               = 0;
 810
 811         sc->bce_rx_quick_cons_trip_int = 1;
 812         sc->bce_rx_quick_cons_trip     = 1;
 813         sc->bce_rx_ticks_int           = 0;
 814         sc->bce_rx_ticks               = 0;
 815 #else
 816         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 817         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 818         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 819         sc->bce_tx_ticks               = bce_tx_ticks;
 820
 821         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 822         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 823         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 824         sc->bce_rx_ticks               = bce_rx_ticks;
 825 #endif
 826
 827         /* Update statistics once every second. */
 828         sc->bce_stats_ticks = 1000000 & 0xffff00;
 829
 830         /* Find the media type for the adapter. */
 831         bce_get_media(sc);
 832
 833         /* Allocate DMA memory resources. */
 834         rc = bce_dma_alloc(sc);
 835         if (rc != 0) {
 836                 device_printf(dev, "DMA resource allocation failed!\n");
 837                 goto fail;
 838         }
 839
 840         /* Initialize the ifnet interface. */
 841         ifp->if_softc = sc;
 842         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 843         ifp->if_ioctl = bce_ioctl;
 844         ifp->if_start = bce_start;
 845         ifp->if_init = bce_init;
 846         ifp->if_watchdog = bce_watchdog;
 847 #ifdef DEVICE_POLLING
 848         ifp->if_poll = bce_poll;
 849 #endif
 850         ifp->if_mtu = ETHERMTU;
 851         ifp->if_hwassist = BCE_IF_HWASSIST;
 852         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 853         ifp->if_capenable = ifp->if_capabilities;
 854         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
 855         ifq_set_ready(&ifp->if_snd);
 856
 857         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 858                 ifp->if_baudrate = IF_Gbps(2.5);
 859         else
 860                 ifp->if_baudrate = IF_Gbps(1);
 861
 862         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 863         sc->mbuf_alloc_size  = MCLBYTES;
 864
 865         /* Look for our PHY. */
 866         rc = mii_phy_probe(dev, &sc->bce_miibus,
 867                            bce_ifmedia_upd, bce_ifmedia_sts);
 868         if (rc != 0) {
 869                 device_printf(dev, "PHY probe failed!\n");
 870                 goto fail;
 871         }
 872
 873         /* Attach to the Ethernet interface list. */
 874         ether_ifattach(ifp, sc->eaddr, NULL);
 875
 876         callout_init(&sc->bce_tick_callout);
 877         callout_init(&sc->bce_pulse_callout);
 878
 879         /* Hookup IRQ last. */
 880         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
 881                             &sc->bce_intrhand, ifp->if_serializer);
 882         if (rc != 0) {
 883                 device_printf(dev, "Failed to setup IRQ!\n");
 884                 ether_ifdetach(ifp);
 885                 goto fail;
 886         }
 887
 888         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
 889         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 890
 891         /* Print some important debugging info. */
 892         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
 893
 894         /* Add the supported sysctls to the kernel. */
 895         bce_add_sysctls(sc);
 896
 897         /*
 898          * The chip reset earlier notified the bootcode that
 899          * a driver is present.  We now need to start our pulse
 900          * routine so that the bootcode is reminded that we're
 901          * still running.
 902          */
 903         bce_pulse(sc);
 904
 905         /* Get the firmware running so IPMI still works */
 906         bce_mgmt_init(sc);
 907
 908         bce_print_adapter_info(sc);
 909
 910         return 0;
 911 fail:
 912         bce_detach(dev);
 913         return(rc);
 914 }
 915
 916
 917 /****************************************************************************/
 918 /* Device detach function.                                                  */
 919 /*                                                                          */
 920 /* Stops the controller, resets the controller, and releases resources.     */
 921 /*                                                                          */
 922 /* Returns:                                                                 */
 923 /*   0 on success, positive value on failure.                               */
 924 /****************************************************************************/
 925 static int
 926 bce_detach(device_t dev)
 927 {
 928         struct bce_softc *sc = device_get_softc(dev);
 929
 930         if (device_is_attached(dev)) {
 931                 struct ifnet *ifp = &sc->arpcom.ac_if;
 932                 uint32_t msg;
 933
 934                 /* Stop and reset the controller. */
 935                 lwkt_serialize_enter(ifp->if_serializer);
 936                 callout_stop(&sc->bce_pulse_callout);
 937                 bce_stop(sc);
 938                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
 939                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
 940                 else
 941                         msg = BCE_DRV_MSG_CODE_UNLOAD;
 942                 bce_reset(sc, msg);
 943                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
 944                 lwkt_serialize_exit(ifp->if_serializer);
 945
 946                 ether_ifdetach(ifp);
 947         }
 948
 949         /* If we have a child device on the MII bus remove it too. */
 950         if (sc->bce_miibus)
 951                 device_delete_child(dev, sc->bce_miibus);
 952         bus_generic_detach(dev);
 953
 954         if (sc->bce_res_irq != NULL) {
 955                 bus_release_resource(dev, SYS_RES_IRQ,
 956                         sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
 957                         sc->bce_res_irq);
 958         }
 959
 960 #ifdef notyet
 961         if (sc->bce_flags & BCE_USING_MSI_FLAG)
 962                 pci_release_msi(dev);
 963 #endif
 964
 965         if (sc->bce_res_mem != NULL) {
 966                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
 967                                      sc->bce_res_mem);
 968         }
 969
 970         bce_dma_free(sc);
 971
 972         if (sc->bce_sysctl_tree != NULL)
 973                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
 974
 975         return 0;
 976 }
 977
 978
 979 /****************************************************************************/
 980 /* Device shutdown function.                                                */
 981 /*                                                                          */
 982 /* Stops and resets the controller.                                         */
 983 /*                                                                          */
 984 /* Returns:                                                                 */
 985 /*   Nothing                                                                */
 986 /****************************************************************************/
 987 static void
 988 bce_shutdown(device_t dev)
 989 {
 990         struct bce_softc *sc = device_get_softc(dev);
 991         struct ifnet *ifp = &sc->arpcom.ac_if;
 992         uint32_t msg;
 993
 994         lwkt_serialize_enter(ifp->if_serializer);
 995         bce_stop(sc);
 996         if (sc->bce_flags & BCE_NO_WOL_FLAG)
 997                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
 998         else
 999                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1000         bce_reset(sc, msg);
1001         lwkt_serialize_exit(ifp->if_serializer);
1002 }
1003
1004
1005 /****************************************************************************/
1006 /* Indirect register read.                                                  */
1007 /*                                                                          */
1008 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1009 /* configuration space.  Using this mechanism avoids issues with posted     */
1010 /* reads but is much slower than memory-mapped I/O.                         */
1011 /*                                                                          */
1012 /* Returns:                                                                 */
1013 /*   The value of the register.                                             */
1014 /****************************************************************************/
1015 static uint32_t
1016 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1017 {
1018         device_t dev = sc->bce_dev;
1019
1020         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1021 #ifdef BCE_DEBUG
1022         {
1023                 uint32_t val;
1024                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1025                 DBPRINT(sc, BCE_EXCESSIVE,
1026                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1027                         __func__, offset, val);
1028                 return val;
1029         }
1030 #else
1031         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1032 #endif
1033 }
1034
1035
1036 /****************************************************************************/
1037 /* Indirect register write.                                                 */
1038 /*                                                                          */
1039 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1040 /* configuration space.  Using this mechanism avoids issues with posted     */
1041 /* writes but is muchh slower than memory-mapped I/O.                       */
1042 /*                                                                          */
1043 /* Returns:                                                                 */
1044 /*   Nothing.                                                               */
1045 /****************************************************************************/
1046 static void
1047 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1048 {
1049         device_t dev = sc->bce_dev;
1050
1051         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1052                 __func__, offset, val);
1053
1054         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1055         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1056 }
1057
1058
1059 /****************************************************************************/
1060 /* Context memory write.                                                    */
1061 /*                                                                          */
1062 /* The NetXtreme II controller uses context memory to track connection      */
1063 /* information for L2 and higher network protocols.                         */
1064 /*                                                                          */
1065 /* Returns:                                                                 */
1066 /*   Nothing.                                                               */
1067 /****************************************************************************/
1068 static void
1069 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1070     uint32_t ctx_val)
1071 {
1072         uint32_t idx, offset = ctx_offset + cid_addr;
1073         uint32_t val, retry_cnt = 5;
1074
1075         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1076             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1077                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1078                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1079
1080                 for (idx = 0; idx < retry_cnt; idx++) {
1081                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1082                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1083                                 break;
1084                         DELAY(5);
1085                 }
1086
1087                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1088                         device_printf(sc->bce_dev,
1089                             "Unable to write CTX memory: "
1090                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1091                             cid_addr, ctx_offset);
1092                 }
1093         } else {
1094                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1095                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1096         }
1097 }
1098
1099
1100 /****************************************************************************/
1101 /* PHY register read.                                                       */
1102 /*                                                                          */
1103 /* Implements register reads on the MII bus.                                */
1104 /*                                                                          */
1105 /* Returns:                                                                 */
1106 /*   The value of the register.                                             */
1107 /****************************************************************************/
1108 static int
1109 bce_miibus_read_reg(device_t dev, int phy, int reg)
1110 {
1111         struct bce_softc *sc = device_get_softc(dev);
1112         uint32_t val;
1113         int i;
1114
1115         /* Make sure we are accessing the correct PHY address. */
1116         if (phy != sc->bce_phy_addr) {
1117                 DBPRINT(sc, BCE_VERBOSE,
1118                         "Invalid PHY address %d for PHY read!\n", phy);
1119                 return 0;
1120         }
1121
1122         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1123                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1124                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1125
1126                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1127                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1128
1129                 DELAY(40);
1130         }
1131
1132         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1133               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1134               BCE_EMAC_MDIO_COMM_START_BUSY;
1135         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1136
1137         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1138                 DELAY(10);
1139
1140                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1141                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1142                         DELAY(5);
1143
1144                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1145                         val &= BCE_EMAC_MDIO_COMM_DATA;
1146                         break;
1147                 }
1148         }
1149
1150         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1151                 if_printf(&sc->arpcom.ac_if,
1152                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1153                           phy, reg);
1154                 val = 0x0;
1155         } else {
1156                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1157         }
1158
1159         DBPRINT(sc, BCE_EXCESSIVE,
1160                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1161                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1162
1163         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1164                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1165                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1166
1167                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1168                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1169
1170                 DELAY(40);
1171         }
1172         return (val & 0xffff);
1173 }
1174
1175
1176 /****************************************************************************/
1177 /* PHY register write.                                                      */
1178 /*                                                                          */
1179 /* Implements register writes on the MII bus.                               */
1180 /*                                                                          */
1181 /* Returns:                                                                 */
1182 /*   The value of the register.                                             */
1183 /****************************************************************************/
1184 static int
1185 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1186 {
1187         struct bce_softc *sc = device_get_softc(dev);
1188         uint32_t val1;
1189         int i;
1190
1191         /* Make sure we are accessing the correct PHY address. */
1192         if (phy != sc->bce_phy_addr) {
1193                 DBPRINT(sc, BCE_WARN,
1194                         "Invalid PHY address %d for PHY write!\n", phy);
1195                 return(0);
1196         }
1197
1198         DBPRINT(sc, BCE_EXCESSIVE,
1199                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1200                 __func__, phy, (uint16_t)(reg & 0xffff),
1201                 (uint16_t)(val & 0xffff));
1202
1203         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1204                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1205                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1206
1207                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1208                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1209
1210                 DELAY(40);
1211         }
1212
1213         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1214                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1215                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1216         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1217
1218         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1219                 DELAY(10);
1220
1221                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1222                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1223                         DELAY(5);
1224                         break;
1225                 }
1226         }
1227
1228         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1229                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1230
1231         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1232                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1233                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1234
1235                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1236                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1237
1238                 DELAY(40);
1239         }
1240         return 0;
1241 }
1242
1243
1244 /****************************************************************************/
1245 /* MII bus status change.                                                   */
1246 /*                                                                          */
1247 /* Called by the MII bus driver when the PHY establishes link to set the    */
1248 /* MAC interface registers.                                                 */
1249 /*                                                                          */
1250 /* Returns:                                                                 */
1251 /*   Nothing.                                                               */
1252 /****************************************************************************/
1253 static void
1254 bce_miibus_statchg(device_t dev)
1255 {
1256         struct bce_softc *sc = device_get_softc(dev);
1257         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1258
1259         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1260                 mii->mii_media_active);
1261
1262 #ifdef BCE_DEBUG
1263         /* Decode the interface media flags. */
1264         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1265         switch(IFM_TYPE(mii->mii_media_active)) {
1266         case IFM_ETHER:
1267                 kprintf("Ethernet )");
1268                 break;
1269         default:
1270                 kprintf("Unknown )");
1271                 break;
1272         }
1273
1274         kprintf(" Media Options: ( ");
1275         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1276         case IFM_AUTO:
1277                 kprintf("Autoselect )");
1278                 break;
1279         case IFM_MANUAL:
1280                 kprintf("Manual )");
1281                 break;
1282         case IFM_NONE:
1283                 kprintf("None )");
1284                 break;
1285         case IFM_10_T:
1286                 kprintf("10Base-T )");
1287                 break;
1288         case IFM_100_TX:
1289                 kprintf("100Base-TX )");
1290                 break;
1291         case IFM_1000_SX:
1292                 kprintf("1000Base-SX )");
1293                 break;
1294         case IFM_1000_T:
1295                 kprintf("1000Base-T )");
1296                 break;
1297         default:
1298                 kprintf("Other )");
1299                 break;
1300         }
1301
1302         kprintf(" Global Options: (");
1303         if (mii->mii_media_active & IFM_FDX)
1304                 kprintf(" FullDuplex");
1305         if (mii->mii_media_active & IFM_HDX)
1306                 kprintf(" HalfDuplex");
1307         if (mii->mii_media_active & IFM_LOOP)
1308                 kprintf(" Loopback");
1309         if (mii->mii_media_active & IFM_FLAG0)
1310                 kprintf(" Flag0");
1311         if (mii->mii_media_active & IFM_FLAG1)
1312                 kprintf(" Flag1");
1313         if (mii->mii_media_active & IFM_FLAG2)
1314                 kprintf(" Flag2");
1315         kprintf(" )\n");
1316 #endif
1317
1318         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1319
1320         /*
1321          * Set MII or GMII interface based on the speed negotiated
1322          * by the PHY.
1323          */
1324         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1325             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1326                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1327                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1328         } else {
1329                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1330                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1331         }
1332
1333         /*
1334          * Set half or full duplex based on the duplicity negotiated
1335          * by the PHY.
1336          */
1337         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1338                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1339                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1340         } else {
1341                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1342                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1343         }
1344 }
1345
1346
1347 /****************************************************************************/
1348 /* Acquire NVRAM lock.                                                      */
1349 /*                                                                          */
1350 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1351 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1352 /* for use by the driver.                                                   */
1353 /*                                                                          */
1354 /* Returns:                                                                 */
1355 /*   0 on success, positive value on failure.                               */
1356 /****************************************************************************/
1357 static int
1358 bce_acquire_nvram_lock(struct bce_softc *sc)
1359 {
1360         uint32_t val;
1361         int j;
1362
1363         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1364
1365         /* Request access to the flash interface. */
1366         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1367         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1368                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1369                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1370                         break;
1371
1372                 DELAY(5);
1373         }
1374
1375         if (j >= NVRAM_TIMEOUT_COUNT) {
1376                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1377                 return EBUSY;
1378         }
1379         return 0;
1380 }
1381
1382
1383 /****************************************************************************/
1384 /* Release NVRAM lock.                                                      */
1385 /*                                                                          */
1386 /* When the caller is finished accessing NVRAM the lock must be released.   */
1387 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1388 /* for use by the driver.                                                   */
1389 /*                                                                          */
1390 /* Returns:                                                                 */
1391 /*   0 on success, positive value on failure.                               */
1392 /****************************************************************************/
1393 static int
1394 bce_release_nvram_lock(struct bce_softc *sc)
1395 {
1396         int j;
1397         uint32_t val;
1398
1399         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1400
1401         /*
1402          * Relinquish nvram interface.
1403          */
1404         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1405
1406         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1407                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1408                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1409                         break;
1410
1411                 DELAY(5);
1412         }
1413
1414         if (j >= NVRAM_TIMEOUT_COUNT) {
1415                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1416                 return EBUSY;
1417         }
1418         return 0;
1419 }
1420
1421
1422 /****************************************************************************/
1423 /* Enable NVRAM access.                                                     */
1424 /*                                                                          */
1425 /* Before accessing NVRAM for read or write operations the caller must      */
1426 /* enabled NVRAM access.                                                    */
1427 /*                                                                          */
1428 /* Returns:                                                                 */
1429 /*   Nothing.                                                               */
1430 /****************************************************************************/
1431 static void
1432 bce_enable_nvram_access(struct bce_softc *sc)
1433 {
1434         uint32_t val;
1435
1436         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1437
1438         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1439         /* Enable both bits, even on read. */
1440         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1441                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1442 }
1443
1444
1445 /****************************************************************************/
1446 /* Disable NVRAM access.                                                    */
1447 /*                                                                          */
1448 /* When the caller is finished accessing NVRAM access must be disabled.     */
1449 /*                                                                          */
1450 /* Returns:                                                                 */
1451 /*   Nothing.                                                               */
1452 /****************************************************************************/
1453 static void
1454 bce_disable_nvram_access(struct bce_softc *sc)
1455 {
1456         uint32_t val;
1457
1458         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1459
1460         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1461
1462         /* Disable both bits, even after read. */
1463         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1464                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1465 }
1466
1467
1468 /****************************************************************************/
1469 /* Read a dword (32 bits) from NVRAM.                                       */
1470 /*                                                                          */
1471 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1472 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1473 /*                                                                          */
1474 /* Returns:                                                                 */
1475 /*   0 on success and the 32 bit value read, positive value on failure.     */
1476 /****************************************************************************/
1477 static int
1478 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1479                      uint32_t cmd_flags)
1480 {
1481         uint32_t cmd;
1482         int i, rc = 0;
1483
1484         /* Build the command word. */
1485         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1486
1487         /* Calculate the offset for buffered flash. */
1488         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1489                 offset = ((offset / sc->bce_flash_info->page_size) <<
1490                           sc->bce_flash_info->page_bits) +
1491                          (offset % sc->bce_flash_info->page_size);
1492         }
1493
1494         /*
1495          * Clear the DONE bit separately, set the address to read,
1496          * and issue the read.
1497          */
1498         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1499         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1500         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1501
1502         /* Wait for completion. */
1503         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1504                 uint32_t val;
1505
1506                 DELAY(5);
1507
1508                 val = REG_RD(sc, BCE_NVM_COMMAND);
1509                 if (val & BCE_NVM_COMMAND_DONE) {
1510                         val = REG_RD(sc, BCE_NVM_READ);
1511
1512                         val = be32toh(val);
1513                         memcpy(ret_val, &val, 4);
1514                         break;
1515                 }
1516         }
1517
1518         /* Check for errors. */
1519         if (i >= NVRAM_TIMEOUT_COUNT) {
1520                 if_printf(&sc->arpcom.ac_if,
1521                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1522                           offset);
1523                 rc = EBUSY;
1524         }
1525         return rc;
1526 }
1527
1528
1529 /****************************************************************************/
1530 /* Initialize NVRAM access.                                                 */
1531 /*                                                                          */
1532 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1533 /* access that device.                                                      */
1534 /*                                                                          */
1535 /* Returns:                                                                 */
1536 /*   0 on success, positive value on failure.                               */
1537 /****************************************************************************/
1538 static int
1539 bce_init_nvram(struct bce_softc *sc)
1540 {
1541         uint32_t val;
1542         int j, entry_count, rc = 0;
1543         const struct flash_spec *flash;
1544
1545         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1546
1547         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1548             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1549                 sc->bce_flash_info = &flash_5709;
1550                 goto bce_init_nvram_get_flash_size;
1551         }
1552
1553         /* Determine the selected interface. */
1554         val = REG_RD(sc, BCE_NVM_CFG1);
1555
1556         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1557
1558         /*
1559          * Flash reconfiguration is required to support additional
1560          * NVRAM devices not directly supported in hardware.
1561          * Check if the flash interface was reconfigured
1562          * by the bootcode.
1563          */
1564
1565         if (val & 0x40000000) {
1566                 /* Flash interface reconfigured by bootcode. */
1567
1568                 DBPRINT(sc, BCE_INFO_LOAD,
1569                         "%s(): Flash WAS reconfigured.\n", __func__);
1570
1571                 for (j = 0, flash = flash_table; j < entry_count;
1572                      j++, flash++) {
1573                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1574                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1575                                 sc->bce_flash_info = flash;
1576                                 break;
1577                         }
1578                 }
1579         } else {
1580                 /* Flash interface not yet reconfigured. */
1581                 uint32_t mask;
1582
1583                 DBPRINT(sc, BCE_INFO_LOAD,
1584                         "%s(): Flash was NOT reconfigured.\n", __func__);
1585
1586                 if (val & (1 << 23))
1587                         mask = FLASH_BACKUP_STRAP_MASK;
1588                 else
1589                         mask = FLASH_STRAP_MASK;
1590
1591                 /* Look for the matching NVRAM device configuration data. */
1592                 for (j = 0, flash = flash_table; j < entry_count;
1593                      j++, flash++) {
1594                         /* Check if the device matches any of the known devices. */
1595                         if ((val & mask) == (flash->strapping & mask)) {
1596                                 /* Found a device match. */
1597                                 sc->bce_flash_info = flash;
1598
1599                                 /* Request access to the flash interface. */
1600                                 rc = bce_acquire_nvram_lock(sc);
1601                                 if (rc != 0)
1602                                         return rc;
1603
1604                                 /* Reconfigure the flash interface. */
1605                                 bce_enable_nvram_access(sc);
1606                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1607                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1608                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1609                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1610                                 bce_disable_nvram_access(sc);
1611                                 bce_release_nvram_lock(sc);
1612                                 break;
1613                         }
1614                 }
1615         }
1616
1617         /* Check if a matching device was found. */
1618         if (j == entry_count) {
1619                 sc->bce_flash_info = NULL;
1620                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1621                 rc = ENODEV;
1622         }
1623
1624 bce_init_nvram_get_flash_size:
1625         /* Write the flash config data to the shared memory interface. */
1626         val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2) &
1627               BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1628         if (val)
1629                 sc->bce_flash_size = val;
1630         else
1631                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1632
1633         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1634                 __func__, sc->bce_flash_info->total_size);
1635
1636         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1637
1638         return rc;
1639 }
1640
1641
1642 /****************************************************************************/
1643 /* Read an arbitrary range of data from NVRAM.                              */
1644 /*                                                                          */
1645 /* Prepares the NVRAM interface for access and reads the requested data     */
1646 /* into the supplied buffer.                                                */
1647 /*                                                                          */
1648 /* Returns:                                                                 */
1649 /*   0 on success and the data read, positive value on failure.             */
1650 /****************************************************************************/
1651 static int
1652 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1653                int buf_size)
1654 {
1655         uint32_t cmd_flags, offset32, len32, extra;
1656         int rc = 0;
1657
1658         if (buf_size == 0)
1659                 return 0;
1660
1661         /* Request access to the flash interface. */
1662         rc = bce_acquire_nvram_lock(sc);
1663         if (rc != 0)
1664                 return rc;
1665
1666         /* Enable access to flash interface */
1667         bce_enable_nvram_access(sc);
1668
1669         len32 = buf_size;
1670         offset32 = offset;
1671         extra = 0;
1672
1673         cmd_flags = 0;
1674
1675         /* XXX should we release nvram lock if read_dword() fails? */
1676         if (offset32 & 3) {
1677                 uint8_t buf[4];
1678                 uint32_t pre_len;
1679
1680                 offset32 &= ~3;
1681                 pre_len = 4 - (offset & 3);
1682
1683                 if (pre_len >= len32) {
1684                         pre_len = len32;
1685                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1686                 } else {
1687                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1688                 }
1689
1690                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1691                 if (rc)
1692                         return rc;
1693
1694                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1695
1696                 offset32 += 4;
1697                 ret_buf += pre_len;
1698                 len32 -= pre_len;
1699         }
1700
1701         if (len32 & 3) {
1702                 extra = 4 - (len32 & 3);
1703                 len32 = (len32 + 4) & ~3;
1704         }
1705
1706         if (len32 == 4) {
1707                 uint8_t buf[4];
1708
1709                 if (cmd_flags)
1710                         cmd_flags = BCE_NVM_COMMAND_LAST;
1711                 else
1712                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1713                                     BCE_NVM_COMMAND_LAST;
1714
1715                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1716
1717                 memcpy(ret_buf, buf, 4 - extra);
1718         } else if (len32 > 0) {
1719                 uint8_t buf[4];
1720
1721                 /* Read the first word. */
1722                 if (cmd_flags)
1723                         cmd_flags = 0;
1724                 else
1725                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1726
1727                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1728
1729                 /* Advance to the next dword. */
1730                 offset32 += 4;
1731                 ret_buf += 4;
1732                 len32 -= 4;
1733
1734                 while (len32 > 4 && rc == 0) {
1735                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1736
1737                         /* Advance to the next dword. */
1738                         offset32 += 4;
1739                         ret_buf += 4;
1740                         len32 -= 4;
1741                 }
1742
1743                 if (rc)
1744                         goto bce_nvram_read_locked_exit;
1745
1746                 cmd_flags = BCE_NVM_COMMAND_LAST;
1747                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1748
1749                 memcpy(ret_buf, buf, 4 - extra);
1750         }
1751
1752 bce_nvram_read_locked_exit:
1753         /* Disable access to flash interface and release the lock. */
1754         bce_disable_nvram_access(sc);
1755         bce_release_nvram_lock(sc);
1756
1757         return rc;
1758 }
1759
1760
1761 /****************************************************************************/
1762 /* Verifies that NVRAM is accessible and contains valid data.               */
1763 /*                                                                          */
1764 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1765 /* correct.                                                                 */
1766 /*                                                                          */
1767 /* Returns:                                                                 */
1768 /*   0 on success, positive value on failure.                               */
1769 /****************************************************************************/
1770 static int
1771 bce_nvram_test(struct bce_softc *sc)
1772 {
1773         uint32_t buf[BCE_NVRAM_SIZE / 4];
1774         uint32_t magic, csum;
1775         uint8_t *data = (uint8_t *)buf;
1776         int rc = 0;
1777
1778         /*
1779          * Check that the device NVRAM is valid by reading
1780          * the magic value at offset 0.
1781          */
1782         rc = bce_nvram_read(sc, 0, data, 4);
1783         if (rc != 0)
1784                 return rc;
1785
1786         magic = be32toh(buf[0]);
1787         if (magic != BCE_NVRAM_MAGIC) {
1788                 if_printf(&sc->arpcom.ac_if,
1789                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1790                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1791                 return ENODEV;
1792         }
1793
1794         /*
1795          * Verify that the device NVRAM includes valid
1796          * configuration data.
1797          */
1798         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1799         if (rc != 0)
1800                 return rc;
1801
1802         csum = ether_crc32_le(data, 0x100);
1803         if (csum != BCE_CRC32_RESIDUAL) {
1804                 if_printf(&sc->arpcom.ac_if,
1805                           "Invalid Manufacturing Information NVRAM CRC! "
1806                           "Expected: 0x%08X, Found: 0x%08X\n",
1807                           BCE_CRC32_RESIDUAL, csum);
1808                 return ENODEV;
1809         }
1810
1811         csum = ether_crc32_le(data + 0x100, 0x100);
1812         if (csum != BCE_CRC32_RESIDUAL) {
1813                 if_printf(&sc->arpcom.ac_if,
1814                           "Invalid Feature Configuration Information "
1815                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1816                           BCE_CRC32_RESIDUAL, csum);
1817                 rc = ENODEV;
1818         }
1819         return rc;
1820 }
1821
1822
1823 /****************************************************************************/
1824 /* Identifies the current media type of the controller and sets the PHY     */
1825 /* address.                                                                 */
1826 /*                                                                          */
1827 /* Returns:                                                                 */
1828 /*   Nothing.                                                               */
1829 /****************************************************************************/
1830 static void
1831 bce_get_media(struct bce_softc *sc)
1832 {
1833         uint32_t val;
1834
1835         sc->bce_phy_addr = 1;
1836
1837         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1838             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1839                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1840                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1841                 uint32_t strap;
1842
1843                 /*
1844                  * The BCM5709S is software configurable
1845                  * for Copper or SerDes operation.
1846                  */
1847                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1848                         return;
1849                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1850                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1851                         return;
1852                 }
1853
1854                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1855                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1856                 } else {
1857                         strap =
1858                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1859                 }
1860
1861                 if (pci_get_function(sc->bce_dev) == 0) {
1862                         switch (strap) {
1863                         case 0x4:
1864                         case 0x5:
1865                         case 0x6:
1866                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1867                                 break;
1868                         }
1869                 } else {
1870                         switch (strap) {
1871                         case 0x1:
1872                         case 0x2:
1873                         case 0x4:
1874                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1875                                 break;
1876                         }
1877                 }
1878         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
1879                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1880         }
1881
1882         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
1883                 sc->bce_flags |= BCE_NO_WOL_FLAG;
1884                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1885                         sc->bce_phy_addr = 2;
1886                         val = REG_RD_IND(sc, sc->bce_shmem_base +
1887                             BCE_SHARED_HW_CFG_CONFIG);
1888                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
1889                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
1890                 }
1891         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
1892             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
1893                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
1894         }
1895 }
1896
1897
1898 /****************************************************************************/
1899 /* Free any DMA memory owned by the driver.                                 */
1900 /*                                                                          */
1901 /* Scans through each data structre that requires DMA memory and frees      */
1902 /* the memory if allocated.                                                 */
1903 /*                                                                          */
1904 /* Returns:                                                                 */
1905 /*   Nothing.                                                               */
1906 /****************************************************************************/
1907 static void
1908 bce_dma_free(struct bce_softc *sc)
1909 {
1910         int i;
1911
1912         /* Destroy the status block. */
1913         if (sc->status_tag != NULL) {
1914                 if (sc->status_block != NULL) {
1915                         bus_dmamap_unload(sc->status_tag, sc->status_map);
1916                         bus_dmamem_free(sc->status_tag, sc->status_block,
1917                                         sc->status_map);
1918                 }
1919                 bus_dma_tag_destroy(sc->status_tag);
1920         }
1921
1922
1923         /* Destroy the statistics block. */
1924         if (sc->stats_tag != NULL) {
1925                 if (sc->stats_block != NULL) {
1926                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
1927                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
1928                                         sc->stats_map);
1929                 }
1930                 bus_dma_tag_destroy(sc->stats_tag);
1931         }
1932
1933         /* Destroy the CTX DMA stuffs. */
1934         if (sc->ctx_tag != NULL) {
1935                 for (i = 0; i < sc->ctx_pages; i++) {
1936                         if (sc->ctx_block[i] != NULL) {
1937                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
1938                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
1939                                                 sc->ctx_map[i]);
1940                         }
1941                 }
1942                 bus_dma_tag_destroy(sc->ctx_tag);
1943         }
1944
1945         /* Destroy the TX buffer descriptor DMA stuffs. */
1946         if (sc->tx_bd_chain_tag != NULL) {
1947                 for (i = 0; i < TX_PAGES; i++) {
1948                         if (sc->tx_bd_chain[i] != NULL) {
1949                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
1950                                                   sc->tx_bd_chain_map[i]);
1951                                 bus_dmamem_free(sc->tx_bd_chain_tag,
1952                                                 sc->tx_bd_chain[i],
1953                                                 sc->tx_bd_chain_map[i]);
1954                         }
1955                 }
1956                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
1957         }
1958
1959         /* Destroy the RX buffer descriptor DMA stuffs. */
1960         if (sc->rx_bd_chain_tag != NULL) {
1961                 for (i = 0; i < RX_PAGES; i++) {
1962                         if (sc->rx_bd_chain[i] != NULL) {
1963                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
1964                                                   sc->rx_bd_chain_map[i]);
1965                                 bus_dmamem_free(sc->rx_bd_chain_tag,
1966                                                 sc->rx_bd_chain[i],
1967                                                 sc->rx_bd_chain_map[i]);
1968                         }
1969                 }
1970                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
1971         }
1972
1973         /* Destroy the TX mbuf DMA stuffs. */
1974         if (sc->tx_mbuf_tag != NULL) {
1975                 for (i = 0; i < TOTAL_TX_BD; i++) {
1976                         /* Must have been unloaded in bce_stop() */
1977                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
1978                         bus_dmamap_destroy(sc->tx_mbuf_tag,
1979                                            sc->tx_mbuf_map[i]);
1980                 }
1981                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
1982         }
1983
1984         /* Destroy the RX mbuf DMA stuffs. */
1985         if (sc->rx_mbuf_tag != NULL) {
1986                 for (i = 0; i < TOTAL_RX_BD; i++) {
1987                         /* Must have been unloaded in bce_stop() */
1988                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
1989                         bus_dmamap_destroy(sc->rx_mbuf_tag,
1990                                            sc->rx_mbuf_map[i]);
1991                 }
1992                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
1993                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
1994         }
1995
1996         /* Destroy the parent tag */
1997         if (sc->parent_tag != NULL)
1998                 bus_dma_tag_destroy(sc->parent_tag);
1999 }
2000
2001
2002 /****************************************************************************/
2003 /* Get DMA memory from the OS.                                              */
2004 /*                                                                          */
2005 /* Validates that the OS has provided DMA buffers in response to a          */
2006 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2007 /* When the callback is used the OS will return 0 for the mapping function  */
2008 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2009 /* failures back to the caller.                                             */
2010 /*                                                                          */
2011 /* Returns:                                                                 */
2012 /*   Nothing.                                                               */
2013 /****************************************************************************/
2014 static void
2015 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2016 {
2017         bus_addr_t *busaddr = arg;
2018
2019         /*
2020          * Simulate a mapping failure.
2021          * XXX not correct.
2022          */
2023         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2024                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2025                         __FILE__, __LINE__);
2026                 error = ENOMEM);
2027
2028         /* Check for an error and signal the caller that an error occurred. */
2029         if (error)
2030                 return;
2031
2032         KASSERT(nseg == 1, ("only one segment is allowed\n"));
2033         *busaddr = segs->ds_addr;
2034 }
2035
2036
2037 /****************************************************************************/
2038 /* Allocate any DMA memory needed by the driver.                            */
2039 /*                                                                          */
2040 /* Allocates DMA memory needed for the various global structures needed by  */
2041 /* hardware.                                                                */
2042 /*                                                                          */
2043 /* Memory alignment requirements:                                           */
2044 /* -----------------+----------+----------+----------+----------+           */
2045 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2046 /* -----------------+----------+----------+----------+----------+           */
2047 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2048 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2049 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2050 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2051 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2052 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2053 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2054 /* -----------------+----------+----------+----------+----------+           */
2055 /*                                                                          */
2056 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2057 /*                                                                          */
2058 /* Returns:                                                                 */
2059 /*   0 for success, positive value for failure.                             */
2060 /****************************************************************************/
2061 static int
2062 bce_dma_alloc(struct bce_softc *sc)
2063 {
2064         struct ifnet *ifp = &sc->arpcom.ac_if;
2065         int i, j, rc = 0;
2066         bus_addr_t busaddr, max_busaddr;
2067         bus_size_t status_align, stats_align;
2068
2069         /*
2070          * The embedded PCIe to PCI-X bridge (EPB)
2071          * in the 5708 cannot address memory above
2072          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2073          */
2074         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2075                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2076         else
2077                 max_busaddr = BUS_SPACE_MAXADDR;
2078
2079         /*
2080          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2081          */
2082         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2083             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2084                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2085                 if (sc->ctx_pages == 0)
2086                         sc->ctx_pages = 1;
2087                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2088                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2089                             sc->ctx_pages);
2090                         return ENOMEM;
2091                 }
2092                 status_align = 16;
2093                 stats_align = 16;
2094         } else {
2095                 status_align = 8;
2096                 stats_align = 8;
2097         }
2098
2099         /*
2100          * Allocate the parent bus DMA tag appropriate for PCI.
2101          */
2102         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2103                                 max_busaddr, BUS_SPACE_MAXADDR,
2104                                 NULL, NULL,
2105                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2106                                 BUS_SPACE_MAXSIZE_32BIT,
2107                                 0, &sc->parent_tag);
2108         if (rc != 0) {
2109                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2110                 return rc;
2111         }
2112
2113         /*
2114          * Allocate status block.
2115          */
2116         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2117                                 status_align, BCE_STATUS_BLK_SZ,
2118                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2119                                 &sc->status_tag, &sc->status_map,
2120                                 &sc->status_block_paddr);
2121         if (sc->status_block == NULL) {
2122                 if_printf(ifp, "Could not allocate status block!\n");
2123                 return ENOMEM;
2124         }
2125
2126         /*
2127          * Allocate statistics block.
2128          */
2129         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2130                                 stats_align, BCE_STATS_BLK_SZ,
2131                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2132                                 &sc->stats_tag, &sc->stats_map,
2133                                 &sc->stats_block_paddr);
2134         if (sc->stats_block == NULL) {
2135                 if_printf(ifp, "Could not allocate statistics block!\n");
2136                 return ENOMEM;
2137         }
2138
2139         /*
2140          * Allocate context block, if needed
2141          */
2142         if (sc->ctx_pages != 0) {
2143                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2144                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2145                                         NULL, NULL,
2146                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2147                                         0, &sc->ctx_tag);
2148                 if (rc != 0) {
2149                         if_printf(ifp, "Could not allocate "
2150                                   "context block DMA tag!\n");
2151                         return rc;
2152                 }
2153
2154                 for (i = 0; i < sc->ctx_pages; i++) {
2155                         rc = bus_dmamem_alloc(sc->ctx_tag,
2156                                               (void **)&sc->ctx_block[i],
2157                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2158                                               BUS_DMA_COHERENT,
2159                                               &sc->ctx_map[i]);
2160                         if (rc != 0) {
2161                                 if_printf(ifp, "Could not allocate %dth context "
2162                                           "DMA memory!\n", i);
2163                                 return rc;
2164                         }
2165
2166                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2167                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2168                                              bce_dma_map_addr, &busaddr,
2169                                              BUS_DMA_WAITOK);
2170                         if (rc != 0) {
2171                                 if (rc == EINPROGRESS) {
2172                                         panic("%s coherent memory loading "
2173                                               "is still in progress!", ifp->if_xname);
2174                                 }
2175                                 if_printf(ifp, "Could not map %dth context "
2176                                           "DMA memory!\n", i);
2177                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2178                                                 sc->ctx_map[i]);
2179                                 sc->ctx_block[i] = NULL;
2180                                 return rc;
2181                         }
2182                         sc->ctx_paddr[i] = busaddr;
2183                 }
2184         }
2185
2186         /*
2187          * Create a DMA tag for the TX buffer descriptor chain,
2188          * allocate and clear the  memory, and fetch the
2189          * physical address of the block.
2190          */
2191         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2192                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2193                                 NULL, NULL,
2194                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2195                                 0, &sc->tx_bd_chain_tag);
2196         if (rc != 0) {
2197                 if_printf(ifp, "Could not allocate "
2198                           "TX descriptor chain DMA tag!\n");
2199                 return rc;
2200         }
2201
2202         for (i = 0; i < TX_PAGES; i++) {
2203                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2204                                       (void **)&sc->tx_bd_chain[i],
2205                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2206                                       BUS_DMA_COHERENT,
2207                                       &sc->tx_bd_chain_map[i]);
2208                 if (rc != 0) {
2209                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2210                                   "chain DMA memory!\n", i);
2211                         return rc;
2212                 }
2213
2214                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2215                                      sc->tx_bd_chain_map[i],
2216                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2217                                      bce_dma_map_addr, &busaddr,
2218                                      BUS_DMA_WAITOK);
2219                 if (rc != 0) {
2220                         if (rc == EINPROGRESS) {
2221                                 panic("%s coherent memory loading "
2222                                       "is still in progress!", ifp->if_xname);
2223                         }
2224                         if_printf(ifp, "Could not map %dth TX descriptor "
2225                                   "chain DMA memory!\n", i);
2226                         bus_dmamem_free(sc->tx_bd_chain_tag,
2227                                         sc->tx_bd_chain[i],
2228                                         sc->tx_bd_chain_map[i]);
2229                         sc->tx_bd_chain[i] = NULL;
2230                         return rc;
2231                 }
2232
2233                 sc->tx_bd_chain_paddr[i] = busaddr;
2234                 /* DRC - Fix for 64 bit systems. */
2235                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2236                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2237         }
2238
2239         /* Create a DMA tag for TX mbufs. */
2240         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2241                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2242                                 NULL, NULL,
2243                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2244                                 BCE_MAX_SEGMENTS, MCLBYTES,
2245                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2246                                 BUS_DMA_ONEBPAGE,
2247                                 &sc->tx_mbuf_tag);
2248         if (rc != 0) {
2249                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2250                 return rc;
2251         }
2252
2253         /* Create DMA maps for the TX mbufs clusters. */
2254         for (i = 0; i < TOTAL_TX_BD; i++) {
2255                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2256                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2257                                        &sc->tx_mbuf_map[i]);
2258                 if (rc != 0) {
2259                         for (j = 0; j < i; ++j) {
2260                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2261                                                    sc->tx_mbuf_map[i]);
2262                         }
2263                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2264                         sc->tx_mbuf_tag = NULL;
2265
2266                         if_printf(ifp, "Unable to create "
2267                                   "%dth TX mbuf DMA map!\n", i);
2268                         return rc;
2269                 }
2270         }
2271
2272         /*
2273          * Create a DMA tag for the RX buffer descriptor chain,
2274          * allocate and clear the  memory, and fetch the physical
2275          * address of the blocks.
2276          */
2277         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2278                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2279                                 NULL, NULL,
2280                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2281                                 0, &sc->rx_bd_chain_tag);
2282         if (rc != 0) {
2283                 if_printf(ifp, "Could not allocate "
2284                           "RX descriptor chain DMA tag!\n");
2285                 return rc;
2286         }
2287
2288         for (i = 0; i < RX_PAGES; i++) {
2289                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2290                                       (void **)&sc->rx_bd_chain[i],
2291                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2292                                       BUS_DMA_COHERENT,
2293                                       &sc->rx_bd_chain_map[i]);
2294                 if (rc != 0) {
2295                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2296                                   "chain DMA memory!\n", i);
2297                         return rc;
2298                 }
2299
2300                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2301                                      sc->rx_bd_chain_map[i],
2302                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2303                                      bce_dma_map_addr, &busaddr,
2304                                      BUS_DMA_WAITOK);
2305                 if (rc != 0) {
2306                         if (rc == EINPROGRESS) {
2307                                 panic("%s coherent memory loading "
2308                                       "is still in progress!", ifp->if_xname);
2309                         }
2310                         if_printf(ifp, "Could not map %dth RX descriptor "
2311                                   "chain DMA memory!\n", i);
2312                         bus_dmamem_free(sc->rx_bd_chain_tag,
2313                                         sc->rx_bd_chain[i],
2314                                         sc->rx_bd_chain_map[i]);
2315                         sc->rx_bd_chain[i] = NULL;
2316                         return rc;
2317                 }
2318
2319                 sc->rx_bd_chain_paddr[i] = busaddr;
2320                 /* DRC - Fix for 64 bit systems. */
2321                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2322                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2323         }
2324
2325         /* Create a DMA tag for RX mbufs. */
2326         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2327                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2328                                 NULL, NULL,
2329                                 MCLBYTES, 1, MCLBYTES,
2330                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2331                                 BUS_DMA_WAITOK,
2332                                 &sc->rx_mbuf_tag);
2333         if (rc != 0) {
2334                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2335                 return rc;
2336         }
2337
2338         /* Create tmp DMA map for RX mbuf clusters. */
2339         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2340                                &sc->rx_mbuf_tmpmap);
2341         if (rc != 0) {
2342                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2343                 sc->rx_mbuf_tag = NULL;
2344
2345                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2346                 return rc;
2347         }
2348
2349         /* Create DMA maps for the RX mbuf clusters. */
2350         for (i = 0; i < TOTAL_RX_BD; i++) {
2351                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2352                                        &sc->rx_mbuf_map[i]);
2353                 if (rc != 0) {
2354                         for (j = 0; j < i; ++j) {
2355                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2356                                                    sc->rx_mbuf_map[j]);
2357                         }
2358                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2359                         sc->rx_mbuf_tag = NULL;
2360
2361                         if_printf(ifp, "Unable to create "
2362                                   "%dth RX mbuf DMA map!\n", i);
2363                         return rc;
2364                 }
2365         }
2366         return 0;
2367 }
2368
2369
2370 /****************************************************************************/
2371 /* Firmware synchronization.                                                */
2372 /*                                                                          */
2373 /* Before performing certain events such as a chip reset, synchronize with  */
2374 /* the firmware first.                                                      */
2375 /*                                                                          */
2376 /* Returns:                                                                 */
2377 /*   0 for success, positive value for failure.                             */
2378 /****************************************************************************/
2379 static int
2380 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2381 {
2382         int i, rc = 0;
2383         uint32_t val;
2384
2385         /* Don't waste any time if we've timed out before. */
2386         if (sc->bce_fw_timed_out)
2387                 return EBUSY;
2388
2389         /* Increment the message sequence number. */
2390         sc->bce_fw_wr_seq++;
2391         msg_data |= sc->bce_fw_wr_seq;
2392
2393         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2394
2395         /* Send the message to the bootcode driver mailbox. */
2396         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2397
2398         /* Wait for the bootcode to acknowledge the message. */
2399         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2400                 /* Check for a response in the bootcode firmware mailbox. */
2401                 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);
2402                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2403                         break;
2404                 DELAY(1000);
2405         }
2406
2407         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2408         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2409             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2410                 if_printf(&sc->arpcom.ac_if,
2411                           "Firmware synchronization timeout! "
2412                           "msg_data = 0x%08X\n", msg_data);
2413
2414                 msg_data &= ~BCE_DRV_MSG_CODE;
2415                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2416
2417                 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2418
2419                 sc->bce_fw_timed_out = 1;
2420                 rc = EBUSY;
2421         }
2422         return rc;
2423 }
2424
2425
2426 /****************************************************************************/
2427 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2428 /*                                                                          */
2429 /* Returns:                                                                 */
2430 /*   Nothing.                                                               */
2431 /****************************************************************************/
2432 static void
2433 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2434                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2435 {
2436         int i;
2437         uint32_t val;
2438
2439         for (i = 0; i < rv2p_code_len; i += 8) {
2440                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2441                 rv2p_code++;
2442                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2443                 rv2p_code++;
2444
2445                 if (rv2p_proc == RV2P_PROC1) {
2446                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2447                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2448                 } else {
2449                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2450                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2451                 }
2452         }
2453
2454         /* Reset the processor, un-stall is done later. */
2455         if (rv2p_proc == RV2P_PROC1)
2456                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2457         else
2458                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2459 }
2460
2461
2462 /****************************************************************************/
2463 /* Load RISC processor firmware.                                            */
2464 /*                                                                          */
2465 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2466 /* associated with a particular processor.                                  */
2467 /*                                                                          */
2468 /* Returns:                                                                 */
2469 /*   Nothing.                                                               */
2470 /****************************************************************************/
2471 static void
2472 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2473                 struct fw_info *fw)
2474 {
2475         uint32_t offset, val;
2476         int j;
2477
2478         /* Halt the CPU. */
2479         val = REG_RD_IND(sc, cpu_reg->mode);
2480         val |= cpu_reg->mode_value_halt;
2481         REG_WR_IND(sc, cpu_reg->mode, val);
2482         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2483
2484         /* Load the Text area. */
2485         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2486         if (fw->text) {
2487                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2488                         REG_WR_IND(sc, offset, fw->text[j]);
2489         }
2490
2491         /* Load the Data area. */
2492         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2493         if (fw->data) {
2494                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2495                         REG_WR_IND(sc, offset, fw->data[j]);
2496         }
2497
2498         /* Load the SBSS area. */
2499         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2500         if (fw->sbss) {
2501                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2502                         REG_WR_IND(sc, offset, fw->sbss[j]);
2503         }
2504
2505         /* Load the BSS area. */
2506         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2507         if (fw->bss) {
2508                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2509                         REG_WR_IND(sc, offset, fw->bss[j]);
2510         }
2511
2512         /* Load the Read-Only area. */
2513         offset = cpu_reg->spad_base +
2514                 (fw->rodata_addr - cpu_reg->mips_view_base);
2515         if (fw->rodata) {
2516                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2517                         REG_WR_IND(sc, offset, fw->rodata[j]);
2518         }
2519
2520         /* Clear the pre-fetch instruction. */
2521         REG_WR_IND(sc, cpu_reg->inst, 0);
2522         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2523
2524         /* Start the CPU. */
2525         val = REG_RD_IND(sc, cpu_reg->mode);
2526         val &= ~cpu_reg->mode_value_halt;
2527         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2528         REG_WR_IND(sc, cpu_reg->mode, val);
2529 }
2530
2531
2532 /****************************************************************************/
2533 /* Initialize the RX CPU.                                                   */
2534 /*                                                                          */
2535 /* Returns:                                                                 */
2536 /*   Nothing.                                                               */
2537 /****************************************************************************/
2538 static void
2539 bce_init_rxp_cpu(struct bce_softc *sc)
2540 {
2541         struct cpu_reg cpu_reg;
2542         struct fw_info fw;
2543
2544         cpu_reg.mode = BCE_RXP_CPU_MODE;
2545         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2546         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2547         cpu_reg.state = BCE_RXP_CPU_STATE;
2548         cpu_reg.state_value_clear = 0xffffff;
2549         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2550         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2551         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2552         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2553         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2554         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2555         cpu_reg.mips_view_base = 0x8000000;
2556
2557         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2558             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2559                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2560                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2561                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2562                 fw.start_addr = bce_RXP_b09FwStartAddr;
2563
2564                 fw.text_addr = bce_RXP_b09FwTextAddr;
2565                 fw.text_len = bce_RXP_b09FwTextLen;
2566                 fw.text_index = 0;
2567                 fw.text = bce_RXP_b09FwText;
2568
2569                 fw.data_addr = bce_RXP_b09FwDataAddr;
2570                 fw.data_len = bce_RXP_b09FwDataLen;
2571                 fw.data_index = 0;
2572                 fw.data = bce_RXP_b09FwData;
2573
2574                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2575                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2576                 fw.sbss_index = 0;
2577                 fw.sbss = bce_RXP_b09FwSbss;
2578
2579                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2580                 fw.bss_len = bce_RXP_b09FwBssLen;
2581                 fw.bss_index = 0;
2582                 fw.bss = bce_RXP_b09FwBss;
2583
2584                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2585                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2586                 fw.rodata_index = 0;
2587                 fw.rodata = bce_RXP_b09FwRodata;
2588         } else {
2589                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2590                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2591                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2592                 fw.start_addr = bce_RXP_b06FwStartAddr;
2593
2594                 fw.text_addr = bce_RXP_b06FwTextAddr;
2595                 fw.text_len = bce_RXP_b06FwTextLen;
2596                 fw.text_index = 0;
2597                 fw.text = bce_RXP_b06FwText;
2598
2599                 fw.data_addr = bce_RXP_b06FwDataAddr;
2600                 fw.data_len = bce_RXP_b06FwDataLen;
2601                 fw.data_index = 0;
2602                 fw.data = bce_RXP_b06FwData;
2603
2604                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2605                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2606                 fw.sbss_index = 0;
2607                 fw.sbss = bce_RXP_b06FwSbss;
2608
2609                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2610                 fw.bss_len = bce_RXP_b06FwBssLen;
2611                 fw.bss_index = 0;
2612                 fw.bss = bce_RXP_b06FwBss;
2613
2614                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2615                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2616                 fw.rodata_index = 0;
2617                 fw.rodata = bce_RXP_b06FwRodata;
2618         }
2619
2620         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2621         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2622 }
2623
2624
2625 /****************************************************************************/
2626 /* Initialize the TX CPU.                                                   */
2627 /*                                                                          */
2628 /* Returns:                                                                 */
2629 /*   Nothing.                                                               */
2630 /****************************************************************************/
2631 static void
2632 bce_init_txp_cpu(struct bce_softc *sc)
2633 {
2634         struct cpu_reg cpu_reg;
2635         struct fw_info fw;
2636
2637         cpu_reg.mode = BCE_TXP_CPU_MODE;
2638         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2639         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2640         cpu_reg.state = BCE_TXP_CPU_STATE;
2641         cpu_reg.state_value_clear = 0xffffff;
2642         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2643         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2644         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2645         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2646         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2647         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2648         cpu_reg.mips_view_base = 0x8000000;
2649
2650         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2651             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2652                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2653                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2654                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2655                 fw.start_addr = bce_TXP_b09FwStartAddr;
2656
2657                 fw.text_addr = bce_TXP_b09FwTextAddr;
2658                 fw.text_len = bce_TXP_b09FwTextLen;
2659                 fw.text_index = 0;
2660                 fw.text = bce_TXP_b09FwText;
2661
2662                 fw.data_addr = bce_TXP_b09FwDataAddr;
2663                 fw.data_len = bce_TXP_b09FwDataLen;
2664                 fw.data_index = 0;
2665                 fw.data = bce_TXP_b09FwData;
2666
2667                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2668                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2669                 fw.sbss_index = 0;
2670                 fw.sbss = bce_TXP_b09FwSbss;
2671
2672                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2673                 fw.bss_len = bce_TXP_b09FwBssLen;
2674                 fw.bss_index = 0;
2675                 fw.bss = bce_TXP_b09FwBss;
2676
2677                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2678                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2679                 fw.rodata_index = 0;
2680                 fw.rodata = bce_TXP_b09FwRodata;
2681         } else {
2682                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2683                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2684                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2685                 fw.start_addr = bce_TXP_b06FwStartAddr;
2686
2687                 fw.text_addr = bce_TXP_b06FwTextAddr;
2688                 fw.text_len = bce_TXP_b06FwTextLen;
2689                 fw.text_index = 0;
2690                 fw.text = bce_TXP_b06FwText;
2691
2692                 fw.data_addr = bce_TXP_b06FwDataAddr;
2693                 fw.data_len = bce_TXP_b06FwDataLen;
2694                 fw.data_index = 0;
2695                 fw.data = bce_TXP_b06FwData;
2696
2697                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2698                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2699                 fw.sbss_index = 0;
2700                 fw.sbss = bce_TXP_b06FwSbss;
2701
2702                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2703                 fw.bss_len = bce_TXP_b06FwBssLen;
2704                 fw.bss_index = 0;
2705                 fw.bss = bce_TXP_b06FwBss;
2706
2707                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2708                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2709                 fw.rodata_index = 0;
2710                 fw.rodata = bce_TXP_b06FwRodata;
2711         }
2712
2713         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2714         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2715 }
2716
2717
2718 /****************************************************************************/
2719 /* Initialize the TPAT CPU.                                                 */
2720 /*                                                                          */
2721 /* Returns:                                                                 */
2722 /*   Nothing.                                                               */
2723 /****************************************************************************/
2724 static void
2725 bce_init_tpat_cpu(struct bce_softc *sc)
2726 {
2727         struct cpu_reg cpu_reg;
2728         struct fw_info fw;
2729
2730         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2731         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2732         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2733         cpu_reg.state = BCE_TPAT_CPU_STATE;
2734         cpu_reg.state_value_clear = 0xffffff;
2735         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2736         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2737         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2738         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2739         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2740         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2741         cpu_reg.mips_view_base = 0x8000000;
2742
2743         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2744             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2745                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2746                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2747                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
2748                 fw.start_addr = bce_TPAT_b09FwStartAddr;
2749
2750                 fw.text_addr = bce_TPAT_b09FwTextAddr;
2751                 fw.text_len = bce_TPAT_b09FwTextLen;
2752                 fw.text_index = 0;
2753                 fw.text = bce_TPAT_b09FwText;
2754
2755                 fw.data_addr = bce_TPAT_b09FwDataAddr;
2756                 fw.data_len = bce_TPAT_b09FwDataLen;
2757                 fw.data_index = 0;
2758                 fw.data = bce_TPAT_b09FwData;
2759
2760                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
2761                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
2762                 fw.sbss_index = 0;
2763                 fw.sbss = bce_TPAT_b09FwSbss;
2764
2765                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
2766                 fw.bss_len = bce_TPAT_b09FwBssLen;
2767                 fw.bss_index = 0;
2768                 fw.bss = bce_TPAT_b09FwBss;
2769
2770                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
2771                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
2772                 fw.rodata_index = 0;
2773                 fw.rodata = bce_TPAT_b09FwRodata;
2774         } else {
2775                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
2776                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
2777                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
2778                 fw.start_addr = bce_TPAT_b06FwStartAddr;
2779
2780                 fw.text_addr = bce_TPAT_b06FwTextAddr;
2781                 fw.text_len = bce_TPAT_b06FwTextLen;
2782                 fw.text_index = 0;
2783                 fw.text = bce_TPAT_b06FwText;
2784
2785                 fw.data_addr = bce_TPAT_b06FwDataAddr;
2786                 fw.data_len = bce_TPAT_b06FwDataLen;
2787                 fw.data_index = 0;
2788                 fw.data = bce_TPAT_b06FwData;
2789
2790                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
2791                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
2792                 fw.sbss_index = 0;
2793                 fw.sbss = bce_TPAT_b06FwSbss;
2794
2795                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
2796                 fw.bss_len = bce_TPAT_b06FwBssLen;
2797                 fw.bss_index = 0;
2798                 fw.bss = bce_TPAT_b06FwBss;
2799
2800                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
2801                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
2802                 fw.rodata_index = 0;
2803                 fw.rodata = bce_TPAT_b06FwRodata;
2804         }
2805
2806         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
2807         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2808 }
2809
2810
2811 /****************************************************************************/
2812 /* Initialize the CP CPU.                                                   */
2813 /*                                                                          */
2814 /* Returns:                                                                 */
2815 /*   Nothing.                                                               */
2816 /****************************************************************************/
2817 static void
2818 bce_init_cp_cpu(struct bce_softc *sc)
2819 {
2820         struct cpu_reg cpu_reg;
2821         struct fw_info fw;
2822
2823         cpu_reg.mode = BCE_CP_CPU_MODE;
2824         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
2825         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
2826         cpu_reg.state = BCE_CP_CPU_STATE;
2827         cpu_reg.state_value_clear = 0xffffff;
2828         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
2829         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
2830         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
2831         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
2832         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
2833         cpu_reg.spad_base = BCE_CP_SCRATCH;
2834         cpu_reg.mips_view_base = 0x8000000;
2835
2836         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2837             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2838                 fw.ver_major = bce_CP_b09FwReleaseMajor;
2839                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
2840                 fw.ver_fix = bce_CP_b09FwReleaseFix;
2841                 fw.start_addr = bce_CP_b09FwStartAddr;
2842
2843                 fw.text_addr = bce_CP_b09FwTextAddr;
2844                 fw.text_len = bce_CP_b09FwTextLen;
2845                 fw.text_index = 0;
2846                 fw.text = bce_CP_b09FwText;
2847
2848                 fw.data_addr = bce_CP_b09FwDataAddr;
2849                 fw.data_len = bce_CP_b09FwDataLen;
2850                 fw.data_index = 0;
2851                 fw.data = bce_CP_b09FwData;
2852
2853                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
2854                 fw.sbss_len = bce_CP_b09FwSbssLen;
2855                 fw.sbss_index = 0;
2856                 fw.sbss = bce_CP_b09FwSbss;
2857
2858                 fw.bss_addr = bce_CP_b09FwBssAddr;
2859                 fw.bss_len = bce_CP_b09FwBssLen;
2860                 fw.bss_index = 0;
2861                 fw.bss = bce_CP_b09FwBss;
2862
2863                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
2864                 fw.rodata_len = bce_CP_b09FwRodataLen;
2865                 fw.rodata_index = 0;
2866                 fw.rodata = bce_CP_b09FwRodata;
2867         } else {
2868                 fw.ver_major = bce_CP_b06FwReleaseMajor;
2869                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
2870                 fw.ver_fix = bce_CP_b06FwReleaseFix;
2871                 fw.start_addr = bce_CP_b06FwStartAddr;
2872
2873                 fw.text_addr = bce_CP_b06FwTextAddr;
2874                 fw.text_len = bce_CP_b06FwTextLen;
2875                 fw.text_index = 0;
2876                 fw.text = bce_CP_b06FwText;
2877
2878                 fw.data_addr = bce_CP_b06FwDataAddr;
2879                 fw.data_len = bce_CP_b06FwDataLen;
2880                 fw.data_index = 0;
2881                 fw.data = bce_CP_b06FwData;
2882
2883                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
2884                 fw.sbss_len = bce_CP_b06FwSbssLen;
2885                 fw.sbss_index = 0;
2886                 fw.sbss = bce_CP_b06FwSbss;
2887
2888                 fw.bss_addr = bce_CP_b06FwBssAddr;
2889                 fw.bss_len = bce_CP_b06FwBssLen;
2890                 fw.bss_index = 0;
2891                 fw.bss = bce_CP_b06FwBss;
2892
2893                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
2894                 fw.rodata_len = bce_CP_b06FwRodataLen;
2895                 fw.rodata_index = 0;
2896                 fw.rodata = bce_CP_b06FwRodata;
2897         }
2898
2899         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
2900         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2901 }
2902
2903
2904 /****************************************************************************/
2905 /* Initialize the COM CPU.                                                 */
2906 /*                                                                          */
2907 /* Returns:                                                                 */
2908 /*   Nothing.                                                               */
2909 /****************************************************************************/
2910 static void
2911 bce_init_com_cpu(struct bce_softc *sc)
2912 {
2913         struct cpu_reg cpu_reg;
2914         struct fw_info fw;
2915
2916         cpu_reg.mode = BCE_COM_CPU_MODE;
2917         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
2918         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
2919         cpu_reg.state = BCE_COM_CPU_STATE;
2920         cpu_reg.state_value_clear = 0xffffff;
2921         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
2922         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
2923         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
2924         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
2925         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
2926         cpu_reg.spad_base = BCE_COM_SCRATCH;
2927         cpu_reg.mips_view_base = 0x8000000;
2928
2929         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2930             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2931                 fw.ver_major = bce_COM_b09FwReleaseMajor;
2932                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
2933                 fw.ver_fix = bce_COM_b09FwReleaseFix;
2934                 fw.start_addr = bce_COM_b09FwStartAddr;
2935
2936                 fw.text_addr = bce_COM_b09FwTextAddr;
2937                 fw.text_len = bce_COM_b09FwTextLen;
2938                 fw.text_index = 0;
2939                 fw.text = bce_COM_b09FwText;
2940
2941                 fw.data_addr = bce_COM_b09FwDataAddr;
2942                 fw.data_len = bce_COM_b09FwDataLen;
2943                 fw.data_index = 0;
2944                 fw.data = bce_COM_b09FwData;
2945
2946                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
2947                 fw.sbss_len = bce_COM_b09FwSbssLen;
2948                 fw.sbss_index = 0;
2949                 fw.sbss = bce_COM_b09FwSbss;
2950
2951                 fw.bss_addr = bce_COM_b09FwBssAddr;
2952                 fw.bss_len = bce_COM_b09FwBssLen;
2953                 fw.bss_index = 0;
2954                 fw.bss = bce_COM_b09FwBss;
2955
2956                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
2957                 fw.rodata_len = bce_COM_b09FwRodataLen;
2958                 fw.rodata_index = 0;
2959                 fw.rodata = bce_COM_b09FwRodata;
2960         } else {
2961                 fw.ver_major = bce_COM_b06FwReleaseMajor;
2962                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
2963                 fw.ver_fix = bce_COM_b06FwReleaseFix;
2964                 fw.start_addr = bce_COM_b06FwStartAddr;
2965
2966                 fw.text_addr = bce_COM_b06FwTextAddr;
2967                 fw.text_len = bce_COM_b06FwTextLen;
2968                 fw.text_index = 0;
2969                 fw.text = bce_COM_b06FwText;
2970
2971                 fw.data_addr = bce_COM_b06FwDataAddr;
2972                 fw.data_len = bce_COM_b06FwDataLen;
2973                 fw.data_index = 0;
2974                 fw.data = bce_COM_b06FwData;
2975
2976                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
2977                 fw.sbss_len = bce_COM_b06FwSbssLen;
2978                 fw.sbss_index = 0;
2979                 fw.sbss = bce_COM_b06FwSbss;
2980
2981                 fw.bss_addr = bce_COM_b06FwBssAddr;
2982                 fw.bss_len = bce_COM_b06FwBssLen;
2983                 fw.bss_index = 0;
2984                 fw.bss = bce_COM_b06FwBss;
2985
2986                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
2987                 fw.rodata_len = bce_COM_b06FwRodataLen;
2988                 fw.rodata_index = 0;
2989                 fw.rodata = bce_COM_b06FwRodata;
2990         }
2991
2992         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
2993         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2994 }
2995
2996
2997 /****************************************************************************/
2998 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
2999 /*                                                                          */
3000 /* Loads the firmware for each CPU and starts the CPU.                      */
3001 /*                                                                          */
3002 /* Returns:                                                                 */
3003 /*   Nothing.                                                               */
3004 /****************************************************************************/
3005 static void
3006 bce_init_cpus(struct bce_softc *sc)
3007 {
3008         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3009             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3010                 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, sizeof(bce_xi_rv2p_proc1),
3011                         RV2P_PROC1);
3012                 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, sizeof(bce_xi_rv2p_proc2),
3013                         RV2P_PROC2);
3014         } else {
3015                 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1),
3016                         RV2P_PROC1);
3017                 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2),
3018                         RV2P_PROC2);
3019         }
3020
3021         bce_init_rxp_cpu(sc);
3022         bce_init_txp_cpu(sc);
3023         bce_init_tpat_cpu(sc);
3024         bce_init_com_cpu(sc);
3025         bce_init_cp_cpu(sc);
3026 }
3027
3028
3029 /****************************************************************************/
3030 /* Initialize context memory.                                               */
3031 /*                                                                          */
3032 /* Clears the memory associated with each Context ID (CID).                 */
3033 /*                                                                          */
3034 /* Returns:                                                                 */
3035 /*   Nothing.                                                               */
3036 /****************************************************************************/
3037 static void
3038 bce_init_ctx(struct bce_softc *sc)
3039 {
3040         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3041             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3042                 /* DRC: Replace this constant value with a #define. */
3043                 int i, retry_cnt = 10;
3044                 uint32_t val;
3045
3046                 /*
3047                  * BCM5709 context memory may be cached
3048                  * in host memory so prepare the host memory
3049                  * for access.
3050                  */
3051                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3052                     (1 << 12);
3053                 val |= (BCM_PAGE_BITS - 8) << 16;
3054                 REG_WR(sc, BCE_CTX_COMMAND, val);
3055
3056                 /* Wait for mem init command to complete. */
3057                 for (i = 0; i < retry_cnt; i++) {
3058                         val = REG_RD(sc, BCE_CTX_COMMAND);
3059                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3060                                 break;
3061                         DELAY(2);
3062                 }
3063
3064                 for (i = 0; i < sc->ctx_pages; i++) {
3065                         int j;
3066
3067                         /*
3068                          * Set the physical address of the context
3069                          * memory cache.
3070                          */
3071                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3072                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3073                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3074                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3075                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3076                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3077                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3078
3079                         /*
3080                          * Verify that the context memory write was successful.
3081                          */
3082                         for (j = 0; j < retry_cnt; j++) {
3083                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3084                                 if ((val &
3085                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3086                                         break;
3087                                 DELAY(5);
3088                         }
3089                 }
3090         } else {
3091                 uint32_t vcid_addr, offset;
3092
3093                 /*
3094                  * For the 5706/5708, context memory is local to
3095                  * the controller, so initialize the controller
3096                  * context memory.
3097                  */
3098
3099                 vcid_addr = GET_CID_ADDR(96);
3100                 while (vcid_addr) {
3101                         vcid_addr -= PHY_CTX_SIZE;
3102
3103                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3104                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3105
3106                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3107                                 CTX_WR(sc, 0x00, offset, 0);
3108
3109                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3110                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3111                 }
3112         }
3113 }
3114
3115
3116 /****************************************************************************/
3117 /* Fetch the permanent MAC address of the controller.                       */
3118 /*                                                                          */
3119 /* Returns:                                                                 */
3120 /*   Nothing.                                                               */
3121 /****************************************************************************/
3122 static void
3123 bce_get_mac_addr(struct bce_softc *sc)
3124 {
3125         uint32_t mac_lo = 0, mac_hi = 0;
3126
3127         /*
3128          * The NetXtreme II bootcode populates various NIC
3129          * power-on and runtime configuration items in a
3130          * shared memory area.  The factory configured MAC
3131          * address is available from both NVRAM and the
3132          * shared memory area so we'll read the value from
3133          * shared memory for speed.
3134          */
3135
3136         mac_hi = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_UPPER);
3137         mac_lo = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_HW_CFG_MAC_LOWER);
3138
3139         if (mac_lo == 0 && mac_hi == 0) {
3140                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3141         } else {
3142                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3143                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3144                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3145                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3146                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3147                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3148         }
3149
3150         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3151 }
3152
3153
3154 /****************************************************************************/
3155 /* Program the MAC address.                                                 */
3156 /*                                                                          */
3157 /* Returns:                                                                 */
3158 /*   Nothing.                                                               */
3159 /****************************************************************************/
3160 static void
3161 bce_set_mac_addr(struct bce_softc *sc)
3162 {
3163         const uint8_t *mac_addr = sc->eaddr;
3164         uint32_t val;
3165
3166         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3167                 sc->eaddr, ":");
3168
3169         val = (mac_addr[0] << 8) | mac_addr[1];
3170         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3171
3172         val = (mac_addr[2] << 24) |
3173               (mac_addr[3] << 16) |
3174               (mac_addr[4] << 8) |
3175               mac_addr[5];
3176         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3177 }
3178
3179
3180 /****************************************************************************/
3181 /* Stop the controller.                                                     */
3182 /*                                                                          */
3183 /* Returns:                                                                 */
3184 /*   Nothing.                                                               */
3185 /****************************************************************************/
3186 static void
3187 bce_stop(struct bce_softc *sc)
3188 {
3189         struct ifnet *ifp = &sc->arpcom.ac_if;
3190         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3191         struct ifmedia_entry *ifm;
3192         int mtmp, itmp;
3193
3194         ASSERT_SERIALIZED(ifp->if_serializer);
3195
3196         callout_stop(&sc->bce_tick_callout);
3197
3198         /* Disable the transmit/receive blocks. */
3199         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3200         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3201         DELAY(20);
3202
3203         bce_disable_intr(sc);
3204
3205         /* Free the RX lists. */
3206         bce_free_rx_chain(sc);
3207
3208         /* Free TX buffers. */
3209         bce_free_tx_chain(sc);
3210
3211         /*
3212          * Isolate/power down the PHY, but leave the media selection
3213          * unchanged so that things will be put back to normal when
3214          * we bring the interface back up.
3215          *
3216          * 'mii' may be NULL if bce_stop() is called by bce_detach().
3217          */
3218         if (mii != NULL) {
3219                 itmp = ifp->if_flags;
3220                 ifp->if_flags |= IFF_UP;
3221                 ifm = mii->mii_media.ifm_cur;
3222                 mtmp = ifm->ifm_media;
3223                 ifm->ifm_media = IFM_ETHER | IFM_NONE;
3224                 mii_mediachg(mii);
3225                 ifm->ifm_media = mtmp;
3226                 ifp->if_flags = itmp;
3227         }
3228
3229         sc->bce_link = 0;
3230         sc->bce_coalchg_mask = 0;
3231
3232         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3233         ifp->if_timer = 0;
3234 }
3235
3236
3237 static int
3238 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3239 {
3240         uint32_t val;
3241         int i, rc = 0;
3242
3243         /* Wait for pending PCI transactions to complete. */
3244         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3245                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3246                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3247                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3248                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3249         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3250         DELAY(5);
3251
3252         /* Disable DMA */
3253         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3254             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3255                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3256                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3257                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3258         }
3259
3260         /* Assume bootcode is running. */
3261         sc->bce_fw_timed_out = 0;
3262
3263         /* Give the firmware a chance to prepare for the reset. */
3264         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3265         if (rc) {
3266                 if_printf(&sc->arpcom.ac_if,
3267                           "Firmware is not ready for reset\n");
3268                 return rc;
3269         }
3270
3271         /* Set a firmware reminder that this is a soft reset. */
3272         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
3273                    BCE_DRV_RESET_SIGNATURE_MAGIC);
3274
3275         /* Dummy read to force the chip to complete all current transactions. */
3276         val = REG_RD(sc, BCE_MISC_ID);
3277
3278         /* Chip reset. */
3279         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3280             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3281                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3282                 REG_RD(sc, BCE_MISC_COMMAND);
3283                 DELAY(5);
3284
3285                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3286                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3287
3288                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3289         } else {
3290                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3291                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3292                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3293                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3294
3295                 /* Allow up to 30us for reset to complete. */
3296                 for (i = 0; i < 10; i++) {
3297                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3298                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3299                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3300                                 break;
3301                         DELAY(10);
3302                 }
3303
3304                 /* Check that reset completed successfully. */
3305                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3306                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3307                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3308                         return EBUSY;
3309                 }
3310         }
3311
3312         /* Make sure byte swapping is properly configured. */
3313         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3314         if (val != 0x01020304) {
3315                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3316                 return ENODEV;
3317         }
3318
3319         /* Just completed a reset, assume that firmware is running again. */
3320         sc->bce_fw_timed_out = 0;
3321
3322         /* Wait for the firmware to finish its initialization. */
3323         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3324         if (rc) {
3325                 if_printf(&sc->arpcom.ac_if,
3326                           "Firmware did not complete initialization!\n");
3327         }
3328         return rc;
3329 }
3330
3331
3332 static int
3333 bce_chipinit(struct bce_softc *sc)
3334 {
3335         uint32_t val;
3336         int rc = 0;
3337
3338         /* Make sure the interrupt is not active. */
3339         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3340         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3341
3342         /*
3343          * Initialize DMA byte/word swapping, configure the number of DMA
3344          * channels and PCI clock compensation delay.
3345          */
3346         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3347               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3348 #if BYTE_ORDER == BIG_ENDIAN
3349               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3350 #endif
3351               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3352               DMA_READ_CHANS << 12 |
3353               DMA_WRITE_CHANS << 16;
3354
3355         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3356
3357         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3358                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3359
3360         /*
3361          * This setting resolves a problem observed on certain Intel PCI
3362          * chipsets that cannot handle multiple outstanding DMA operations.
3363          * See errata E9_5706A1_65.
3364          */
3365         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3366             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3367             !(sc->bce_flags & BCE_PCIX_FLAG))
3368                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3369
3370         REG_WR(sc, BCE_DMA_CONFIG, val);
3371
3372         /* Enable the RX_V2P and Context state machines before access. */
3373         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3374                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3375                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3376                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3377
3378         /* Initialize context mapping and zero out the quick contexts. */
3379         bce_init_ctx(sc);
3380
3381         /* Initialize the on-boards CPUs */
3382         bce_init_cpus(sc);
3383
3384         /* Prepare NVRAM for access. */
3385         rc = bce_init_nvram(sc);
3386         if (rc != 0)
3387                 return rc;
3388
3389         /* Set the kernel bypass block size */
3390         val = REG_RD(sc, BCE_MQ_CONFIG);
3391         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3392         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3393
3394         /* Enable bins used on the 5709/5716. */
3395         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3396             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3397                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3398                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3399                         val |= BCE_MQ_CONFIG_HALT_DIS;
3400         }
3401
3402         REG_WR(sc, BCE_MQ_CONFIG, val);
3403
3404         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3405         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3406         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3407
3408         /* Set the page size and clear the RV2P processor stall bits. */
3409         val = (BCM_PAGE_BITS - 8) << 24;
3410         REG_WR(sc, BCE_RV2P_CONFIG, val);
3411
3412         /* Configure page size. */
3413         val = REG_RD(sc, BCE_TBDR_CONFIG);
3414         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3415         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3416         REG_WR(sc, BCE_TBDR_CONFIG, val);
3417
3418         /* Set the perfect match control register to default. */
3419         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3420
3421         return 0;
3422 }
3423
3424
3425 /****************************************************************************/
3426 /* Initialize the controller in preparation to send/receive traffic.        */
3427 /*                                                                          */
3428 /* Returns:                                                                 */
3429 /*   0 for success, positive value for failure.                             */
3430 /****************************************************************************/
3431 static int
3432 bce_blockinit(struct bce_softc *sc)
3433 {
3434         uint32_t reg, val;
3435         int rc = 0;
3436
3437         /* Load the hardware default MAC address. */
3438         bce_set_mac_addr(sc);
3439
3440         /* Set the Ethernet backoff seed value */
3441         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3442               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3443         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3444
3445         sc->last_status_idx = 0;
3446         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3447
3448         /* Set up link change interrupt generation. */
3449         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3450
3451         /* Program the physical address of the status block. */
3452         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3453         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3454
3455         /* Program the physical address of the statistics block. */
3456         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3457                BCE_ADDR_LO(sc->stats_block_paddr));
3458         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3459                BCE_ADDR_HI(sc->stats_block_paddr));
3460
3461         /* Program various host coalescing parameters. */
3462         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3463                (sc->bce_tx_quick_cons_trip_int << 16) |
3464                sc->bce_tx_quick_cons_trip);
3465         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3466                (sc->bce_rx_quick_cons_trip_int << 16) |
3467                sc->bce_rx_quick_cons_trip);
3468         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3469                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3470         REG_WR(sc, BCE_HC_TX_TICKS,
3471                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3472         REG_WR(sc, BCE_HC_RX_TICKS,
3473                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3474         REG_WR(sc, BCE_HC_COM_TICKS,
3475                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3476         REG_WR(sc, BCE_HC_CMD_TICKS,
3477                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3478         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3479         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3480         REG_WR(sc, BCE_HC_CONFIG,
3481                BCE_HC_CONFIG_TX_TMR_MODE |
3482                BCE_HC_CONFIG_COLLECT_STATS);
3483
3484         /* Clear the internal statistics counters. */
3485         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3486
3487         /* Verify that bootcode is running. */
3488         reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
3489
3490         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3491                 if_printf(&sc->arpcom.ac_if,
3492                           "%s(%d): Simulating bootcode failure.\n",
3493                           __FILE__, __LINE__);
3494                 reg = 0);
3495
3496         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3497             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3498                 if_printf(&sc->arpcom.ac_if,
3499                           "Bootcode not running! Found: 0x%08X, "
3500                           "Expected: 08%08X\n",
3501                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3502                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3503                 return ENODEV;
3504         }
3505
3506         /* Enable DMA */
3507         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3508             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3509                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3510                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3511                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3512         }
3513
3514         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3515         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3516
3517         /* Enable link state change interrupt generation. */
3518         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3519
3520         /* Enable all remaining blocks in the MAC. */
3521         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3522             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3523                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3524                     BCE_MISC_ENABLE_DEFAULT_XI);
3525         } else {
3526                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3527         }
3528         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3529         DELAY(20);
3530
3531         /* Save the current host coalescing block settings. */
3532         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3533
3534         return 0;
3535 }
3536
3537
3538 /****************************************************************************/
3539 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3540 /*                                                                          */
3541 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3542 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3543 /* necessary.                                                               */
3544 /*                                                                          */
3545 /* Returns:                                                                 */
3546 /*   0 for success, positive value for failure.                             */
3547 /****************************************************************************/
3548 static int
3549 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3550                uint32_t *prod_bseq, int init)
3551 {
3552         bus_dmamap_t map;
3553         bus_dma_segment_t seg;
3554         struct mbuf *m_new;
3555         int error, nseg;
3556 #ifdef BCE_DEBUG
3557         uint16_t debug_chain_prod = *chain_prod;
3558 #endif
3559
3560         /* Make sure the inputs are valid. */
3561         DBRUNIF((*chain_prod > MAX_RX_BD),
3562                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3563                           "RX producer out of range: 0x%04X > 0x%04X\n",
3564                           __FILE__, __LINE__,
3565                           *chain_prod, (uint16_t)MAX_RX_BD));
3566
3567         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3568                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3569
3570         DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3571                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3572                           "Simulating mbuf allocation failure.\n",
3573                           __FILE__, __LINE__);
3574                 sc->mbuf_alloc_failed++;
3575                 return ENOBUFS);
3576
3577         /* This is a new mbuf allocation. */
3578         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3579         if (m_new == NULL)
3580                 return ENOBUFS;
3581         DBRUNIF(1, sc->rx_mbuf_alloc++);
3582
3583         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3584
3585         /* Map the mbuf cluster into device memory. */
3586         error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3587                         sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3588                         BUS_DMA_NOWAIT);
3589         if (error) {
3590                 m_freem(m_new);
3591                 if (init) {
3592                         if_printf(&sc->arpcom.ac_if,
3593                                   "Error mapping mbuf into RX chain!\n");
3594                 }
3595                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3596                 return error;
3597         }
3598
3599         if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3600                 bus_dmamap_unload(sc->rx_mbuf_tag,
3601                                   sc->rx_mbuf_map[*chain_prod]);
3602         }
3603
3604         map = sc->rx_mbuf_map[*chain_prod];
3605         sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3606         sc->rx_mbuf_tmpmap = map;
3607
3608         /* Watch for overflow. */
3609         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD),
3610                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3611                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3612                           __FILE__, __LINE__, sc->free_rx_bd,
3613                           (uint16_t)USABLE_RX_BD));
3614
3615         /* Update some debug statistic counters */
3616         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3617                 sc->rx_low_watermark = sc->free_rx_bd);
3618         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3619
3620         /* Save the mbuf and update our counter. */
3621         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3622         sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3623         sc->free_rx_bd--;
3624
3625         bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3626
3627         DBRUN(BCE_VERBOSE_RECV,
3628               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3629
3630         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3631                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3632
3633         return 0;
3634 }
3635
3636
3637 static void
3638 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3639 {
3640         struct rx_bd *rxbd;
3641         bus_addr_t paddr;
3642         int len;
3643
3644         paddr = sc->rx_mbuf_paddr[chain_prod];
3645         len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3646
3647         /* Setup the rx_bd for the first segment. */
3648         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3649
3650         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3651         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3652         rxbd->rx_bd_len = htole32(len);
3653         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3654         *prod_bseq += len;
3655
3656         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3657 }
3658
3659
3660 /****************************************************************************/
3661 /* Initialize the TX context memory.                                        */
3662 /*                                                                          */
3663 /* Returns:                                                                 */
3664 /*   Nothing                                                                */
3665 /****************************************************************************/
3666 static void
3667 bce_init_tx_context(struct bce_softc *sc)
3668 {
3669         uint32_t val;
3670
3671         /* Initialize the context ID for an L2 TX chain. */
3672         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3673             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3674                 /* Set the CID type to support an L2 connection. */
3675                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3676                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3677                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3678                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3679
3680                 /* Point the hardware to the first page in the chain. */
3681                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3682                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3683                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3684                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3685                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3686                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3687         } else {
3688                 /* Set the CID type to support an L2 connection. */
3689                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3690                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3691                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3692                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3693
3694                 /* Point the hardware to the first page in the chain. */
3695                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3696                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3697                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3698                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3699                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3700                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3701         }
3702 }
3703
3704
3705 /****************************************************************************/
3706 /* Allocate memory and initialize the TX data structures.                   */
3707 /*                                                                          */
3708 /* Returns:                                                                 */
3709 /*   0 for success, positive value for failure.                             */
3710 /****************************************************************************/
3711 static int
3712 bce_init_tx_chain(struct bce_softc *sc)
3713 {
3714         struct tx_bd *txbd;
3715         int i, rc = 0;
3716
3717         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3718
3719         /* Set the initial TX producer/consumer indices. */
3720         sc->tx_prod = 0;
3721         sc->tx_cons = 0;
3722         sc->tx_prod_bseq   = 0;
3723         sc->used_tx_bd = 0;
3724         sc->max_tx_bd = USABLE_TX_BD;
3725         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD);
3726         DBRUNIF(1, sc->tx_full_count = 0);
3727
3728         /*
3729          * The NetXtreme II supports a linked-list structre called
3730          * a Buffer Descriptor Chain (or BD chain).  A BD chain
3731          * consists of a series of 1 or more chain pages, each of which
3732          * consists of a fixed number of BD entries.
3733          * The last BD entry on each page is a pointer to the next page
3734          * in the chain, and the last pointer in the BD chain
3735          * points back to the beginning of the chain.
3736          */
3737
3738         /* Set the TX next pointer chain entries. */
3739         for (i = 0; i < TX_PAGES; i++) {
3740                 int j;
3741
3742                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
3743
3744                 /* Check if we've reached the last page. */
3745                 if (i == (TX_PAGES - 1))
3746                         j = 0;
3747                 else
3748                         j = i + 1;
3749
3750                 txbd->tx_bd_haddr_hi =
3751                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
3752                 txbd->tx_bd_haddr_lo =
3753                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
3754         }
3755         bce_init_tx_context(sc);
3756
3757         return(rc);
3758 }
3759
3760
3761 /****************************************************************************/
3762 /* Free memory and clear the TX data structures.                            */
3763 /*                                                                          */
3764 /* Returns:                                                                 */
3765 /*   Nothing.                                                               */
3766 /****************************************************************************/
3767 static void
3768 bce_free_tx_chain(struct bce_softc *sc)
3769 {
3770         int i;
3771
3772         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3773
3774         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
3775         for (i = 0; i < TOTAL_TX_BD; i++) {
3776                 if (sc->tx_mbuf_ptr[i] != NULL) {
3777                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
3778                         m_freem(sc->tx_mbuf_ptr[i]);
3779                         sc->tx_mbuf_ptr[i] = NULL;
3780                         DBRUNIF(1, sc->tx_mbuf_alloc--);
3781                 }
3782         }
3783
3784         /* Clear each TX chain page. */
3785         for (i = 0; i < TX_PAGES; i++)
3786                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
3787         sc->used_tx_bd = 0;
3788
3789         /* Check if we lost any mbufs in the process. */
3790         DBRUNIF((sc->tx_mbuf_alloc),
3791                 if_printf(&sc->arpcom.ac_if,
3792                           "%s(%d): Memory leak! "
3793                           "Lost %d mbufs from tx chain!\n",
3794                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
3795
3796         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3797 }
3798
3799
3800 /****************************************************************************/
3801 /* Initialize the RX context memory.                                        */
3802 /*                                                                          */
3803 /* Returns:                                                                 */
3804 /*   Nothing                                                                */
3805 /****************************************************************************/
3806 static void
3807 bce_init_rx_context(struct bce_softc *sc)
3808 {
3809         uint32_t val;
3810
3811         /* Initialize the context ID for an L2 RX chain. */
3812         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
3813             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
3814
3815         /*
3816          * Set the level for generating pause frames
3817          * when the number of available rx_bd's gets
3818          * too low (the low watermark) and the level
3819          * when pause frames can be stopped (the high
3820          * watermark).
3821          */
3822         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3823             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3824                 uint32_t lo_water, hi_water;
3825
3826                 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
3827                 hi_water = USABLE_RX_BD / 4;
3828
3829                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
3830                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
3831
3832                 if (hi_water > 0xf)
3833                         hi_water = 0xf;
3834                 else if (hi_water == 0)
3835                         lo_water = 0;
3836                 val |= lo_water |
3837                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
3838         }
3839
3840         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
3841
3842         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
3843         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3844             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3845                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
3846                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
3847         }
3848
3849         /* Point the hardware to the first page in the chain. */
3850         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
3851         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
3852         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
3853         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
3854 }
3855
3856
3857 /****************************************************************************/
3858 /* Allocate memory and initialize the RX data structures.                   */
3859 /*                                                                          */
3860 /* Returns:                                                                 */
3861 /*   0 for success, positive value for failure.                             */
3862 /****************************************************************************/
3863 static int
3864 bce_init_rx_chain(struct bce_softc *sc)
3865 {
3866         struct rx_bd *rxbd;
3867         int i, rc = 0;
3868         uint16_t prod, chain_prod;
3869         uint32_t prod_bseq;
3870
3871         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3872
3873         /* Initialize the RX producer and consumer indices. */
3874         sc->rx_prod = 0;
3875         sc->rx_cons = 0;
3876         sc->rx_prod_bseq = 0;
3877         sc->free_rx_bd = USABLE_RX_BD;
3878         sc->max_rx_bd = USABLE_RX_BD;
3879         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD);
3880         DBRUNIF(1, sc->rx_empty_count = 0);
3881
3882         /* Initialize the RX next pointer chain entries. */
3883         for (i = 0; i < RX_PAGES; i++) {
3884                 int j;
3885
3886                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
3887
3888                 /* Check if we've reached the last page. */
3889                 if (i == (RX_PAGES - 1))
3890                         j = 0;
3891                 else
3892                         j = i + 1;
3893
3894                 /* Setup the chain page pointers. */
3895                 rxbd->rx_bd_haddr_hi =
3896                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
3897                 rxbd->rx_bd_haddr_lo =
3898                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
3899         }
3900
3901         /* Allocate mbuf clusters for the rx_bd chain. */
3902         prod = prod_bseq = 0;
3903         while (prod < TOTAL_RX_BD) {
3904                 chain_prod = RX_CHAIN_IDX(prod);
3905                 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
3906                         if_printf(&sc->arpcom.ac_if,
3907                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
3908                                   chain_prod);
3909                         rc = ENOBUFS;
3910                         break;
3911                 }
3912                 prod = NEXT_RX_BD(prod);
3913         }
3914
3915         /* Save the RX chain producer index. */
3916         sc->rx_prod = prod;
3917         sc->rx_prod_bseq = prod_bseq;
3918
3919         /* Tell the chip about the waiting rx_bd's. */
3920         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
3921             sc->rx_prod);
3922         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
3923             sc->rx_prod_bseq);
3924
3925         bce_init_rx_context(sc);
3926
3927         return(rc);
3928 }
3929
3930
3931 /****************************************************************************/
3932 /* Free memory and clear the RX data structures.                            */
3933 /*                                                                          */
3934 /* Returns:                                                                 */
3935 /*   Nothing.                                                               */
3936 /****************************************************************************/
3937 static void
3938 bce_free_rx_chain(struct bce_softc *sc)
3939 {
3940         int i;
3941
3942         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
3943
3944         /* Free any mbufs still in the RX mbuf chain. */
3945         for (i = 0; i < TOTAL_RX_BD; i++) {
3946                 if (sc->rx_mbuf_ptr[i] != NULL) {
3947                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
3948                         m_freem(sc->rx_mbuf_ptr[i]);
3949                         sc->rx_mbuf_ptr[i] = NULL;
3950                         DBRUNIF(1, sc->rx_mbuf_alloc--);
3951                 }
3952         }
3953
3954         /* Clear each RX chain page. */
3955         for (i = 0; i < RX_PAGES; i++)
3956                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
3957
3958         /* Check if we lost any mbufs in the process. */
3959         DBRUNIF((sc->rx_mbuf_alloc),
3960                 if_printf(&sc->arpcom.ac_if,
3961                           "%s(%d): Memory leak! "
3962                           "Lost %d mbufs from rx chain!\n",
3963                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
3964
3965         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
3966 }
3967
3968
3969 /****************************************************************************/
3970 /* Set media options.                                                       */
3971 /*                                                                          */
3972 /* Returns:                                                                 */
3973 /*   0 for success, positive value for failure.                             */
3974 /****************************************************************************/
3975 static int
3976 bce_ifmedia_upd(struct ifnet *ifp)
3977 {
3978         struct bce_softc *sc = ifp->if_softc;
3979         struct mii_data *mii = device_get_softc(sc->bce_miibus);
3980
3981         /*
3982          * 'mii' will be NULL, when this function is called on following
3983          * code path: bce_attach() -> bce_mgmt_init()
3984          */
3985         if (mii != NULL) {
3986                 /* Make sure the MII bus has been enumerated. */
3987                 sc->bce_link = 0;
3988                 if (mii->mii_instance) {
3989                         struct mii_softc *miisc;
3990
3991                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3992                                 mii_phy_reset(miisc);
3993                 }
3994                 mii_mediachg(mii);
3995         }
3996         return 0;
3997 }
3998
3999
4000 /****************************************************************************/
4001 /* Reports current media status.                                            */
4002 /*                                                                          */
4003 /* Returns:                                                                 */
4004 /*   Nothing.                                                               */
4005 /****************************************************************************/
4006 static void
4007 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4008 {
4009         struct bce_softc *sc = ifp->if_softc;
4010         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4011
4012         mii_pollstat(mii);
4013         ifmr->ifm_active = mii->mii_media_active;
4014         ifmr->ifm_status = mii->mii_media_status;
4015 }
4016
4017
4018 /****************************************************************************/
4019 /* Handles PHY generated interrupt events.                                  */
4020 /*                                                                          */
4021 /* Returns:                                                                 */
4022 /*   Nothing.                                                               */
4023 /****************************************************************************/
4024 static void
4025 bce_phy_intr(struct bce_softc *sc)
4026 {
4027         uint32_t new_link_state, old_link_state;
4028         struct ifnet *ifp = &sc->arpcom.ac_if;
4029
4030         ASSERT_SERIALIZED(ifp->if_serializer);
4031
4032         new_link_state = sc->status_block->status_attn_bits &
4033                          STATUS_ATTN_BITS_LINK_STATE;
4034         old_link_state = sc->status_block->status_attn_bits_ack &
4035                          STATUS_ATTN_BITS_LINK_STATE;
4036
4037         /* Handle any changes if the link state has changed. */
4038         if (new_link_state != old_link_state) { /* XXX redundant? */
4039                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4040
4041                 /* Update the status_attn_bits_ack field in the status block. */
4042                 if (new_link_state) {
4043                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4044                                STATUS_ATTN_BITS_LINK_STATE);
4045                         if (bootverbose)
4046                                 if_printf(ifp, "Link is now UP.\n");
4047                 } else {
4048                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4049                                STATUS_ATTN_BITS_LINK_STATE);
4050                         if (bootverbose)
4051                                 if_printf(ifp, "Link is now DOWN.\n");
4052                 }
4053
4054                 /*
4055                  * Assume link is down and allow tick routine to
4056                  * update the state based on the actual media state.
4057                  */
4058                 sc->bce_link = 0;
4059                 callout_stop(&sc->bce_tick_callout);
4060                 bce_tick_serialized(sc);
4061         }
4062
4063         /* Acknowledge the link change interrupt. */
4064         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4065 }
4066
4067
4068 /****************************************************************************/
4069 /* Reads the receive consumer value from the status block (skipping over    */
4070 /* chain page pointer if necessary).                                        */
4071 /*                                                                          */
4072 /* Returns:                                                                 */
4073 /*   hw_cons                                                                */
4074 /****************************************************************************/
4075 static __inline uint16_t
4076 bce_get_hw_rx_cons(struct bce_softc *sc)
4077 {
4078         uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4079
4080         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4081                 hw_cons++;
4082         return hw_cons;
4083 }
4084
4085
4086 /****************************************************************************/
4087 /* Handles received frame interrupt events.                                 */
4088 /*                                                                          */
4089 /* Returns:                                                                 */
4090 /*   Nothing.                                                               */
4091 /****************************************************************************/
4092 static void
4093 bce_rx_intr(struct bce_softc *sc, int count)
4094 {
4095         struct ifnet *ifp = &sc->arpcom.ac_if;
4096         uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4097         uint32_t sw_prod_bseq;
4098         struct mbuf_chain chain[MAXCPU];
4099
4100         ASSERT_SERIALIZED(ifp->if_serializer);
4101
4102         ether_input_chain_init(chain);
4103
4104         DBRUNIF(1, sc->rx_interrupts++);
4105
4106         /* Get the hardware's view of the RX consumer index. */
4107         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4108
4109         /* Get working copies of the driver's view of the RX indices. */
4110         sw_cons = sc->rx_cons;
4111         sw_prod = sc->rx_prod;
4112         sw_prod_bseq = sc->rx_prod_bseq;
4113
4114         DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4115                 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4116                 __func__, sw_prod, sw_cons, sw_prod_bseq);
4117
4118         /* Prevent speculative reads from getting ahead of the status block. */
4119         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4120                           BUS_SPACE_BARRIER_READ);
4121
4122         /* Update some debug statistics counters */
4123         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4124                 sc->rx_low_watermark = sc->free_rx_bd);
4125         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4126
4127         /* Scan through the receive chain as long as there is work to do. */
4128         while (sw_cons != hw_cons) {
4129                 struct mbuf *m = NULL;
4130                 struct l2_fhdr *l2fhdr = NULL;
4131                 struct rx_bd *rxbd;
4132                 unsigned int len;
4133                 uint32_t status = 0;
4134
4135 #ifdef DEVICE_POLLING
4136                 if (count >= 0 && count-- == 0) {
4137                         sc->hw_rx_cons = sw_cons;
4138                         break;
4139                 }
4140 #endif
4141
4142                 /*
4143                  * Convert the producer/consumer indices
4144                  * to an actual rx_bd index.
4145                  */
4146                 sw_chain_cons = RX_CHAIN_IDX(sw_cons);
4147                 sw_chain_prod = RX_CHAIN_IDX(sw_prod);
4148
4149                 /* Get the used rx_bd. */
4150                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4151                                        [RX_IDX(sw_chain_cons)];
4152                 sc->free_rx_bd++;
4153
4154                 DBRUN(BCE_VERBOSE_RECV,
4155                       if_printf(ifp, "%s(): ", __func__);
4156                       bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4157
4158                 /* The mbuf is stored with the last rx_bd entry of a packet. */
4159                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4160                         /* Validate that this is the last rx_bd. */
4161                         DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4162                                 if_printf(ifp, "%s(%d): "
4163                                 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4164                                 __FILE__, __LINE__, sw_chain_cons);
4165                                 bce_breakpoint(sc));
4166
4167                         if (sw_chain_cons != sw_chain_prod) {
4168                                 if_printf(ifp, "RX cons(%d) != prod(%d), "
4169                                           "drop!\n", sw_chain_cons,
4170                                           sw_chain_prod);
4171                                 ifp->if_ierrors++;
4172
4173                                 bce_setup_rxdesc_std(sc, sw_chain_cons,
4174                                                      &sw_prod_bseq);
4175                                 m = NULL;
4176                                 goto bce_rx_int_next_rx;
4177                         }
4178
4179                         /* Unmap the mbuf from DMA space. */
4180                         bus_dmamap_sync(sc->rx_mbuf_tag,
4181                                         sc->rx_mbuf_map[sw_chain_cons],
4182                                         BUS_DMASYNC_POSTREAD);
4183
4184                         /* Save the mbuf from the driver's chain. */
4185                         m = sc->rx_mbuf_ptr[sw_chain_cons];
4186
4187                         /*
4188                          * Frames received on the NetXteme II are prepended
4189                          * with an l2_fhdr structure which provides status
4190                          * information about the received frame (including
4191                          * VLAN tags and checksum info).  The frames are also
4192                          * automatically adjusted to align the IP header
4193                          * (i.e. two null bytes are inserted before the
4194                          * Ethernet header).
4195                          */
4196                         l2fhdr = mtod(m, struct l2_fhdr *);
4197
4198                         len = l2fhdr->l2_fhdr_pkt_len;
4199                         status = l2fhdr->l2_fhdr_status;
4200
4201                         DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4202                                 if_printf(ifp,
4203                                 "Simulating l2_fhdr status error.\n");
4204                                 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4205
4206                         /* Watch for unusual sized frames. */
4207                         DBRUNIF((len < BCE_MIN_MTU ||
4208                                  len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4209                                 if_printf(ifp,
4210                                 "%s(%d): Unusual frame size found. "
4211                                 "Min(%d), Actual(%d), Max(%d)\n",
4212                                 __FILE__, __LINE__,
4213                                 (int)BCE_MIN_MTU, len,
4214                                 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4215                                 bce_dump_mbuf(sc, m);
4216                                 bce_breakpoint(sc));
4217
4218                         len -= ETHER_CRC_LEN;
4219
4220                         /* Check the received frame for errors. */
4221                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
4222                                       L2_FHDR_ERRORS_PHY_DECODE |
4223                                       L2_FHDR_ERRORS_ALIGNMENT |
4224                                       L2_FHDR_ERRORS_TOO_SHORT |
4225                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
4226                                 ifp->if_ierrors++;
4227                                 DBRUNIF(1, sc->l2fhdr_status_errors++);
4228
4229                                 /* Reuse the mbuf for a new frame. */
4230                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4231                                                      &sw_prod_bseq);
4232                                 m = NULL;
4233                                 goto bce_rx_int_next_rx;
4234                         }
4235
4236                         /*
4237                          * Get a new mbuf for the rx_bd.   If no new
4238                          * mbufs are available then reuse the current mbuf,
4239                          * log an ierror on the interface, and generate
4240                          * an error in the system log.
4241                          */
4242                         if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4243                                            &sw_prod_bseq, 0)) {
4244                                 DBRUN(BCE_WARN,
4245                                       if_printf(ifp,
4246                                       "%s(%d): Failed to allocate new mbuf, "
4247                                       "incoming frame dropped!\n",
4248                                       __FILE__, __LINE__));
4249
4250                                 ifp->if_ierrors++;
4251
4252                                 /* Try and reuse the exisitng mbuf. */
4253                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4254                                                      &sw_prod_bseq);
4255                                 m = NULL;
4256                                 goto bce_rx_int_next_rx;
4257                         }
4258
4259                         /*
4260                          * Skip over the l2_fhdr when passing
4261                          * the data up the stack.
4262                          */
4263                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4264
4265                         m->m_pkthdr.len = m->m_len = len;
4266                         m->m_pkthdr.rcvif = ifp;
4267
4268                         DBRUN(BCE_VERBOSE_RECV,
4269                               struct ether_header *eh;
4270                               eh = mtod(m, struct ether_header *);
4271                               if_printf(ifp, "%s(): to: %6D, from: %6D, "
4272                                         "type: 0x%04X\n", __func__,
4273                                         eh->ether_dhost, ":",
4274                                         eh->ether_shost, ":",
4275                                         htons(eh->ether_type)));
4276
4277                         /* Validate the checksum if offload enabled. */
4278                         if (ifp->if_capenable & IFCAP_RXCSUM) {
4279                                 /* Check for an IP datagram. */
4280                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4281                                         m->m_pkthdr.csum_flags |=
4282                                                 CSUM_IP_CHECKED;
4283
4284                                         /* Check if the IP checksum is valid. */
4285                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
4286                                              0xffff) == 0) {
4287                                                 m->m_pkthdr.csum_flags |=
4288                                                         CSUM_IP_VALID;
4289                                         } else {
4290                                                 DBPRINT(sc, BCE_WARN_RECV,
4291                                                         "%s(): Invalid IP checksum = 0x%04X!\n",
4292                                                         __func__, l2fhdr->l2_fhdr_ip_xsum);
4293                                         }
4294                                 }
4295
4296                                 /* Check for a valid TCP/UDP frame. */
4297                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4298                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
4299
4300                                         /* Check for a good TCP/UDP checksum. */
4301                                         if ((status &
4302                                              (L2_FHDR_ERRORS_TCP_XSUM |
4303                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4304                                                 m->m_pkthdr.csum_data =
4305                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
4306                                                 m->m_pkthdr.csum_flags |=
4307                                                         CSUM_DATA_VALID |
4308                                                         CSUM_PSEUDO_HDR;
4309                                         } else {
4310                                                 DBPRINT(sc, BCE_WARN_RECV,
4311                                                         "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4312                                                         __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4313                                         }
4314                                 }
4315                         }
4316
4317                         ifp->if_ipackets++;
4318 bce_rx_int_next_rx:
4319                         sw_prod = NEXT_RX_BD(sw_prod);
4320                 }
4321
4322                 sw_cons = NEXT_RX_BD(sw_cons);
4323
4324                 /* If we have a packet, pass it up the stack */
4325                 if (m) {
4326                         DBPRINT(sc, BCE_VERBOSE_RECV,
4327                                 "%s(): Passing received frame up.\n", __func__);
4328
4329                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4330                                 m->m_flags |= M_VLANTAG;
4331                                 m->m_pkthdr.ether_vlantag =
4332                                         l2fhdr->l2_fhdr_vlan_tag;
4333                         }
4334                         ether_input_chain(ifp, m, NULL, chain);
4335
4336                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4337                 }
4338
4339                 /*
4340                  * If polling(4) is not enabled, refresh hw_cons to see
4341                  * whether there's new work.
4342                  *
4343                  * If polling(4) is enabled, i.e count >= 0, refreshing
4344                  * should not be performed, so that we would not spend
4345                  * too much time in RX processing.
4346                  */
4347                 if (count < 0 && sw_cons == hw_cons)
4348                         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4349
4350                 /*
4351                  * Prevent speculative reads from getting ahead
4352                  * of the status block.
4353                  */
4354                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4355                                   BUS_SPACE_BARRIER_READ);
4356         }
4357
4358         ether_input_dispatch(chain);
4359
4360         sc->rx_cons = sw_cons;
4361         sc->rx_prod = sw_prod;
4362         sc->rx_prod_bseq = sw_prod_bseq;
4363
4364         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4365             sc->rx_prod);
4366         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4367             sc->rx_prod_bseq);
4368
4369         DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4370                 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4371                 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4372 }
4373
4374
4375 /****************************************************************************/
4376 /* Reads the transmit consumer value from the status block (skipping over   */
4377 /* chain page pointer if necessary).                                        */
4378 /*                                                                          */
4379 /* Returns:                                                                 */
4380 /*   hw_cons                                                                */
4381 /****************************************************************************/
4382 static __inline uint16_t
4383 bce_get_hw_tx_cons(struct bce_softc *sc)
4384 {
4385         uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4386
4387         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4388                 hw_cons++;
4389         return hw_cons;
4390 }
4391
4392
4393 /****************************************************************************/
4394 /* Handles transmit completion interrupt events.                            */
4395 /*                                                                          */
4396 /* Returns:                                                                 */
4397 /*   Nothing.                                                               */
4398 /****************************************************************************/
4399 static void
4400 bce_tx_intr(struct bce_softc *sc)
4401 {
4402         struct ifnet *ifp = &sc->arpcom.ac_if;
4403         uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4404
4405         ASSERT_SERIALIZED(ifp->if_serializer);
4406
4407         DBRUNIF(1, sc->tx_interrupts++);
4408
4409         /* Get the hardware's view of the TX consumer index. */
4410         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4411         sw_tx_cons = sc->tx_cons;
4412
4413         /* Prevent speculative reads from getting ahead of the status block. */
4414         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4415                           BUS_SPACE_BARRIER_READ);
4416
4417         /* Cycle through any completed TX chain page entries. */
4418         while (sw_tx_cons != hw_tx_cons) {
4419 #ifdef BCE_DEBUG
4420                 struct tx_bd *txbd = NULL;
4421 #endif
4422                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
4423
4424                 DBPRINT(sc, BCE_INFO_SEND,
4425                         "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4426                         "sw_tx_chain_cons = 0x%04X\n",
4427                         __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4428
4429                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
4430                         if_printf(ifp, "%s(%d): "
4431                                   "TX chain consumer out of range! "
4432                                   " 0x%04X > 0x%04X\n",
4433                                   __FILE__, __LINE__, sw_tx_chain_cons,
4434                                   (int)MAX_TX_BD);
4435                         bce_breakpoint(sc));
4436
4437                 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4438                                 [TX_IDX(sw_tx_chain_cons)]);
4439
4440                 DBRUNIF((txbd == NULL),
4441                         if_printf(ifp, "%s(%d): "
4442                                   "Unexpected NULL tx_bd[0x%04X]!\n",
4443                                   __FILE__, __LINE__, sw_tx_chain_cons);
4444                         bce_breakpoint(sc));
4445
4446                 DBRUN(BCE_INFO_SEND,
4447                       if_printf(ifp, "%s(): ", __func__);
4448                       bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4449
4450                 /*
4451                  * Free the associated mbuf. Remember
4452                  * that only the last tx_bd of a packet
4453                  * has an mbuf pointer and DMA map.
4454                  */
4455                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4456                         /* Validate that this is the last tx_bd. */
4457                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4458                                 if_printf(ifp, "%s(%d): "
4459                                 "tx_bd END flag not set but "
4460                                 "txmbuf == NULL!\n", __FILE__, __LINE__);
4461                                 bce_breakpoint(sc));
4462
4463                         DBRUN(BCE_INFO_SEND,
4464                               if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4465                                         "from tx_bd[0x%04X]\n", __func__,
4466                                         sw_tx_chain_cons));
4467
4468                         /* Unmap the mbuf. */
4469                         bus_dmamap_unload(sc->tx_mbuf_tag,
4470                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4471
4472                         /* Free the mbuf. */
4473                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4474                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4475                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4476
4477                         ifp->if_opackets++;
4478                 }
4479
4480                 sc->used_tx_bd--;
4481                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4482
4483                 if (sw_tx_cons == hw_tx_cons) {
4484                         /* Refresh hw_cons to see if there's new work. */
4485                         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4486                 }
4487
4488                 /*
4489                  * Prevent speculative reads from getting
4490                  * ahead of the status block.
4491                  */
4492                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4493                                   BUS_SPACE_BARRIER_READ);
4494         }
4495
4496         if (sc->used_tx_bd == 0) {
4497                 /* Clear the TX timeout timer. */
4498                 ifp->if_timer = 0;
4499         }
4500
4501         /* Clear the tx hardware queue full flag. */
4502         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4503                 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4504                         DBPRINT(sc, BCE_WARN_SEND,
4505                                 "%s(): Open TX chain! %d/%d (used/total)\n",
4506                                 __func__, sc->used_tx_bd, sc->max_tx_bd));
4507                 ifp->if_flags &= ~IFF_OACTIVE;
4508         }
4509         sc->tx_cons = sw_tx_cons;
4510 }
4511
4512
4513 /****************************************************************************/
4514 /* Disables interrupt generation.                                           */
4515 /*                                                                          */
4516 /* Returns:                                                                 */
4517 /*   Nothing.                                                               */
4518 /****************************************************************************/
4519 static void
4520 bce_disable_intr(struct bce_softc *sc)
4521 {
4522         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4523         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4524         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4525 }
4526
4527
4528 /****************************************************************************/
4529 /* Enables interrupt generation.                                            */
4530 /*                                                                          */
4531 /* Returns:                                                                 */
4532 /*   Nothing.                                                               */
4533 /****************************************************************************/
4534 static void
4535 bce_enable_intr(struct bce_softc *sc, int coal_now)
4536 {
4537         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4538
4539         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4540                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4541                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4542
4543         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4544                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4545
4546         if (coal_now) {
4547                 REG_WR(sc, BCE_HC_COMMAND,
4548                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4549         }
4550 }
4551
4552
4553 /****************************************************************************/
4554 /* Handles controller initialization.                                       */
4555 /*                                                                          */
4556 /* Returns:                                                                 */
4557 /*   Nothing.                                                               */
4558 /****************************************************************************/
4559 static void
4560 bce_init(void *xsc)
4561 {
4562         struct bce_softc *sc = xsc;
4563         struct ifnet *ifp = &sc->arpcom.ac_if;
4564         uint32_t ether_mtu;
4565         int error;
4566
4567         ASSERT_SERIALIZED(ifp->if_serializer);
4568
4569         /* Check if the driver is still running and bail out if it is. */
4570         if (ifp->if_flags & IFF_RUNNING)
4571                 return;
4572
4573         bce_stop(sc);
4574
4575         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4576         if (error) {
4577                 if_printf(ifp, "Controller reset failed!\n");
4578                 goto back;
4579         }
4580
4581         error = bce_chipinit(sc);
4582         if (error) {
4583                 if_printf(ifp, "Controller initialization failed!\n");
4584                 goto back;
4585         }
4586
4587         error = bce_blockinit(sc);
4588         if (error) {
4589                 if_printf(ifp, "Block initialization failed!\n");
4590                 goto back;
4591         }
4592
4593         /* Load our MAC address. */
4594         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4595         bce_set_mac_addr(sc);
4596
4597         /* Calculate and program the Ethernet MTU size. */
4598         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4599
4600         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4601
4602         /*
4603          * Program the mtu, enabling jumbo frame
4604          * support if necessary.  Also set the mbuf
4605          * allocation count for RX frames.
4606          */
4607         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4608 #ifdef notyet
4609                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4610                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4611                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4612                 sc->mbuf_alloc_size = MJUM9BYTES;
4613 #else
4614                 panic("jumbo buffer is not supported yet\n");
4615 #endif
4616         } else {
4617                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4618                 sc->mbuf_alloc_size = MCLBYTES;
4619         }
4620
4621         /* Calculate the RX Ethernet frame size for rx_bd's. */
4622         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4623
4624         DBPRINT(sc, BCE_INFO,
4625                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4626                 "max_frame_size = %d\n",
4627                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4628                 sc->max_frame_size);
4629
4630         /* Program appropriate promiscuous/multicast filtering. */
4631         bce_set_rx_mode(sc);
4632
4633         /* Init RX buffer descriptor chain. */
4634         bce_init_rx_chain(sc);  /* XXX return value */
4635
4636         /* Init TX buffer descriptor chain. */
4637         bce_init_tx_chain(sc);  /* XXX return value */
4638
4639 #ifdef DEVICE_POLLING
4640         /* Disable interrupts if we are polling. */
4641         if (ifp->if_flags & IFF_POLLING) {
4642                 bce_disable_intr(sc);
4643
4644                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4645                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4646                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4647                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4648         } else
4649 #endif
4650         /* Enable host interrupts. */
4651         bce_enable_intr(sc, 1);
4652
4653         bce_ifmedia_upd(ifp);
4654
4655         ifp->if_flags |= IFF_RUNNING;
4656         ifp->if_flags &= ~IFF_OACTIVE;
4657
4658         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4659 back:
4660         if (error)
4661                 bce_stop(sc);
4662 }
4663
4664
4665 /****************************************************************************/
4666 /* Initialize the controller just enough so that any management firmware    */
4667 /* running on the device will continue to operate corectly.                 */
4668 /*                                                                          */
4669 /* Returns:                                                                 */
4670 /*   Nothing.                                                               */
4671 /****************************************************************************/
4672 static void
4673 bce_mgmt_init(struct bce_softc *sc)
4674 {
4675         struct ifnet *ifp = &sc->arpcom.ac_if;
4676
4677         /* Bail out if management firmware is not running. */
4678         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4679                 return;
4680
4681         /* Enable all critical blocks in the MAC. */
4682         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4683             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4684                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4685                     BCE_MISC_ENABLE_DEFAULT_XI);
4686         } else {
4687                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4688         }
4689         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4690         DELAY(20);
4691
4692         bce_ifmedia_upd(ifp);
4693 }
4694
4695
4696 /****************************************************************************/
4697 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4698 /* memory visible to the controller.                                        */
4699 /*                                                                          */
4700 /* Returns:                                                                 */
4701 /*   0 for success, positive value for failure.                             */
4702 /****************************************************************************/
4703 static int
4704 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4705 {
4706         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4707         bus_dmamap_t map, tmp_map;
4708         struct mbuf *m0 = *m_head;
4709         struct tx_bd *txbd = NULL;
4710         uint16_t vlan_tag = 0, flags = 0;
4711         uint16_t chain_prod, chain_prod_start, prod;
4712         uint32_t prod_bseq;
4713         int i, error, maxsegs, nsegs;
4714 #ifdef BCE_DEBUG
4715         uint16_t debug_prod;
4716 #endif
4717
4718         /* Transfer any checksum offload flags to the bd. */
4719         if (m0->m_pkthdr.csum_flags) {
4720                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
4721                         flags |= TX_BD_FLAGS_IP_CKSUM;
4722                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
4723                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4724         }
4725
4726         /* Transfer any VLAN tags to the bd. */
4727         if (m0->m_flags & M_VLANTAG) {
4728                 flags |= TX_BD_FLAGS_VLAN_TAG;
4729                 vlan_tag = m0->m_pkthdr.ether_vlantag;
4730         }
4731
4732         prod = sc->tx_prod;
4733         chain_prod_start = chain_prod = TX_CHAIN_IDX(prod);
4734
4735         /* Map the mbuf into DMAable memory. */
4736         map = sc->tx_mbuf_map[chain_prod_start];
4737
4738         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
4739         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
4740                 ("not enough segements %d\n", maxsegs));
4741         if (maxsegs > BCE_MAX_SEGMENTS)
4742                 maxsegs = BCE_MAX_SEGMENTS;
4743
4744         /* Map the mbuf into our DMA address space. */
4745         error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
4746                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
4747         if (error)
4748                 goto back;
4749         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
4750
4751         /* Reset m0 */
4752         m0 = *m_head;
4753
4754         /* prod points to an empty tx_bd at this point. */
4755         prod_bseq  = sc->tx_prod_bseq;
4756
4757 #ifdef BCE_DEBUG
4758         debug_prod = chain_prod;
4759 #endif
4760
4761         DBPRINT(sc, BCE_INFO_SEND,
4762                 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
4763                 "prod_bseq = 0x%08X\n",
4764                 __func__, prod, chain_prod, prod_bseq);
4765
4766         /*
4767          * Cycle through each mbuf segment that makes up
4768          * the outgoing frame, gathering the mapping info
4769          * for that segment and creating a tx_bd to for
4770          * the mbuf.
4771          */
4772         for (i = 0; i < nsegs; i++) {
4773                 chain_prod = TX_CHAIN_IDX(prod);
4774                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
4775
4776                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
4777                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
4778                 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
4779                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
4780                 txbd->tx_bd_flags = htole16(flags);
4781                 prod_bseq += segs[i].ds_len;
4782                 if (i == 0)
4783                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
4784                 prod = NEXT_TX_BD(prod);
4785         }
4786
4787         /* Set the END flag on the last TX buffer descriptor. */
4788         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
4789
4790         DBRUN(BCE_EXCESSIVE_SEND,
4791               bce_dump_tx_chain(sc, debug_prod, nsegs));
4792
4793         DBPRINT(sc, BCE_INFO_SEND,
4794                 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
4795                 "prod_bseq = 0x%08X\n",
4796                 __func__, prod, chain_prod, prod_bseq);
4797
4798         /*
4799          * Ensure that the mbuf pointer for this transmission
4800          * is placed at the array index of the last
4801          * descriptor in this chain.  This is done
4802          * because a single map is used for all
4803          * segments of the mbuf and we don't want to
4804          * unload the map before all of the segments
4805          * have been freed.
4806          */
4807         sc->tx_mbuf_ptr[chain_prod] = m0;
4808
4809         tmp_map = sc->tx_mbuf_map[chain_prod];
4810         sc->tx_mbuf_map[chain_prod] = map;
4811         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
4812
4813         sc->used_tx_bd += nsegs;
4814
4815         /* Update some debug statistic counters */
4816         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
4817                 sc->tx_hi_watermark = sc->used_tx_bd);
4818         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
4819         DBRUNIF(1, sc->tx_mbuf_alloc++);
4820
4821         DBRUN(BCE_VERBOSE_SEND,
4822               bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
4823
4824         /* prod points to the next free tx_bd at this point. */
4825         sc->tx_prod = prod;
4826         sc->tx_prod_bseq = prod_bseq;
4827 back:
4828         if (error) {
4829                 m_freem(*m_head);
4830                 *m_head = NULL;
4831         }
4832         return error;
4833 }
4834
4835
4836 /****************************************************************************/
4837 /* Main transmit routine when called from another routine with a lock.      */
4838 /*                                                                          */
4839 /* Returns:                                                                 */
4840 /*   Nothing.                                                               */
4841 /****************************************************************************/
4842 static void
4843 bce_start(struct ifnet *ifp)
4844 {
4845         struct bce_softc *sc = ifp->if_softc;
4846         int count = 0;
4847
4848         ASSERT_SERIALIZED(ifp->if_serializer);
4849
4850         /* If there's no link or the transmit queue is empty then just exit. */
4851         if (!sc->bce_link) {
4852                 ifq_purge(&ifp->if_snd);
4853                 return;
4854         }
4855
4856         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
4857                 return;
4858
4859         DBPRINT(sc, BCE_INFO_SEND,
4860                 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
4861                 "tx_prod_bseq = 0x%08X\n",
4862                 __func__,
4863                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4864
4865         for (;;) {
4866                 struct mbuf *m_head;
4867
4868                 /*
4869                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
4870                  * unlikely to fail.
4871                  */
4872                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
4873                         ifp->if_flags |= IFF_OACTIVE;
4874                         break;
4875                 }
4876
4877                 /* Check for any frames to send. */
4878                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
4879                 if (m_head == NULL)
4880                         break;
4881
4882                 /*
4883                  * Pack the data into the transmit ring. If we
4884                  * don't have room, place the mbuf back at the
4885                  * head of the queue and set the OACTIVE flag
4886                  * to wait for the NIC to drain the chain.
4887                  */
4888                 if (bce_encap(sc, &m_head)) {
4889                         ifp->if_oerrors++;
4890                         if (sc->used_tx_bd == 0) {
4891                                 continue;
4892                         } else {
4893                                 ifp->if_flags |= IFF_OACTIVE;
4894                                 break;
4895                         }
4896                 }
4897
4898                 count++;
4899
4900                 /* Send a copy of the frame to any BPF listeners. */
4901                 ETHER_BPF_MTAP(ifp, m_head);
4902         }
4903
4904         if (count == 0) {
4905                 /* no packets were dequeued */
4906                 DBPRINT(sc, BCE_VERBOSE_SEND,
4907                         "%s(): No packets were dequeued\n", __func__);
4908                 return;
4909         }
4910
4911         DBPRINT(sc, BCE_INFO_SEND,
4912                 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
4913                 "tx_prod_bseq = 0x%08X\n",
4914                 __func__,
4915                 sc->tx_prod, TX_CHAIN_IDX(sc->tx_prod), sc->tx_prod_bseq);
4916
4917         REG_WR(sc, BCE_MQ_COMMAND,
4918             REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
4919
4920         /* Start the transmit. */
4921         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
4922         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
4923
4924         /* Set the tx timeout. */
4925         ifp->if_timer = BCE_TX_TIMEOUT;
4926 }
4927
4928
4929 /****************************************************************************/
4930 /* Handles any IOCTL calls from the operating system.                       */
4931 /*                                                                          */
4932 /* Returns:                                                                 */
4933 /*   0 for success, positive value for failure.                             */
4934 /****************************************************************************/
4935 static int
4936 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
4937 {
4938         struct bce_softc *sc = ifp->if_softc;
4939         struct ifreq *ifr = (struct ifreq *)data;
4940         struct mii_data *mii;
4941         int mask, error = 0;
4942
4943         ASSERT_SERIALIZED(ifp->if_serializer);
4944
4945         switch(command) {
4946         case SIOCSIFMTU:
4947                 /* Check that the MTU setting is supported. */
4948                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
4949 #ifdef notyet
4950                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
4951 #else
4952                     ifr->ifr_mtu > ETHERMTU
4953 #endif
4954                    ) {
4955                         error = EINVAL;
4956                         break;
4957                 }
4958
4959                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
4960
4961                 ifp->if_mtu = ifr->ifr_mtu;
4962                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
4963                 bce_init(sc);
4964                 break;
4965
4966         case SIOCSIFFLAGS:
4967                 if (ifp->if_flags & IFF_UP) {
4968                         if (ifp->if_flags & IFF_RUNNING) {
4969                                 mask = ifp->if_flags ^ sc->bce_if_flags;
4970
4971                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
4972                                         bce_set_rx_mode(sc);
4973                         } else {
4974                                 bce_init(sc);
4975                         }
4976                 } else if (ifp->if_flags & IFF_RUNNING) {
4977                         bce_stop(sc);
4978
4979                         /* If MFW is running, restart the controller a bit. */
4980                         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
4981                                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4982                                 bce_chipinit(sc);
4983                                 bce_mgmt_init(sc);
4984                         }
4985                 }
4986                 sc->bce_if_flags = ifp->if_flags;
4987                 break;
4988
4989         case SIOCADDMULTI:
4990         case SIOCDELMULTI:
4991                 if (ifp->if_flags & IFF_RUNNING)
4992                         bce_set_rx_mode(sc);
4993                 break;
4994
4995         case SIOCSIFMEDIA:
4996         case SIOCGIFMEDIA:
4997                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
4998                         sc->bce_phy_flags);
4999                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5000
5001                 mii = device_get_softc(sc->bce_miibus);
5002                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5003                 break;
5004
5005         case SIOCSIFCAP:
5006                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5007                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5008                         (uint32_t) mask);
5009
5010                 if (mask & IFCAP_HWCSUM) {
5011                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5012                         if (IFCAP_HWCSUM & ifp->if_capenable)
5013                                 ifp->if_hwassist = BCE_IF_HWASSIST;
5014                         else
5015                                 ifp->if_hwassist = 0;
5016                 }
5017                 break;
5018
5019         default:
5020                 error = ether_ioctl(ifp, command, data);
5021                 break;
5022         }
5023         return error;
5024 }
5025
5026
5027 /****************************************************************************/
5028 /* Transmit timeout handler.                                                */
5029 /*                                                                          */
5030 /* Returns:                                                                 */
5031 /*   Nothing.                                                               */
5032 /****************************************************************************/
5033 static void
5034 bce_watchdog(struct ifnet *ifp)
5035 {
5036         struct bce_softc *sc = ifp->if_softc;
5037
5038         ASSERT_SERIALIZED(ifp->if_serializer);
5039
5040         DBRUN(BCE_VERBOSE_SEND,
5041               bce_dump_driver_state(sc);
5042               bce_dump_status_block(sc));
5043
5044         /*
5045          * If we are in this routine because of pause frames, then
5046          * don't reset the hardware.
5047          */
5048         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5049                 return;
5050
5051         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5052
5053         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5054
5055         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5056         bce_init(sc);
5057
5058         ifp->if_oerrors++;
5059
5060         if (!ifq_is_empty(&ifp->if_snd))
5061                 if_devstart(ifp);
5062 }
5063
5064
5065 #ifdef DEVICE_POLLING
5066
5067 static void
5068 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5069 {
5070         struct bce_softc *sc = ifp->if_softc;
5071         struct status_block *sblk = sc->status_block;
5072         uint16_t hw_tx_cons, hw_rx_cons;
5073
5074         ASSERT_SERIALIZED(ifp->if_serializer);
5075
5076         switch (cmd) {
5077         case POLL_REGISTER:
5078                 bce_disable_intr(sc);
5079
5080                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5081                        (1 << 16) | sc->bce_rx_quick_cons_trip);
5082                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5083                        (1 << 16) | sc->bce_tx_quick_cons_trip);
5084                 return;
5085         case POLL_DEREGISTER:
5086                 bce_enable_intr(sc, 1);
5087
5088                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5089                        (sc->bce_tx_quick_cons_trip_int << 16) |
5090                        sc->bce_tx_quick_cons_trip);
5091                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5092                        (sc->bce_rx_quick_cons_trip_int << 16) |
5093                        sc->bce_rx_quick_cons_trip);
5094                 return;
5095         default:
5096                 break;
5097         }
5098
5099         if (cmd == POLL_AND_CHECK_STATUS) {
5100                 uint32_t status_attn_bits;
5101
5102                 status_attn_bits = sblk->status_attn_bits;
5103
5104                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5105                         if_printf(ifp,
5106                         "Simulating unexpected status attention bit set.");
5107                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5108
5109                 /* Was it a link change interrupt? */
5110                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5111                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5112                         bce_phy_intr(sc);
5113
5114                 /* Clear any transient status updates during link state change. */
5115                 REG_WR(sc, BCE_HC_COMMAND,
5116                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5117                 REG_RD(sc, BCE_HC_COMMAND);
5118
5119                 /*
5120                  * If any other attention is asserted then
5121                  * the chip is toast.
5122                  */
5123                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5124                      (sblk->status_attn_bits_ack &
5125                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5126                         DBRUN(1, sc->unexpected_attentions++);
5127
5128                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5129                                   sblk->status_attn_bits);
5130
5131                         DBRUN(BCE_FATAL,
5132                         if (bce_debug_unexpected_attention == 0)
5133                                 bce_breakpoint(sc));
5134
5135                         bce_init(sc);
5136                         return;
5137                 }
5138         }
5139
5140         hw_rx_cons = bce_get_hw_rx_cons(sc);
5141         hw_tx_cons = bce_get_hw_tx_cons(sc);
5142
5143         /* Check for any completed RX frames. */
5144         if (hw_rx_cons != sc->hw_rx_cons)
5145                 bce_rx_intr(sc, count);
5146
5147         /* Check for any completed TX frames. */
5148         if (hw_tx_cons != sc->hw_tx_cons)
5149                 bce_tx_intr(sc);
5150
5151         /* Check for new frames to transmit. */
5152         if (!ifq_is_empty(&ifp->if_snd))
5153                 if_devstart(ifp);
5154 }
5155
5156 #endif  /* DEVICE_POLLING */
5157
5158
5159 /*
5160  * Interrupt handler.
5161  */
5162 /****************************************************************************/
5163 /* Main interrupt entry point.  Verifies that the controller generated the  */
5164 /* interrupt and then calls a separate routine for handle the various       */
5165 /* interrupt causes (PHY, TX, RX).                                          */
5166 /*                                                                          */
5167 /* Returns:                                                                 */
5168 /*   0 for success, positive value for failure.                             */
5169 /****************************************************************************/
5170 static void
5171 bce_intr(void *xsc)
5172 {
5173         struct bce_softc *sc = xsc;
5174         struct ifnet *ifp = &sc->arpcom.ac_if;
5175         struct status_block *sblk;
5176         uint16_t hw_rx_cons, hw_tx_cons;
5177
5178         ASSERT_SERIALIZED(ifp->if_serializer);
5179
5180         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5181         DBRUNIF(1, sc->interrupts_generated++);
5182
5183         sblk = sc->status_block;
5184
5185         /*
5186          * If the hardware status block index matches the last value
5187          * read by the driver and we haven't asserted our interrupt
5188          * then there's nothing to do.
5189          */
5190         if (sblk->status_idx == sc->last_status_idx &&
5191             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5192              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5193                 return;
5194
5195         /* Ack the interrupt and stop others from occuring. */
5196         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5197                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5198                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5199
5200         /* Check if the hardware has finished any work. */
5201         hw_rx_cons = bce_get_hw_rx_cons(sc);
5202         hw_tx_cons = bce_get_hw_tx_cons(sc);
5203
5204         /* Keep processing data as long as there is work to do. */
5205         for (;;) {
5206                 uint32_t status_attn_bits;
5207
5208                 status_attn_bits = sblk->status_attn_bits;
5209
5210                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5211                         if_printf(ifp,
5212                         "Simulating unexpected status attention bit set.");
5213                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5214
5215                 /* Was it a link change interrupt? */
5216                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5217                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5218                         bce_phy_intr(sc);
5219
5220                         /*
5221                          * Clear any transient status updates during link state
5222                          * change.
5223                          */
5224                         REG_WR(sc, BCE_HC_COMMAND,
5225                             sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5226                         REG_RD(sc, BCE_HC_COMMAND);
5227                 }
5228
5229                 /*
5230                  * If any other attention is asserted then
5231                  * the chip is toast.
5232                  */
5233                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5234                      (sblk->status_attn_bits_ack &
5235                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5236                         DBRUN(1, sc->unexpected_attentions++);
5237
5238                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5239                                   sblk->status_attn_bits);
5240
5241                         DBRUN(BCE_FATAL,
5242                         if (bce_debug_unexpected_attention == 0)
5243                                 bce_breakpoint(sc));
5244
5245                         bce_init(sc);
5246                         return;
5247                 }
5248
5249                 /* Check for any completed RX frames. */
5250                 if (hw_rx_cons != sc->hw_rx_cons)
5251                         bce_rx_intr(sc, -1);
5252
5253                 /* Check for any completed TX frames. */
5254                 if (hw_tx_cons != sc->hw_tx_cons)
5255                         bce_tx_intr(sc);
5256
5257                 /*
5258                  * Save the status block index value
5259                  * for use during the next interrupt.
5260                  */
5261                 sc->last_status_idx = sblk->status_idx;
5262
5263                 /*
5264                  * Prevent speculative reads from getting
5265                  * ahead of the status block.
5266                  */
5267                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5268                                   BUS_SPACE_BARRIER_READ);
5269
5270                 /*
5271                  * If there's no work left then exit the
5272                  * interrupt service routine.
5273                  */
5274                 hw_rx_cons = bce_get_hw_rx_cons(sc);
5275                 hw_tx_cons = bce_get_hw_tx_cons(sc);
5276                 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5277                         break;
5278         }
5279
5280         /* Re-enable interrupts. */
5281         bce_enable_intr(sc, 0);
5282
5283         if (sc->bce_coalchg_mask)
5284                 bce_coal_change(sc);
5285
5286         /* Handle any frames that arrived while handling the interrupt. */
5287         if (!ifq_is_empty(&ifp->if_snd))
5288                 if_devstart(ifp);
5289 }
5290
5291
5292 /****************************************************************************/
5293 /* Programs the various packet receive modes (broadcast and multicast).     */
5294 /*                                                                          */
5295 /* Returns:                                                                 */
5296 /*   Nothing.                                                               */
5297 /****************************************************************************/
5298 static void
5299 bce_set_rx_mode(struct bce_softc *sc)
5300 {
5301         struct ifnet *ifp = &sc->arpcom.ac_if;
5302         struct ifmultiaddr *ifma;
5303         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5304         uint32_t rx_mode, sort_mode;
5305         int h, i;
5306
5307         ASSERT_SERIALIZED(ifp->if_serializer);
5308
5309         /* Initialize receive mode default settings. */
5310         rx_mode = sc->rx_mode &
5311                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5312                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5313         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5314
5315         /*
5316          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5317          * be enbled.
5318          */
5319         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5320             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5321                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5322
5323         /*
5324          * Check for promiscuous, all multicast, or selected
5325          * multicast address filtering.
5326          */
5327         if (ifp->if_flags & IFF_PROMISC) {
5328                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5329
5330                 /* Enable promiscuous mode. */
5331                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5332                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5333         } else if (ifp->if_flags & IFF_ALLMULTI) {
5334                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5335
5336                 /* Enable all multicast addresses. */
5337                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5338                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5339                                0xffffffff);
5340                 }
5341                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5342         } else {
5343                 /* Accept one or more multicast(s). */
5344                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5345
5346                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5347                         if (ifma->ifma_addr->sa_family != AF_LINK)
5348                                 continue;
5349                         h = ether_crc32_le(
5350                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5351                             ETHER_ADDR_LEN) & 0xFF;
5352                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5353                 }
5354
5355                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5356                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5357                                hashes[i]);
5358                 }
5359                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5360         }
5361
5362         /* Only make changes if the recive mode has actually changed. */
5363         if (rx_mode != sc->rx_mode) {
5364                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5365                         rx_mode);
5366
5367                 sc->rx_mode = rx_mode;
5368                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5369         }
5370
5371         /* Disable and clear the exisitng sort before enabling a new sort. */
5372         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5373         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5374         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5375 }
5376
5377
5378 /****************************************************************************/
5379 /* Called periodically to updates statistics from the controllers           */
5380 /* statistics block.                                                        */
5381 /*                                                                          */
5382 /* Returns:                                                                 */
5383 /*   Nothing.                                                               */
5384 /****************************************************************************/
5385 static void
5386 bce_stats_update(struct bce_softc *sc)
5387 {
5388         struct ifnet *ifp = &sc->arpcom.ac_if;
5389         struct statistics_block *stats = sc->stats_block;
5390
5391         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5392
5393         ASSERT_SERIALIZED(ifp->if_serializer);
5394
5395         /*
5396          * Certain controllers don't report carrier sense errors correctly.
5397          * See errata E11_5708CA0_1165.
5398          */
5399         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5400             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5401                 ifp->if_oerrors +=
5402                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5403         }
5404
5405         /*
5406          * Update the sysctl statistics from the hardware statistics.
5407          */
5408         sc->stat_IfHCInOctets =
5409                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5410                  (uint64_t)stats->stat_IfHCInOctets_lo;
5411
5412         sc->stat_IfHCInBadOctets =
5413                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5414                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5415
5416         sc->stat_IfHCOutOctets =
5417                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5418                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5419
5420         sc->stat_IfHCOutBadOctets =
5421                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5422                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5423
5424         sc->stat_IfHCInUcastPkts =
5425                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5426                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5427
5428         sc->stat_IfHCInMulticastPkts =
5429                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5430                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5431
5432         sc->stat_IfHCInBroadcastPkts =
5433                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5434                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5435
5436         sc->stat_IfHCOutUcastPkts =
5437                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5438                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5439
5440         sc->stat_IfHCOutMulticastPkts =
5441                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5442                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5443
5444         sc->stat_IfHCOutBroadcastPkts =
5445                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5446                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5447
5448         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5449                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5450
5451         sc->stat_Dot3StatsCarrierSenseErrors =
5452                 stats->stat_Dot3StatsCarrierSenseErrors;
5453
5454         sc->stat_Dot3StatsFCSErrors =
5455                 stats->stat_Dot3StatsFCSErrors;
5456
5457         sc->stat_Dot3StatsAlignmentErrors =
5458                 stats->stat_Dot3StatsAlignmentErrors;
5459
5460         sc->stat_Dot3StatsSingleCollisionFrames =
5461                 stats->stat_Dot3StatsSingleCollisionFrames;
5462
5463         sc->stat_Dot3StatsMultipleCollisionFrames =
5464                 stats->stat_Dot3StatsMultipleCollisionFrames;
5465
5466         sc->stat_Dot3StatsDeferredTransmissions =
5467                 stats->stat_Dot3StatsDeferredTransmissions;
5468
5469         sc->stat_Dot3StatsExcessiveCollisions =
5470                 stats->stat_Dot3StatsExcessiveCollisions;
5471
5472         sc->stat_Dot3StatsLateCollisions =
5473                 stats->stat_Dot3StatsLateCollisions;
5474
5475         sc->stat_EtherStatsCollisions =
5476                 stats->stat_EtherStatsCollisions;
5477
5478         sc->stat_EtherStatsFragments =
5479                 stats->stat_EtherStatsFragments;
5480
5481         sc->stat_EtherStatsJabbers =
5482                 stats->stat_EtherStatsJabbers;
5483
5484         sc->stat_EtherStatsUndersizePkts =
5485                 stats->stat_EtherStatsUndersizePkts;
5486
5487         sc->stat_EtherStatsOverrsizePkts =
5488                 stats->stat_EtherStatsOverrsizePkts;
5489
5490         sc->stat_EtherStatsPktsRx64Octets =
5491                 stats->stat_EtherStatsPktsRx64Octets;
5492
5493         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5494                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5495
5496         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5497                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5498
5499         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5500                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5501
5502         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5503                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5504
5505         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5506                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5507
5508         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5509                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5510
5511         sc->stat_EtherStatsPktsTx64Octets =
5512                 stats->stat_EtherStatsPktsTx64Octets;
5513
5514         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5515                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5516
5517         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5518                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5519
5520         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5521                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5522
5523         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5524                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5525
5526         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5527                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5528
5529         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5530                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5531
5532         sc->stat_XonPauseFramesReceived =
5533                 stats->stat_XonPauseFramesReceived;
5534
5535         sc->stat_XoffPauseFramesReceived =
5536                 stats->stat_XoffPauseFramesReceived;
5537
5538         sc->stat_OutXonSent =
5539                 stats->stat_OutXonSent;
5540
5541         sc->stat_OutXoffSent =
5542                 stats->stat_OutXoffSent;
5543
5544         sc->stat_FlowControlDone =
5545                 stats->stat_FlowControlDone;
5546
5547         sc->stat_MacControlFramesReceived =
5548                 stats->stat_MacControlFramesReceived;
5549
5550         sc->stat_XoffStateEntered =
5551                 stats->stat_XoffStateEntered;
5552
5553         sc->stat_IfInFramesL2FilterDiscards =
5554                 stats->stat_IfInFramesL2FilterDiscards;
5555
5556         sc->stat_IfInRuleCheckerDiscards =
5557                 stats->stat_IfInRuleCheckerDiscards;
5558
5559         sc->stat_IfInFTQDiscards =
5560                 stats->stat_IfInFTQDiscards;
5561
5562         sc->stat_IfInMBUFDiscards =
5563                 stats->stat_IfInMBUFDiscards;
5564
5565         sc->stat_IfInRuleCheckerP4Hit =
5566                 stats->stat_IfInRuleCheckerP4Hit;
5567
5568         sc->stat_CatchupInRuleCheckerDiscards =
5569                 stats->stat_CatchupInRuleCheckerDiscards;
5570
5571         sc->stat_CatchupInFTQDiscards =
5572                 stats->stat_CatchupInFTQDiscards;
5573
5574         sc->stat_CatchupInMBUFDiscards =
5575                 stats->stat_CatchupInMBUFDiscards;
5576
5577         sc->stat_CatchupInRuleCheckerP4Hit =
5578                 stats->stat_CatchupInRuleCheckerP4Hit;
5579
5580         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5581
5582         /*
5583          * Update the interface statistics from the
5584          * hardware statistics.
5585          */
5586         ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5587
5588         ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5589             (u_long)sc->stat_EtherStatsOverrsizePkts +
5590             (u_long)sc->stat_IfInMBUFDiscards +
5591             (u_long)sc->stat_Dot3StatsAlignmentErrors +
5592             (u_long)sc->stat_Dot3StatsFCSErrors +
5593             (u_long)sc->stat_IfInFramesL2FilterDiscards +
5594             (u_long)sc->stat_IfInRuleCheckerDiscards +
5595             (u_long)sc->stat_IfInFTQDiscards +
5596             (u_long)sc->com_no_buffers;
5597
5598         ifp->if_oerrors =
5599             (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5600             (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5601             (u_long)sc->stat_Dot3StatsLateCollisions;
5602
5603         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5604 }
5605
5606
5607 /****************************************************************************/
5608 /* Periodic function to notify the bootcode that the driver is still        */
5609 /* present.                                                                 */
5610 /*                                                                          */
5611 /* Returns:                                                                 */
5612 /*   Nothing.                                                               */
5613 /****************************************************************************/
5614 static void
5615 bce_pulse(void *xsc)
5616 {
5617         struct bce_softc *sc = xsc;
5618         struct ifnet *ifp = &sc->arpcom.ac_if;
5619         uint32_t msg;
5620
5621         lwkt_serialize_enter(ifp->if_serializer);
5622
5623         /* Tell the firmware that the driver is still running. */
5624         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5625         REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
5626
5627         /* Schedule the next pulse. */
5628         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5629
5630         lwkt_serialize_exit(ifp->if_serializer);
5631 }
5632
5633
5634 /****************************************************************************/
5635 /* Periodic function to perform maintenance tasks.                          */
5636 /*                                                                          */
5637 /* Returns:                                                                 */
5638 /*   Nothing.                                                               */
5639 /****************************************************************************/
5640 static void
5641 bce_tick_serialized(struct bce_softc *sc)
5642 {
5643         struct ifnet *ifp = &sc->arpcom.ac_if;
5644         struct mii_data *mii;
5645
5646         ASSERT_SERIALIZED(ifp->if_serializer);
5647
5648         /* Update the statistics from the hardware statistics block. */
5649         bce_stats_update(sc);
5650
5651         /* Schedule the next tick. */
5652         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5653
5654         /* If link is up already up then we're done. */
5655         if (sc->bce_link)
5656                 return;
5657
5658         mii = device_get_softc(sc->bce_miibus);
5659         mii_tick(mii);
5660
5661         /* Check if the link has come up. */
5662         if ((mii->mii_media_status & IFM_ACTIVE) &&
5663             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
5664                 sc->bce_link++;
5665                 /* Now that link is up, handle any outstanding TX traffic. */
5666                 if (!ifq_is_empty(&ifp->if_snd))
5667                         if_devstart(ifp);
5668         }
5669 }
5670
5671
5672 static void
5673 bce_tick(void *xsc)
5674 {
5675         struct bce_softc *sc = xsc;
5676         struct ifnet *ifp = &sc->arpcom.ac_if;
5677
5678         lwkt_serialize_enter(ifp->if_serializer);
5679         bce_tick_serialized(sc);
5680         lwkt_serialize_exit(ifp->if_serializer);
5681 }
5682
5683
5684 #ifdef BCE_DEBUG
5685 /****************************************************************************/
5686 /* Allows the driver state to be dumped through the sysctl interface.       */
5687 /*                                                                          */
5688 /* Returns:                                                                 */
5689 /*   0 for success, positive value for failure.                             */
5690 /****************************************************************************/
5691 static int
5692 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
5693 {
5694         int error;
5695         int result;
5696         struct bce_softc *sc;
5697
5698         result = -1;
5699         error = sysctl_handle_int(oidp, &result, 0, req);
5700
5701         if (error || !req->newptr)
5702                 return (error);
5703
5704         if (result == 1) {
5705                 sc = (struct bce_softc *)arg1;
5706                 bce_dump_driver_state(sc);
5707         }
5708
5709         return error;
5710 }
5711
5712
5713 /****************************************************************************/
5714 /* Allows the hardware state to be dumped through the sysctl interface.     */
5715 /*                                                                          */
5716 /* Returns:                                                                 */
5717 /*   0 for success, positive value for failure.                             */
5718 /****************************************************************************/
5719 static int
5720 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
5721 {
5722         int error;
5723         int result;
5724         struct bce_softc *sc;
5725
5726         result = -1;
5727         error = sysctl_handle_int(oidp, &result, 0, req);
5728
5729         if (error || !req->newptr)
5730                 return (error);
5731
5732         if (result == 1) {
5733                 sc = (struct bce_softc *)arg1;
5734                 bce_dump_hw_state(sc);
5735         }
5736
5737         return error;
5738 }
5739
5740
5741 /****************************************************************************/
5742 /* Provides a sysctl interface to allows dumping the RX chain.              */
5743 /*                                                                          */
5744 /* Returns:                                                                 */
5745 /*   0 for success, positive value for failure.                             */
5746 /****************************************************************************/
5747 static int
5748 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
5749 {
5750         int error;
5751         int result;
5752         struct bce_softc *sc;
5753
5754         result = -1;
5755         error = sysctl_handle_int(oidp, &result, 0, req);
5756
5757         if (error || !req->newptr)
5758                 return (error);
5759
5760         if (result == 1) {
5761                 sc = (struct bce_softc *)arg1;
5762                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
5763         }
5764
5765         return error;
5766 }
5767
5768
5769 /****************************************************************************/
5770 /* Provides a sysctl interface to allows dumping the TX chain.              */
5771 /*                                                                          */
5772 /* Returns:                                                                 */
5773 /*   0 for success, positive value for failure.                             */
5774 /****************************************************************************/
5775 static int
5776 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
5777 {
5778         int error;
5779         int result;
5780         struct bce_softc *sc;
5781
5782         result = -1;
5783         error = sysctl_handle_int(oidp, &result, 0, req);
5784
5785         if (error || !req->newptr)
5786                 return (error);
5787
5788         if (result == 1) {
5789                 sc = (struct bce_softc *)arg1;
5790                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
5791         }
5792
5793         return error;
5794 }
5795
5796
5797 /****************************************************************************/
5798 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
5799 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
5800 /*                                                                          */
5801 /* Returns:                                                                 */
5802 /*   0 for success, positive value for failure.                             */
5803 /****************************************************************************/
5804 static int
5805 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
5806 {
5807         struct bce_softc *sc;
5808         int error;
5809         uint32_t val, result;
5810
5811         result = -1;
5812         error = sysctl_handle_int(oidp, &result, 0, req);
5813         if (error || (req->newptr == NULL))
5814                 return (error);
5815
5816         /* Make sure the register is accessible. */
5817         if (result < 0x8000) {
5818                 sc = (struct bce_softc *)arg1;
5819                 val = REG_RD(sc, result);
5820                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5821                           result, val);
5822         } else if (result < 0x0280000) {
5823                 sc = (struct bce_softc *)arg1;
5824                 val = REG_RD_IND(sc, result);
5825                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
5826                           result, val);
5827         }
5828         return (error);
5829 }
5830
5831
5832 /****************************************************************************/
5833 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
5834 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
5835 /*                                                                          */
5836 /* Returns:                                                                 */
5837 /*   0 for success, positive value for failure.                             */
5838 /****************************************************************************/
5839 static int
5840 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
5841 {
5842         struct bce_softc *sc;
5843         device_t dev;
5844         int error, result;
5845         uint16_t val;
5846
5847         result = -1;
5848         error = sysctl_handle_int(oidp, &result, 0, req);
5849         if (error || (req->newptr == NULL))
5850                 return (error);
5851
5852         /* Make sure the register is accessible. */
5853         if (result < 0x20) {
5854                 sc = (struct bce_softc *)arg1;
5855                 dev = sc->bce_dev;
5856                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
5857                 if_printf(&sc->arpcom.ac_if,
5858                           "phy 0x%02X = 0x%04X\n", result, val);
5859         }
5860         return (error);
5861 }
5862
5863
5864 /****************************************************************************/
5865 /* Provides a sysctl interface to forcing the driver to dump state and      */
5866 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
5867 /*                                                                          */
5868 /* Returns:                                                                 */
5869 /*   0 for success, positive value for failure.                             */
5870 /****************************************************************************/
5871 static int
5872 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
5873 {
5874         int error;
5875         int result;
5876         struct bce_softc *sc;
5877
5878         result = -1;
5879         error = sysctl_handle_int(oidp, &result, 0, req);
5880
5881         if (error || !req->newptr)
5882                 return (error);
5883
5884         if (result == 1) {
5885                 sc = (struct bce_softc *)arg1;
5886                 bce_breakpoint(sc);
5887         }
5888
5889         return error;
5890 }
5891 #endif
5892
5893
5894 /****************************************************************************/
5895 /* Adds any sysctl parameters for tuning or debugging purposes.             */
5896 /*                                                                          */
5897 /* Returns:                                                                 */
5898 /*   0 for success, positive value for failure.                             */
5899 /****************************************************************************/
5900 static void
5901 bce_add_sysctls(struct bce_softc *sc)
5902 {
5903         struct sysctl_ctx_list *ctx;
5904         struct sysctl_oid_list *children;
5905
5906         sysctl_ctx_init(&sc->bce_sysctl_ctx);
5907         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
5908                                               SYSCTL_STATIC_CHILDREN(_hw),
5909                                               OID_AUTO,
5910                                               device_get_nameunit(sc->bce_dev),
5911                                               CTLFLAG_RD, 0, "");
5912         if (sc->bce_sysctl_tree == NULL) {
5913                 device_printf(sc->bce_dev, "can't add sysctl node\n");
5914                 return;
5915         }
5916
5917         ctx = &sc->bce_sysctl_ctx;
5918         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
5919
5920         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
5921                         CTLTYPE_INT | CTLFLAG_RW,
5922                         sc, 0, bce_sysctl_tx_bds_int, "I",
5923                         "Send max coalesced BD count during interrupt");
5924         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
5925                         CTLTYPE_INT | CTLFLAG_RW,
5926                         sc, 0, bce_sysctl_tx_bds, "I",
5927                         "Send max coalesced BD count");
5928         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
5929                         CTLTYPE_INT | CTLFLAG_RW,
5930                         sc, 0, bce_sysctl_tx_ticks_int, "I",
5931                         "Send coalescing ticks during interrupt");
5932         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
5933                         CTLTYPE_INT | CTLFLAG_RW,
5934                         sc, 0, bce_sysctl_tx_ticks, "I",
5935                         "Send coalescing ticks");
5936
5937         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
5938                         CTLTYPE_INT | CTLFLAG_RW,
5939                         sc, 0, bce_sysctl_rx_bds_int, "I",
5940                         "Receive max coalesced BD count during interrupt");
5941         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
5942                         CTLTYPE_INT | CTLFLAG_RW,
5943                         sc, 0, bce_sysctl_rx_bds, "I",
5944                         "Receive max coalesced BD count");
5945         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
5946                         CTLTYPE_INT | CTLFLAG_RW,
5947                         sc, 0, bce_sysctl_rx_ticks_int, "I",
5948                         "Receive coalescing ticks during interrupt");
5949         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
5950                         CTLTYPE_INT | CTLFLAG_RW,
5951                         sc, 0, bce_sysctl_rx_ticks, "I",
5952                         "Receive coalescing ticks");
5953
5954 #ifdef BCE_DEBUG
5955         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5956                 "rx_low_watermark",
5957                 CTLFLAG_RD, &sc->rx_low_watermark,
5958                 0, "Lowest level of free rx_bd's");
5959
5960         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5961                 "rx_empty_count",
5962                 CTLFLAG_RD, &sc->rx_empty_count,
5963                 0, "Number of times the RX chain was empty");
5964
5965         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5966                 "tx_hi_watermark",
5967                 CTLFLAG_RD, &sc->tx_hi_watermark,
5968                 0, "Highest level of used tx_bd's");
5969
5970         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5971                 "tx_full_count",
5972                 CTLFLAG_RD, &sc->tx_full_count,
5973                 0, "Number of times the TX chain was full");
5974
5975         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5976                 "l2fhdr_status_errors",
5977                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
5978                 0, "l2_fhdr status errors");
5979
5980         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5981                 "unexpected_attentions",
5982                 CTLFLAG_RD, &sc->unexpected_attentions,
5983                 0, "unexpected attentions");
5984
5985         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5986                 "lost_status_block_updates",
5987                 CTLFLAG_RD, &sc->lost_status_block_updates,
5988                 0, "lost status block updates");
5989
5990         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
5991                 "mbuf_alloc_failed",
5992                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
5993                 0, "mbuf cluster allocation failures");
5994 #endif
5995
5996         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
5997                 "stat_IfHCInOctets",
5998                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
5999                 "Bytes received");
6000
6001         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6002                 "stat_IfHCInBadOctets",
6003                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6004                 "Bad bytes received");
6005
6006         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6007                 "stat_IfHCOutOctets",
6008                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6009                 "Bytes sent");
6010
6011         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6012                 "stat_IfHCOutBadOctets",
6013                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6014                 "Bad bytes sent");
6015
6016         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6017                 "stat_IfHCInUcastPkts",
6018                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6019                 "Unicast packets received");
6020
6021         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6022                 "stat_IfHCInMulticastPkts",
6023                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6024                 "Multicast packets received");
6025
6026         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6027                 "stat_IfHCInBroadcastPkts",
6028                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6029                 "Broadcast packets received");
6030
6031         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6032                 "stat_IfHCOutUcastPkts",
6033                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6034                 "Unicast packets sent");
6035
6036         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6037                 "stat_IfHCOutMulticastPkts",
6038                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6039                 "Multicast packets sent");
6040
6041         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6042                 "stat_IfHCOutBroadcastPkts",
6043                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6044                 "Broadcast packets sent");
6045
6046         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6047                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6048                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6049                 0, "Internal MAC transmit errors");
6050
6051         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6052                 "stat_Dot3StatsCarrierSenseErrors",
6053                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6054                 0, "Carrier sense errors");
6055
6056         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6057                 "stat_Dot3StatsFCSErrors",
6058                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6059                 0, "Frame check sequence errors");
6060
6061         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6062                 "stat_Dot3StatsAlignmentErrors",
6063                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6064                 0, "Alignment errors");
6065
6066         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6067                 "stat_Dot3StatsSingleCollisionFrames",
6068                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6069                 0, "Single Collision Frames");
6070
6071         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6072                 "stat_Dot3StatsMultipleCollisionFrames",
6073                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6074                 0, "Multiple Collision Frames");
6075
6076         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6077                 "stat_Dot3StatsDeferredTransmissions",
6078                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6079                 0, "Deferred Transmissions");
6080
6081         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6082                 "stat_Dot3StatsExcessiveCollisions",
6083                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6084                 0, "Excessive Collisions");
6085
6086         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6087                 "stat_Dot3StatsLateCollisions",
6088                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6089                 0, "Late Collisions");
6090
6091         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6092                 "stat_EtherStatsCollisions",
6093                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6094                 0, "Collisions");
6095
6096         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6097                 "stat_EtherStatsFragments",
6098                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6099                 0, "Fragments");
6100
6101         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6102                 "stat_EtherStatsJabbers",
6103                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6104                 0, "Jabbers");
6105
6106         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6107                 "stat_EtherStatsUndersizePkts",
6108                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6109                 0, "Undersize packets");
6110
6111         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6112                 "stat_EtherStatsOverrsizePkts",
6113                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6114                 0, "stat_EtherStatsOverrsizePkts");
6115
6116         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6117                 "stat_EtherStatsPktsRx64Octets",
6118                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6119                 0, "Bytes received in 64 byte packets");
6120
6121         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6122                 "stat_EtherStatsPktsRx65Octetsto127Octets",
6123                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6124                 0, "Bytes received in 65 to 127 byte packets");
6125
6126         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6127                 "stat_EtherStatsPktsRx128Octetsto255Octets",
6128                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6129                 0, "Bytes received in 128 to 255 byte packets");
6130
6131         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6132                 "stat_EtherStatsPktsRx256Octetsto511Octets",
6133                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6134                 0, "Bytes received in 256 to 511 byte packets");
6135
6136         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6137                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6138                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6139                 0, "Bytes received in 512 to 1023 byte packets");
6140
6141         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6142                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6143                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6144                 0, "Bytes received in 1024 t0 1522 byte packets");
6145
6146         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6147                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6148                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6149                 0, "Bytes received in 1523 to 9022 byte packets");
6150
6151         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6152                 "stat_EtherStatsPktsTx64Octets",
6153                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6154                 0, "Bytes sent in 64 byte packets");
6155
6156         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6157                 "stat_EtherStatsPktsTx65Octetsto127Octets",
6158                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6159                 0, "Bytes sent in 65 to 127 byte packets");
6160
6161         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6162                 "stat_EtherStatsPktsTx128Octetsto255Octets",
6163                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6164                 0, "Bytes sent in 128 to 255 byte packets");
6165
6166         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6167                 "stat_EtherStatsPktsTx256Octetsto511Octets",
6168                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6169                 0, "Bytes sent in 256 to 511 byte packets");
6170
6171         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6172                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6173                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6174                 0, "Bytes sent in 512 to 1023 byte packets");
6175
6176         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6177                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6178                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6179                 0, "Bytes sent in 1024 to 1522 byte packets");
6180
6181         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6182                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6183                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6184                 0, "Bytes sent in 1523 to 9022 byte packets");
6185
6186         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6187                 "stat_XonPauseFramesReceived",
6188                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6189                 0, "XON pause frames receved");
6190
6191         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6192                 "stat_XoffPauseFramesReceived",
6193                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6194                 0, "XOFF pause frames received");
6195
6196         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6197                 "stat_OutXonSent",
6198                 CTLFLAG_RD, &sc->stat_OutXonSent,
6199                 0, "XON pause frames sent");
6200
6201         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6202                 "stat_OutXoffSent",
6203                 CTLFLAG_RD, &sc->stat_OutXoffSent,
6204                 0, "XOFF pause frames sent");
6205
6206         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6207                 "stat_FlowControlDone",
6208                 CTLFLAG_RD, &sc->stat_FlowControlDone,
6209                 0, "Flow control done");
6210
6211         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6212                 "stat_MacControlFramesReceived",
6213                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6214                 0, "MAC control frames received");
6215
6216         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6217                 "stat_XoffStateEntered",
6218                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6219                 0, "XOFF state entered");
6220
6221         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6222                 "stat_IfInFramesL2FilterDiscards",
6223                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6224                 0, "Received L2 packets discarded");
6225
6226         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6227                 "stat_IfInRuleCheckerDiscards",
6228                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6229                 0, "Received packets discarded by rule");
6230
6231         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6232                 "stat_IfInFTQDiscards",
6233                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6234                 0, "Received packet FTQ discards");
6235
6236         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6237                 "stat_IfInMBUFDiscards",
6238                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6239                 0, "Received packets discarded due to lack of controller buffer memory");
6240
6241         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6242                 "stat_IfInRuleCheckerP4Hit",
6243                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6244                 0, "Received packets rule checker hits");
6245
6246         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6247                 "stat_CatchupInRuleCheckerDiscards",
6248                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6249                 0, "Received packets discarded in Catchup path");
6250
6251         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6252                 "stat_CatchupInFTQDiscards",
6253                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6254                 0, "Received packets discarded in FTQ in Catchup path");
6255
6256         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6257                 "stat_CatchupInMBUFDiscards",
6258                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6259                 0, "Received packets discarded in controller buffer memory in Catchup path");
6260
6261         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6262                 "stat_CatchupInRuleCheckerP4Hit",
6263                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6264                 0, "Received packets rule checker hits in Catchup path");
6265
6266         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6267                 "com_no_buffers",
6268                 CTLFLAG_RD, &sc->com_no_buffers,
6269                 0, "Valid packets received but no RX buffers available");
6270
6271 #ifdef BCE_DEBUG
6272         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6273                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6274                 (void *)sc, 0,
6275                 bce_sysctl_driver_state, "I", "Drive state information");
6276
6277         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6278                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6279                 (void *)sc, 0,
6280                 bce_sysctl_hw_state, "I", "Hardware state information");
6281
6282         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6283                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6284                 (void *)sc, 0,
6285                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6286
6287         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6288                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6289                 (void *)sc, 0,
6290                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6291
6292         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6293                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6294                 (void *)sc, 0,
6295                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6296
6297         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6298                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6299                 (void *)sc, 0,
6300                 bce_sysctl_reg_read, "I", "Register read");
6301
6302         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6303                 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6304                 (void *)sc, 0,
6305                 bce_sysctl_phy_read, "I", "PHY register read");
6306
6307 #endif
6308
6309 }
6310
6311
6312 /****************************************************************************/
6313 /* BCE Debug Routines                                                       */
6314 /****************************************************************************/
6315 #ifdef BCE_DEBUG
6316
6317 /****************************************************************************/
6318 /* Freezes the controller to allow for a cohesive state dump.               */
6319 /*                                                                          */
6320 /* Returns:                                                                 */
6321 /*   Nothing.                                                               */
6322 /****************************************************************************/
6323 static void
6324 bce_freeze_controller(struct bce_softc *sc)
6325 {
6326         uint32_t val;
6327
6328         val = REG_RD(sc, BCE_MISC_COMMAND);
6329         val |= BCE_MISC_COMMAND_DISABLE_ALL;
6330         REG_WR(sc, BCE_MISC_COMMAND, val);
6331 }
6332
6333
6334 /****************************************************************************/
6335 /* Unfreezes the controller after a freeze operation.  This may not always  */
6336 /* work and the controller will require a reset!                            */
6337 /*                                                                          */
6338 /* Returns:                                                                 */
6339 /*   Nothing.                                                               */
6340 /****************************************************************************/
6341 static void
6342 bce_unfreeze_controller(struct bce_softc *sc)
6343 {
6344         uint32_t val;
6345
6346         val = REG_RD(sc, BCE_MISC_COMMAND);
6347         val |= BCE_MISC_COMMAND_ENABLE_ALL;
6348         REG_WR(sc, BCE_MISC_COMMAND, val);
6349 }
6350
6351
6352 /****************************************************************************/
6353 /* Prints out information about an mbuf.                                    */
6354 /*                                                                          */
6355 /* Returns:                                                                 */
6356 /*   Nothing.                                                               */
6357 /****************************************************************************/
6358 static void
6359 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6360 {
6361         struct ifnet *ifp = &sc->arpcom.ac_if;
6362         uint32_t val_hi, val_lo;
6363         struct mbuf *mp = m;
6364
6365         if (m == NULL) {
6366                 /* Index out of range. */
6367                 if_printf(ifp, "mbuf: null pointer\n");
6368                 return;
6369         }
6370
6371         while (mp) {
6372                 val_hi = BCE_ADDR_HI(mp);
6373                 val_lo = BCE_ADDR_LO(mp);
6374                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6375                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
6376
6377                 if (mp->m_flags & M_EXT)
6378                         kprintf("M_EXT ");
6379                 if (mp->m_flags & M_PKTHDR)
6380                         kprintf("M_PKTHDR ");
6381                 if (mp->m_flags & M_EOR)
6382                         kprintf("M_EOR ");
6383 #ifdef M_RDONLY
6384                 if (mp->m_flags & M_RDONLY)
6385                         kprintf("M_RDONLY ");
6386 #endif
6387
6388                 val_hi = BCE_ADDR_HI(mp->m_data);
6389                 val_lo = BCE_ADDR_LO(mp->m_data);
6390                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6391
6392                 if (mp->m_flags & M_PKTHDR) {
6393                         if_printf(ifp, "- m_pkthdr: flags = ( ");
6394                         if (mp->m_flags & M_BCAST)
6395                                 kprintf("M_BCAST ");
6396                         if (mp->m_flags & M_MCAST)
6397                                 kprintf("M_MCAST ");
6398                         if (mp->m_flags & M_FRAG)
6399                                 kprintf("M_FRAG ");
6400                         if (mp->m_flags & M_FIRSTFRAG)
6401                                 kprintf("M_FIRSTFRAG ");
6402                         if (mp->m_flags & M_LASTFRAG)
6403                                 kprintf("M_LASTFRAG ");
6404 #ifdef M_VLANTAG
6405                         if (mp->m_flags & M_VLANTAG)
6406                                 kprintf("M_VLANTAG ");
6407 #endif
6408 #ifdef M_PROMISC
6409                         if (mp->m_flags & M_PROMISC)
6410                                 kprintf("M_PROMISC ");
6411 #endif
6412                         kprintf(") csum_flags = ( ");
6413                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
6414                                 kprintf("CSUM_IP ");
6415                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6416                                 kprintf("CSUM_TCP ");
6417                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6418                                 kprintf("CSUM_UDP ");
6419                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6420                                 kprintf("CSUM_IP_FRAGS ");
6421                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6422                                 kprintf("CSUM_FRAGMENT ");
6423 #ifdef CSUM_TSO
6424                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6425                                 kprintf("CSUM_TSO ");
6426 #endif
6427                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6428                                 kprintf("CSUM_IP_CHECKED ");
6429                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6430                                 kprintf("CSUM_IP_VALID ");
6431                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6432                                 kprintf("CSUM_DATA_VALID ");
6433                         kprintf(")\n");
6434                 }
6435
6436                 if (mp->m_flags & M_EXT) {
6437                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6438                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6439                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6440                                   "ext_size = %d\n",
6441                                   val_hi, val_lo, mp->m_ext.ext_size);
6442                 }
6443                 mp = mp->m_next;
6444         }
6445 }
6446
6447
6448 /****************************************************************************/
6449 /* Prints out the mbufs in the TX mbuf chain.                               */
6450 /*                                                                          */
6451 /* Returns:                                                                 */
6452 /*   Nothing.                                                               */
6453 /****************************************************************************/
6454 static void
6455 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6456 {
6457         struct ifnet *ifp = &sc->arpcom.ac_if;
6458         int i;
6459
6460         if_printf(ifp,
6461         "----------------------------"
6462         "  tx mbuf data  "
6463         "----------------------------\n");
6464
6465         for (i = 0; i < count; i++) {
6466                 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6467                 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6468                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
6469         }
6470
6471         if_printf(ifp,
6472         "----------------------------"
6473         "----------------"
6474         "----------------------------\n");
6475 }
6476
6477
6478 /****************************************************************************/
6479 /* Prints out the mbufs in the RX mbuf chain.                               */
6480 /*                                                                          */
6481 /* Returns:                                                                 */
6482 /*   Nothing.                                                               */
6483 /****************************************************************************/
6484 static void
6485 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6486 {
6487         struct ifnet *ifp = &sc->arpcom.ac_if;
6488         int i;
6489
6490         if_printf(ifp,
6491         "----------------------------"
6492         "  rx mbuf data  "
6493         "----------------------------\n");
6494
6495         for (i = 0; i < count; i++) {
6496                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6497                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6498                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
6499         }
6500
6501         if_printf(ifp,
6502         "----------------------------"
6503         "----------------"
6504         "----------------------------\n");
6505 }
6506
6507
6508 /****************************************************************************/
6509 /* Prints out a tx_bd structure.                                            */
6510 /*                                                                          */
6511 /* Returns:                                                                 */
6512 /*   Nothing.                                                               */
6513 /****************************************************************************/
6514 static void
6515 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6516 {
6517         struct ifnet *ifp = &sc->arpcom.ac_if;
6518
6519         if (idx > MAX_TX_BD) {
6520                 /* Index out of range. */
6521                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6522         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6523                 /* TX Chain page pointer. */
6524                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6525                           "chain page pointer\n",
6526                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6527         } else {
6528                 /* Normal tx_bd entry. */
6529                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6530                           "nbytes = 0x%08X, "
6531                           "vlan tag= 0x%04X, flags = 0x%04X (",
6532                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6533                           txbd->tx_bd_mss_nbytes,
6534                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6535
6536                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6537                         kprintf(" CONN_FAULT");
6538
6539                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6540                         kprintf(" TCP_UDP_CKSUM");
6541
6542                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6543                         kprintf(" IP_CKSUM");
6544
6545                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6546                         kprintf("  VLAN");
6547
6548                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6549                         kprintf(" COAL_NOW");
6550
6551                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6552                         kprintf(" DONT_GEN_CRC");
6553
6554                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6555                         kprintf(" START");
6556
6557                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6558                         kprintf(" END");
6559
6560                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6561                         kprintf(" LSO");
6562
6563                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6564                         kprintf(" OPTION_WORD");
6565
6566                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6567                         kprintf(" FLAGS");
6568
6569                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6570                         kprintf(" SNAP");
6571
6572                 kprintf(" )\n");
6573         }
6574 }
6575
6576
6577 /****************************************************************************/
6578 /* Prints out a rx_bd structure.                                            */
6579 /*                                                                          */
6580 /* Returns:                                                                 */
6581 /*   Nothing.                                                               */
6582 /****************************************************************************/
6583 static void
6584 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6585 {
6586         struct ifnet *ifp = &sc->arpcom.ac_if;
6587
6588         if (idx > MAX_RX_BD) {
6589                 /* Index out of range. */
6590                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6591         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6592                 /* TX Chain page pointer. */
6593                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6594                           "chain page pointer\n",
6595                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6596         } else {
6597                 /* Normal tx_bd entry. */
6598                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6599                           "nbytes = 0x%08X, flags = 0x%08X\n",
6600                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6601                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6602         }
6603 }
6604
6605
6606 /****************************************************************************/
6607 /* Prints out a l2_fhdr structure.                                          */
6608 /*                                                                          */
6609 /* Returns:                                                                 */
6610 /*   Nothing.                                                               */
6611 /****************************************************************************/
6612 static void
6613 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
6614 {
6615         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
6616                   "pkt_len = 0x%04X, vlan = 0x%04x, "
6617                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
6618                   idx, l2fhdr->l2_fhdr_status,
6619                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
6620                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
6621 }
6622
6623
6624 /****************************************************************************/
6625 /* Prints out the tx chain.                                                 */
6626 /*                                                                          */
6627 /* Returns:                                                                 */
6628 /*   Nothing.                                                               */
6629 /****************************************************************************/
6630 static void
6631 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
6632 {
6633         struct ifnet *ifp = &sc->arpcom.ac_if;
6634         int i;
6635
6636         /* First some info about the tx_bd chain structure. */
6637         if_printf(ifp,
6638         "----------------------------"
6639         "  tx_bd  chain  "
6640         "----------------------------\n");
6641
6642         if_printf(ifp, "page size      = 0x%08X, "
6643                   "tx chain pages        = 0x%08X\n",
6644                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)TX_PAGES);
6645
6646         if_printf(ifp, "tx_bd per page = 0x%08X, "
6647                   "usable tx_bd per page = 0x%08X\n",
6648                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
6649                   (uint32_t)USABLE_TX_BD_PER_PAGE);
6650
6651         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
6652
6653         if_printf(ifp,
6654         "----------------------------"
6655         "  tx_bd data    "
6656         "----------------------------\n");
6657
6658         /* Now print out the tx_bd's themselves. */
6659         for (i = 0; i < count; i++) {
6660                 struct tx_bd *txbd;
6661
6662                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
6663                 bce_dump_txbd(sc, tx_prod, txbd);
6664                 tx_prod = TX_CHAIN_IDX(NEXT_TX_BD(tx_prod));
6665         }
6666
6667         if_printf(ifp,
6668         "----------------------------"
6669         "----------------"
6670         "----------------------------\n");
6671 }
6672
6673
6674 /****************************************************************************/
6675 /* Prints out the rx chain.                                                 */
6676 /*                                                                          */
6677 /* Returns:                                                                 */
6678 /*   Nothing.                                                               */
6679 /****************************************************************************/
6680 static void
6681 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
6682 {
6683         struct ifnet *ifp = &sc->arpcom.ac_if;
6684         int i;
6685
6686         /* First some info about the tx_bd chain structure. */
6687         if_printf(ifp,
6688         "----------------------------"
6689         "  rx_bd  chain  "
6690         "----------------------------\n");
6691
6692         if_printf(ifp, "page size      = 0x%08X, "
6693                   "rx chain pages        = 0x%08X\n",
6694                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)RX_PAGES);
6695
6696         if_printf(ifp, "rx_bd per page = 0x%08X, "
6697                   "usable rx_bd per page = 0x%08X\n",
6698                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
6699                   (uint32_t)USABLE_RX_BD_PER_PAGE);
6700
6701         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
6702
6703         if_printf(ifp,
6704         "----------------------------"
6705         "   rx_bd data   "
6706         "----------------------------\n");
6707
6708         /* Now print out the rx_bd's themselves. */
6709         for (i = 0; i < count; i++) {
6710                 struct rx_bd *rxbd;
6711
6712                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
6713                 bce_dump_rxbd(sc, rx_prod, rxbd);
6714                 rx_prod = RX_CHAIN_IDX(NEXT_RX_BD(rx_prod));
6715         }
6716
6717         if_printf(ifp,
6718         "----------------------------"
6719         "----------------"
6720         "----------------------------\n");
6721 }
6722
6723
6724 /****************************************************************************/
6725 /* Prints out the status block from host memory.                            */
6726 /*                                                                          */
6727 /* Returns:                                                                 */
6728 /*   Nothing.                                                               */
6729 /****************************************************************************/
6730 static void
6731 bce_dump_status_block(struct bce_softc *sc)
6732 {
6733         struct status_block *sblk = sc->status_block;
6734         struct ifnet *ifp = &sc->arpcom.ac_if;
6735
6736         if_printf(ifp,
6737         "----------------------------"
6738         "  Status Block  "
6739         "----------------------------\n");
6740
6741         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
6742
6743         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
6744                   sblk->status_attn_bits_ack);
6745
6746         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
6747             sblk->status_rx_quick_consumer_index0,
6748             (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
6749
6750         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
6751             sblk->status_tx_quick_consumer_index0,
6752             (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
6753
6754         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
6755
6756         /* Theses indices are not used for normal L2 drivers. */
6757         if (sblk->status_rx_quick_consumer_index1) {
6758                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
6759                 sblk->status_rx_quick_consumer_index1,
6760                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index1));
6761         }
6762
6763         if (sblk->status_tx_quick_consumer_index1) {
6764                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
6765                 sblk->status_tx_quick_consumer_index1,
6766                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index1));
6767         }
6768
6769         if (sblk->status_rx_quick_consumer_index2) {
6770                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
6771                 sblk->status_rx_quick_consumer_index2,
6772                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index2));
6773         }
6774
6775         if (sblk->status_tx_quick_consumer_index2) {
6776                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
6777                 sblk->status_tx_quick_consumer_index2,
6778                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index2));
6779         }
6780
6781         if (sblk->status_rx_quick_consumer_index3) {
6782                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
6783                 sblk->status_rx_quick_consumer_index3,
6784                 (uint16_t)RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
6785         }
6786
6787         if (sblk->status_tx_quick_consumer_index3) {
6788                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
6789                 sblk->status_tx_quick_consumer_index3,
6790                 (uint16_t)TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
6791         }
6792
6793         if (sblk->status_rx_quick_consumer_index4 ||
6794             sblk->status_rx_quick_consumer_index5) {
6795                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
6796                           sblk->status_rx_quick_consumer_index4,
6797                           sblk->status_rx_quick_consumer_index5);
6798         }
6799
6800         if (sblk->status_rx_quick_consumer_index6 ||
6801             sblk->status_rx_quick_consumer_index7) {
6802                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
6803                           sblk->status_rx_quick_consumer_index6,
6804                           sblk->status_rx_quick_consumer_index7);
6805         }
6806
6807         if (sblk->status_rx_quick_consumer_index8 ||
6808             sblk->status_rx_quick_consumer_index9) {
6809                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
6810                           sblk->status_rx_quick_consumer_index8,
6811                           sblk->status_rx_quick_consumer_index9);
6812         }
6813
6814         if (sblk->status_rx_quick_consumer_index10 ||
6815             sblk->status_rx_quick_consumer_index11) {
6816                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
6817                           sblk->status_rx_quick_consumer_index10,
6818                           sblk->status_rx_quick_consumer_index11);
6819         }
6820
6821         if (sblk->status_rx_quick_consumer_index12 ||
6822             sblk->status_rx_quick_consumer_index13) {
6823                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
6824                           sblk->status_rx_quick_consumer_index12,
6825                           sblk->status_rx_quick_consumer_index13);
6826         }
6827
6828         if (sblk->status_rx_quick_consumer_index14 ||
6829             sblk->status_rx_quick_consumer_index15) {
6830                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
6831                           sblk->status_rx_quick_consumer_index14,
6832                           sblk->status_rx_quick_consumer_index15);
6833         }
6834
6835         if (sblk->status_completion_producer_index ||
6836             sblk->status_cmd_consumer_index) {
6837                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
6838                           sblk->status_completion_producer_index,
6839                           sblk->status_cmd_consumer_index);
6840         }
6841
6842         if_printf(ifp,
6843         "----------------------------"
6844         "----------------"
6845         "----------------------------\n");
6846 }
6847
6848
6849 /****************************************************************************/
6850 /* Prints out the statistics block.                                         */
6851 /*                                                                          */
6852 /* Returns:                                                                 */
6853 /*   Nothing.                                                               */
6854 /****************************************************************************/
6855 static void
6856 bce_dump_stats_block(struct bce_softc *sc)
6857 {
6858         struct statistics_block *sblk = sc->stats_block;
6859         struct ifnet *ifp = &sc->arpcom.ac_if;
6860
6861         if_printf(ifp,
6862         "---------------"
6863         " Stats Block  (All Stats Not Shown Are 0) "
6864         "---------------\n");
6865
6866         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
6867                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
6868                           sblk->stat_IfHCInOctets_hi,
6869                           sblk->stat_IfHCInOctets_lo);
6870         }
6871
6872         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
6873                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
6874                           sblk->stat_IfHCInBadOctets_hi,
6875                           sblk->stat_IfHCInBadOctets_lo);
6876         }
6877
6878         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
6879                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
6880                           sblk->stat_IfHCOutOctets_hi,
6881                           sblk->stat_IfHCOutOctets_lo);
6882         }
6883
6884         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
6885                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
6886                           sblk->stat_IfHCOutBadOctets_hi,
6887                           sblk->stat_IfHCOutBadOctets_lo);
6888         }
6889
6890         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
6891                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
6892                           sblk->stat_IfHCInUcastPkts_hi,
6893                           sblk->stat_IfHCInUcastPkts_lo);
6894         }
6895
6896         if (sblk->stat_IfHCInBroadcastPkts_hi ||
6897             sblk->stat_IfHCInBroadcastPkts_lo) {
6898                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
6899                           sblk->stat_IfHCInBroadcastPkts_hi,
6900                           sblk->stat_IfHCInBroadcastPkts_lo);
6901         }
6902
6903         if (sblk->stat_IfHCInMulticastPkts_hi ||
6904             sblk->stat_IfHCInMulticastPkts_lo) {
6905                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
6906                           sblk->stat_IfHCInMulticastPkts_hi,
6907                           sblk->stat_IfHCInMulticastPkts_lo);
6908         }
6909
6910         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
6911                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
6912                           sblk->stat_IfHCOutUcastPkts_hi,
6913                           sblk->stat_IfHCOutUcastPkts_lo);
6914         }
6915
6916         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
6917             sblk->stat_IfHCOutBroadcastPkts_lo) {
6918                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
6919                           sblk->stat_IfHCOutBroadcastPkts_hi,
6920                           sblk->stat_IfHCOutBroadcastPkts_lo);
6921         }
6922
6923         if (sblk->stat_IfHCOutMulticastPkts_hi ||
6924             sblk->stat_IfHCOutMulticastPkts_lo) {
6925                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
6926                           sblk->stat_IfHCOutMulticastPkts_hi,
6927                           sblk->stat_IfHCOutMulticastPkts_lo);
6928         }
6929
6930         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
6931                 if_printf(ifp, "         0x%08X : "
6932                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
6933                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
6934         }
6935
6936         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
6937                 if_printf(ifp, "         0x%08X : "
6938                           "Dot3StatsCarrierSenseErrors\n",
6939                           sblk->stat_Dot3StatsCarrierSenseErrors);
6940         }
6941
6942         if (sblk->stat_Dot3StatsFCSErrors) {
6943                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
6944                           sblk->stat_Dot3StatsFCSErrors);
6945         }
6946
6947         if (sblk->stat_Dot3StatsAlignmentErrors) {
6948                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
6949                           sblk->stat_Dot3StatsAlignmentErrors);
6950         }
6951
6952         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
6953                 if_printf(ifp, "         0x%08X : "
6954                           "Dot3StatsSingleCollisionFrames\n",
6955                           sblk->stat_Dot3StatsSingleCollisionFrames);
6956         }
6957
6958         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
6959                 if_printf(ifp, "         0x%08X : "
6960                           "Dot3StatsMultipleCollisionFrames\n",
6961                           sblk->stat_Dot3StatsMultipleCollisionFrames);
6962         }
6963
6964         if (sblk->stat_Dot3StatsDeferredTransmissions) {
6965                 if_printf(ifp, "         0x%08X : "
6966                           "Dot3StatsDeferredTransmissions\n",
6967                           sblk->stat_Dot3StatsDeferredTransmissions);
6968         }
6969
6970         if (sblk->stat_Dot3StatsExcessiveCollisions) {
6971                 if_printf(ifp, "         0x%08X : "
6972                           "Dot3StatsExcessiveCollisions\n",
6973                           sblk->stat_Dot3StatsExcessiveCollisions);
6974         }
6975
6976         if (sblk->stat_Dot3StatsLateCollisions) {
6977                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
6978                           sblk->stat_Dot3StatsLateCollisions);
6979         }
6980
6981         if (sblk->stat_EtherStatsCollisions) {
6982                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
6983                           sblk->stat_EtherStatsCollisions);
6984         }
6985
6986         if (sblk->stat_EtherStatsFragments)  {
6987                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
6988                           sblk->stat_EtherStatsFragments);
6989         }
6990
6991         if (sblk->stat_EtherStatsJabbers) {
6992                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
6993                           sblk->stat_EtherStatsJabbers);
6994         }
6995
6996         if (sblk->stat_EtherStatsUndersizePkts) {
6997                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
6998                           sblk->stat_EtherStatsUndersizePkts);
6999         }
7000
7001         if (sblk->stat_EtherStatsOverrsizePkts) {
7002                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
7003                           sblk->stat_EtherStatsOverrsizePkts);
7004         }
7005
7006         if (sblk->stat_EtherStatsPktsRx64Octets) {
7007                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
7008                           sblk->stat_EtherStatsPktsRx64Octets);
7009         }
7010
7011         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7012                 if_printf(ifp, "         0x%08X : "
7013                           "EtherStatsPktsRx65Octetsto127Octets\n",
7014                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7015         }
7016
7017         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7018                 if_printf(ifp, "         0x%08X : "
7019                           "EtherStatsPktsRx128Octetsto255Octets\n",
7020                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7021         }
7022
7023         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7024                 if_printf(ifp, "         0x%08X : "
7025                           "EtherStatsPktsRx256Octetsto511Octets\n",
7026                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7027         }
7028
7029         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7030                 if_printf(ifp, "         0x%08X : "
7031                           "EtherStatsPktsRx512Octetsto1023Octets\n",
7032                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7033         }
7034
7035         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7036                 if_printf(ifp, "         0x%08X : "
7037                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
7038                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7039         }
7040
7041         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7042                 if_printf(ifp, "         0x%08X : "
7043                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
7044                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7045         }
7046
7047         if (sblk->stat_EtherStatsPktsTx64Octets) {
7048                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
7049                           sblk->stat_EtherStatsPktsTx64Octets);
7050         }
7051
7052         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7053                 if_printf(ifp, "         0x%08X : "
7054                           "EtherStatsPktsTx65Octetsto127Octets\n",
7055                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7056         }
7057
7058         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7059                 if_printf(ifp, "         0x%08X : "
7060                           "EtherStatsPktsTx128Octetsto255Octets\n",
7061                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7062         }
7063
7064         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7065                 if_printf(ifp, "         0x%08X : "
7066                           "EtherStatsPktsTx256Octetsto511Octets\n",
7067                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7068         }
7069
7070         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7071                 if_printf(ifp, "         0x%08X : "
7072                           "EtherStatsPktsTx512Octetsto1023Octets\n",
7073                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7074         }
7075
7076         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7077                 if_printf(ifp, "         0x%08X : "
7078                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
7079                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7080         }
7081
7082         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7083                 if_printf(ifp, "         0x%08X : "
7084                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
7085                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7086         }
7087
7088         if (sblk->stat_XonPauseFramesReceived) {
7089                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
7090                           sblk->stat_XonPauseFramesReceived);
7091         }
7092
7093         if (sblk->stat_XoffPauseFramesReceived) {
7094                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
7095                           sblk->stat_XoffPauseFramesReceived);
7096         }
7097
7098         if (sblk->stat_OutXonSent) {
7099                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7100                           sblk->stat_OutXonSent);
7101         }
7102
7103         if (sblk->stat_OutXoffSent) {
7104                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7105                           sblk->stat_OutXoffSent);
7106         }
7107
7108         if (sblk->stat_FlowControlDone) {
7109                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
7110                           sblk->stat_FlowControlDone);
7111         }
7112
7113         if (sblk->stat_MacControlFramesReceived) {
7114                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
7115                           sblk->stat_MacControlFramesReceived);
7116         }
7117
7118         if (sblk->stat_XoffStateEntered) {
7119                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
7120                           sblk->stat_XoffStateEntered);
7121         }
7122
7123         if (sblk->stat_IfInFramesL2FilterDiscards) {
7124                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
7125         }
7126
7127         if (sblk->stat_IfInRuleCheckerDiscards) {
7128                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
7129                           sblk->stat_IfInRuleCheckerDiscards);
7130         }
7131
7132         if (sblk->stat_IfInFTQDiscards) {
7133                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
7134                           sblk->stat_IfInFTQDiscards);
7135         }
7136
7137         if (sblk->stat_IfInMBUFDiscards) {
7138                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
7139                           sblk->stat_IfInMBUFDiscards);
7140         }
7141
7142         if (sblk->stat_IfInRuleCheckerP4Hit) {
7143                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
7144                           sblk->stat_IfInRuleCheckerP4Hit);
7145         }
7146
7147         if (sblk->stat_CatchupInRuleCheckerDiscards) {
7148                 if_printf(ifp, "         0x%08X : "
7149                           "CatchupInRuleCheckerDiscards\n",
7150                           sblk->stat_CatchupInRuleCheckerDiscards);
7151         }
7152
7153         if (sblk->stat_CatchupInFTQDiscards) {
7154                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
7155                           sblk->stat_CatchupInFTQDiscards);
7156         }
7157
7158         if (sblk->stat_CatchupInMBUFDiscards) {
7159                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
7160                           sblk->stat_CatchupInMBUFDiscards);
7161         }
7162
7163         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7164                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
7165                           sblk->stat_CatchupInRuleCheckerP4Hit);
7166         }
7167
7168         if_printf(ifp,
7169         "----------------------------"
7170         "----------------"
7171         "----------------------------\n");
7172 }
7173
7174
7175 /****************************************************************************/
7176 /* Prints out a summary of the driver state.                                */
7177 /*                                                                          */
7178 /* Returns:                                                                 */
7179 /*   Nothing.                                                               */
7180 /****************************************************************************/
7181 static void
7182 bce_dump_driver_state(struct bce_softc *sc)
7183 {
7184         struct ifnet *ifp = &sc->arpcom.ac_if;
7185         uint32_t val_hi, val_lo;
7186
7187         if_printf(ifp,
7188         "-----------------------------"
7189         " Driver State "
7190         "-----------------------------\n");
7191
7192         val_hi = BCE_ADDR_HI(sc);
7193         val_lo = BCE_ADDR_LO(sc);
7194         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7195                   "virtual address\n", val_hi, val_lo);
7196
7197         val_hi = BCE_ADDR_HI(sc->status_block);
7198         val_lo = BCE_ADDR_LO(sc->status_block);
7199         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7200                   "virtual address\n", val_hi, val_lo);
7201
7202         val_hi = BCE_ADDR_HI(sc->stats_block);
7203         val_lo = BCE_ADDR_LO(sc->stats_block);
7204         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7205                   "virtual address\n", val_hi, val_lo);
7206
7207         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7208         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7209         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7210                   "virtual adddress\n", val_hi, val_lo);
7211
7212         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7213         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7214         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7215                   "virtual address\n", val_hi, val_lo);
7216
7217         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7218         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7219         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7220                   "virtual address\n", val_hi, val_lo);
7221
7222         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7223         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7224         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7225                   "virtual address\n", val_hi, val_lo);
7226
7227         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
7228                   "h/w intrs\n", sc->interrupts_generated);
7229
7230         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
7231                   "rx interrupts handled\n", sc->rx_interrupts);
7232
7233         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
7234                   "tx interrupts handled\n", sc->tx_interrupts);
7235
7236         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
7237                   "status block index\n", sc->last_status_idx);
7238
7239         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
7240                   "tx producer index\n",
7241                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc->tx_prod));
7242
7243         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
7244                   "tx consumer index\n",
7245                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc->tx_cons));
7246
7247         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
7248                   "tx producer bseq index\n", sc->tx_prod_bseq);
7249
7250         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
7251                   "rx producer index\n",
7252                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc->rx_prod));
7253
7254         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
7255                   "rx consumer index\n",
7256                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc->rx_cons));
7257
7258         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
7259                   "rx producer bseq index\n", sc->rx_prod_bseq);
7260
7261         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7262                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7263
7264         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
7265                   "free rx_bd's\n", sc->free_rx_bd);
7266
7267         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7268                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7269
7270         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
7271                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7272
7273         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7274                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7275
7276         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7277                   sc->used_tx_bd);
7278
7279         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7280                   sc->tx_hi_watermark, sc->max_tx_bd);
7281
7282         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
7283                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7284
7285         if_printf(ifp,
7286         "----------------------------"
7287         "----------------"
7288         "----------------------------\n");
7289 }
7290
7291
7292 /****************************************************************************/
7293 /* Prints out the hardware state through a summary of important registers,  */
7294 /* followed by a complete register dump.                                    */
7295 /*                                                                          */
7296 /* Returns:                                                                 */
7297 /*   Nothing.                                                               */
7298 /****************************************************************************/
7299 static void
7300 bce_dump_hw_state(struct bce_softc *sc)
7301 {
7302         struct ifnet *ifp = &sc->arpcom.ac_if;
7303         uint32_t val1;
7304         int i;
7305
7306         if_printf(ifp,
7307         "----------------------------"
7308         " Hardware State "
7309         "----------------------------\n");
7310
7311         if_printf(ifp, "0x%08X - bootcode version\n", sc->bce_fw_ver);
7312
7313         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7314         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7315                   val1, BCE_MISC_ENABLE_STATUS_BITS);
7316
7317         val1 = REG_RD(sc, BCE_DMA_STATUS);
7318         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7319
7320         val1 = REG_RD(sc, BCE_CTX_STATUS);
7321         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7322
7323         val1 = REG_RD(sc, BCE_EMAC_STATUS);
7324         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7325                   val1, BCE_EMAC_STATUS);
7326
7327         val1 = REG_RD(sc, BCE_RPM_STATUS);
7328         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7329
7330         val1 = REG_RD(sc, BCE_TBDR_STATUS);
7331         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7332                   val1, BCE_TBDR_STATUS);
7333
7334         val1 = REG_RD(sc, BCE_TDMA_STATUS);
7335         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7336                   val1, BCE_TDMA_STATUS);
7337
7338         val1 = REG_RD(sc, BCE_HC_STATUS);
7339         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7340
7341         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7342         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7343                   val1, BCE_TXP_CPU_STATE);
7344
7345         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7346         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7347                   val1, BCE_TPAT_CPU_STATE);
7348
7349         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7350         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7351                   val1, BCE_RXP_CPU_STATE);
7352
7353         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7354         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7355                   val1, BCE_COM_CPU_STATE);
7356
7357         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7358         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7359                   val1, BCE_MCP_CPU_STATE);
7360
7361         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7362         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7363                   val1, BCE_CP_CPU_STATE);
7364
7365         if_printf(ifp,
7366         "----------------------------"
7367         "----------------"
7368         "----------------------------\n");
7369
7370         if_printf(ifp,
7371         "----------------------------"
7372         " Register  Dump "
7373         "----------------------------\n");
7374
7375         for (i = 0x400; i < 0x8000; i += 0x10) {
7376                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7377                           REG_RD(sc, i),
7378                           REG_RD(sc, i + 0x4),
7379                           REG_RD(sc, i + 0x8),
7380                           REG_RD(sc, i + 0xc));
7381         }
7382
7383         if_printf(ifp,
7384         "----------------------------"
7385         "----------------"
7386         "----------------------------\n");
7387 }
7388
7389
7390 /****************************************************************************/
7391 /* Prints out the TXP state.                                                */
7392 /*                                                                          */
7393 /* Returns:                                                                 */
7394 /*   Nothing.                                                               */
7395 /****************************************************************************/
7396 static void
7397 bce_dump_txp_state(struct bce_softc *sc)
7398 {
7399         struct ifnet *ifp = &sc->arpcom.ac_if;
7400         uint32_t val1;
7401         int i;
7402
7403         if_printf(ifp,
7404         "----------------------------"
7405         "   TXP  State   "
7406         "----------------------------\n");
7407
7408         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7409         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7410                   val1, BCE_TXP_CPU_MODE);
7411
7412         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7413         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7414                   val1, BCE_TXP_CPU_STATE);
7415
7416         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7417         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7418                   val1, BCE_TXP_CPU_EVENT_MASK);
7419
7420         if_printf(ifp,
7421         "----------------------------"
7422         " Register  Dump "
7423         "----------------------------\n");
7424
7425         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7426                 /* Skip the big blank spaces */
7427                 if (i < 0x454000 && i > 0x5ffff) {
7428                         if_printf(ifp, "0x%04X: "
7429                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7430                                   REG_RD_IND(sc, i),
7431                                   REG_RD_IND(sc, i + 0x4),
7432                                   REG_RD_IND(sc, i + 0x8),
7433                                   REG_RD_IND(sc, i + 0xc));
7434                 }
7435         }
7436
7437         if_printf(ifp,
7438         "----------------------------"
7439         "----------------"
7440         "----------------------------\n");
7441 }
7442
7443
7444 /****************************************************************************/
7445 /* Prints out the RXP state.                                                */
7446 /*                                                                          */
7447 /* Returns:                                                                 */
7448 /*   Nothing.                                                               */
7449 /****************************************************************************/
7450 static void
7451 bce_dump_rxp_state(struct bce_softc *sc)
7452 {
7453         struct ifnet *ifp = &sc->arpcom.ac_if;
7454         uint32_t val1;
7455         int i;
7456
7457         if_printf(ifp,
7458         "----------------------------"
7459         "   RXP  State   "
7460         "----------------------------\n");
7461
7462         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7463         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7464                   val1, BCE_RXP_CPU_MODE);
7465
7466         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7467         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7468                   val1, BCE_RXP_CPU_STATE);
7469
7470         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7471         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7472                   val1, BCE_RXP_CPU_EVENT_MASK);
7473
7474         if_printf(ifp,
7475         "----------------------------"
7476         " Register  Dump "
7477         "----------------------------\n");
7478
7479         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7480                 /* Skip the big blank sapces */
7481                 if (i < 0xc5400 && i > 0xdffff) {
7482                         if_printf(ifp, "0x%04X: "
7483                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7484                                   REG_RD_IND(sc, i),
7485                                   REG_RD_IND(sc, i + 0x4),
7486                                   REG_RD_IND(sc, i + 0x8),
7487                                   REG_RD_IND(sc, i + 0xc));
7488                 }
7489         }
7490
7491         if_printf(ifp,
7492         "----------------------------"
7493         "----------------"
7494         "----------------------------\n");
7495 }
7496
7497
7498 /****************************************************************************/
7499 /* Prints out the TPAT state.                                               */
7500 /*                                                                          */
7501 /* Returns:                                                                 */
7502 /*   Nothing.                                                               */
7503 /****************************************************************************/
7504 static void
7505 bce_dump_tpat_state(struct bce_softc *sc)
7506 {
7507         struct ifnet *ifp = &sc->arpcom.ac_if;
7508         uint32_t val1;
7509         int i;
7510
7511         if_printf(ifp,
7512         "----------------------------"
7513         "   TPAT State   "
7514         "----------------------------\n");
7515
7516         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7517         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7518                   val1, BCE_TPAT_CPU_MODE);
7519
7520         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7521         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7522                   val1, BCE_TPAT_CPU_STATE);
7523
7524         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7525         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7526                   val1, BCE_TPAT_CPU_EVENT_MASK);
7527
7528         if_printf(ifp,
7529         "----------------------------"
7530         " Register  Dump "
7531         "----------------------------\n");
7532
7533         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7534                 /* Skip the big blank spaces */
7535                 if (i < 0x854000 && i > 0x9ffff) {
7536                         if_printf(ifp, "0x%04X: "
7537                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7538                                   REG_RD_IND(sc, i),
7539                                   REG_RD_IND(sc, i + 0x4),
7540                                   REG_RD_IND(sc, i + 0x8),
7541                                   REG_RD_IND(sc, i + 0xc));
7542                 }
7543         }
7544
7545         if_printf(ifp,
7546         "----------------------------"
7547         "----------------"
7548         "----------------------------\n");
7549 }
7550
7551
7552 /****************************************************************************/
7553 /* Prints out the driver state and then enters the debugger.                */
7554 /*                                                                          */
7555 /* Returns:                                                                 */
7556 /*   Nothing.                                                               */
7557 /****************************************************************************/
7558 static void
7559 bce_breakpoint(struct bce_softc *sc)
7560 {
7561 #if 0
7562         bce_freeze_controller(sc);
7563 #endif
7564
7565         bce_dump_driver_state(sc);
7566         bce_dump_status_block(sc);
7567         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
7568         bce_dump_hw_state(sc);
7569         bce_dump_txp_state(sc);
7570
7571 #if 0
7572         bce_unfreeze_controller(sc);
7573 #endif
7574
7575         /* Call the debugger. */
7576         breakpoint();
7577 }
7578
7579 #endif  /* BCE_DEBUG */
7580
7581 static int
7582 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7583 {
7584         struct bce_softc *sc = arg1;
7585
7586         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7587                         &sc->bce_tx_quick_cons_trip_int,
7588                         BCE_COALMASK_TX_BDS_INT);
7589 }
7590
7591 static int
7592 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7593 {
7594         struct bce_softc *sc = arg1;
7595
7596         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7597                         &sc->bce_tx_quick_cons_trip,
7598                         BCE_COALMASK_TX_BDS);
7599 }
7600
7601 static int
7602 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
7603 {
7604         struct bce_softc *sc = arg1;
7605
7606         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7607                         &sc->bce_tx_ticks_int,
7608                         BCE_COALMASK_TX_TICKS_INT);
7609 }
7610
7611 static int
7612 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
7613 {
7614         struct bce_softc *sc = arg1;
7615
7616         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7617                         &sc->bce_tx_ticks,
7618                         BCE_COALMASK_TX_TICKS);
7619 }
7620
7621 static int
7622 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
7623 {
7624         struct bce_softc *sc = arg1;
7625
7626         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7627                         &sc->bce_rx_quick_cons_trip_int,
7628                         BCE_COALMASK_RX_BDS_INT);
7629 }
7630
7631 static int
7632 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
7633 {
7634         struct bce_softc *sc = arg1;
7635
7636         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7637                         &sc->bce_rx_quick_cons_trip,
7638                         BCE_COALMASK_RX_BDS);
7639 }
7640
7641 static int
7642 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
7643 {
7644         struct bce_softc *sc = arg1;
7645
7646         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7647                         &sc->bce_rx_ticks_int,
7648                         BCE_COALMASK_RX_TICKS_INT);
7649 }
7650
7651 static int
7652 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
7653 {
7654         struct bce_softc *sc = arg1;
7655
7656         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7657                         &sc->bce_rx_ticks,
7658                         BCE_COALMASK_RX_TICKS);
7659 }
7660
7661 static int
7662 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
7663                        uint32_t coalchg_mask)
7664 {
7665         struct bce_softc *sc = arg1;
7666         struct ifnet *ifp = &sc->arpcom.ac_if;
7667         int error = 0, v;
7668
7669         lwkt_serialize_enter(ifp->if_serializer);
7670
7671         v = *coal;
7672         error = sysctl_handle_int(oidp, &v, 0, req);
7673         if (!error && req->newptr != NULL) {
7674                 if (v < 0) {
7675                         error = EINVAL;
7676                 } else {
7677                         *coal = v;
7678                         sc->bce_coalchg_mask |= coalchg_mask;
7679                 }
7680         }
7681
7682         lwkt_serialize_exit(ifp->if_serializer);
7683         return error;
7684 }
7685
7686 static void
7687 bce_coal_change(struct bce_softc *sc)
7688 {
7689         struct ifnet *ifp = &sc->arpcom.ac_if;
7690
7691         ASSERT_SERIALIZED(ifp->if_serializer);
7692
7693         if ((ifp->if_flags & IFF_RUNNING) == 0) {
7694                 sc->bce_coalchg_mask = 0;
7695                 return;
7696         }
7697
7698         if (sc->bce_coalchg_mask &
7699             (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
7700                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
7701                        (sc->bce_tx_quick_cons_trip_int << 16) |
7702                        sc->bce_tx_quick_cons_trip);
7703                 if (bootverbose) {
7704                         if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
7705                                   sc->bce_tx_quick_cons_trip,
7706                                   sc->bce_tx_quick_cons_trip_int);
7707                 }
7708         }
7709
7710         if (sc->bce_coalchg_mask &
7711             (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
7712                 REG_WR(sc, BCE_HC_TX_TICKS,
7713                        (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
7714                 if (bootverbose) {
7715                         if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
7716                                   sc->bce_tx_ticks, sc->bce_tx_ticks_int);
7717                 }
7718         }
7719
7720         if (sc->bce_coalchg_mask &
7721             (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
7722                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
7723                        (sc->bce_rx_quick_cons_trip_int << 16) |
7724                        sc->bce_rx_quick_cons_trip);
7725                 if (bootverbose) {
7726                         if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
7727                                   sc->bce_rx_quick_cons_trip,
7728                                   sc->bce_rx_quick_cons_trip_int);
7729                 }
7730         }
7731
7732         if (sc->bce_coalchg_mask &
7733             (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
7734                 REG_WR(sc, BCE_HC_RX_TICKS,
7735                        (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
7736                 if (bootverbose) {
7737                         if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
7738                                   sc->bce_rx_ticks, sc->bce_rx_ticks_int);
7739                 }
7740         }
7741
7742         sc->bce_coalchg_mask = 0;
7743 }