2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
4 * Copyright (c) 2008 The DragonFly Project.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the University of
18 * California, Berkeley and its contributors.
19 * 4. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * $FreeBSD: src/sys/amd64/include/cpufunc.h,v 1.139 2004/01/28 23:53:04 peter Exp $
39 * Functions to provide access to special i386 instructions.
40 * This in included in sys/systm.h, and that file should be
41 * used in preference to this.
44 #ifndef _CPU_CPUFUNC_H_
45 #define _CPU_CPUFUNC_H_
47 #include <sys/cdefs.h>
48 #include <machine/psl.h>
51 struct region_descriptor;
54 #define readb(va) (*(volatile u_int8_t *) (va))
55 #define readw(va) (*(volatile u_int16_t *) (va))
56 #define readl(va) (*(volatile u_int32_t *) (va))
57 #define readq(va) (*(volatile u_int64_t *) (va))
59 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
60 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
61 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
62 #define writeq(va, d) (*(volatile u_int64_t *) (va) = (d))
67 #include <machine/lock.h> /* XXX */
73 __asm __volatile("int $3");
79 __asm __volatile("pause");
87 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
91 static __inline u_long
96 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
100 static __inline u_int
105 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
109 static __inline u_long
114 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
119 do_cpuid(u_int ax, u_int *p)
121 __asm __volatile("cpuid"
122 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
127 cpuid_count(u_int ax, u_int cx, u_int *p)
129 __asm __volatile("cpuid"
130 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
131 : "0" (ax), "c" (cx));
134 #ifndef _CPU_DISABLE_INTR_DEFINED
137 cpu_disable_intr(void)
139 __asm __volatile("cli" : : : "memory");
144 #ifndef _CPU_ENABLE_INTR_DEFINED
147 cpu_enable_intr(void)
149 __asm __volatile("sti");
155 * Cpu and compiler memory ordering fence. mfence ensures strong read and
158 * A serializing or fence instruction is required here. A locked bus
159 * cycle on data for which we already own cache mastership is the most
166 __asm __volatile("mfence" : : : "memory");
168 __asm __volatile("" : : : "memory");
173 * cpu_lfence() ensures strong read ordering for reads issued prior
174 * to the instruction verses reads issued afterwords.
176 * A serializing or fence instruction is required here. A locked bus
177 * cycle on data for which we already own cache mastership is the most
184 __asm __volatile("lfence" : : : "memory");
186 __asm __volatile("" : : : "memory");
191 * cpu_sfence() ensures strong write ordering for writes issued prior
192 * to the instruction verses writes issued afterwords. Writes are
193 * ordered on intel cpus so we do not actually have to do anything.
200 * Don't use 'sfence' here, as it will create a lot of
201 * unnecessary stalls.
203 __asm __volatile("" : : : "memory");
207 * cpu_ccfence() prevents the compiler from reordering instructions, in
208 * particular stores, relative to the current cpu. Use cpu_sfence() if
209 * you need to guarentee ordering by both the compiler and by the cpu.
211 * This also prevents the compiler from caching memory loads into local
212 * variables across the routine.
217 __asm __volatile("" : : : "memory");
222 #define HAVE_INLINE_FFS
229 * Note that gcc-2's builtin ffs would be used if we didn't declare
230 * this inline or turn off the builtin. The builtin is faster but
231 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
234 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
236 /* Actually, the above is way out of date. The builtins use cmov etc */
237 return (__builtin_ffs(mask));
241 #define HAVE_INLINE_FFSL
246 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
249 #define HAVE_INLINE_FLS
254 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
257 #define HAVE_INLINE_FLSL
262 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
270 __asm __volatile("hlt");
274 * The following complications are to get around gcc not having a
275 * constraint letter for the range 0..255. We still put "d" in the
276 * constraint because "i" isn't a valid constraint when the port
277 * isn't constant. This only matters for -O0 because otherwise
278 * the non-working version gets optimized away.
280 * Use an expression-statement instead of a conditional expression
281 * because gcc-2.6.0 would promote the operands of the conditional
282 * and produce poor code for "if ((inb(var) & const1) == const2)".
284 * The unnecessary test `(port) < 0x10000' is to generate a warning if
285 * the `port' has type u_short or smaller. Such types are pessimal.
286 * This actually only works for signed types. The range check is
287 * careful to avoid generating warnings.
289 #define inb(port) __extension__ ({ \
291 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
292 && (port) < 0x10000) \
293 _data = inbc(port); \
295 _data = inbv(port); \
298 #define outb(port, data) ( \
299 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
300 && (port) < 0x10000 \
301 ? outbc(port, data) : outbv(port, data))
303 static __inline u_char
308 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
313 outbc(u_int port, u_char data)
315 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
318 static __inline u_char
323 * We use %%dx and not %1 here because i/o is done at %dx and not at
324 * %edx, while gcc generates inferior code (movw instead of movl)
325 * if we tell it to load (u_short) port.
327 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
331 static __inline u_int
336 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
341 insb(u_int port, void *addr, size_t cnt)
343 __asm __volatile("cld; rep; insb"
344 : "+D" (addr), "+c" (cnt)
350 insw(u_int port, void *addr, size_t cnt)
352 __asm __volatile("cld; rep; insw"
353 : "+D" (addr), "+c" (cnt)
359 insl(u_int port, void *addr, size_t cnt)
361 __asm __volatile("cld; rep; insl"
362 : "+D" (addr), "+c" (cnt)
370 __asm __volatile("invd");
376 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
377 * will cause the invl*() functions to be equivalent to the cpu_invl*()
381 void smp_invltlb(void);
382 void smp_invltlb_intr(void);
384 #define smp_invltlb()
387 #ifndef _CPU_INVLPG_DEFINED
390 * Invalidate a patricular VA on this cpu only
393 cpu_invlpg(void *addr)
395 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
403 __asm __volatile("rep; nop");
408 static __inline u_short
413 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
417 static __inline u_int
418 loadandclear(volatile u_int *addr)
422 __asm __volatile("xorl %0,%0; xchgl %1,%0"
423 : "=&r" (result) : "m" (*addr));
428 outbv(u_int port, u_char data)
432 * Use an unnecessary assignment to help gcc's register allocator.
433 * This make a large difference for gcc-1.40 and a tiny difference
434 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
435 * best results. gcc-2.6.0 can't handle this.
438 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
442 outl(u_int port, u_int data)
445 * outl() and outw() aren't used much so we haven't looked at
446 * possible micro-optimizations such as the unnecessary
447 * assignment for them.
449 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
453 outsb(u_int port, const void *addr, size_t cnt)
455 __asm __volatile("cld; rep; outsb"
456 : "+S" (addr), "+c" (cnt)
461 outsw(u_int port, const void *addr, size_t cnt)
463 __asm __volatile("cld; rep; outsw"
464 : "+S" (addr), "+c" (cnt)
469 outsl(u_int port, const void *addr, size_t cnt)
471 __asm __volatile("cld; rep; outsl"
472 : "+S" (addr), "+c" (cnt)
477 outw(u_int port, u_short data)
479 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
485 __asm __volatile("pause");
488 static __inline u_long
493 __asm __volatile("pushfq; popq %0" : "=r" (rf));
497 static __inline u_int64_t
502 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
503 return (low | ((u_int64_t)high << 32));
506 static __inline u_int64_t
511 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
512 return (low | ((u_int64_t)high << 32));
515 #define _RDTSC_SUPPORTED_
517 static __inline u_int64_t
522 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
523 return (low | ((u_int64_t)high << 32));
529 __asm __volatile("wbinvd");
533 write_rflags(u_long rf)
535 __asm __volatile("pushq %0; popfq" : : "r" (rf));
539 wrmsr(u_int msr, u_int64_t newval)
545 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
549 load_cr0(u_long data)
552 __asm __volatile("movq %0,%%cr0" : : "r" (data));
555 static __inline u_long
560 __asm __volatile("movq %%cr0,%0" : "=r" (data));
564 static __inline u_long
569 __asm __volatile("movq %%cr2,%0" : "=r" (data));
574 load_cr3(u_long data)
577 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
580 static __inline u_long
585 __asm __volatile("movq %%cr3,%0" : "=r" (data));
590 load_cr4(u_long data)
592 __asm __volatile("movq %0,%%cr4" : : "r" (data));
595 static __inline u_long
600 __asm __volatile("movq %%cr4,%0" : "=r" (data));
604 #ifndef _CPU_INVLTLB_DEFINED
607 * Invalidate the TLB on this cpu only
613 #if defined(SWTCH_OPTIM_STATS)
621 * TLB flush for an individual page (even if it has PG_G).
622 * Only works on 486+ CPUs (i386 does not have PG_G).
628 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
631 static __inline u_short
635 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
639 static __inline u_short
643 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
650 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
656 __asm __volatile("movw %0,%%es" : : "rm" (sel));
660 /* This is defined in <machine/specialreg.h> but is too painful to get to */
662 #define MSR_FSBASE 0xc0000100
667 /* Preserve the fsbase value across the selector load */
668 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
669 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
673 #define MSR_GSBASE 0xc0000101
679 * Preserve the gsbase value across the selector load.
680 * Note that we have to disable interrupts because the gsbase
681 * being trashed happens to be the kernel gsbase at the time.
683 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
684 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
687 /* Usable by userland */
691 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
697 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
701 /* void lidt(struct region_descriptor *addr); */
703 lidt(struct region_descriptor *addr)
705 __asm __volatile("lidt (%0)" : : "r" (addr));
708 /* void lldt(u_short sel); */
712 __asm __volatile("lldt %0" : : "r" (sel));
715 /* void ltr(u_short sel); */
719 __asm __volatile("ltr %0" : : "r" (sel));
722 static __inline u_int64_t
726 __asm __volatile("movq %%dr0,%0" : "=r" (data));
731 load_dr0(u_int64_t dr0)
733 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
736 static __inline u_int64_t
740 __asm __volatile("movq %%dr1,%0" : "=r" (data));
745 load_dr1(u_int64_t dr1)
747 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
750 static __inline u_int64_t
754 __asm __volatile("movq %%dr2,%0" : "=r" (data));
759 load_dr2(u_int64_t dr2)
761 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
764 static __inline u_int64_t
768 __asm __volatile("movq %%dr3,%0" : "=r" (data));
773 load_dr3(u_int64_t dr3)
775 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
778 static __inline u_int64_t
782 __asm __volatile("movq %%dr4,%0" : "=r" (data));
787 load_dr4(u_int64_t dr4)
789 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
792 static __inline u_int64_t
796 __asm __volatile("movq %%dr5,%0" : "=r" (data));
801 load_dr5(u_int64_t dr5)
803 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
806 static __inline u_int64_t
810 __asm __volatile("movq %%dr6,%0" : "=r" (data));
815 load_dr6(u_int64_t dr6)
817 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
820 static __inline u_int64_t
824 __asm __volatile("movq %%dr7,%0" : "=r" (data));
829 load_dr7(u_int64_t dr7)
831 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
834 static __inline register_t
839 rflags = read_rflags();
845 intr_restore(register_t rflags)
847 write_rflags(rflags);
850 #else /* !__GNUC__ */
852 int breakpoint(void);
853 void cpu_pause(void);
854 u_int bsfl(u_int mask);
855 u_int bsrl(u_int mask);
856 void cpu_disable_intr(void);
857 void cpu_enable_intr(void);
858 void cpu_invlpg(u_long addr);
859 void cpu_invlpg_range(u_long start, u_long end);
860 void do_cpuid(u_int ax, u_int *p);
862 u_char inb(u_int port);
863 u_int inl(u_int port);
864 void insb(u_int port, void *addr, size_t cnt);
865 void insl(u_int port, void *addr, size_t cnt);
866 void insw(u_int port, void *addr, size_t cnt);
868 void invlpg(u_int addr);
869 void invlpg_range(u_int start, u_int end);
870 void cpu_invltlb(void);
871 u_short inw(u_int port);
872 void load_cr0(u_int cr0);
873 void load_cr3(u_int cr3);
874 void load_cr4(u_int cr4);
875 void load_fs(u_int sel);
876 void load_gs(u_int sel);
877 struct region_descriptor;
878 void lidt(struct region_descriptor *addr);
879 void lldt(u_short sel);
880 void ltr(u_short sel);
881 void outb(u_int port, u_char data);
882 void outl(u_int port, u_int data);
883 void outsb(u_int port, void *addr, size_t cnt);
884 void outsl(u_int port, void *addr, size_t cnt);
885 void outsw(u_int port, void *addr, size_t cnt);
886 void outw(u_int port, u_short data);
887 void ia32_pause(void);
894 u_int64_t rdmsr(u_int msr);
895 u_int64_t rdpmc(u_int pmc);
896 u_int64_t rdtsc(void);
897 u_int read_rflags(void);
899 void write_rflags(u_int rf);
900 void wrmsr(u_int msr, u_int64_t newval);
901 u_int64_t rdr0(void);
902 void load_dr0(u_int64_t dr0);
903 u_int64_t rdr1(void);
904 void load_dr1(u_int64_t dr1);
905 u_int64_t rdr2(void);
906 void load_dr2(u_int64_t dr2);
907 u_int64_t rdr3(void);
908 void load_dr3(u_int64_t dr3);
909 u_int64_t rdr4(void);
910 void load_dr4(u_int64_t dr4);
911 u_int64_t rdr5(void);
912 void load_dr5(u_int64_t dr5);
913 u_int64_t rdr6(void);
914 void load_dr6(u_int64_t dr6);
915 u_int64_t rdr7(void);
916 void load_dr7(u_int64_t dr7);
917 register_t intr_disable(void);
918 void intr_restore(register_t rf);
920 #endif /* __GNUC__ */
922 int rdmsr_safe(u_int msr, uint64_t *val);
923 void reset_dbregs(void);
927 #endif /* !_CPU_CPUFUNC_H_ */