2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_xl.c,v 1.72.2.28 2003/10/08 06:01:57 murray Exp $
33 * $DragonFly: src/sys/dev/netif/xl/if_xl.c,v 1.17 2005/02/20 04:04:55 joerg Exp $
37 * 3Com 3c90x Etherlink XL PCI NIC driver
39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
40 * bus-master chips (3c90x cards and embedded controllers) including
43 * 3Com 3c900-TPO 10Mbps/RJ-45
44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC
45 * 3Com 3c905-TX 10/100Mbps/RJ-45
46 * 3Com 3c905-T4 10/100Mbps/RJ-45
47 * 3Com 3c900B-TPO 10Mbps/RJ-45
48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC
49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC
50 * 3Com 3c900B-FL 10Mbps/Fiber-optic
51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC
52 * 3Com 3c905B-TX 10/100Mbps/RJ-45
53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic
54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC)
55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC)
56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC)
57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC)
58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC)
59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
69 * Dell on-board 3c920 10/100Mbps/RJ-45
70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
71 * Dell Latitude laptop docking station embedded 3c905-TX
73 * Written by Bill Paul <wpaul@ctr.columbia.edu>
74 * Electrical Engineering Department
75 * Columbia University, New York City
79 * The 3c90x series chips use a bus-master DMA interface for transfering
80 * packets to and from the controller chip. Some of the "vortex" cards
81 * (3c59x) also supported a bus master mode, however for those chips
82 * you could only DMA packets to/from a contiguous memory buffer. For
83 * transmission this would mean copying the contents of the queued mbuf
84 * chain into an mbuf cluster and then DMAing the cluster. This extra
85 * copy would sort of defeat the purpose of the bus master support for
86 * any packet that doesn't fit into a single mbuf.
88 * By contrast, the 3c90x cards support a fragment-based bus master
89 * mode where mbuf chains can be encapsulated using TX descriptors.
90 * This is similar to other PCI chips such as the Texas Instruments
91 * ThunderLAN and the Intel 82557/82558.
93 * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
94 * bus master chips because they maintain the old PIO interface for
95 * backwards compatibility, but starting with the 3c905B and the
96 * "cyclone" chips, the compatibility interface has been dropped.
97 * Since using bus master DMA is a big win, we use this driver to
98 * support the PCI "boomerang" chips even though they work with the
99 * "vortex" driver in order to obtain better performance.
101 * This driver is in the /sys/pci directory because it only supports
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/sockio.h>
108 #include <sys/endian.h>
109 #include <sys/mbuf.h>
110 #include <sys/kernel.h>
111 #include <sys/socket.h>
114 #include <net/ifq_var.h>
115 #include <net/if_arp.h>
116 #include <net/ethernet.h>
117 #include <net/if_dl.h>
118 #include <net/if_media.h>
119 #include <net/vlan/if_vlan_var.h>
123 #include <machine/bus_memio.h>
124 #include <machine/bus_pio.h>
125 #include <machine/bus.h>
126 #include <machine/clock.h> /* for DELAY */
127 #include <machine/resource.h>
129 #include <sys/rman.h>
131 #include "../mii_layer/mii.h"
132 #include "../mii_layer/miivar.h"
134 #include <bus/pci/pcireg.h>
135 #include <bus/pci/pcivar.h>
137 /* "controller miibus0" required. See GENERIC if you get errors here. */
138 #include "miibus_if.h"
140 #include "if_xlreg.h"
142 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
145 * Various supported device vendors/types and their names.
147 static struct xl_type xl_devs[] = {
148 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
149 "3Com 3c900-TPO Etherlink XL" },
150 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
151 "3Com 3c900-COMBO Etherlink XL" },
152 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
153 "3Com 3c905-TX Fast Etherlink XL" },
154 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
155 "3Com 3c905-T4 Fast Etherlink XL" },
156 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
157 "3Com 3c900B-TPO Etherlink XL" },
158 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
159 "3Com 3c900B-COMBO Etherlink XL" },
160 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
161 "3Com 3c900B-TPC Etherlink XL" },
162 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
163 "3Com 3c900B-FL Etherlink XL" },
164 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
165 "3Com 3c905B-TX Fast Etherlink XL" },
166 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
167 "3Com 3c905B-T4 Fast Etherlink XL" },
168 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
169 "3Com 3c905B-FX/SC Fast Etherlink XL" },
170 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
171 "3Com 3c905B-COMBO Fast Etherlink XL" },
172 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
173 "3Com 3c905C-TX Fast Etherlink XL" },
174 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
175 "3Com 3c920B-EMB Integrated Fast Etherlink XL" },
176 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
177 "3Com 3c980 Fast Etherlink XL" },
178 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
179 "3Com 3c980C Fast Etherlink XL" },
180 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
181 "3Com 3cSOHO100-TX OfficeConnect" },
182 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
183 "3Com 3c450-TX HomeConnect" },
184 { TC_VENDORID, TC_DEVICEID_HURRICANE_555,
185 "3Com 3c555 Fast Etherlink XL" },
186 { TC_VENDORID, TC_DEVICEID_HURRICANE_556,
187 "3Com 3c556 Fast Etherlink XL" },
188 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
189 "3Com 3c556B Fast Etherlink XL" },
190 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
191 "3Com 3c575TX Fast Etherlink XL" },
192 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
193 "3Com 3c575B Fast Etherlink XL" },
194 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
195 "3Com 3c575C Fast Etherlink XL" },
196 { TC_VENDORID, TC_DEVICEID_HURRICANE_656,
197 "3Com 3c656 Fast Etherlink XL" },
198 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
199 "3Com 3c656B Fast Etherlink XL" },
200 { TC_VENDORID, TC_DEVICEID_TORNADO_656C,
201 "3Com 3c656C Fast Etherlink XL" },
205 static int xl_probe (device_t);
206 static int xl_attach (device_t);
207 static int xl_detach (device_t);
209 static int xl_newbuf (struct xl_softc *, struct xl_chain_onefrag *);
210 static void xl_stats_update (void *);
211 static int xl_encap (struct xl_softc *, struct xl_chain *,
213 static void xl_rxeof (struct xl_softc *);
214 static int xl_rx_resync (struct xl_softc *);
215 static void xl_txeof (struct xl_softc *);
216 static void xl_txeof_90xB (struct xl_softc *);
217 static void xl_txeoc (struct xl_softc *);
218 static void xl_intr (void *);
219 static void xl_start (struct ifnet *);
220 static void xl_start_90xB (struct ifnet *);
221 static int xl_ioctl (struct ifnet *, u_long, caddr_t,
223 static void xl_init (void *);
224 static void xl_stop (struct xl_softc *);
225 static void xl_watchdog (struct ifnet *);
226 static void xl_shutdown (device_t);
227 static int xl_suspend (device_t);
228 static int xl_resume (device_t);
230 static int xl_ifmedia_upd (struct ifnet *);
231 static void xl_ifmedia_sts (struct ifnet *, struct ifmediareq *);
233 static int xl_eeprom_wait (struct xl_softc *);
234 static int xl_read_eeprom (struct xl_softc *, caddr_t, int, int, int);
235 static void xl_mii_sync (struct xl_softc *);
236 static void xl_mii_send (struct xl_softc *, u_int32_t, int);
237 static int xl_mii_readreg (struct xl_softc *, struct xl_mii_frame *);
238 static int xl_mii_writereg (struct xl_softc *, struct xl_mii_frame *);
240 static void xl_setcfg (struct xl_softc *);
241 static void xl_setmode (struct xl_softc *, int);
242 static u_int8_t xl_calchash (caddr_t);
243 static void xl_setmulti (struct xl_softc *);
244 static void xl_setmulti_hash (struct xl_softc *);
245 static void xl_reset (struct xl_softc *);
246 static int xl_list_rx_init (struct xl_softc *);
247 static int xl_list_tx_init (struct xl_softc *);
248 static int xl_list_tx_init_90xB (struct xl_softc *);
249 static void xl_wait (struct xl_softc *);
250 static void xl_mediacheck (struct xl_softc *);
251 static void xl_choose_xcvr (struct xl_softc *, int);
252 static void xl_dma_map_addr (void *, bus_dma_segment_t *, int, int);
253 static void xl_dma_map_rxbuf (void *, bus_dma_segment_t *, int, bus_size_t,
255 static void xl_dma_map_txbuf (void *, bus_dma_segment_t *, int, bus_size_t,
258 static void xl_testpacket (struct xl_softc *);
261 static int xl_miibus_readreg (device_t, int, int);
262 static int xl_miibus_writereg (device_t, int, int, int);
263 static void xl_miibus_statchg (device_t);
264 static void xl_miibus_mediainit (device_t);
266 static device_method_t xl_methods[] = {
267 /* Device interface */
268 DEVMETHOD(device_probe, xl_probe),
269 DEVMETHOD(device_attach, xl_attach),
270 DEVMETHOD(device_detach, xl_detach),
271 DEVMETHOD(device_shutdown, xl_shutdown),
272 DEVMETHOD(device_suspend, xl_suspend),
273 DEVMETHOD(device_resume, xl_resume),
276 DEVMETHOD(bus_print_child, bus_generic_print_child),
277 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
280 DEVMETHOD(miibus_readreg, xl_miibus_readreg),
281 DEVMETHOD(miibus_writereg, xl_miibus_writereg),
282 DEVMETHOD(miibus_statchg, xl_miibus_statchg),
283 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit),
288 static driver_t xl_driver = {
291 sizeof(struct xl_softc)
294 static devclass_t xl_devclass;
296 DECLARE_DUMMY_MODULE(if_xl);
297 MODULE_DEPEND(if_xl, miibus, 1, 1, 1);
298 DRIVER_MODULE(if_xl, pci, xl_driver, xl_devclass, 0, 0);
299 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0);
302 xl_dma_map_addr(arg, segs, nseg, error)
304 bus_dma_segment_t *segs;
310 *paddr = segs->ds_addr;
314 xl_dma_map_rxbuf(arg, segs, nseg, mapsize, error)
316 bus_dma_segment_t *segs;
325 KASSERT(nseg == 1, ("xl_dma_map_rxbuf: too many DMA segments"));
327 *paddr = segs->ds_addr;
331 xl_dma_map_txbuf(arg, segs, nseg, mapsize, error)
333 bus_dma_segment_t *segs;
344 KASSERT(nseg <= XL_MAXFRAGS, ("too many DMA segments"));
348 for (i = 0; i < nseg; i++) {
349 KASSERT(segs[i].ds_len <= MCLBYTES, ("segment size too large"));
350 l->xl_frag[i].xl_addr = htole32(segs[i].ds_addr);
351 l->xl_frag[i].xl_len = htole32(segs[i].ds_len);
352 total_len += segs[i].ds_len;
354 l->xl_frag[nseg - 1].xl_len = htole32(segs[nseg - 1].ds_len |
356 l->xl_status = htole32(total_len);
361 * Murphy's law says that it's possible the chip can wedge and
362 * the 'command in progress' bit may never clear. Hence, we wait
363 * only a finite amount of time to avoid getting caught in an
364 * infinite loop. Normally this delay routine would be a macro,
365 * but it isn't called during normal operation so we can afford
366 * to make it a function.
374 for (i = 0; i < XL_TIMEOUT; i++) {
375 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
380 printf("xl%d: command never completed!\n", sc->xl_unit);
386 * MII access routines are provided for adapters with external
387 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
388 * autoneg logic that's faked up to look like a PHY (3c905B-TX).
389 * Note: if you don't perform the MDIO operations just right,
390 * it's possible to end up with code that works correctly with
391 * some chips/CPUs/processor speeds/bus speeds/etc but not
395 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
396 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
399 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
400 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
403 * Sync the PHYs by setting data bit and strobing the clock 32 times.
412 MII_SET(XL_MII_DIR|XL_MII_DATA);
414 for (i = 0; i < 32; i++) {
416 MII_SET(XL_MII_DATA);
417 MII_SET(XL_MII_DATA);
419 MII_SET(XL_MII_DATA);
420 MII_SET(XL_MII_DATA);
427 * Clock a series of bits through the MII.
430 xl_mii_send(sc, bits, cnt)
440 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
442 MII_SET(XL_MII_DATA);
444 MII_CLR(XL_MII_DATA);
452 * Read an PHY register through the MII.
455 xl_mii_readreg(sc, frame)
457 struct xl_mii_frame *frame;
465 * Set up frame for RX.
467 frame->mii_stdelim = XL_MII_STARTDELIM;
468 frame->mii_opcode = XL_MII_READOP;
469 frame->mii_turnaround = 0;
473 * Select register window 4.
478 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
487 * Send command/address info.
489 xl_mii_send(sc, frame->mii_stdelim, 2);
490 xl_mii_send(sc, frame->mii_opcode, 2);
491 xl_mii_send(sc, frame->mii_phyaddr, 5);
492 xl_mii_send(sc, frame->mii_regaddr, 5);
495 MII_CLR((XL_MII_CLK|XL_MII_DATA));
503 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
507 * Now try reading data bits. If the ack failed, we still
508 * need to clock through 16 cycles to keep the PHY(s) in sync.
511 for(i = 0; i < 16; i++) {
518 for (i = 0x8000; i; i >>= 1) {
521 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
522 frame->mii_data |= i;
540 * Write to a PHY register through the MII.
543 xl_mii_writereg(sc, frame)
545 struct xl_mii_frame *frame;
553 * Set up frame for TX.
556 frame->mii_stdelim = XL_MII_STARTDELIM;
557 frame->mii_opcode = XL_MII_WRITEOP;
558 frame->mii_turnaround = XL_MII_TURNAROUND;
561 * Select the window 4.
566 * Turn on data output.
572 xl_mii_send(sc, frame->mii_stdelim, 2);
573 xl_mii_send(sc, frame->mii_opcode, 2);
574 xl_mii_send(sc, frame->mii_phyaddr, 5);
575 xl_mii_send(sc, frame->mii_regaddr, 5);
576 xl_mii_send(sc, frame->mii_turnaround, 2);
577 xl_mii_send(sc, frame->mii_data, 16);
594 xl_miibus_readreg(dev, phy, reg)
599 struct xl_mii_frame frame;
601 sc = device_get_softc(dev);
604 * Pretend that PHYs are only available at MII address 24.
605 * This is to guard against problems with certain 3Com ASIC
606 * revisions that incorrectly map the internal transceiver
607 * control registers at all MII addresses. This can cause
608 * the miibus code to attach the same PHY several times over.
610 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
613 bzero((char *)&frame, sizeof(frame));
615 frame.mii_phyaddr = phy;
616 frame.mii_regaddr = reg;
617 xl_mii_readreg(sc, &frame);
619 return(frame.mii_data);
623 xl_miibus_writereg(dev, phy, reg, data)
628 struct xl_mii_frame frame;
630 sc = device_get_softc(dev);
632 if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24)
635 bzero((char *)&frame, sizeof(frame));
637 frame.mii_phyaddr = phy;
638 frame.mii_regaddr = reg;
639 frame.mii_data = data;
641 xl_mii_writereg(sc, &frame);
647 xl_miibus_statchg(dev)
651 struct mii_data *mii;
654 sc = device_get_softc(dev);
655 mii = device_get_softc(sc->xl_miibus);
659 /* Set ASIC's duplex mode to match the PHY. */
661 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
662 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
664 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
665 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
671 * Special support for the 3c905B-COMBO. This card has 10/100 support
672 * plus BNC and AUI ports. This means we will have both an miibus attached
673 * plus some non-MII media settings. In order to allow this, we have to
674 * add the extra media to the miibus's ifmedia struct, but we can't do
675 * that during xl_attach() because the miibus hasn't been attached yet.
676 * So instead, we wait until the miibus probe/attach is done, at which
677 * point we will get a callback telling is that it's safe to add our
681 xl_miibus_mediainit(dev)
685 struct mii_data *mii;
688 sc = device_get_softc(dev);
689 mii = device_get_softc(sc->xl_miibus);
690 ifm = &mii->mii_media;
692 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
694 * Check for a 10baseFL board in disguise.
696 if (sc->xl_type == XL_TYPE_905B &&
697 sc->xl_media == XL_MEDIAOPT_10FL) {
699 printf("xl%d: found 10baseFL\n", sc->xl_unit);
700 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
701 ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX, 0, NULL);
702 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
704 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
707 printf("xl%d: found AUI\n", sc->xl_unit);
708 ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
712 if (sc->xl_media & XL_MEDIAOPT_BNC) {
714 printf("xl%d: found BNC\n", sc->xl_unit);
715 ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
722 * The EEPROM is slow: give it time to come ready after issuing
731 for (i = 0; i < 100; i++) {
732 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
739 printf("xl%d: eeprom failed to come ready\n", sc->xl_unit);
747 * Read a sequence of words from the EEPROM. Note that ethernet address
748 * data is stored in the EEPROM in network byte order.
751 xl_read_eeprom(sc, dest, off, cnt, swap)
759 u_int16_t word = 0, *ptr;
760 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
761 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
763 * It's easy to accidentally overwrite the rom content!
764 * Note: the 3c575 uses 8bit EEPROM offsets.
768 if (xl_eeprom_wait(sc))
771 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
774 for (i = 0; i < cnt; i++) {
775 if (sc->xl_flags & XL_FLAG_8BITROM)
776 CSR_WRITE_2(sc, XL_W0_EE_CMD,
777 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
779 CSR_WRITE_2(sc, XL_W0_EE_CMD,
780 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
781 err = xl_eeprom_wait(sc);
784 word = CSR_READ_2(sc, XL_W0_EE_DATA);
785 ptr = (u_int16_t *)(dest + (i * 2));
796 * This routine is taken from the 3Com Etherlink XL manual,
797 * page 10-7. It calculates a CRC of the supplied multicast
798 * group address and returns the lower 8 bits, which are used
799 * as the multicast filter position.
800 * Note: the 3c905B currently only supports a 64-bit hash table,
801 * which means we really only need 6 bits, but the manual indicates
802 * that future chip revisions will have a 256-bit hash table,
803 * hence the routine is set up to calculate 8 bits of position
804 * info in case we need it some day.
805 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have a
806 * 256 bit hash table. This means we have to use all 8 bits regardless.
807 * On older cards, the upper 2 bits will be ignored. Grrrr....
809 static u_int8_t xl_calchash(addr)
812 u_int32_t crc, carry;
816 /* Compute CRC for the address value. */
817 crc = 0xFFFFFFFF; /* initial value */
819 for (i = 0; i < 6; i++) {
821 for (j = 0; j < 8; j++) {
822 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
826 crc = (crc ^ 0x04c11db6) | carry;
830 /* return the filter bit position */
831 return(crc & 0x000000FF);
835 * NICs older than the 3c905B have only one multicast option, which
836 * is to enable reception of all multicast frames.
843 struct ifmultiaddr *ifma;
847 ifp = &sc->arpcom.ac_if;
850 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
852 if (ifp->if_flags & IFF_ALLMULTI) {
853 rxfilt |= XL_RXFILTER_ALLMULTI;
854 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
858 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
859 ifma = ifma->ifma_link.le_next)
863 rxfilt |= XL_RXFILTER_ALLMULTI;
865 rxfilt &= ~XL_RXFILTER_ALLMULTI;
867 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
873 * 3c905B adapters have a hash filter that we can program.
881 struct ifmultiaddr *ifma;
885 ifp = &sc->arpcom.ac_if;
888 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
890 if (ifp->if_flags & IFF_ALLMULTI) {
891 rxfilt |= XL_RXFILTER_ALLMULTI;
892 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
895 rxfilt &= ~XL_RXFILTER_ALLMULTI;
898 /* first, zot all the existing hash bits */
899 for (i = 0; i < XL_HASHFILT_SIZE; i++)
900 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
902 /* now program new ones */
903 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
904 ifma = ifma->ifma_link.le_next) {
905 if (ifma->ifma_addr->sa_family != AF_LINK)
907 h = xl_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
908 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
913 rxfilt |= XL_RXFILTER_MULTIHASH;
915 rxfilt &= ~XL_RXFILTER_MULTIHASH;
917 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
930 ifp = &sc->arpcom.ac_if;
932 MGETHDR(m, MB_DONTWAIT, MT_DATA);
937 bcopy(&sc->arpcom.ac_enaddr,
938 mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
939 bcopy(&sc->arpcom.ac_enaddr,
940 mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
941 mtod(m, struct ether_header *)->ether_type = htons(3);
942 mtod(m, unsigned char *)[14] = 0;
943 mtod(m, unsigned char *)[15] = 0;
944 mtod(m, unsigned char *)[16] = 0xE3;
945 m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
946 IF_ENQUEUE(&ifp->if_snd, m);
960 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
961 icfg &= ~XL_ICFG_CONNECTOR_MASK;
962 if (sc->xl_media & XL_MEDIAOPT_MII ||
963 sc->xl_media & XL_MEDIAOPT_BT4)
964 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
965 if (sc->xl_media & XL_MEDIAOPT_BTX)
966 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
968 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
969 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
975 xl_setmode(sc, media)
982 printf("xl%d: selecting ", sc->xl_unit);
985 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
987 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
989 if (sc->xl_media & XL_MEDIAOPT_BT) {
990 if (IFM_SUBTYPE(media) == IFM_10_T) {
991 printf("10baseT transceiver, ");
992 sc->xl_xcvr = XL_XCVR_10BT;
993 icfg &= ~XL_ICFG_CONNECTOR_MASK;
994 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
995 mediastat |= XL_MEDIASTAT_LINKBEAT|
996 XL_MEDIASTAT_JABGUARD;
997 mediastat &= ~XL_MEDIASTAT_SQEENB;
1001 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1002 if (IFM_SUBTYPE(media) == IFM_100_FX) {
1003 printf("100baseFX port, ");
1004 sc->xl_xcvr = XL_XCVR_100BFX;
1005 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1006 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
1007 mediastat |= XL_MEDIASTAT_LINKBEAT;
1008 mediastat &= ~XL_MEDIASTAT_SQEENB;
1012 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1013 if (IFM_SUBTYPE(media) == IFM_10_5) {
1014 printf("AUI port, ");
1015 sc->xl_xcvr = XL_XCVR_AUI;
1016 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1017 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
1018 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1019 XL_MEDIASTAT_JABGUARD);
1020 mediastat |= ~XL_MEDIASTAT_SQEENB;
1022 if (IFM_SUBTYPE(media) == IFM_10_FL) {
1023 printf("10baseFL transceiver, ");
1024 sc->xl_xcvr = XL_XCVR_AUI;
1025 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1026 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
1027 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1028 XL_MEDIASTAT_JABGUARD);
1029 mediastat |= ~XL_MEDIASTAT_SQEENB;
1033 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1034 if (IFM_SUBTYPE(media) == IFM_10_2) {
1035 printf("BNC port, ");
1036 sc->xl_xcvr = XL_XCVR_COAX;
1037 icfg &= ~XL_ICFG_CONNECTOR_MASK;
1038 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
1039 mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
1040 XL_MEDIASTAT_JABGUARD|
1041 XL_MEDIASTAT_SQEENB);
1045 if ((media & IFM_GMASK) == IFM_FDX ||
1046 IFM_SUBTYPE(media) == IFM_100_FX) {
1047 printf("full duplex\n");
1049 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
1051 printf("half duplex\n");
1053 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
1054 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
1057 if (IFM_SUBTYPE(media) == IFM_10_2)
1058 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1060 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1061 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
1063 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
1072 struct xl_softc *sc;
1077 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
1078 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
1079 XL_RESETOPT_DISADVFD:0));
1082 * If we're using memory mapped register mode, pause briefly
1083 * after issuing the reset command before trying to access any
1084 * other registers. With my 3c575C cardbus card, failing to do
1085 * this results in the system locking up while trying to poll
1086 * the command busy bit in the status register.
1088 if (sc->xl_flags & XL_FLAG_USE_MMIO)
1091 for (i = 0; i < XL_TIMEOUT; i++) {
1093 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
1097 if (i == XL_TIMEOUT)
1098 printf("xl%d: reset didn't complete\n", sc->xl_unit);
1100 /* Reset TX and RX. */
1101 /* Note: the RX reset takes an absurd amount of time
1102 * on newer versions of the Tornado chips such as those
1103 * on the 3c905CX and newer 3c908C cards. We wait an
1104 * extra amount of time so that xl_wait() doesn't complain
1105 * and annoy the users.
1107 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1110 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1113 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
1114 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
1116 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
1117 XL_W2_RESET_OPTIONS)
1118 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
1119 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
1123 /* Wait a little while for the chip to get its brains in order. */
1129 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
1130 * IDs against our list and return a device name if we find a match.
1140 while(t->xl_name != NULL) {
1141 if ((pci_get_vendor(dev) == t->xl_vid) &&
1142 (pci_get_device(dev) == t->xl_did)) {
1143 device_set_desc(dev, t->xl_name);
1153 * This routine is a kludge to work around possible hardware faults
1154 * or manufacturing defects that can cause the media options register
1155 * (or reset options register, as it's called for the first generation
1156 * 3c90x adapters) to return an incorrect result. I have encountered
1157 * one Dell Latitude laptop docking station with an integrated 3c905-TX
1158 * which doesn't have any of the 'mediaopt' bits set. This screws up
1159 * the attach routine pretty badly because it doesn't know what media
1160 * to look for. If we find ourselves in this predicament, this routine
1161 * will try to guess the media options values and warn the user of a
1162 * possible manufacturing defect with his adapter/system/whatever.
1166 struct xl_softc *sc;
1170 * If some of the media options bits are set, assume they are
1171 * correct. If not, try to figure it out down below.
1172 * XXX I should check for 10baseFL, but I don't have an adapter
1175 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
1177 * Check the XCVR value. If it's not in the normal range
1178 * of values, we need to fake it up here.
1180 if (sc->xl_xcvr <= XL_XCVR_AUTO)
1183 printf("xl%d: bogus xcvr value "
1184 "in EEPROM (%x)\n", sc->xl_unit, sc->xl_xcvr);
1185 printf("xl%d: choosing new default based "
1186 "on card type\n", sc->xl_unit);
1189 if (sc->xl_type == XL_TYPE_905B &&
1190 sc->xl_media & XL_MEDIAOPT_10FL)
1192 printf("xl%d: WARNING: no media options bits set in "
1193 "the media options register!!\n", sc->xl_unit);
1194 printf("xl%d: this could be a manufacturing defect in "
1195 "your adapter or system\n", sc->xl_unit);
1196 printf("xl%d: attempting to guess media type; you "
1197 "should probably consult your vendor\n", sc->xl_unit);
1200 xl_choose_xcvr(sc, 1);
1206 xl_choose_xcvr(sc, verbose)
1207 struct xl_softc *sc;
1213 * Read the device ID from the EEPROM.
1214 * This is what's loaded into the PCI device ID register, so it has
1215 * to be correct otherwise we wouldn't have gotten this far.
1217 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
1220 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */
1221 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */
1222 sc->xl_media = XL_MEDIAOPT_BT;
1223 sc->xl_xcvr = XL_XCVR_10BT;
1225 printf("xl%d: guessing 10BaseT "
1226 "transceiver\n", sc->xl_unit);
1228 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */
1229 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */
1230 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1231 sc->xl_xcvr = XL_XCVR_10BT;
1233 printf("xl%d: guessing COMBO "
1234 "(AUI/BNC/TP)\n", sc->xl_unit);
1236 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */
1237 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
1238 sc->xl_xcvr = XL_XCVR_10BT;
1240 printf("xl%d: guessing TPC (BNC/TP)\n", sc->xl_unit);
1242 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */
1243 sc->xl_media = XL_MEDIAOPT_10FL;
1244 sc->xl_xcvr = XL_XCVR_AUI;
1246 printf("xl%d: guessing 10baseFL\n", sc->xl_unit);
1248 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */
1249 case TC_DEVICEID_HURRICANE_555: /* 3c555 */
1250 case TC_DEVICEID_HURRICANE_556: /* 3c556 */
1251 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */
1252 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */
1253 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */
1254 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */
1255 case TC_DEVICEID_HURRICANE_656: /* 3c656 */
1256 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */
1257 case TC_DEVICEID_TORNADO_656C: /* 3c656C */
1258 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
1259 sc->xl_media = XL_MEDIAOPT_MII;
1260 sc->xl_xcvr = XL_XCVR_MII;
1262 printf("xl%d: guessing MII\n", sc->xl_unit);
1264 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */
1265 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */
1266 sc->xl_media = XL_MEDIAOPT_BT4;
1267 sc->xl_xcvr = XL_XCVR_MII;
1269 printf("xl%d: guessing 100BaseT4/MII\n", sc->xl_unit);
1271 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */
1272 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1273 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
1274 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */
1275 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */
1276 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */
1277 sc->xl_media = XL_MEDIAOPT_BTX;
1278 sc->xl_xcvr = XL_XCVR_AUTO;
1280 printf("xl%d: guessing 10/100 internal\n", sc->xl_unit);
1282 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */
1283 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1284 sc->xl_xcvr = XL_XCVR_AUTO;
1286 printf("xl%d: guessing 10/100 "
1287 "plus BNC/AUI\n", sc->xl_unit);
1290 printf("xl%d: unknown device ID: %x -- "
1291 "defaulting to 10baseT\n", sc->xl_unit, devid);
1292 sc->xl_media = XL_MEDIAOPT_BT;
1300 * Attach the interface. Allocate softc structures, do ifmedia
1301 * setup and ethernet/BPF attach.
1308 u_char eaddr[ETHER_ADDR_LEN];
1311 struct xl_softc *sc;
1313 int media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1314 int unit, error = 0, rid, res;
1318 sc = device_get_softc(dev);
1319 unit = device_get_unit(dev);
1321 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1324 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555)
1325 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1326 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556 ||
1327 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1328 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1329 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1330 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1331 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_555 ||
1332 pci_get_device(dev) == TC_DEVICEID_HURRICANE_556)
1333 sc->xl_flags |= XL_FLAG_8BITROM;
1334 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_556B)
1335 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1337 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575A ||
1338 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B ||
1339 pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C ||
1340 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B ||
1341 pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1342 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1343 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_8BITROM;
1344 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656)
1345 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1346 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575B)
1347 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1348 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_575C)
1349 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1350 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_656C)
1351 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1352 if (pci_get_device(dev) == TC_DEVICEID_HURRICANE_656 ||
1353 pci_get_device(dev) == TC_DEVICEID_HURRICANE_656B)
1354 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1355 XL_FLAG_INVERT_LED_PWR;
1356 if (pci_get_device(dev) == TC_DEVICEID_TORNADO_10_100BT_920B)
1357 sc->xl_flags |= XL_FLAG_PHYOK;
1358 #ifndef BURN_BRIDGES
1360 * If this is a 3c905B, we have to check one extra thing.
1361 * The 905B supports power management and may be placed in
1362 * a low-power mode (D3 mode), typically by certain operating
1363 * systems which shall not be named. The PCI BIOS is supposed
1364 * to reset the NIC and bring it out of low-power mode, but
1365 * some do not. Consequently, we have to see if this chip
1366 * supports power management, and if so, make sure it's not
1367 * in low-power mode. If power management is available, the
1368 * capid byte will be 0x01.
1370 * I _think_ that what actually happens is that the chip
1371 * loses its PCI configuration during the transition from
1372 * D3 back to D0; this means that it should be possible for
1373 * us to save the PCI iobase, membase and IRQ, put the chip
1374 * back in the D0 state, then restore the PCI config ourselves.
1377 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1378 u_int32_t iobase, membase, irq;
1380 /* Save important PCI config data. */
1381 iobase = pci_read_config(dev, XL_PCI_LOIO, 4);
1382 membase = pci_read_config(dev, XL_PCI_LOMEM, 4);
1383 irq = pci_read_config(dev, XL_PCI_INTLINE, 4);
1385 /* Reset the power state. */
1386 printf("xl%d: chip is in D%d power mode "
1387 "-- setting to D0\n", unit,
1388 pci_get_powerstate(dev));
1390 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1392 /* Restore PCI config data. */
1393 pci_write_config(dev, XL_PCI_LOIO, iobase, 4);
1394 pci_write_config(dev, XL_PCI_LOMEM, membase, 4);
1395 pci_write_config(dev, XL_PCI_INTLINE, irq, 4);
1399 * Map control/status registers.
1401 pci_enable_busmaster(dev);
1402 pci_enable_io(dev, SYS_RES_IOPORT);
1403 pci_enable_io(dev, SYS_RES_MEMORY);
1404 command = pci_read_config(dev, PCIR_COMMAND, 4);
1406 if (!(command & PCIM_CMD_PORTEN) && !(command & PCIM_CMD_MEMEN)) {
1407 printf("xl%d: failed to enable I/O ports and memory mappings!\n", unit);
1413 res = SYS_RES_MEMORY;
1416 sc->xl_res = bus_alloc_resource(dev, res, &rid,
1417 0, ~0, 1, RF_ACTIVE);
1420 if (sc->xl_res != NULL) {
1421 sc->xl_flags |= XL_FLAG_USE_MMIO;
1423 printf("xl%d: using memory mapped I/O\n", unit);
1426 res = SYS_RES_IOPORT;
1427 sc->xl_res = bus_alloc_resource(dev, res, &rid,
1428 0, ~0, 1, RF_ACTIVE);
1429 if (sc->xl_res == NULL) {
1430 printf ("xl%d: couldn't map ports/memory\n", unit);
1435 printf("xl%d: using port I/O\n", unit);
1438 sc->xl_btag = rman_get_bustag(sc->xl_res);
1439 sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1441 if (sc->xl_flags & XL_FLAG_FUNCREG) {
1442 rid = XL_PCI_FUNCMEM;
1443 sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1444 0, ~0, 1, RF_ACTIVE);
1446 if (sc->xl_fres == NULL) {
1447 printf ("xl%d: couldn't map ports/memory\n", unit);
1452 sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1453 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1456 /* Allocate interrupt */
1458 sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1459 RF_SHAREABLE | RF_ACTIVE);
1460 if (sc->xl_irq == NULL) {
1461 printf("xl%d: couldn't map interrupt\n", unit);
1466 sc->xl_flags |= XL_FLAG_ATTACH_MAPPED;
1468 /* Reset the adapter. */
1472 * Get station address from the EEPROM.
1474 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1475 printf("xl%d: failed to read station address\n", sc->xl_unit);
1481 callout_init(&sc->xl_stat_timer);
1484 * Now allocate a tag for the DMA descriptor lists and a chunk
1485 * of DMA-able memory based on the tag. Also obtain the DMA
1486 * addresses of the RX and TX ring, which we'll need later.
1487 * All of our lists are allocated as a contiguous block
1490 error = bus_dma_tag_create(NULL, 8, 0,
1491 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1492 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0,
1493 &sc->xl_ldata.xl_rx_tag);
1495 printf("xl%d: failed to allocate rx dma tag\n", unit);
1499 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1500 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT,
1501 &sc->xl_ldata.xl_rx_dmamap);
1503 printf("xl%d: no memory for rx list buffers!\n", unit);
1504 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1505 sc->xl_ldata.xl_rx_tag = NULL;
1509 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1510 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1511 XL_RX_LIST_SZ, xl_dma_map_addr,
1512 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1514 printf("xl%d: cannot get dma address of the rx ring!\n", unit);
1515 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1516 sc->xl_ldata.xl_rx_dmamap);
1517 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1518 sc->xl_ldata.xl_rx_tag = NULL;
1522 error = bus_dma_tag_create(NULL, 8, 0,
1523 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1524 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0,
1525 &sc->xl_ldata.xl_tx_tag);
1527 printf("xl%d: failed to allocate tx dma tag\n", unit);
1531 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1532 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT,
1533 &sc->xl_ldata.xl_tx_dmamap);
1535 printf("xl%d: no memory for list buffers!\n", unit);
1536 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1537 sc->xl_ldata.xl_tx_tag = NULL;
1541 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1542 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1543 XL_TX_LIST_SZ, xl_dma_map_addr,
1544 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1546 printf("xl%d: cannot get dma address of the tx ring!\n", unit);
1547 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1548 sc->xl_ldata.xl_tx_dmamap);
1549 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1550 sc->xl_ldata.xl_tx_tag = NULL;
1555 * Allocate a DMA tag for the mapping of mbufs.
1557 error = bus_dma_tag_create(NULL, 1, 0,
1558 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1559 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0,
1562 printf("xl%d: failed to allocate mbuf dma tag\n", unit);
1566 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
1567 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
1569 /* We need a spare DMA map for the RX ring. */
1570 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1575 * Figure out the card type. 3c905B adapters have the
1576 * 'supportsNoTxLength' bit set in the capabilities
1577 * word in the EEPROM.
1578 * Note: my 3c575C cardbus card lies. It returns a value
1579 * of 0x1578 for its capabilities word, which is somewhat
1580 * nonsensical. Another way to distinguish a 3c90x chip
1581 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1582 * bit. This will only be set for 3c90x boomerage chips.
1584 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1585 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1586 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1587 sc->xl_type = XL_TYPE_905B;
1589 sc->xl_type = XL_TYPE_90X;
1591 ifp = &sc->arpcom.ac_if;
1593 if_initname(ifp, "xl", unit);
1594 ifp->if_mtu = ETHERMTU;
1595 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1596 ifp->if_ioctl = xl_ioctl;
1597 ifp->if_capabilities = 0;
1598 if (sc->xl_type == XL_TYPE_905B) {
1599 ifp->if_start = xl_start_90xB;
1600 ifp->if_capabilities |= IFCAP_HWCSUM;
1602 ifp->if_start = xl_start;
1604 ifp->if_watchdog = xl_watchdog;
1605 ifp->if_init = xl_init;
1606 ifp->if_baudrate = 10000000;
1607 ifq_set_maxlen(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1608 ifq_set_ready(&ifp->if_snd);
1610 * NOTE: features disabled by default. This seems to corrupt
1611 * tx packet data one out of a million packets or so and then
1612 * generates a good checksum so the receiver doesn't
1613 * know the packet is bad
1615 ifp->if_capenable = 0; /*ifp->if_capabilities;*/
1616 if (ifp->if_capenable & IFCAP_TXCSUM)
1617 ifp->if_hwassist = XL905B_CSUM_FEATURES;
1620 * Now we have to see what sort of media we have.
1621 * This includes probing for an MII interace and a
1625 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1627 printf("xl%d: media options word: %x\n", sc->xl_unit,
1630 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1631 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1632 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1633 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1637 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
1638 || sc->xl_media & XL_MEDIAOPT_BT4) {
1640 printf("xl%d: found MII/AUTO\n", sc->xl_unit);
1642 if (mii_phy_probe(dev, &sc->xl_miibus,
1643 xl_ifmedia_upd, xl_ifmedia_sts)) {
1644 printf("xl%d: no PHY found!\n", sc->xl_unit);
1653 * Sanity check. If the user has selected "auto" and this isn't
1654 * a 10/100 card of some kind, we need to force the transceiver
1655 * type to something sane.
1657 if (sc->xl_xcvr == XL_XCVR_AUTO)
1658 xl_choose_xcvr(sc, bootverbose);
1663 if (sc->xl_media & XL_MEDIAOPT_BT) {
1665 printf("xl%d: found 10baseT\n", sc->xl_unit);
1666 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1667 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1668 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1669 ifmedia_add(&sc->ifmedia,
1670 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1673 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1675 * Check for a 10baseFL board in disguise.
1677 if (sc->xl_type == XL_TYPE_905B &&
1678 sc->xl_media == XL_MEDIAOPT_10FL) {
1680 printf("xl%d: found 10baseFL\n", sc->xl_unit);
1681 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1682 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1684 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1685 ifmedia_add(&sc->ifmedia,
1686 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1689 printf("xl%d: found AUI\n", sc->xl_unit);
1690 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1694 if (sc->xl_media & XL_MEDIAOPT_BNC) {
1696 printf("xl%d: found BNC\n", sc->xl_unit);
1697 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1700 if (sc->xl_media & XL_MEDIAOPT_BFX) {
1702 printf("xl%d: found 100baseFX\n", sc->xl_unit);
1703 ifp->if_baudrate = 100000000;
1704 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1707 /* Choose a default media. */
1708 switch(sc->xl_xcvr) {
1710 media = IFM_ETHER|IFM_10_T;
1711 xl_setmode(sc, media);
1714 if (sc->xl_type == XL_TYPE_905B &&
1715 sc->xl_media == XL_MEDIAOPT_10FL) {
1716 media = IFM_ETHER|IFM_10_FL;
1717 xl_setmode(sc, media);
1719 media = IFM_ETHER|IFM_10_5;
1720 xl_setmode(sc, media);
1724 media = IFM_ETHER|IFM_10_2;
1725 xl_setmode(sc, media);
1728 case XL_XCVR_100BTX:
1730 /* Chosen by miibus */
1732 case XL_XCVR_100BFX:
1733 media = IFM_ETHER|IFM_100_FX;
1736 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit,
1739 * This will probably be wrong, but it prevents
1740 * the ifmedia code from panicking.
1742 media = IFM_ETHER|IFM_10_T;
1746 if (sc->xl_miibus == NULL)
1747 ifmedia_set(&sc->ifmedia, media);
1751 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1753 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1757 * Call MI attach routine.
1759 ether_ifattach(ifp, eaddr);
1762 * Tell the upper layer(s) we support long frames.
1764 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1766 /* Hook interrupt last to avoid having to lock softc */
1767 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET,
1768 xl_intr, sc, &sc->xl_intrhand);
1770 printf("xl%d: couldn't set up irq\n", unit);
1771 ether_ifdetach(ifp);
1785 * Shutdown hardware and free up resources. This can be called any
1786 * time after the mutex has been initialized. It is called in both
1787 * the error case in attach and the normal detach case so it needs
1788 * to be careful about only freeing resources that have actually been
1795 struct xl_softc *sc;
1802 sc = device_get_softc(dev);
1803 ifp = &sc->arpcom.ac_if;
1805 if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1807 res = SYS_RES_MEMORY;
1810 res = SYS_RES_IOPORT;
1814 * Only try to communicate with the device if we were able to map
1815 * the ports. This flag is set before ether_ifattach() so it also
1816 * governs our call to ether_ifdetach().
1818 if (sc->xl_flags & XL_FLAG_ATTACH_MAPPED) {
1821 ether_ifdetach(ifp);
1825 device_delete_child(dev, sc->xl_miibus);
1826 bus_generic_detach(dev);
1827 ifmedia_removeall(&sc->ifmedia);
1829 if (sc->xl_intrhand)
1830 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1832 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1833 if (sc->xl_fres != NULL)
1834 bus_release_resource(dev, SYS_RES_MEMORY,
1835 XL_PCI_FUNCMEM, sc->xl_fres);
1837 bus_release_resource(dev, res, rid, sc->xl_res);
1840 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1841 bus_dma_tag_destroy(sc->xl_mtag);
1843 if (sc->xl_ldata.xl_rx_tag) {
1844 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1845 sc->xl_ldata.xl_rx_dmamap);
1846 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1847 sc->xl_ldata.xl_rx_dmamap);
1848 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1850 if (sc->xl_ldata.xl_tx_tag) {
1851 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1852 sc->xl_ldata.xl_tx_dmamap);
1853 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1854 sc->xl_ldata.xl_tx_dmamap);
1855 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1864 * Initialize the transmit descriptors.
1868 struct xl_softc *sc;
1870 struct xl_chain_data *cd;
1871 struct xl_list_data *ld;
1876 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1877 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1878 error = bus_dmamap_create(sc->xl_mtag, 0,
1879 &cd->xl_tx_chain[i].xl_map);
1882 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1883 i * sizeof(struct xl_list);
1884 if (i == (XL_TX_LIST_CNT - 1))
1885 cd->xl_tx_chain[i].xl_next = NULL;
1887 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1890 cd->xl_tx_free = &cd->xl_tx_chain[0];
1891 cd->xl_tx_tail = cd->xl_tx_head = NULL;
1893 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1898 * Initialize the transmit descriptors.
1901 xl_list_tx_init_90xB(sc)
1902 struct xl_softc *sc;
1904 struct xl_chain_data *cd;
1905 struct xl_list_data *ld;
1910 for (i = 0; i < XL_TX_LIST_CNT; i++) {
1911 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1912 error = bus_dmamap_create(sc->xl_mtag, 0,
1913 &cd->xl_tx_chain[i].xl_map);
1916 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1917 i * sizeof(struct xl_list);
1918 if (i == (XL_TX_LIST_CNT - 1))
1919 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1921 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1923 cd->xl_tx_chain[i].xl_prev =
1924 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1926 cd->xl_tx_chain[i].xl_prev =
1927 &cd->xl_tx_chain[i - 1];
1930 bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1931 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1937 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1942 * Initialize the RX descriptors and allocate mbufs for them. Note that
1943 * we arrange the descriptors in a closed ring, so that the last descriptor
1944 * points back to the first.
1948 struct xl_softc *sc;
1950 struct xl_chain_data *cd;
1951 struct xl_list_data *ld;
1958 for (i = 0; i < XL_RX_LIST_CNT; i++) {
1959 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1960 error = bus_dmamap_create(sc->xl_mtag, 0,
1961 &cd->xl_rx_chain[i].xl_map);
1964 error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1967 if (i == (XL_RX_LIST_CNT - 1))
1971 nextptr = ld->xl_rx_dmaaddr +
1972 next * sizeof(struct xl_list_onefrag);
1973 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1974 ld->xl_rx_list[i].xl_next = htole32(nextptr);
1977 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1978 cd->xl_rx_head = &cd->xl_rx_chain[0];
1984 * Initialize an RX descriptor and attach an MBUF cluster.
1985 * If we fail to do so, we need to leave the old mbuf and
1986 * the old DMA map untouched so that it can be reused.
1990 struct xl_softc *sc;
1991 struct xl_chain_onefrag *c;
1993 struct mbuf *m_new = NULL;
1998 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
2002 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
2004 /* Force longword alignment for packet payload. */
2005 m_adj(m_new, ETHER_ALIGN);
2007 error = bus_dmamap_load_mbuf(sc->xl_mtag, sc->xl_tmpmap, m_new,
2008 xl_dma_map_rxbuf, &baddr, BUS_DMA_NOWAIT);
2011 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error);
2015 bus_dmamap_unload(sc->xl_mtag, c->xl_map);
2017 c->xl_map = sc->xl_tmpmap;
2018 sc->xl_tmpmap = map;
2020 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
2021 c->xl_ptr->xl_status = 0;
2022 c->xl_ptr->xl_frag.xl_addr = htole32(baddr);
2023 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
2029 struct xl_softc *sc;
2031 struct xl_chain_onefrag *pos;
2034 pos = sc->xl_cdata.xl_rx_head;
2036 for (i = 0; i < XL_RX_LIST_CNT; i++) {
2037 if (pos->xl_ptr->xl_status)
2042 if (i == XL_RX_LIST_CNT)
2045 sc->xl_cdata.xl_rx_head = pos;
2051 * A frame has been uploaded: pass the resulting mbuf chain up to
2052 * the higher level protocols.
2056 struct xl_softc *sc;
2060 struct xl_chain_onefrag *cur_rx;
2064 ifp = &sc->arpcom.ac_if;
2068 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
2069 BUS_DMASYNC_POSTREAD);
2070 while((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
2071 cur_rx = sc->xl_cdata.xl_rx_head;
2072 sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
2073 total_len = rxstat & XL_RXSTAT_LENMASK;
2076 * Since we have told the chip to allow large frames,
2077 * we need to trap giant frame errors in software. We allow
2078 * a little more than the normal frame size to account for
2079 * frames with VLAN tags.
2081 if (total_len > XL_MAX_FRAMELEN)
2082 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
2085 * If an error occurs, update stats, clear the
2086 * status word and leave the mbuf cluster in place:
2087 * it should simply get re-used next time this descriptor
2088 * comes up in the ring.
2090 if (rxstat & XL_RXSTAT_UP_ERROR) {
2092 cur_rx->xl_ptr->xl_status = 0;
2093 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2094 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2099 * If the error bit was not set, the upload complete
2100 * bit should be set which means we have a valid packet.
2101 * If not, something truly strange has happened.
2103 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
2104 printf("xl%d: bad receive status -- "
2105 "packet dropped\n", sc->xl_unit);
2107 cur_rx->xl_ptr->xl_status = 0;
2108 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2109 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2113 /* No errors; receive the packet. */
2114 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
2115 BUS_DMASYNC_POSTREAD);
2116 m = cur_rx->xl_mbuf;
2119 * Try to conjure up a new mbuf cluster. If that
2120 * fails, it means we have an out of memory condition and
2121 * should leave the buffer in place and continue. This will
2122 * result in a lost packet, but there's little else we
2123 * can do in this situation.
2125 if (xl_newbuf(sc, cur_rx)) {
2127 cur_rx->xl_ptr->xl_status = 0;
2128 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2129 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2132 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
2133 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
2136 m->m_pkthdr.rcvif = ifp;
2137 m->m_pkthdr.len = m->m_len = total_len;
2139 if (ifp->if_capenable & IFCAP_RXCSUM) {
2140 /* Do IP checksum checking. */
2141 if (rxstat & XL_RXSTAT_IPCKOK)
2142 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2143 if (!(rxstat & XL_RXSTAT_IPCKERR))
2144 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2145 if ((rxstat & XL_RXSTAT_TCPCOK &&
2146 !(rxstat & XL_RXSTAT_TCPCKERR)) ||
2147 (rxstat & XL_RXSTAT_UDPCKOK &&
2148 !(rxstat & XL_RXSTAT_UDPCKERR))) {
2149 m->m_pkthdr.csum_flags |=
2150 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2151 m->m_pkthdr.csum_data = 0xffff;
2155 (*ifp->if_input)(ifp, m);
2159 * Handle the 'end of channel' condition. When the upload
2160 * engine hits the end of the RX ring, it will stall. This
2161 * is our cue to flush the RX ring, reload the uplist pointer
2162 * register and unstall the engine.
2163 * XXX This is actually a little goofy. With the ThunderLAN
2164 * chip, you get an interrupt when the receiver hits the end
2165 * of the receive ring, which tells you exactly when you
2166 * you need to reload the ring pointer. Here we have to
2167 * fake it. I'm mad at myself for not being clever enough
2168 * to avoid the use of a goto here.
2170 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
2171 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
2172 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2174 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2175 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
2176 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2184 * A frame was downloaded to the chip. It's safe for us to clean up
2189 struct xl_softc *sc;
2191 struct xl_chain *cur_tx;
2194 ifp = &sc->arpcom.ac_if;
2196 /* Clear the timeout timer. */
2200 * Go through our tx list and free mbufs for those
2201 * frames that have been uploaded. Note: the 3c905B
2202 * sets a special bit in the status word to let us
2203 * know that a frame has been downloaded, but the
2204 * original 3c900/3c905 adapters don't do that.
2205 * Consequently, we have to use a different test if
2206 * xl_type != XL_TYPE_905B.
2208 while(sc->xl_cdata.xl_tx_head != NULL) {
2209 cur_tx = sc->xl_cdata.xl_tx_head;
2211 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2214 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2215 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2216 BUS_DMASYNC_POSTWRITE);
2217 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2218 m_freem(cur_tx->xl_mbuf);
2219 cur_tx->xl_mbuf = NULL;
2222 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2223 sc->xl_cdata.xl_tx_free = cur_tx;
2226 if (sc->xl_cdata.xl_tx_head == NULL) {
2227 ifp->if_flags &= ~IFF_OACTIVE;
2228 sc->xl_cdata.xl_tx_tail = NULL;
2230 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2231 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2232 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2233 sc->xl_cdata.xl_tx_head->xl_phys);
2234 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2243 struct xl_softc *sc;
2245 struct xl_chain *cur_tx = NULL;
2249 ifp = &sc->arpcom.ac_if;
2251 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2252 BUS_DMASYNC_POSTREAD);
2253 idx = sc->xl_cdata.xl_tx_cons;
2254 while(idx != sc->xl_cdata.xl_tx_prod) {
2256 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2258 if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2259 XL_TXSTAT_DL_COMPLETE))
2262 if (cur_tx->xl_mbuf != NULL) {
2263 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2264 BUS_DMASYNC_POSTWRITE);
2265 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2266 m_freem(cur_tx->xl_mbuf);
2267 cur_tx->xl_mbuf = NULL;
2272 sc->xl_cdata.xl_tx_cnt--;
2273 XL_INC(idx, XL_TX_LIST_CNT);
2277 sc->xl_cdata.xl_tx_cons = idx;
2280 ifp->if_flags &= ~IFF_OACTIVE;
2286 * TX 'end of channel' interrupt handler. Actually, we should
2287 * only get a 'TX complete' interrupt if there's a transmit error,
2288 * so this is really TX error handler.
2292 struct xl_softc *sc;
2296 while((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2297 if (txstat & XL_TXSTATUS_UNDERRUN ||
2298 txstat & XL_TXSTATUS_JABBER ||
2299 txstat & XL_TXSTATUS_RECLAIM) {
2300 printf("xl%d: transmission error: %x\n",
2301 sc->xl_unit, txstat);
2302 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2304 if (sc->xl_type == XL_TYPE_905B) {
2305 if (sc->xl_cdata.xl_tx_cnt) {
2308 i = sc->xl_cdata.xl_tx_cons;
2309 c = &sc->xl_cdata.xl_tx_chain[i];
2310 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2312 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2315 if (sc->xl_cdata.xl_tx_head != NULL)
2316 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2317 sc->xl_cdata.xl_tx_head->xl_phys);
2320 * Remember to set this for the
2321 * first generation 3c90X chips.
2323 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2324 if (txstat & XL_TXSTATUS_UNDERRUN &&
2325 sc->xl_tx_thresh < XL_PACKET_SIZE) {
2326 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2327 printf("xl%d: tx underrun, increasing tx start"
2328 " threshold to %d bytes\n", sc->xl_unit,
2331 CSR_WRITE_2(sc, XL_COMMAND,
2332 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2333 if (sc->xl_type == XL_TYPE_905B) {
2334 CSR_WRITE_2(sc, XL_COMMAND,
2335 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2337 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2338 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2340 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2341 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2344 * Write an arbitrary byte to the TX_STATUS register
2345 * to clear this interrupt/error and advance to the next.
2347 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2357 struct xl_softc *sc;
2362 ifp = &sc->arpcom.ac_if;
2364 while((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
2366 CSR_WRITE_2(sc, XL_COMMAND,
2367 XL_CMD_INTR_ACK|(status & XL_INTRS));
2369 if (status & XL_STAT_UP_COMPLETE) {
2372 curpkts = ifp->if_ipackets;
2374 if (curpkts == ifp->if_ipackets) {
2375 while (xl_rx_resync(sc))
2380 if (status & XL_STAT_DOWN_COMPLETE) {
2381 if (sc->xl_type == XL_TYPE_905B)
2387 if (status & XL_STAT_TX_COMPLETE) {
2392 if (status & XL_STAT_ADFAIL) {
2397 if (status & XL_STAT_STATSOFLOW) {
2398 sc->xl_stats_no_timeout = 1;
2399 xl_stats_update(sc);
2400 sc->xl_stats_no_timeout = 0;
2404 if (!ifq_is_empty(&ifp->if_snd))
2405 (*ifp->if_start)(ifp);
2411 xl_stats_update(xsc)
2414 struct xl_softc *sc;
2416 struct xl_stats xl_stats;
2419 struct mii_data *mii = NULL;
2421 bzero((char *)&xl_stats, sizeof(struct xl_stats));
2424 ifp = &sc->arpcom.ac_if;
2425 if (sc->xl_miibus != NULL)
2426 mii = device_get_softc(sc->xl_miibus);
2428 p = (u_int8_t *)&xl_stats;
2430 /* Read all the stats registers. */
2433 for (i = 0; i < 16; i++)
2434 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2436 ifp->if_ierrors += xl_stats.xl_rx_overrun;
2438 ifp->if_collisions += xl_stats.xl_tx_multi_collision +
2439 xl_stats.xl_tx_single_collision +
2440 xl_stats.xl_tx_late_collision;
2443 * Boomerang and cyclone chips have an extra stats counter
2444 * in window 4 (BadSSD). We have to read this too in order
2445 * to clear out all the stats registers and avoid a statsoflow
2449 CSR_READ_1(sc, XL_W4_BADSSD);
2451 if ((mii != NULL) && (!sc->xl_stats_no_timeout))
2456 if (!sc->xl_stats_no_timeout)
2457 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2463 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2464 * pointers to the fragment pointers.
2467 xl_encap(sc, c, m_head)
2468 struct xl_softc *sc;
2470 struct mbuf *m_head;
2476 ifp = &sc->arpcom.ac_if;
2479 * Start packing the mbufs in this chain into
2480 * the fragment pointers. Stop when we run out
2481 * of fragments or hit the end of the mbuf chain.
2483 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map, m_head,
2484 xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2486 if (error && error != EFBIG) {
2488 printf("xl%d: can't map mbuf (error %d)\n", sc->xl_unit, error);
2493 * Handle special case: we used up all 63 fragments,
2494 * but we have more mbufs left in the chain. Copy the
2495 * data into an mbuf cluster. Note that we don't
2496 * bother clearing the values in the other fragment
2497 * pointers/counters; it wouldn't gain us anything,
2498 * and would waste cycles.
2503 m_new = m_defrag(m_head, MB_DONTWAIT);
2504 if (m_new == NULL) {
2511 error = bus_dmamap_load_mbuf(sc->xl_mtag, c->xl_map,
2512 m_head, xl_dma_map_txbuf, c->xl_ptr, BUS_DMA_NOWAIT);
2515 printf("xl%d: can't map mbuf (error %d)\n",
2516 sc->xl_unit, error);
2521 if (sc->xl_type == XL_TYPE_905B) {
2522 status = XL_TXSTAT_RND_DEFEAT;
2524 if (m_head->m_pkthdr.csum_flags) {
2525 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2526 status |= XL_TXSTAT_IPCKSUM;
2527 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
2528 status |= XL_TXSTAT_TCPCKSUM;
2529 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
2530 status |= XL_TXSTAT_UDPCKSUM;
2532 c->xl_ptr->xl_status = htole32(status);
2535 c->xl_mbuf = m_head;
2536 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2541 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2542 * to the mbuf data regions directly in the transmit lists. We also save a
2543 * copy of the pointers since the transmit list fragment pointers are
2544 * physical addresses.
2550 struct xl_softc *sc;
2551 struct mbuf *m_head = NULL;
2552 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2553 struct xl_chain *prev_tx;
2559 * Check for an available queue slot. If there are none,
2562 if (sc->xl_cdata.xl_tx_free == NULL) {
2565 if (sc->xl_cdata.xl_tx_free == NULL) {
2566 ifp->if_flags |= IFF_OACTIVE;
2571 start_tx = sc->xl_cdata.xl_tx_free;
2573 while(sc->xl_cdata.xl_tx_free != NULL) {
2574 m_head = ifq_dequeue(&ifp->if_snd);
2578 /* Pick a descriptor off the free list. */
2580 cur_tx = sc->xl_cdata.xl_tx_free;
2582 /* Pack the data into the descriptor. */
2583 error = xl_encap(sc, cur_tx, m_head);
2589 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2590 cur_tx->xl_next = NULL;
2592 /* Chain it together. */
2594 prev->xl_next = cur_tx;
2595 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2599 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2603 * If there are no packets queued, bail.
2605 if (cur_tx == NULL) {
2610 * Place the request for the upload interrupt
2611 * in the last descriptor in the chain. This way, if
2612 * we're chaining several packets at once, we'll only
2613 * get an interupt once for the whole chain rather than
2614 * once for each packet.
2616 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2618 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2619 BUS_DMASYNC_PREWRITE);
2622 * Queue the packets. If the TX channel is clear, update
2623 * the downlist pointer register.
2625 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2628 if (sc->xl_cdata.xl_tx_head != NULL) {
2629 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2630 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2631 htole32(start_tx->xl_phys);
2632 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status;
2633 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status =
2634 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR);
2635 sc->xl_cdata.xl_tx_tail = cur_tx;
2637 sc->xl_cdata.xl_tx_head = start_tx;
2638 sc->xl_cdata.xl_tx_tail = cur_tx;
2640 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2641 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2643 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2648 * Set a timeout in case the chip goes out to lunch.
2653 * XXX Under certain conditions, usually on slower machines
2654 * where interrupts may be dropped, it's possible for the
2655 * adapter to chew up all the buffers in the receive ring
2656 * and stall, without us being able to do anything about it.
2657 * To guard against this, we need to make a pass over the
2658 * RX queue to make sure there aren't any packets pending.
2659 * Doing it here means we can flush the receive ring at the
2660 * same time the chip is DMAing the transmit descriptors we
2663 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2664 * nature of their chips in all their marketing literature;
2665 * we may as well take advantage of it. :)
2676 struct xl_softc *sc;
2677 struct mbuf *m_head = NULL;
2678 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
2679 struct xl_chain *prev_tx;
2684 if (ifp->if_flags & IFF_OACTIVE) {
2688 idx = sc->xl_cdata.xl_tx_prod;
2689 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2691 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
2693 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2694 ifp->if_flags |= IFF_OACTIVE;
2698 m_head = ifq_dequeue(&ifp->if_snd);
2703 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2705 /* Pack the data into the descriptor. */
2706 error = xl_encap(sc, cur_tx, m_head);
2712 /* Chain it together. */
2714 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2717 BPF_MTAP(ifp, cur_tx->xl_mbuf);
2719 XL_INC(idx, XL_TX_LIST_CNT);
2720 sc->xl_cdata.xl_tx_cnt++;
2724 * If there are no packets queued, bail.
2726 if (cur_tx == NULL) {
2731 * Place the request for the upload interrupt
2732 * in the last descriptor in the chain. This way, if
2733 * we're chaining several packets at once, we'll only
2734 * get an interupt once for the whole chain rather than
2735 * once for each packet.
2737 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) |
2739 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2740 BUS_DMASYNC_PREWRITE);
2742 /* Start transmission */
2743 sc->xl_cdata.xl_tx_prod = idx;
2744 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2747 * Set a timeout in case the chip goes out to lunch.
2758 struct xl_softc *sc = xsc;
2759 struct ifnet *ifp = &sc->arpcom.ac_if;
2761 u_int16_t rxfilt = 0;
2762 struct mii_data *mii = NULL;
2768 * Cancel pending I/O and free all RX/TX buffers.
2772 if (sc->xl_miibus == NULL) {
2773 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2776 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2780 if (sc->xl_miibus != NULL)
2781 mii = device_get_softc(sc->xl_miibus);
2783 /* Init our MAC address */
2785 for (i = 0; i < ETHER_ADDR_LEN; i++) {
2786 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2787 sc->arpcom.ac_enaddr[i]);
2790 /* Clear the station mask. */
2791 for (i = 0; i < 3; i++)
2792 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2794 /* Reset TX and RX. */
2795 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2797 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2800 /* Init circular RX list. */
2801 error = xl_list_rx_init(sc);
2803 printf("xl%d: initialization of the rx ring failed (%d)\n",
2804 sc->xl_unit, error);
2810 /* Init TX descriptors. */
2811 if (sc->xl_type == XL_TYPE_905B)
2812 error = xl_list_tx_init_90xB(sc);
2814 error = xl_list_tx_init(sc);
2816 printf("xl%d: initialization of the tx ring failed (%d)\n",
2817 sc->xl_unit, error);
2823 * Set the TX freethresh value.
2824 * Note that this has no effect on 3c905B "cyclone"
2825 * cards but is required for 3c900/3c905 "boomerang"
2826 * cards in order to enable the download engine.
2828 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2830 /* Set the TX start threshold for best performance. */
2831 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2832 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2835 * If this is a 3c905B, also set the tx reclaim threshold.
2836 * This helps cut down on the number of tx reclaim errors
2837 * that could happen on a busy network. The chip multiplies
2838 * the register value by 16 to obtain the actual threshold
2839 * in bytes, so we divide by 16 when setting the value here.
2840 * The existing threshold value can be examined by reading
2841 * the register at offset 9 in window 5.
2843 if (sc->xl_type == XL_TYPE_905B) {
2844 CSR_WRITE_2(sc, XL_COMMAND,
2845 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2848 /* Set RX filter bits. */
2850 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
2852 /* Set the individual bit to receive frames for this host only. */
2853 rxfilt |= XL_RXFILTER_INDIVIDUAL;
2855 /* If we want promiscuous mode, set the allframes bit. */
2856 if (ifp->if_flags & IFF_PROMISC) {
2857 rxfilt |= XL_RXFILTER_ALLFRAMES;
2858 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2860 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
2861 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2865 * Set capture broadcast bit to capture broadcast frames.
2867 if (ifp->if_flags & IFF_BROADCAST) {
2868 rxfilt |= XL_RXFILTER_BROADCAST;
2869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2871 rxfilt &= ~XL_RXFILTER_BROADCAST;
2872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
2876 * Program the multicast filter, if necessary.
2878 if (sc->xl_type == XL_TYPE_905B)
2879 xl_setmulti_hash(sc);
2884 * Load the address of the RX list. We have to
2885 * stall the upload engine before we can manipulate
2886 * the uplist pointer register, then unstall it when
2887 * we're finished. We also have to wait for the
2888 * stall command to complete before proceeding.
2889 * Note that we have to do this after any RX resets
2890 * have completed since the uplist register is cleared
2893 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2895 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2896 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2900 if (sc->xl_type == XL_TYPE_905B) {
2901 /* Set polling interval */
2902 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2903 /* Load the address of the TX list */
2904 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2906 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2907 sc->xl_cdata.xl_tx_chain[0].xl_phys);
2908 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2913 * If the coax transceiver is on, make sure to enable
2914 * the DC-DC converter.
2917 if (sc->xl_xcvr == XL_XCVR_COAX)
2918 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2920 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2923 * increase packet size to allow reception of 802.1q or ISL packets.
2924 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2925 * control register. For 3c90xB/C chips, use the RX packet size
2929 if (sc->xl_type == XL_TYPE_905B)
2930 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2933 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2934 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2935 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2938 /* Clear out the stats counters. */
2939 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2940 sc->xl_stats_no_timeout = 1;
2941 xl_stats_update(sc);
2942 sc->xl_stats_no_timeout = 0;
2944 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2945 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2948 * Enable interrupts.
2950 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2951 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2952 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2953 if (sc->xl_flags & XL_FLAG_FUNCREG)
2954 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2956 /* Set the RX early threshold */
2957 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2958 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2960 /* Enable receiver and transmitter. */
2961 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2963 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2969 /* Select window 7 for normal operations. */
2972 ifp->if_flags |= IFF_RUNNING;
2973 ifp->if_flags &= ~IFF_OACTIVE;
2975 callout_reset(&sc->xl_stat_timer, hz, xl_stats_update, sc);
2983 * Set media options.
2989 struct xl_softc *sc;
2990 struct ifmedia *ifm = NULL;
2991 struct mii_data *mii = NULL;
2994 if (sc->xl_miibus != NULL)
2995 mii = device_get_softc(sc->xl_miibus);
2999 ifm = &mii->mii_media;
3001 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3006 xl_setmode(sc, ifm->ifm_media);
3013 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
3014 || sc->xl_media & XL_MEDIAOPT_BT4) {
3017 xl_setmode(sc, ifm->ifm_media);
3024 * Report current media status.
3027 xl_ifmedia_sts(ifp, ifmr)
3029 struct ifmediareq *ifmr;
3031 struct xl_softc *sc;
3033 struct mii_data *mii = NULL;
3036 if (sc->xl_miibus != NULL)
3037 mii = device_get_softc(sc->xl_miibus);
3040 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
3041 icfg >>= XL_ICFG_CONNECTOR_BITS;
3043 ifmr->ifm_active = IFM_ETHER;
3047 ifmr->ifm_active = IFM_ETHER|IFM_10_T;
3048 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3049 ifmr->ifm_active |= IFM_FDX;
3051 ifmr->ifm_active |= IFM_HDX;
3054 if (sc->xl_type == XL_TYPE_905B &&
3055 sc->xl_media == XL_MEDIAOPT_10FL) {
3056 ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
3057 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
3058 ifmr->ifm_active |= IFM_FDX;
3060 ifmr->ifm_active |= IFM_HDX;
3062 ifmr->ifm_active = IFM_ETHER|IFM_10_5;
3065 ifmr->ifm_active = IFM_ETHER|IFM_10_2;
3068 * XXX MII and BTX/AUTO should be separate cases.
3071 case XL_XCVR_100BTX:
3076 ifmr->ifm_active = mii->mii_media_active;
3077 ifmr->ifm_status = mii->mii_media_status;
3080 case XL_XCVR_100BFX:
3081 ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
3084 printf("xl%d: unknown XCVR type: %d\n", sc->xl_unit, icfg);
3092 xl_ioctl(ifp, command, data, cr)
3098 struct xl_softc *sc = ifp->if_softc;
3099 struct ifreq *ifr = (struct ifreq *) data;
3101 struct mii_data *mii = NULL;
3111 error = ether_ioctl(ifp, command, data);
3115 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
3116 if (ifp->if_flags & IFF_UP) {
3117 if (ifp->if_flags & IFF_RUNNING &&
3118 ifp->if_flags & IFF_PROMISC &&
3119 !(sc->xl_if_flags & IFF_PROMISC)) {
3120 rxfilt |= XL_RXFILTER_ALLFRAMES;
3121 CSR_WRITE_2(sc, XL_COMMAND,
3122 XL_CMD_RX_SET_FILT|rxfilt);
3124 } else if (ifp->if_flags & IFF_RUNNING &&
3125 !(ifp->if_flags & IFF_PROMISC) &&
3126 sc->xl_if_flags & IFF_PROMISC) {
3127 rxfilt &= ~XL_RXFILTER_ALLFRAMES;
3128 CSR_WRITE_2(sc, XL_COMMAND,
3129 XL_CMD_RX_SET_FILT|rxfilt);
3134 if (ifp->if_flags & IFF_RUNNING)
3137 sc->xl_if_flags = ifp->if_flags;
3142 if (sc->xl_type == XL_TYPE_905B)
3143 xl_setmulti_hash(sc);
3150 if (sc->xl_miibus != NULL)
3151 mii = device_get_softc(sc->xl_miibus);
3153 error = ifmedia_ioctl(ifp, ifr,
3154 &sc->ifmedia, command);
3156 error = ifmedia_ioctl(ifp, ifr,
3157 &mii->mii_media, command);
3160 ifp->if_capenable = ifr->ifr_reqcap;
3161 if (ifp->if_capenable & IFCAP_TXCSUM)
3162 ifp->if_hwassist = XL905B_CSUM_FEATURES;
3164 ifp->if_hwassist = 0;
3179 struct xl_softc *sc;
3180 u_int16_t status = 0;
3186 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3187 printf("xl%d: watchdog timeout\n", sc->xl_unit);
3189 if (status & XL_MEDIASTAT_CARRIER)
3190 printf("xl%d: no carrier - transceiver cable problem?\n",
3198 if (!ifq_is_empty(&ifp->if_snd))
3199 (*ifp->if_start)(ifp);
3205 * Stop the adapter and free any mbufs allocated to the
3210 struct xl_softc *sc;
3215 ifp = &sc->arpcom.ac_if;
3218 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3219 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3220 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3221 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3223 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3224 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3228 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3230 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3234 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3235 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3236 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3237 if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3239 /* Stop the stats updater. */
3240 callout_stop(&sc->xl_stat_timer);
3243 * Free data in the RX lists.
3245 for (i = 0; i < XL_RX_LIST_CNT; i++) {
3246 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3247 bus_dmamap_unload(sc->xl_mtag,
3248 sc->xl_cdata.xl_rx_chain[i].xl_map);
3249 bus_dmamap_destroy(sc->xl_mtag,
3250 sc->xl_cdata.xl_rx_chain[i].xl_map);
3251 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3252 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3255 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3257 * Free the TX list buffers.
3259 for (i = 0; i < XL_TX_LIST_CNT; i++) {
3260 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3261 bus_dmamap_unload(sc->xl_mtag,
3262 sc->xl_cdata.xl_tx_chain[i].xl_map);
3263 bus_dmamap_destroy(sc->xl_mtag,
3264 sc->xl_cdata.xl_tx_chain[i].xl_map);
3265 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3266 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3269 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3271 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3277 * Stop all chip I/O so that the kernel's probe routines don't
3278 * get confused by errant DMAs when rebooting.
3284 struct xl_softc *sc;
3286 sc = device_get_softc(dev);
3298 struct xl_softc *sc;
3303 sc = device_get_softc(dev);
3316 struct xl_softc *sc;
3322 sc = device_get_softc(dev);
3323 ifp = &sc->arpcom.ac_if;
3326 if (ifp->if_flags & IFF_UP)