3 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
5 * Copyright (c) 2001-2006, Intel Corporation
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived from
20 * this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
35 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
37 * This code is derived from software contributed to The DragonFly Project
38 * by Matthew Dillon <dillon@backplane.com>
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
50 * 3. Neither the name of The DragonFly Project nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific, prior written permission.
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
57 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
58 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
59 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
60 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
61 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
62 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
64 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 * $DragonFly: src/sys/dev/netif/em/if_em.c,v 1.69 2008/05/01 02:03:28 sephe Exp $
71 * SERIALIZATION API RULES:
73 * - If the driver uses the same serializer for the interrupt as for the
74 * ifnet, most of the serialization will be done automatically for the
77 * - ifmedia entry points will be serialized by the ifmedia code using the
80 * - if_* entry points except for if_input will be serialized by the IF
81 * and protocol layers.
83 * - The device driver must be sure to serialize access from timeout code
84 * installed by the device driver.
86 * - The device driver typically holds the serializer at the time it wishes
87 * to call if_input. If so, it should pass the serializer to if_input and
88 * note that the serializer might be dropped temporarily by if_input
89 * (e.g. in case it has to bridge the packet to another interface).
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
96 #include "opt_polling.h"
98 #include "opt_serializer.h"
100 #include <sys/param.h>
102 #include <sys/endian.h>
103 #include <sys/kernel.h>
105 #include <sys/malloc.h>
106 #include <sys/mbuf.h>
107 #include <sys/module.h>
108 #include <sys/rman.h>
109 #include <sys/serialize.h>
110 #include <sys/socket.h>
111 #include <sys/sockio.h>
112 #include <sys/sysctl.h>
115 #include <net/ethernet.h>
117 #include <net/if_arp.h>
118 #include <net/if_dl.h>
119 #include <net/if_media.h>
120 #include <net/if_types.h>
121 #include <net/ifq_var.h>
122 #include <net/vlan/if_vlan_var.h>
123 #include <net/vlan/if_vlan_ether.h>
126 #include <netinet/in.h>
127 #include <netinet/in_systm.h>
128 #include <netinet/in_var.h>
129 #include <netinet/ip.h>
130 #include <netinet/tcp.h>
131 #include <netinet/udp.h>
134 #include <dev/netif/em/if_em_hw.h>
135 #include <dev/netif/em/if_em.h>
137 #define EM_X60_WORKAROUND
139 /*********************************************************************
140 * Set this to one to display debug statistics
141 *********************************************************************/
142 int em_display_debug_stats = 0;
144 /*********************************************************************
146 *********************************************************************/
148 char em_driver_version[] = "6.2.9";
151 /*********************************************************************
152 * PCI Device ID Table
154 * Used by probe to select devices to load on
155 * Last field stores an index into em_strings
156 * Last entry must be all 0s
158 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
159 *********************************************************************/
161 static em_vendor_info_t em_vendor_info_array[] =
163 /* Intel(R) PRO/1000 Network Connection */
164 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0},
165 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
166 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0},
167 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
168 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0},
170 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0},
171 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0},
172 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
173 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
174 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0},
175 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0},
176 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
178 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0},
180 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
181 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
183 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
184 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
185 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
186 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
188 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
189 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
190 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
191 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
192 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
194 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
195 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
196 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
197 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
198 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
199 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
200 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0},
201 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
202 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,
203 PCI_ANY_ID, PCI_ANY_ID, 0},
205 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0},
206 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
207 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0},
209 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
210 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
211 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
212 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER,
213 PCI_ANY_ID, PCI_ANY_ID, 0},
214 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE,
215 PCI_ANY_ID, PCI_ANY_ID, 0},
217 { 0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER,
218 PCI_ANY_ID, PCI_ANY_ID, 0},
219 { 0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER,
220 PCI_ANY_ID, PCI_ANY_ID, 0},
221 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
222 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
223 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
224 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0},
226 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0},
227 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0},
228 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0},
230 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT,
231 PCI_ANY_ID, PCI_ANY_ID, 0},
232 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT,
233 PCI_ANY_ID, PCI_ANY_ID, 0},
234 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT,
235 PCI_ANY_ID, PCI_ANY_ID, 0},
236 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT,
237 PCI_ANY_ID, PCI_ANY_ID, 0},
239 { 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
240 { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
241 { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0},
242 { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0},
243 { 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0},
244 { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0},
245 { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0},
247 { 0x8086, E1000_DEV_ID_ICH9_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
248 { 0x8086, E1000_DEV_ID_ICH9_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0},
249 { 0x8086, E1000_DEV_ID_ICH9_IFE, PCI_ANY_ID, PCI_ANY_ID, 0},
250 { 0x8086, E1000_DEV_ID_ICH9_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0},
251 { 0x8086, E1000_DEV_ID_ICH9_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0},
253 { 0x8086, E1000_DEV_ID_82575EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
254 { 0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES,
255 PCI_ANY_ID, PCI_ANY_ID, 0},
256 { 0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER,
257 PCI_ANY_ID, PCI_ANY_ID, 0},
258 { 0x8086, 0x101A, PCI_ANY_ID, PCI_ANY_ID, 0},
259 { 0x8086, 0x1014, PCI_ANY_ID, PCI_ANY_ID, 0},
260 /* required last entry */
264 /*********************************************************************
265 * Table of branding strings for all supported NICs.
266 *********************************************************************/
268 static const char *em_strings[] = {
269 "Intel(R) PRO/1000 Network Connection"
272 /*********************************************************************
273 * Function prototypes
274 *********************************************************************/
275 static int em_probe(device_t);
276 static int em_attach(device_t);
277 static int em_detach(device_t);
278 static int em_shutdown(device_t);
279 static void em_intr(void *);
280 static int em_suspend(device_t);
281 static int em_resume(device_t);
282 static void em_start(struct ifnet *);
283 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
284 static void em_watchdog(struct ifnet *);
285 static void em_init(void *);
286 static void em_stop(void *);
287 static void em_media_status(struct ifnet *, struct ifmediareq *);
288 static int em_media_change(struct ifnet *);
289 static void em_identify_hardware(struct adapter *);
290 static int em_allocate_pci_resources(device_t);
291 static void em_free_pci_resources(device_t);
292 static void em_local_timer(void *);
293 static int em_hardware_init(struct adapter *);
294 static void em_setup_interface(device_t, struct adapter *);
295 static int em_setup_transmit_structures(struct adapter *);
296 static void em_initialize_transmit_unit(struct adapter *);
297 static int em_setup_receive_structures(struct adapter *);
298 static void em_initialize_receive_unit(struct adapter *);
299 static void em_enable_intr(struct adapter *);
300 static void em_disable_intr(struct adapter *);
301 static void em_free_transmit_structures(struct adapter *);
302 static void em_free_receive_structures(struct adapter *);
303 static void em_update_stats_counters(struct adapter *);
304 static void em_txeof(struct adapter *);
305 static int em_allocate_receive_structures(struct adapter *);
306 static void em_rxeof(struct adapter *, int);
307 static void em_receive_checksum(struct adapter *, struct em_rx_desc *,
309 static void em_transmit_checksum_setup(struct adapter *, struct mbuf *,
310 uint32_t *, uint32_t *);
311 static void em_set_promisc(struct adapter *);
312 static void em_disable_promisc(struct adapter *);
313 static void em_set_multi(struct adapter *);
314 static void em_print_hw_stats(struct adapter *);
315 static void em_update_link_status(struct adapter *);
316 static int em_get_buf(int i, struct adapter *, struct mbuf *, int how);
317 static void em_enable_vlans(struct adapter *);
318 static void em_disable_vlans(struct adapter *);
319 static int em_encap(struct adapter *, struct mbuf *);
320 static void em_smartspeed(struct adapter *);
321 static int em_82547_fifo_workaround(struct adapter *, int);
322 static void em_82547_update_fifo_head(struct adapter *, int);
323 static int em_82547_tx_fifo_reset(struct adapter *);
324 static void em_82547_move_tail(void *);
325 static void em_82547_move_tail_serialized(struct adapter *);
326 static int em_dma_malloc(struct adapter *, bus_size_t,
327 struct em_dma_alloc *);
328 static void em_dma_free(struct adapter *, struct em_dma_alloc *);
329 static void em_print_debug_info(struct adapter *);
330 static int em_is_valid_ether_addr(uint8_t *);
331 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
332 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
333 static uint32_t em_fill_descriptors(bus_addr_t address, uint32_t length,
334 PDESC_ARRAY desc_array);
335 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
336 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
337 static void em_add_int_delay_sysctl(struct adapter *, const char *,
339 struct em_int_delay_info *, int, int);
341 /*********************************************************************
342 * FreeBSD Device Interface Entry Points
343 *********************************************************************/
345 static device_method_t em_methods[] = {
346 /* Device interface */
347 DEVMETHOD(device_probe, em_probe),
348 DEVMETHOD(device_attach, em_attach),
349 DEVMETHOD(device_detach, em_detach),
350 DEVMETHOD(device_shutdown, em_shutdown),
351 DEVMETHOD(device_suspend, em_suspend),
352 DEVMETHOD(device_resume, em_resume),
356 static driver_t em_driver = {
357 "em", em_methods, sizeof(struct adapter),
360 static devclass_t em_devclass;
362 DECLARE_DUMMY_MODULE(if_em);
363 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, 0, 0);
365 /*********************************************************************
366 * Tunable default values.
367 *********************************************************************/
369 #define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
370 #define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
372 static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV);
373 static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR);
374 static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV);
375 static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV);
376 static int em_int_throttle_ceil = 10000;
377 static int em_rxd = EM_DEFAULT_RXD;
378 static int em_txd = EM_DEFAULT_TXD;
379 static int em_smart_pwr_down = FALSE;
381 TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt);
382 TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt);
383 TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt);
384 TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt);
385 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
386 TUNABLE_INT("hw.em.rxd", &em_rxd);
387 TUNABLE_INT("hw.em.txd", &em_txd);
388 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
391 * Kernel trace for characterization of operations
393 #if !defined(KTR_IF_EM)
394 #define KTR_IF_EM KTR_ALL
396 KTR_INFO_MASTER(if_em);
397 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin", 0);
398 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end", 0);
399 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet", 0);
400 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet", 0);
401 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean", 0);
402 #define logif(name) KTR_LOG(if_em_ ## name)
404 /*********************************************************************
405 * Device identification routine
407 * em_probe determines if the driver should be loaded on
408 * adapter based on PCI vendor/device id of the adapter.
410 * return 0 on success, positive on failure
411 *********************************************************************/
414 em_probe(device_t dev)
416 em_vendor_info_t *ent;
418 uint16_t pci_vendor_id = 0;
419 uint16_t pci_device_id = 0;
420 uint16_t pci_subvendor_id = 0;
421 uint16_t pci_subdevice_id = 0;
422 char adapter_name[60];
424 INIT_DEBUGOUT("em_probe: begin");
426 pci_vendor_id = pci_get_vendor(dev);
427 if (pci_vendor_id != EM_VENDOR_ID)
430 pci_device_id = pci_get_device(dev);
431 pci_subvendor_id = pci_get_subvendor(dev);
432 pci_subdevice_id = pci_get_subdevice(dev);
434 ent = em_vendor_info_array;
435 while (ent->vendor_id != 0) {
436 if ((pci_vendor_id == ent->vendor_id) &&
437 (pci_device_id == ent->device_id) &&
439 ((pci_subvendor_id == ent->subvendor_id) ||
440 (ent->subvendor_id == PCI_ANY_ID)) &&
442 ((pci_subdevice_id == ent->subdevice_id) ||
443 (ent->subdevice_id == PCI_ANY_ID))) {
444 ksnprintf(adapter_name, sizeof(adapter_name),
445 "%s, Version - %s", em_strings[ent->index],
447 device_set_desc_copy(dev, adapter_name);
448 device_set_async_attach(dev, TRUE);
457 /*********************************************************************
458 * Device initialization routine
460 * The attach entry point is called when the driver is being loaded.
461 * This routine identifies the type of hardware, allocates all resources
462 * and initializes the hardware.
464 * return 0 on success, positive on failure
465 *********************************************************************/
468 em_attach(device_t dev)
470 struct adapter *adapter;
474 INIT_DEBUGOUT("em_attach: begin");
476 adapter = device_get_softc(dev);
478 callout_init(&adapter->timer);
479 callout_init(&adapter->tx_fifo_timer);
482 adapter->osdep.dev = dev;
485 sysctl_ctx_init(&adapter->sysctl_ctx);
486 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx,
487 SYSCTL_STATIC_CHILDREN(_hw),
489 device_get_nameunit(dev),
493 if (adapter->sysctl_tree == NULL) {
494 device_printf(dev, "Unable to create sysctl tree\n");
498 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
499 SYSCTL_CHILDREN(adapter->sysctl_tree),
500 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW,
502 em_sysctl_debug_info, "I", "Debug Information");
504 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
505 SYSCTL_CHILDREN(adapter->sysctl_tree),
506 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW,
508 em_sysctl_stats, "I", "Statistics");
510 /* Determine hardware revision */
511 em_identify_hardware(adapter);
513 /* Set up some sysctls for the tunable interrupt delays */
514 em_add_int_delay_sysctl(adapter, "rx_int_delay",
515 "receive interrupt delay in usecs",
516 &adapter->rx_int_delay,
517 E1000_REG_OFFSET(&adapter->hw, RDTR),
518 em_rx_int_delay_dflt);
519 em_add_int_delay_sysctl(adapter, "tx_int_delay",
520 "transmit interrupt delay in usecs",
521 &adapter->tx_int_delay,
522 E1000_REG_OFFSET(&adapter->hw, TIDV),
523 em_tx_int_delay_dflt);
524 if (adapter->hw.mac_type >= em_82540) {
525 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
526 "receive interrupt delay limit in usecs",
527 &adapter->rx_abs_int_delay,
528 E1000_REG_OFFSET(&adapter->hw, RADV),
529 em_rx_abs_int_delay_dflt);
530 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
531 "transmit interrupt delay limit in usecs",
532 &adapter->tx_abs_int_delay,
533 E1000_REG_OFFSET(&adapter->hw, TADV),
534 em_tx_abs_int_delay_dflt);
535 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
536 SYSCTL_CHILDREN(adapter->sysctl_tree),
537 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
538 adapter, 0, em_sysctl_int_throttle, "I", NULL);
542 * Validate number of transmit and receive descriptors. It
543 * must not exceed hardware maximum, and must be multiple
546 if (((em_txd * sizeof(struct em_tx_desc)) % EM_DBA_ALIGN) != 0 ||
547 (adapter->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) ||
548 (adapter->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) ||
549 (em_txd < EM_MIN_TXD)) {
550 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
551 EM_DEFAULT_TXD, em_txd);
552 adapter->num_tx_desc = EM_DEFAULT_TXD;
554 adapter->num_tx_desc = em_txd;
557 if (((em_rxd * sizeof(struct em_rx_desc)) % EM_DBA_ALIGN) != 0 ||
558 (adapter->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) ||
559 (adapter->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) ||
560 (em_rxd < EM_MIN_RXD)) {
561 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
562 EM_DEFAULT_RXD, em_rxd);
563 adapter->num_rx_desc = EM_DEFAULT_RXD;
565 adapter->num_rx_desc = em_rxd;
568 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
569 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, "rxd",
570 CTLFLAG_RD, &adapter->num_rx_desc, 0, NULL);
571 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
572 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, "txd",
573 CTLFLAG_RD, &adapter->num_tx_desc, 0, NULL);
575 adapter->hw.autoneg = DO_AUTO_NEG;
576 adapter->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT;
577 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
578 adapter->hw.tbi_compatibility_en = TRUE;
579 adapter->rx_buffer_len = EM_RXBUFFER_2048;
581 adapter->hw.phy_init_script = 1;
582 adapter->hw.phy_reset_disable = FALSE;
584 #ifndef EM_MASTER_SLAVE
585 adapter->hw.master_slave = em_ms_hw_default;
587 adapter->hw.master_slave = EM_MASTER_SLAVE;
591 * Set the max frame size assuming standard ethernet
594 adapter->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
596 adapter->hw.min_frame_size =
597 MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN;
600 * This controls when hardware reports transmit completion
603 adapter->hw.report_tx_early = 1;
605 error = em_allocate_pci_resources(dev);
609 /* Initialize eeprom parameters */
610 em_init_eeprom_params(&adapter->hw);
612 tsize = roundup2(adapter->num_tx_desc * sizeof(struct em_tx_desc),
615 /* Allocate Transmit Descriptor ring */
616 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
618 device_printf(dev, "Unable to allocate TxDescriptor memory\n");
621 adapter->tx_desc_base = (struct em_tx_desc *)adapter->txdma.dma_vaddr;
623 rsize = roundup2(adapter->num_rx_desc * sizeof(struct em_rx_desc),
626 /* Allocate Receive Descriptor ring */
627 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
629 device_printf(dev, "Unable to allocate rx_desc memory\n");
632 adapter->rx_desc_base = (struct em_rx_desc *)adapter->rxdma.dma_vaddr;
634 /* Initialize the hardware */
635 if (em_hardware_init(adapter)) {
636 device_printf(dev, "Unable to initialize the hardware\n");
641 /* Copy the permanent MAC address out of the EEPROM */
642 if (em_read_mac_addr(&adapter->hw) < 0) {
644 "EEPROM read error while reading MAC address\n");
649 if (!em_is_valid_ether_addr(adapter->hw.mac_addr)) {
650 device_printf(dev, "Invalid MAC address\n");
655 /* Setup OS specific network interface */
656 em_setup_interface(dev, adapter);
658 /* Initialize statistics */
659 em_clear_hw_cntrs(&adapter->hw);
660 em_update_stats_counters(adapter);
661 adapter->hw.get_link_status = 1;
662 em_update_link_status(adapter);
664 /* Indicate SOL/IDER usage */
665 if (em_check_phy_reset_block(&adapter->hw)) {
666 device_printf(dev, "PHY reset is blocked due to "
667 "SOL/IDER session.\n");
670 /* Identify 82544 on PCIX */
671 em_get_bus_info(&adapter->hw);
672 if (adapter->hw.bus_type == em_bus_type_pcix &&
673 adapter->hw.mac_type == em_82544)
674 adapter->pcix_82544 = TRUE;
676 adapter->pcix_82544 = FALSE;
678 error = bus_setup_intr(dev, adapter->res_interrupt, INTR_NETSAFE,
680 &adapter->int_handler_tag,
681 adapter->interface_data.ac_if.if_serializer);
683 device_printf(dev, "Error registering interrupt handler!\n");
684 ether_ifdetach(&adapter->interface_data.ac_if);
688 INIT_DEBUGOUT("em_attach: end");
696 /*********************************************************************
697 * Device removal routine
699 * The detach entry point is called when the driver is being removed.
700 * This routine stops the adapter and deallocates all the resources
701 * that were allocated for driver operation.
703 * return 0 on success, positive on failure
704 *********************************************************************/
707 em_detach(device_t dev)
709 struct adapter *adapter = device_get_softc(dev);
711 INIT_DEBUGOUT("em_detach: begin");
713 if (device_is_attached(dev)) {
714 struct ifnet *ifp = &adapter->interface_data.ac_if;
716 lwkt_serialize_enter(ifp->if_serializer);
717 adapter->in_detach = 1;
719 em_phy_hw_reset(&adapter->hw);
720 bus_teardown_intr(dev, adapter->res_interrupt,
721 adapter->int_handler_tag);
722 lwkt_serialize_exit(ifp->if_serializer);
726 bus_generic_detach(dev);
728 em_free_pci_resources(dev);
730 /* Free Transmit Descriptor ring */
731 if (adapter->tx_desc_base != NULL) {
732 em_dma_free(adapter, &adapter->txdma);
733 adapter->tx_desc_base = NULL;
736 /* Free Receive Descriptor ring */
737 if (adapter->rx_desc_base != NULL) {
738 em_dma_free(adapter, &adapter->rxdma);
739 adapter->rx_desc_base = NULL;
742 /* Free sysctl tree */
743 if (adapter->sysctl_tree != NULL) {
744 adapter->sysctl_tree = NULL;
745 sysctl_ctx_free(&adapter->sysctl_ctx);
751 /*********************************************************************
753 * Shutdown entry point
755 **********************************************************************/
758 em_shutdown(device_t dev)
760 struct adapter *adapter = device_get_softc(dev);
761 struct ifnet *ifp = &adapter->interface_data.ac_if;
763 lwkt_serialize_enter(ifp->if_serializer);
765 lwkt_serialize_exit(ifp->if_serializer);
771 * Suspend/resume device methods.
774 em_suspend(device_t dev)
776 struct adapter *adapter = device_get_softc(dev);
777 struct ifnet *ifp = &adapter->interface_data.ac_if;
779 lwkt_serialize_enter(ifp->if_serializer);
781 lwkt_serialize_exit(ifp->if_serializer);
786 em_resume(device_t dev)
788 struct adapter *adapter = device_get_softc(dev);
789 struct ifnet *ifp = &adapter->interface_data.ac_if;
791 lwkt_serialize_enter(ifp->if_serializer);
792 ifp->if_flags &= ~IFF_RUNNING;
794 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
796 lwkt_serialize_exit(ifp->if_serializer);
798 return bus_generic_resume(dev);
801 /*********************************************************************
802 * Transmit entry point
804 * em_start is called by the stack to initiate a transmit.
805 * The driver will remain in this routine as long as there are
806 * packets to transmit and transmit resources are available.
807 * In case resources are not available stack is notified and
808 * the packet is requeued.
809 **********************************************************************/
812 em_start(struct ifnet *ifp)
815 struct adapter *adapter = ifp->if_softc;
817 ASSERT_SERIALIZED(ifp->if_serializer);
819 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
821 if (!adapter->link_active)
823 while (!ifq_is_empty(&ifp->if_snd)) {
824 m_head = ifq_poll(&ifp->if_snd);
830 if (em_encap(adapter, m_head)) {
831 ifp->if_flags |= IFF_OACTIVE;
834 ifq_dequeue(&ifp->if_snd, m_head);
836 /* Send a copy of the frame to the BPF listener */
837 ETHER_BPF_MTAP(ifp, m_head);
839 /* Set timeout in case hardware has problems transmitting. */
840 ifp->if_timer = EM_TX_TIMEOUT;
844 /*********************************************************************
847 * em_ioctl is called when the user wants to configure the
850 * return 0 on success, positive on failure
851 **********************************************************************/
854 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
856 int max_frame_size, mask, error = 0, reinit = 0;
857 struct ifreq *ifr = (struct ifreq *) data;
858 struct adapter *adapter = ifp->if_softc;
859 uint16_t eeprom_data = 0;
861 ASSERT_SERIALIZED(ifp->if_serializer);
863 if (adapter->in_detach)
868 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
869 switch (adapter->hw.mac_type) {
872 * 82573 only supports jumbo frames
873 * if ASPM is disabled.
875 em_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3,
877 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
878 max_frame_size = ETHER_MAX_LEN;
881 /* Allow Jumbo frames */
886 case em_80003es2lan: /* Limit Jumbo Frame size */
887 max_frame_size = 9234;
890 /* ICH8 does not support jumbo frames */
891 max_frame_size = ETHER_MAX_LEN;
894 max_frame_size = MAX_JUMBO_FRAME_SIZE;
898 max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
901 ifp->if_mtu = ifr->ifr_mtu;
902 adapter->hw.max_frame_size =
903 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
904 ifp->if_flags &= ~IFF_RUNNING;
909 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS "
910 "(Set Interface Flags)");
911 if (ifp->if_flags & IFF_UP) {
912 if (!(ifp->if_flags & IFF_RUNNING)) {
914 } else if ((ifp->if_flags ^ adapter->if_flags) &
916 em_disable_promisc(adapter);
917 em_set_promisc(adapter);
920 if (ifp->if_flags & IFF_RUNNING)
923 adapter->if_flags = ifp->if_flags;
927 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI");
928 if (ifp->if_flags & IFF_RUNNING) {
929 em_disable_intr(adapter);
930 em_set_multi(adapter);
931 if (adapter->hw.mac_type == em_82542_rev2_0)
932 em_initialize_receive_unit(adapter);
933 #ifdef DEVICE_POLLING
934 /* Do not enable interrupt if polling(4) is enabled */
935 if ((ifp->if_flags & IFF_POLLING) == 0)
937 em_enable_intr(adapter);
941 /* Check SOL/IDER usage */
942 if (em_check_phy_reset_block(&adapter->hw)) {
943 if_printf(ifp, "Media change is blocked due to "
944 "SOL/IDER session.\n");
949 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA "
950 "(Get/Set Interface Media)");
951 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
954 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)");
955 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
956 if (mask & IFCAP_HWCSUM) {
957 ifp->if_capenable ^= IFCAP_HWCSUM;
960 if (mask & IFCAP_VLAN_HWTAGGING) {
961 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
964 if (reinit && (ifp->if_flags & IFF_RUNNING)) {
965 ifp->if_flags &= ~IFF_RUNNING;
970 error = ether_ioctl(ifp, command, data);
977 /*********************************************************************
978 * Watchdog entry point
980 * This routine is called whenever hardware quits transmitting.
982 **********************************************************************/
985 em_watchdog(struct ifnet *ifp)
987 struct adapter *adapter = ifp->if_softc;
990 * If we are in this routine because of pause frames, then
991 * don't reset the hardware.
993 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF) {
994 ifp->if_timer = EM_TX_TIMEOUT;
998 if (em_check_for_link(&adapter->hw) == 0)
999 if_printf(ifp, "watchdog timeout -- resetting\n");
1001 ifp->if_flags &= ~IFF_RUNNING;
1004 adapter->watchdog_timeouts++;
1007 /*********************************************************************
1010 * This routine is used in two ways. It is used by the stack as
1011 * init entry point in network interface structure. It is also used
1012 * by the driver as a hw/sw initialization routine to get to a
1015 * return 0 on success, positive on failure
1016 **********************************************************************/
1021 struct adapter *adapter = arg;
1023 struct ifnet *ifp = &adapter->interface_data.ac_if;
1025 ASSERT_SERIALIZED(ifp->if_serializer);
1027 INIT_DEBUGOUT("em_init: begin");
1029 if (ifp->if_flags & IFF_RUNNING)
1035 * Packet Buffer Allocation (PBA)
1036 * Writing PBA sets the receive portion of the buffer
1037 * the remainder is used for the transmit buffer.
1039 * Devices before the 82547 had a Packet Buffer of 64K.
1040 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
1041 * After the 82547 the buffer was reduced to 40K.
1042 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
1043 * Note: default does not leave enough room for Jumbo Frame >10k.
1045 switch (adapter->hw.mac_type) {
1047 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
1048 if (adapter->hw.max_frame_size > EM_RXBUFFER_8192)
1049 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
1051 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
1053 adapter->tx_fifo_head = 0;
1054 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1055 adapter->tx_fifo_size =
1056 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
1058 /* Total Packet Buffer on these is 48K */
1061 case em_80003es2lan:
1062 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1064 case em_82573: /* 82573: Total Packet Buffer is 32K */
1065 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1071 #define E1000_PBA_10K 0x000A
1072 pba = E1000_PBA_10K;
1075 /* Devices before 82547 had a Packet Buffer of 64K. */
1076 if(adapter->hw.max_frame_size > EM_RXBUFFER_8192)
1077 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1079 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1082 INIT_DEBUGOUT1("em_init: pba=%dK",pba);
1083 E1000_WRITE_REG(&adapter->hw, PBA, pba);
1085 /* Get the latest mac address, User can use a LAA */
1086 bcopy(adapter->interface_data.ac_enaddr, adapter->hw.mac_addr,
1089 /* Initialize the hardware */
1090 if (em_hardware_init(adapter)) {
1091 if_printf(ifp, "Unable to initialize the hardware\n");
1094 em_update_link_status(adapter);
1096 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1097 em_enable_vlans(adapter);
1099 /* Set hardware offload abilities */
1100 if (adapter->hw.mac_type >= em_82543) {
1101 if (ifp->if_capenable & IFCAP_TXCSUM)
1102 ifp->if_hwassist = EM_CHECKSUM_FEATURES;
1104 ifp->if_hwassist = 0;
1107 /* Prepare transmit descriptors and buffers */
1108 if (em_setup_transmit_structures(adapter)) {
1109 if_printf(ifp, "Could not setup transmit structures\n");
1113 em_initialize_transmit_unit(adapter);
1115 /* Setup Multicast table */
1116 em_set_multi(adapter);
1118 /* Prepare receive descriptors and buffers */
1119 if (em_setup_receive_structures(adapter)) {
1120 if_printf(ifp, "Could not setup receive structures\n");
1124 em_initialize_receive_unit(adapter);
1126 /* Don't lose promiscuous settings */
1127 em_set_promisc(adapter);
1129 ifp->if_flags |= IFF_RUNNING;
1130 ifp->if_flags &= ~IFF_OACTIVE;
1132 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1133 em_clear_hw_cntrs(&adapter->hw);
1135 #ifdef DEVICE_POLLING
1136 /* Do not enable interrupt if polling(4) is enabled */
1137 if (ifp->if_flags & IFF_POLLING)
1138 em_disable_intr(adapter);
1141 em_enable_intr(adapter);
1143 /* Don't reset the phy next time init gets called */
1144 adapter->hw.phy_reset_disable = TRUE;
1147 #ifdef DEVICE_POLLING
1150 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1152 struct adapter *adapter = ifp->if_softc;
1155 ASSERT_SERIALIZED(ifp->if_serializer);
1159 em_disable_intr(adapter);
1161 case POLL_DEREGISTER:
1162 em_enable_intr(adapter);
1164 case POLL_AND_CHECK_STATUS:
1165 reg_icr = E1000_READ_REG(&adapter->hw, ICR);
1166 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1167 callout_stop(&adapter->timer);
1168 adapter->hw.get_link_status = 1;
1169 em_check_for_link(&adapter->hw);
1170 em_update_link_status(adapter);
1171 callout_reset(&adapter->timer, hz, em_local_timer,
1176 if (ifp->if_flags & IFF_RUNNING) {
1177 em_rxeof(adapter, count);
1180 if (!ifq_is_empty(&ifp->if_snd))
1187 #endif /* DEVICE_POLLING */
1189 /*********************************************************************
1191 * Interrupt Service routine
1193 *********************************************************************/
1199 struct adapter *adapter = arg;
1201 ifp = &adapter->interface_data.ac_if;
1204 ASSERT_SERIALIZED(ifp->if_serializer);
1206 reg_icr = E1000_READ_REG(&adapter->hw, ICR);
1207 if ((adapter->hw.mac_type >= em_82571 &&
1208 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1215 * XXX: some laptops trigger several spurious interrupts on em(4)
1216 * when in the resume cycle. The ICR register reports all-ones
1217 * value in this case. Processing such interrupts would lead to
1218 * a freeze. I don't know why.
1220 if (reg_icr == 0xffffffff) {
1226 * note: do not attempt to improve efficiency by looping. This
1227 * only results in unnecessary piecemeal collection of received
1228 * packets and unnecessary piecemeal cleanups of the transmit ring.
1230 if (ifp->if_flags & IFF_RUNNING) {
1231 em_rxeof(adapter, -1);
1235 /* Link status change */
1236 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1237 callout_stop(&adapter->timer);
1238 adapter->hw.get_link_status = 1;
1239 em_check_for_link(&adapter->hw);
1240 em_update_link_status(adapter);
1241 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1244 if (reg_icr & E1000_ICR_RXO)
1245 adapter->rx_overruns++;
1247 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1252 /*********************************************************************
1254 * Media Ioctl callback
1256 * This routine is called whenever the user queries the status of
1257 * the interface using ifconfig.
1259 **********************************************************************/
1261 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1263 struct adapter *adapter = ifp->if_softc;
1264 u_char fiber_type = IFM_1000_SX;
1266 INIT_DEBUGOUT("em_media_status: begin");
1268 ASSERT_SERIALIZED(ifp->if_serializer);
1270 em_check_for_link(&adapter->hw);
1271 em_update_link_status(adapter);
1273 ifmr->ifm_status = IFM_AVALID;
1274 ifmr->ifm_active = IFM_ETHER;
1276 if (!adapter->link_active)
1279 ifmr->ifm_status |= IFM_ACTIVE;
1281 if (adapter->hw.media_type == em_media_type_fiber ||
1282 adapter->hw.media_type == em_media_type_internal_serdes) {
1283 if (adapter->hw.mac_type == em_82545)
1284 fiber_type = IFM_1000_LX;
1285 ifmr->ifm_active |= fiber_type | IFM_FDX;
1287 switch (adapter->link_speed) {
1289 ifmr->ifm_active |= IFM_10_T;
1292 ifmr->ifm_active |= IFM_100_TX;
1295 ifmr->ifm_active |= IFM_1000_T;
1298 if (adapter->link_duplex == FULL_DUPLEX)
1299 ifmr->ifm_active |= IFM_FDX;
1301 ifmr->ifm_active |= IFM_HDX;
1305 /*********************************************************************
1307 * Media Ioctl callback
1309 * This routine is called when the user changes speed/duplex using
1310 * media/mediopt option with ifconfig.
1312 **********************************************************************/
1314 em_media_change(struct ifnet *ifp)
1316 struct adapter *adapter = ifp->if_softc;
1317 struct ifmedia *ifm = &adapter->media;
1319 INIT_DEBUGOUT("em_media_change: begin");
1321 ASSERT_SERIALIZED(ifp->if_serializer);
1323 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1326 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1328 adapter->hw.autoneg = DO_AUTO_NEG;
1329 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1334 adapter->hw.autoneg = DO_AUTO_NEG;
1335 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
1338 adapter->hw.autoneg = FALSE;
1339 adapter->hw.autoneg_advertised = 0;
1340 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1341 adapter->hw.forced_speed_duplex = em_100_full;
1343 adapter->hw.forced_speed_duplex = em_100_half;
1346 adapter->hw.autoneg = FALSE;
1347 adapter->hw.autoneg_advertised = 0;
1348 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1349 adapter->hw.forced_speed_duplex = em_10_full;
1351 adapter->hw.forced_speed_duplex = em_10_half;
1354 if_printf(ifp, "Unsupported media type\n");
1357 * As the speed/duplex settings may have changed we need to
1360 adapter->hw.phy_reset_disable = FALSE;
1362 ifp->if_flags &= ~IFF_RUNNING;
1369 em_tx_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize,
1372 struct em_q *q = arg;
1376 KASSERT(nsegs <= EM_MAX_SCATTER,
1377 ("Too many DMA segments returned when mapping tx packet"));
1379 bcopy(seg, q->segs, nsegs * sizeof(seg[0]));
1382 /*********************************************************************
1384 * This routine maps the mbufs to tx descriptors.
1386 * return 0 on success, positive on failure
1387 **********************************************************************/
1389 em_encap(struct adapter *adapter, struct mbuf *m_head)
1391 uint32_t txd_upper = 0, txd_lower = 0, txd_used = 0, txd_saved = 0;
1392 int i, j, error, last = 0;
1395 struct em_buffer *tx_buffer = NULL, *tx_buffer_first;
1397 struct em_tx_desc *current_tx_desc = NULL;
1398 struct ifnet *ifp = &adapter->interface_data.ac_if;
1401 * Force a cleanup if number of TX descriptors
1402 * available hits the threshold
1404 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1406 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1407 adapter->no_tx_desc_avail1++;
1413 * Capture the first descriptor index, this descriptor will have
1414 * the index of the EOP which is the only one that now gets a
1415 * DONE bit writeback.
1417 tx_buffer_first = &adapter->tx_buffer_area[adapter->next_avail_tx_desc];
1420 * Map the packet for DMA.
1422 map = tx_buffer_first->map;
1423 error = bus_dmamap_load_mbuf(adapter->txtag, map, m_head, em_tx_cb,
1424 &q, BUS_DMA_NOWAIT);
1426 adapter->no_tx_dma_setup++;
1429 KASSERT(q.nsegs != 0, ("em_encap: empty packet"));
1431 if (q.nsegs > (adapter->num_tx_desc_avail - 2)) {
1432 adapter->no_tx_desc_avail2++;
1437 if (ifp->if_hwassist > 0) {
1438 em_transmit_checksum_setup(adapter, m_head,
1439 &txd_upper, &txd_lower);
1442 i = adapter->next_avail_tx_desc;
1443 if (adapter->pcix_82544)
1446 /* Set up our transmit descriptors */
1447 for (j = 0; j < q.nsegs; j++) {
1448 /* If adapter is 82544 and on PCIX bus */
1449 if(adapter->pcix_82544) {
1450 DESC_ARRAY desc_array;
1451 uint32_t array_elements, counter;
1454 * Check the Address and Length combination and
1455 * split the data accordingly
1457 array_elements = em_fill_descriptors(q.segs[j].ds_addr,
1458 q.segs[j].ds_len, &desc_array);
1459 for (counter = 0; counter < array_elements; counter++) {
1460 if (txd_used == adapter->num_tx_desc_avail) {
1461 adapter->next_avail_tx_desc = txd_saved;
1462 adapter->no_tx_desc_avail2++;
1466 tx_buffer = &adapter->tx_buffer_area[i];
1467 current_tx_desc = &adapter->tx_desc_base[i];
1468 current_tx_desc->buffer_addr = htole64(
1469 desc_array.descriptor[counter].address);
1470 current_tx_desc->lower.data = htole32(
1471 adapter->txd_cmd | txd_lower |
1472 (uint16_t)desc_array.descriptor[counter].length);
1473 current_tx_desc->upper.data = htole32(txd_upper);
1476 if (++i == adapter->num_tx_desc)
1479 tx_buffer->m_head = NULL;
1480 tx_buffer->next_eop = -1;
1484 tx_buffer = &adapter->tx_buffer_area[i];
1485 current_tx_desc = &adapter->tx_desc_base[i];
1487 current_tx_desc->buffer_addr = htole64(q.segs[j].ds_addr);
1488 current_tx_desc->lower.data = htole32(
1489 adapter->txd_cmd | txd_lower | q.segs[j].ds_len);
1490 current_tx_desc->upper.data = htole32(txd_upper);
1493 if (++i == adapter->num_tx_desc)
1496 tx_buffer->m_head = NULL;
1497 tx_buffer->next_eop = -1;
1501 adapter->next_avail_tx_desc = i;
1502 if (adapter->pcix_82544)
1503 adapter->num_tx_desc_avail -= txd_used;
1505 adapter->num_tx_desc_avail -= q.nsegs;
1507 /* Find out if we are in vlan mode */
1508 if (m_head->m_flags & M_VLANTAG) {
1509 /* Set the vlan id */
1510 current_tx_desc->upper.fields.special =
1511 htole16(m_head->m_pkthdr.ether_vlantag);
1513 /* Tell hardware to add tag */
1514 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE);
1517 tx_buffer->m_head = m_head;
1518 tx_buffer_first->map = tx_buffer->map;
1519 tx_buffer->map = map;
1520 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
1523 * Last Descriptor of Packet needs End Of Packet (EOP)
1524 * and Report Status (RS)
1526 current_tx_desc->lower.data |=
1527 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
1530 * Keep track in the first buffer which descriptor will be
1533 tx_buffer_first->next_eop = last;
1535 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
1536 BUS_DMASYNC_PREWRITE);
1539 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000
1540 * that this frame is available to transmit.
1542 if (adapter->hw.mac_type == em_82547 &&
1543 adapter->link_duplex == HALF_DUPLEX) {
1544 em_82547_move_tail_serialized(adapter);
1546 E1000_WRITE_REG(&adapter->hw, TDT, i);
1547 if (adapter->hw.mac_type == em_82547) {
1548 em_82547_update_fifo_head(adapter,
1549 m_head->m_pkthdr.len);
1555 bus_dmamap_unload(adapter->txtag, map);
1559 /*********************************************************************
1561 * 82547 workaround to avoid controller hang in half-duplex environment.
1562 * The workaround is to avoid queuing a large packet that would span
1563 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1564 * in this case. We do that only when FIFO is quiescent.
1566 **********************************************************************/
1568 em_82547_move_tail(void *arg)
1570 struct adapter *adapter = arg;
1571 struct ifnet *ifp = &adapter->interface_data.ac_if;
1573 lwkt_serialize_enter(ifp->if_serializer);
1574 em_82547_move_tail_serialized(adapter);
1575 lwkt_serialize_exit(ifp->if_serializer);
1579 em_82547_move_tail_serialized(struct adapter *adapter)
1583 struct em_tx_desc *tx_desc;
1584 uint16_t length = 0;
1587 hw_tdt = E1000_READ_REG(&adapter->hw, TDT);
1588 sw_tdt = adapter->next_avail_tx_desc;
1590 while (hw_tdt != sw_tdt) {
1591 tx_desc = &adapter->tx_desc_base[hw_tdt];
1592 length += tx_desc->lower.flags.length;
1593 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
1594 if (++hw_tdt == adapter->num_tx_desc)
1598 if (em_82547_fifo_workaround(adapter, length)) {
1599 adapter->tx_fifo_wrk_cnt++;
1600 callout_reset(&adapter->tx_fifo_timer, 1,
1601 em_82547_move_tail, adapter);
1604 E1000_WRITE_REG(&adapter->hw, TDT, hw_tdt);
1605 em_82547_update_fifo_head(adapter, length);
1612 em_82547_fifo_workaround(struct adapter *adapter, int len)
1614 int fifo_space, fifo_pkt_len;
1616 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1618 if (adapter->link_duplex == HALF_DUPLEX) {
1619 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
1621 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
1622 if (em_82547_tx_fifo_reset(adapter))
1633 em_82547_update_fifo_head(struct adapter *adapter, int len)
1635 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1637 /* tx_fifo_head is always 16 byte aligned */
1638 adapter->tx_fifo_head += fifo_pkt_len;
1639 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1640 adapter->tx_fifo_head -= adapter->tx_fifo_size;
1644 em_82547_tx_fifo_reset(struct adapter *adapter)
1648 if (E1000_READ_REG(&adapter->hw, TDT) == E1000_READ_REG(&adapter->hw, TDH) &&
1649 E1000_READ_REG(&adapter->hw, TDFT) == E1000_READ_REG(&adapter->hw, TDFH) &&
1650 E1000_READ_REG(&adapter->hw, TDFTS) == E1000_READ_REG(&adapter->hw, TDFHS) &&
1651 E1000_READ_REG(&adapter->hw, TDFPC) == 0) {
1652 /* Disable TX unit */
1653 tctl = E1000_READ_REG(&adapter->hw, TCTL);
1654 E1000_WRITE_REG(&adapter->hw, TCTL, tctl & ~E1000_TCTL_EN);
1656 /* Reset FIFO pointers */
1657 E1000_WRITE_REG(&adapter->hw, TDFT, adapter->tx_head_addr);
1658 E1000_WRITE_REG(&adapter->hw, TDFH, adapter->tx_head_addr);
1659 E1000_WRITE_REG(&adapter->hw, TDFTS, adapter->tx_head_addr);
1660 E1000_WRITE_REG(&adapter->hw, TDFHS, adapter->tx_head_addr);
1662 /* Re-enable TX unit */
1663 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
1664 E1000_WRITE_FLUSH(&adapter->hw);
1666 adapter->tx_fifo_head = 0;
1667 adapter->tx_fifo_reset_cnt++;
1676 em_set_promisc(struct adapter *adapter)
1679 struct ifnet *ifp = &adapter->interface_data.ac_if;
1681 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1683 adapter->em_insert_vlan_header = 0;
1684 if (ifp->if_flags & IFF_PROMISC) {
1685 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1686 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1689 * Disable VLAN stripping in promiscous mode.
1690 * This enables bridging of vlan tagged frames to occur
1691 * and also allows vlan tags to be seen in tcpdump.
1693 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1694 em_disable_vlans(adapter);
1695 adapter->em_insert_vlan_header = 1;
1696 } else if (ifp->if_flags & IFF_ALLMULTI) {
1697 reg_rctl |= E1000_RCTL_MPE;
1698 reg_rctl &= ~E1000_RCTL_UPE;
1699 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1704 em_disable_promisc(struct adapter *adapter)
1706 struct ifnet *ifp = &adapter->interface_data.ac_if;
1710 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1712 reg_rctl &= (~E1000_RCTL_UPE);
1713 reg_rctl &= (~E1000_RCTL_MPE);
1714 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1716 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1717 em_enable_vlans(adapter);
1718 adapter->em_insert_vlan_header = 0;
1721 /*********************************************************************
1724 * This routine is called whenever multicast address list is updated.
1726 **********************************************************************/
1729 em_set_multi(struct adapter *adapter)
1731 uint32_t reg_rctl = 0;
1732 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS];
1733 struct ifmultiaddr *ifma;
1735 struct ifnet *ifp = &adapter->interface_data.ac_if;
1737 IOCTL_DEBUGOUT("em_set_multi: begin");
1739 if (adapter->hw.mac_type == em_82542_rev2_0) {
1740 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1741 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1742 em_pci_clear_mwi(&adapter->hw);
1743 reg_rctl |= E1000_RCTL_RST;
1744 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1748 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1749 if (ifma->ifma_addr->sa_family != AF_LINK)
1752 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1755 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1756 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS);
1760 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1761 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1762 reg_rctl |= E1000_RCTL_MPE;
1763 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1765 em_mc_addr_list_update(&adapter->hw, mta, mcnt, 0, 1);
1768 if (adapter->hw.mac_type == em_82542_rev2_0) {
1769 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1770 reg_rctl &= ~E1000_RCTL_RST;
1771 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1773 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1774 em_pci_set_mwi(&adapter->hw);
1778 /*********************************************************************
1781 * This routine checks for link status and updates statistics.
1783 **********************************************************************/
1786 em_local_timer(void *arg)
1789 struct adapter *adapter = arg;
1790 ifp = &adapter->interface_data.ac_if;
1792 lwkt_serialize_enter(ifp->if_serializer);
1794 em_check_for_link(&adapter->hw);
1795 em_update_link_status(adapter);
1796 em_update_stats_counters(adapter);
1797 if (em_display_debug_stats && ifp->if_flags & IFF_RUNNING)
1798 em_print_hw_stats(adapter);
1799 em_smartspeed(adapter);
1801 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1803 lwkt_serialize_exit(ifp->if_serializer);
1807 em_update_link_status(struct adapter *adapter)
1810 ifp = &adapter->interface_data.ac_if;
1812 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) {
1813 if (adapter->link_active == 0) {
1814 em_get_speed_and_duplex(&adapter->hw,
1815 &adapter->link_speed,
1816 &adapter->link_duplex);
1817 /* Check if we may set SPEED_MODE bit on PCI-E */
1818 if (adapter->link_speed == SPEED_1000 &&
1819 (adapter->hw.mac_type == em_82571 ||
1820 adapter->hw.mac_type == em_82572)) {
1823 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
1824 tarc0 |= SPEED_MODE_BIT;
1825 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
1828 if_printf(&adapter->interface_data.ac_if,
1829 "Link is up %d Mbps %s\n",
1830 adapter->link_speed,
1831 adapter->link_duplex == FULL_DUPLEX ?
1832 "Full Duplex" : "Half Duplex");
1834 adapter->link_active = 1;
1835 adapter->smartspeed = 0;
1836 ifp->if_baudrate = adapter->link_speed * 1000000;
1837 ifp->if_link_state = LINK_STATE_UP;
1838 if_link_state_change(ifp);
1841 if (adapter->link_active == 1) {
1842 ifp->if_baudrate = 0;
1843 adapter->link_speed = 0;
1844 adapter->link_duplex = 0;
1846 if_printf(&adapter->interface_data.ac_if,
1849 adapter->link_active = 0;
1850 ifp->if_link_state = LINK_STATE_DOWN;
1851 if_link_state_change(ifp);
1856 /*********************************************************************
1858 * This routine disables all traffic on the adapter by issuing a
1859 * global reset on the MAC and deallocates TX/RX buffers.
1861 **********************************************************************/
1867 struct adapter * adapter = arg;
1868 ifp = &adapter->interface_data.ac_if;
1870 ASSERT_SERIALIZED(ifp->if_serializer);
1872 INIT_DEBUGOUT("em_stop: begin");
1873 em_disable_intr(adapter);
1874 em_reset_hw(&adapter->hw);
1875 callout_stop(&adapter->timer);
1876 callout_stop(&adapter->tx_fifo_timer);
1877 em_free_transmit_structures(adapter);
1878 em_free_receive_structures(adapter);
1880 /* Tell the stack that the interface is no longer active */
1881 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1885 /*********************************************************************
1887 * Determine hardware revision.
1889 **********************************************************************/
1891 em_identify_hardware(struct adapter *adapter)
1893 device_t dev = adapter->dev;
1895 /* Make sure our PCI config space has the necessary stuff set */
1896 adapter->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1897 if (!((adapter->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
1898 (adapter->hw.pci_cmd_word & PCIM_CMD_MEMEN))) {
1899 device_printf(dev, "Memory Access and/or Bus Master bits "
1901 adapter->hw.pci_cmd_word |= PCIM_CMD_BUSMASTEREN |
1903 pci_write_config(dev, PCIR_COMMAND,
1904 adapter->hw.pci_cmd_word, 2);
1907 /* Save off the information about this board */
1908 adapter->hw.vendor_id = pci_get_vendor(dev);
1909 adapter->hw.device_id = pci_get_device(dev);
1910 adapter->hw.revision_id = pci_get_revid(dev);
1911 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
1912 adapter->hw.subsystem_id = pci_get_subdevice(dev);
1914 /* Identify the MAC */
1915 if (em_set_mac_type(&adapter->hw))
1916 device_printf(dev, "Unknown MAC Type\n");
1918 if (adapter->hw.mac_type == em_82541 ||
1919 adapter->hw.mac_type == em_82541_rev_2 ||
1920 adapter->hw.mac_type == em_82547 ||
1921 adapter->hw.mac_type == em_82547_rev_2)
1922 adapter->hw.phy_init_script = TRUE;
1926 em_allocate_pci_resources(device_t dev)
1928 struct adapter *adapter = device_get_softc(dev);
1932 adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1934 if (adapter->res_memory == NULL) {
1935 device_printf(dev, "Unable to allocate bus resource: memory\n");
1938 adapter->osdep.mem_bus_space_tag =
1939 rman_get_bustag(adapter->res_memory);
1940 adapter->osdep.mem_bus_space_handle =
1941 rman_get_bushandle(adapter->res_memory);
1942 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
1944 if (adapter->hw.mac_type > em_82543) {
1945 /* Figure our where our IO BAR is ? */
1946 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1949 val = pci_read_config(dev, rid, 4);
1950 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1951 adapter->io_rid = rid;
1955 /* check for 64bit BAR */
1956 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1959 if (rid >= PCIR_CIS) {
1960 device_printf(dev, "Unable to locate IO BAR\n");
1964 adapter->res_ioport = bus_alloc_resource_any(dev,
1965 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1966 if (!(adapter->res_ioport)) {
1967 device_printf(dev, "Unable to allocate bus resource: "
1971 adapter->hw.io_base = 0;
1972 adapter->osdep.io_bus_space_tag =
1973 rman_get_bustag(adapter->res_ioport);
1974 adapter->osdep.io_bus_space_handle =
1975 rman_get_bushandle(adapter->res_ioport);
1978 /* For ICH8 we need to find the flash memory. */
1979 if ((adapter->hw.mac_type == em_ich8lan) ||
1980 (adapter->hw.mac_type == em_ich9lan)) {
1982 adapter->flash_mem = bus_alloc_resource_any(dev,
1983 SYS_RES_MEMORY, &rid, RF_ACTIVE);
1984 if (adapter->flash_mem == NULL) {
1985 device_printf(dev, "Unable to allocate bus resource: "
1989 adapter->osdep.flash_bus_space_tag =
1990 rman_get_bustag(adapter->flash_mem);
1991 adapter->osdep.flash_bus_space_handle =
1992 rman_get_bushandle(adapter->flash_mem);
1996 adapter->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1997 &rid, RF_SHAREABLE | RF_ACTIVE);
1998 if (adapter->res_interrupt == NULL) {
1999 device_printf(dev, "Unable to allocate bus resource: "
2004 adapter->hw.back = &adapter->osdep;
2010 em_free_pci_resources(device_t dev)
2012 struct adapter *adapter = device_get_softc(dev);
2014 if (adapter->res_interrupt != NULL) {
2015 bus_release_resource(dev, SYS_RES_IRQ, 0,
2016 adapter->res_interrupt);
2018 if (adapter->res_memory != NULL) {
2019 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
2020 adapter->res_memory);
2023 if (adapter->res_ioport != NULL) {
2024 bus_release_resource(dev, SYS_RES_IOPORT, adapter->io_rid,
2025 adapter->res_ioport);
2028 if (adapter->flash_mem != NULL) {
2029 bus_release_resource(dev, SYS_RES_MEMORY, EM_FLASH,
2030 adapter->flash_mem);
2034 /*********************************************************************
2036 * Initialize the hardware to a configuration as specified by the
2037 * adapter structure. The controller is reset, the EEPROM is
2038 * verified, the MAC address is set, then the shared initialization
2039 * routines are called.
2041 **********************************************************************/
2043 em_hardware_init(struct adapter *adapter)
2045 uint16_t rx_buffer_size;
2047 INIT_DEBUGOUT("em_hardware_init: begin");
2048 /* Issue a global reset */
2049 em_reset_hw(&adapter->hw);
2051 /* When hardware is reset, fifo_head is also reset */
2052 adapter->tx_fifo_head = 0;
2054 /* Make sure we have a good EEPROM before we read from it */
2055 if (em_validate_eeprom_checksum(&adapter->hw) < 0) {
2056 if (em_validate_eeprom_checksum(&adapter->hw) < 0) {
2057 device_printf(adapter->dev,
2058 "The EEPROM Checksum Is Not Valid\n");
2063 if (em_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) {
2064 device_printf(adapter->dev,
2065 "EEPROM read error while reading part number\n");
2069 /* Set up smart power down as default off on newer adapters. */
2070 if (!em_smart_pwr_down &&
2071 (adapter->hw.mac_type == em_82571 ||
2072 adapter->hw.mac_type == em_82572)) {
2073 uint16_t phy_tmp = 0;
2075 /* Speed up time to link by disabling smart power down. */
2076 em_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
2078 phy_tmp &= ~IGP02E1000_PM_SPD;
2079 em_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
2084 * These parameters control the automatic generation (Tx) and
2085 * response (Rx) to Ethernet PAUSE frames.
2086 * - High water mark should allow for at least two frames to be
2087 * received after sending an XOFF.
2088 * - Low water mark works best when it is very near the high water mark.
2089 * This allows the receiver to restart by sending XON when it has
2090 * drained a bit. Here we use an arbitary value of 1500 which will
2091 * restart after one full frame is pulled from the buffer. There
2092 * could be several smaller frames in the buffer and if so they will
2093 * not trigger the XON until their total number reduces the buffer
2095 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2097 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff) << 10);
2099 adapter->hw.fc_high_water =
2100 rx_buffer_size - roundup2(adapter->hw.max_frame_size, 1024);
2101 adapter->hw.fc_low_water = adapter->hw.fc_high_water - 1500;
2102 if (adapter->hw.mac_type == em_80003es2lan)
2103 adapter->hw.fc_pause_time = 0xFFFF;
2105 adapter->hw.fc_pause_time = 1000;
2106 adapter->hw.fc_send_xon = TRUE;
2107 adapter->hw.fc = E1000_FC_FULL;
2109 if (em_init_hw(&adapter->hw) < 0) {
2110 device_printf(adapter->dev, "Hardware Initialization Failed");
2114 em_check_for_link(&adapter->hw);
2119 /*********************************************************************
2121 * Setup networking device structure and register an interface.
2123 **********************************************************************/
2125 em_setup_interface(device_t dev, struct adapter *adapter)
2128 u_char fiber_type = IFM_1000_SX; /* default type */
2129 INIT_DEBUGOUT("em_setup_interface: begin");
2131 ifp = &adapter->interface_data.ac_if;
2132 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2133 ifp->if_mtu = ETHERMTU;
2134 ifp->if_baudrate = 1000000000;
2135 ifp->if_init = em_init;
2136 ifp->if_softc = adapter;
2137 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2138 ifp->if_ioctl = em_ioctl;
2139 ifp->if_start = em_start;
2140 #ifdef DEVICE_POLLING
2141 ifp->if_poll = em_poll;
2143 ifp->if_watchdog = em_watchdog;
2144 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
2145 ifq_set_ready(&ifp->if_snd);
2147 if (adapter->hw.mac_type >= em_82543)
2148 ifp->if_capabilities |= IFCAP_HWCSUM;
2150 ifp->if_capenable = ifp->if_capabilities;
2152 ether_ifattach(ifp, adapter->hw.mac_addr, NULL);
2154 #ifdef PROFILE_SERIALIZER
2155 SYSCTL_ADD_UINT(&adapter->sysctl_ctx,
2156 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO,
2157 "serializer_sleep", CTLFLAG_RW,
2158 &ifp->if_serializer->sleep_cnt, 0, NULL);
2159 SYSCTL_ADD_UINT(&adapter->sysctl_ctx,
2160 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO,
2161 "serializer_tryfail", CTLFLAG_RW,
2162 &ifp->if_serializer->tryfail_cnt, 0, NULL);
2163 SYSCTL_ADD_UINT(&adapter->sysctl_ctx,
2164 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO,
2165 "serializer_enter", CTLFLAG_RW,
2166 &ifp->if_serializer->enter_cnt, 0, NULL);
2167 SYSCTL_ADD_UINT(&adapter->sysctl_ctx,
2168 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO,
2169 "serializer_try", CTLFLAG_RW,
2170 &ifp->if_serializer->try_cnt, 0, NULL);
2174 * Tell the upper layer(s) we support long frames.
2176 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2177 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2179 ifp->if_capenable |= IFCAP_VLAN_MTU;
2183 * Specify the media types supported by this adapter and register
2184 * callbacks to update media and link information
2186 ifmedia_init(&adapter->media, IFM_IMASK, em_media_change,
2188 if (adapter->hw.media_type == em_media_type_fiber ||
2189 adapter->hw.media_type == em_media_type_internal_serdes) {
2190 if (adapter->hw.mac_type == em_82545)
2191 fiber_type = IFM_1000_LX;
2192 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
2194 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2196 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2197 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2199 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
2201 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2203 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX,
2205 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2207 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2208 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
2211 /*********************************************************************
2213 * Workaround for SmartSpeed on 82541 and 82547 controllers
2215 **********************************************************************/
2217 em_smartspeed(struct adapter *adapter)
2221 if (adapter->link_active || (adapter->hw.phy_type != em_phy_igp) ||
2222 !adapter->hw.autoneg ||
2223 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
2226 if (adapter->smartspeed == 0) {
2228 * If Master/Slave config fault is asserted twice,
2229 * we assume back-to-back.
2231 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2232 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2234 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2235 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2236 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2237 if (phy_tmp & CR_1000T_MS_ENABLE) {
2238 phy_tmp &= ~CR_1000T_MS_ENABLE;
2239 em_write_phy_reg(&adapter->hw,
2240 PHY_1000T_CTRL, phy_tmp);
2241 adapter->smartspeed++;
2242 if (adapter->hw.autoneg &&
2243 !em_phy_setup_autoneg(&adapter->hw) &&
2244 !em_read_phy_reg(&adapter->hw, PHY_CTRL,
2246 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2247 MII_CR_RESTART_AUTO_NEG);
2248 em_write_phy_reg(&adapter->hw,
2254 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2255 /* If still no link, perhaps using 2/3 pair cable */
2256 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2257 phy_tmp |= CR_1000T_MS_ENABLE;
2258 em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2259 if (adapter->hw.autoneg &&
2260 !em_phy_setup_autoneg(&adapter->hw) &&
2261 !em_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_tmp)) {
2262 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2263 MII_CR_RESTART_AUTO_NEG);
2264 em_write_phy_reg(&adapter->hw, PHY_CTRL, phy_tmp);
2267 /* Restart process after EM_SMARTSPEED_MAX iterations */
2268 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2269 adapter->smartspeed = 0;
2273 * Manage DMA'able memory.
2276 em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2280 *(bus_addr_t *)arg = segs->ds_addr;
2284 em_dma_malloc(struct adapter *adapter, bus_size_t size,
2285 struct em_dma_alloc *dma)
2287 device_t dev = adapter->dev;
2290 error = bus_dma_tag_create(NULL, /* parent */
2291 EM_DBA_ALIGN, 0, /* alignment, bounds */
2292 BUS_SPACE_MAXADDR, /* lowaddr */
2293 BUS_SPACE_MAXADDR, /* highaddr */
2294 NULL, NULL, /* filter, filterarg */
2297 size, /* maxsegsize */
2301 device_printf(dev, "%s: bus_dma_tag_create failed; error %d\n",
2306 error = bus_dmamem_alloc(dma->dma_tag, (void**)&dma->dma_vaddr,
2307 BUS_DMA_WAITOK, &dma->dma_map);
2309 device_printf(dev, "%s: bus_dmammem_alloc failed; "
2310 "size %llu, error %d\n",
2311 __func__, (uintmax_t)size, error);
2315 error = bus_dmamap_load(dma->dma_tag, dma->dma_map,
2316 dma->dma_vaddr, size,
2317 em_dmamap_cb, &dma->dma_paddr,
2320 device_printf(dev, "%s: bus_dmamap_load failed; error %u\n",
2322 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2328 bus_dma_tag_destroy(dma->dma_tag);
2329 dma->dma_tag = NULL;
2334 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2336 if (dma->dma_tag != NULL) {
2337 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2338 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2339 bus_dma_tag_destroy(dma->dma_tag);
2340 dma->dma_tag = NULL;
2344 /*********************************************************************
2346 * Allocate and initialize transmit structures.
2348 **********************************************************************/
2350 em_setup_transmit_structures(struct adapter *adapter)
2352 struct em_buffer *tx_buffer;
2357 * Setup DMA descriptor areas.
2359 size = roundup2(adapter->hw.max_frame_size, MCLBYTES);
2360 if (bus_dma_tag_create(NULL, /* parent */
2361 1, 0, /* alignment, bounds */
2362 BUS_SPACE_MAXADDR, /* lowaddr */
2363 BUS_SPACE_MAXADDR, /* highaddr */
2364 NULL, NULL, /* filter, filterarg */
2366 EM_MAX_SCATTER, /* nsegments */
2367 size, /* maxsegsize */
2370 device_printf(adapter->dev, "Unable to allocate TX DMA tag\n");
2374 adapter->tx_buffer_area =
2375 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2376 M_DEVBUF, M_WAITOK | M_ZERO);
2378 bzero(adapter->tx_desc_base,
2379 sizeof(struct em_tx_desc) * adapter->num_tx_desc);
2380 tx_buffer = adapter->tx_buffer_area;
2381 for (i = 0; i < adapter->num_tx_desc; i++) {
2382 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map);
2384 device_printf(adapter->dev,
2385 "Unable to create TX DMA map\n");
2391 adapter->next_avail_tx_desc = 0;
2392 adapter->next_tx_to_clean = 0;
2394 /* Set number of descriptors available */
2395 adapter->num_tx_desc_avail = adapter->num_tx_desc;
2397 /* Set checksum context */
2398 adapter->active_checksum_context = OFFLOAD_NONE;
2400 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2401 BUS_DMASYNC_PREWRITE);
2405 em_free_transmit_structures(adapter);
2409 /*********************************************************************
2411 * Enable transmit unit.
2413 **********************************************************************/
2415 em_initialize_transmit_unit(struct adapter *adapter)
2418 uint32_t reg_tipg = 0;
2421 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2423 /* Setup the Base and Length of the Tx Descriptor Ring */
2424 bus_addr = adapter->txdma.dma_paddr;
2425 E1000_WRITE_REG(&adapter->hw, TDLEN,
2426 adapter->num_tx_desc * sizeof(struct em_tx_desc));
2427 E1000_WRITE_REG(&adapter->hw, TDBAH, (uint32_t)(bus_addr >> 32));
2428 E1000_WRITE_REG(&adapter->hw, TDBAL, (uint32_t)bus_addr);
2430 /* Setup the HW Tx Head and Tail descriptor pointers */
2431 E1000_WRITE_REG(&adapter->hw, TDT, 0);
2432 E1000_WRITE_REG(&adapter->hw, TDH, 0);
2434 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2435 E1000_READ_REG(&adapter->hw, TDBAL),
2436 E1000_READ_REG(&adapter->hw, TDLEN));
2438 /* Set the default values for the Tx Inter Packet Gap timer */
2439 switch (adapter->hw.mac_type) {
2440 case em_82542_rev2_0:
2441 case em_82542_rev2_1:
2442 reg_tipg = DEFAULT_82542_TIPG_IPGT;
2443 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2444 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2446 case em_80003es2lan:
2447 reg_tipg = DEFAULT_82543_TIPG_IPGR1;
2449 DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2452 if (adapter->hw.media_type == em_media_type_fiber ||
2453 adapter->hw.media_type == em_media_type_internal_serdes)
2454 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2456 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2457 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2458 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2461 E1000_WRITE_REG(&adapter->hw, TIPG, reg_tipg);
2462 E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay.value);
2463 if (adapter->hw.mac_type >= em_82540) {
2464 E1000_WRITE_REG(&adapter->hw, TADV,
2465 adapter->tx_abs_int_delay.value);
2468 /* Program the Transmit Control Register */
2469 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
2470 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2471 if (adapter->hw.mac_type >= em_82571)
2472 reg_tctl |= E1000_TCTL_MULR;
2473 if (adapter->link_duplex == 1)
2474 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2476 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2478 /* This write will effectively turn on the transmit unit. */
2479 E1000_WRITE_REG(&adapter->hw, TCTL, reg_tctl);
2481 /* Setup Transmit Descriptor Base Settings */
2482 adapter->txd_cmd = E1000_TXD_CMD_IFCS;
2484 if (adapter->tx_int_delay.value > 0)
2485 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2488 /*********************************************************************
2490 * Free all transmit related data structures.
2492 **********************************************************************/
2494 em_free_transmit_structures(struct adapter *adapter)
2496 struct em_buffer *tx_buffer;
2499 INIT_DEBUGOUT("free_transmit_structures: begin");
2501 if (adapter->tx_buffer_area != NULL) {
2502 tx_buffer = adapter->tx_buffer_area;
2503 for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) {
2504 if (tx_buffer->m_head != NULL) {
2505 bus_dmamap_unload(adapter->txtag,
2507 m_freem(tx_buffer->m_head);
2510 if (tx_buffer->map != NULL) {
2511 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
2512 tx_buffer->map = NULL;
2514 tx_buffer->m_head = NULL;
2517 if (adapter->tx_buffer_area != NULL) {
2518 kfree(adapter->tx_buffer_area, M_DEVBUF);
2519 adapter->tx_buffer_area = NULL;
2521 if (adapter->txtag != NULL) {
2522 bus_dma_tag_destroy(adapter->txtag);
2523 adapter->txtag = NULL;
2527 /*********************************************************************
2529 * The offload context needs to be set when we transfer the first
2530 * packet of a particular protocol (TCP/UDP). We change the
2531 * context only if the protocol type changes.
2533 **********************************************************************/
2535 em_transmit_checksum_setup(struct adapter *adapter,
2537 uint32_t *txd_upper,
2538 uint32_t *txd_lower)
2540 struct em_context_desc *TXD;
2541 struct em_buffer *tx_buffer;
2544 if (mp->m_pkthdr.csum_flags) {
2545 if (mp->m_pkthdr.csum_flags & CSUM_TCP) {
2546 *txd_upper = E1000_TXD_POPTS_TXSM << 8;
2547 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2548 if (adapter->active_checksum_context == OFFLOAD_TCP_IP)
2551 adapter->active_checksum_context = OFFLOAD_TCP_IP;
2552 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) {
2553 *txd_upper = E1000_TXD_POPTS_TXSM << 8;
2554 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2555 if (adapter->active_checksum_context == OFFLOAD_UDP_IP)
2558 adapter->active_checksum_context = OFFLOAD_UDP_IP;
2571 * If we reach this point, the checksum offload context
2572 * needs to be reset.
2574 curr_txd = adapter->next_avail_tx_desc;
2575 tx_buffer = &adapter->tx_buffer_area[curr_txd];
2576 TXD = (struct em_context_desc *) &adapter->tx_desc_base[curr_txd];
2578 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN;
2579 TXD->lower_setup.ip_fields.ipcso =
2580 ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
2581 TXD->lower_setup.ip_fields.ipcse =
2582 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1);
2584 TXD->upper_setup.tcp_fields.tucss =
2585 ETHER_HDR_LEN + sizeof(struct ip);
2586 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2588 if (adapter->active_checksum_context == OFFLOAD_TCP_IP) {
2589 TXD->upper_setup.tcp_fields.tucso =
2590 ETHER_HDR_LEN + sizeof(struct ip) +
2591 offsetof(struct tcphdr, th_sum);
2592 } else if (adapter->active_checksum_context == OFFLOAD_UDP_IP) {
2593 TXD->upper_setup.tcp_fields.tucso =
2594 ETHER_HDR_LEN + sizeof(struct ip) +
2595 offsetof(struct udphdr, uh_sum);
2598 TXD->tcp_seg_setup.data = htole32(0);
2599 TXD->cmd_and_length = htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT);
2601 tx_buffer->m_head = NULL;
2602 tx_buffer->next_eop = -1;
2604 if (++curr_txd == adapter->num_tx_desc)
2607 adapter->num_tx_desc_avail--;
2608 adapter->next_avail_tx_desc = curr_txd;
2611 /**********************************************************************
2613 * Examine each tx_buffer in the used queue. If the hardware is done
2614 * processing the packet then free associated resources. The
2615 * tx_buffer is put back on the free queue.
2617 **********************************************************************/
2620 em_txeof(struct adapter *adapter)
2622 int first, last, done, num_avail;
2623 struct em_buffer *tx_buffer;
2624 struct em_tx_desc *tx_desc, *eop_desc;
2625 struct ifnet *ifp = &adapter->interface_data.ac_if;
2627 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2630 num_avail = adapter->num_tx_desc_avail;
2631 first = adapter->next_tx_to_clean;
2632 tx_desc = &adapter->tx_desc_base[first];
2633 tx_buffer = &adapter->tx_buffer_area[first];
2634 last = tx_buffer->next_eop;
2635 KKASSERT(last >= 0 && last < adapter->num_tx_desc);
2636 eop_desc = &adapter->tx_desc_base[last];
2639 * Now caculate the terminating index for the cleanup loop below
2641 if (++last == adapter->num_tx_desc)
2645 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2646 BUS_DMASYNC_POSTREAD);
2648 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2649 while (first != done) {
2650 tx_desc->upper.data = 0;
2651 tx_desc->lower.data = 0;
2656 if (tx_buffer->m_head) {
2658 bus_dmamap_sync(adapter->txtag, tx_buffer->map,
2659 BUS_DMASYNC_POSTWRITE);
2660 bus_dmamap_unload(adapter->txtag,
2663 m_freem(tx_buffer->m_head);
2664 tx_buffer->m_head = NULL;
2666 tx_buffer->next_eop = -1;
2668 if (++first == adapter->num_tx_desc)
2671 tx_buffer = &adapter->tx_buffer_area[first];
2672 tx_desc = &adapter->tx_desc_base[first];
2674 /* See if we can continue to the next packet */
2675 last = tx_buffer->next_eop;
2677 KKASSERT(last >= 0 && last < adapter->num_tx_desc);
2678 eop_desc = &adapter->tx_desc_base[last];
2679 if (++last == adapter->num_tx_desc)
2687 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2688 BUS_DMASYNC_PREWRITE);
2690 adapter->next_tx_to_clean = first;
2693 * If we have enough room, clear IFF_OACTIVE to tell the stack
2694 * that it is OK to send packets.
2695 * If there are no pending descriptors, clear the timeout. Otherwise,
2696 * if some descriptors have been freed, restart the timeout.
2698 if (num_avail > EM_TX_CLEANUP_THRESHOLD) {
2699 ifp->if_flags &= ~IFF_OACTIVE;
2700 if (num_avail == adapter->num_tx_desc)
2702 else if (num_avail == adapter->num_tx_desc_avail)
2703 ifp->if_timer = EM_TX_TIMEOUT;
2705 adapter->num_tx_desc_avail = num_avail;
2708 /*********************************************************************
2710 * Get a buffer from system mbuf buffer pool.
2712 **********************************************************************/
2714 em_get_buf(int i, struct adapter *adapter, struct mbuf *nmp, int how)
2716 struct mbuf *mp = nmp;
2717 struct em_buffer *rx_buffer;
2722 ifp = &adapter->interface_data.ac_if;
2725 mp = m_getcl(how, MT_DATA, M_PKTHDR);
2727 adapter->mbuf_cluster_failed++;
2730 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2732 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2733 mp->m_data = mp->m_ext.ext_buf;
2737 if (ifp->if_mtu <= ETHERMTU)
2738 m_adj(mp, ETHER_ALIGN);
2740 rx_buffer = &adapter->rx_buffer_area[i];
2743 * Using memory from the mbuf cluster pool, invoke the
2744 * bus_dma machinery to arrange the memory mapping.
2746 error = bus_dmamap_load(adapter->rxtag, rx_buffer->map,
2747 mtod(mp, void *), mp->m_len,
2748 em_dmamap_cb, &paddr, 0);
2753 rx_buffer->m_head = mp;
2754 adapter->rx_desc_base[i].buffer_addr = htole64(paddr);
2755 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD);
2760 /*********************************************************************
2762 * Allocate memory for rx_buffer structures. Since we use one
2763 * rx_buffer per received packet, the maximum number of rx_buffer's
2764 * that we'll need is equal to the number of receive descriptors
2765 * that we've allocated.
2767 **********************************************************************/
2769 em_allocate_receive_structures(struct adapter *adapter)
2772 struct em_buffer *rx_buffer;
2774 size = adapter->num_rx_desc * sizeof(struct em_buffer);
2775 adapter->rx_buffer_area = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
2777 error = bus_dma_tag_create(NULL, /* parent */
2778 1, 0, /* alignment, bounds */
2779 BUS_SPACE_MAXADDR, /* lowaddr */
2780 BUS_SPACE_MAXADDR, /* highaddr */
2781 NULL, NULL, /* filter, filterarg */
2782 MCLBYTES, /* maxsize */
2784 MCLBYTES, /* maxsegsize */
2788 device_printf(adapter->dev, "%s: bus_dma_tag_create failed; "
2789 "error %u\n", __func__, error);
2793 rx_buffer = adapter->rx_buffer_area;
2794 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
2795 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT,
2798 device_printf(adapter->dev,
2799 "%s: bus_dmamap_create failed; "
2800 "error %u\n", __func__, error);
2805 for (i = 0; i < adapter->num_rx_desc; i++) {
2806 error = em_get_buf(i, adapter, NULL, MB_DONTWAIT);
2811 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
2812 BUS_DMASYNC_PREWRITE);
2816 em_free_receive_structures(adapter);
2820 /*********************************************************************
2822 * Allocate and initialize receive structures.
2824 **********************************************************************/
2826 em_setup_receive_structures(struct adapter *adapter)
2830 bzero(adapter->rx_desc_base,
2831 sizeof(struct em_rx_desc) * adapter->num_rx_desc);
2833 error = em_allocate_receive_structures(adapter);
2837 /* Setup our descriptor pointers */
2838 adapter->next_rx_desc_to_check = 0;
2843 /*********************************************************************
2845 * Enable receive unit.
2847 **********************************************************************/
2849 em_initialize_receive_unit(struct adapter *adapter)
2852 uint32_t reg_rxcsum;
2856 INIT_DEBUGOUT("em_initialize_receive_unit: begin");
2858 ifp = &adapter->interface_data.ac_if;
2861 * Make sure receives are disabled while setting
2862 * up the descriptor ring
2864 E1000_WRITE_REG(&adapter->hw, RCTL, 0);
2866 /* Set the Receive Delay Timer Register */
2867 E1000_WRITE_REG(&adapter->hw, RDTR,
2868 adapter->rx_int_delay.value | E1000_RDT_FPDB);
2870 if(adapter->hw.mac_type >= em_82540) {
2871 E1000_WRITE_REG(&adapter->hw, RADV,
2872 adapter->rx_abs_int_delay.value);
2874 /* Set the interrupt throttling rate in 256ns increments */
2875 if (em_int_throttle_ceil) {
2876 E1000_WRITE_REG(&adapter->hw, ITR,
2877 1000000000 / 256 / em_int_throttle_ceil);
2879 E1000_WRITE_REG(&adapter->hw, ITR, 0);
2883 /* Setup the Base and Length of the Rx Descriptor Ring */
2884 bus_addr = adapter->rxdma.dma_paddr;
2885 E1000_WRITE_REG(&adapter->hw, RDLEN, adapter->num_rx_desc *
2886 sizeof(struct em_rx_desc));
2887 E1000_WRITE_REG(&adapter->hw, RDBAH, (uint32_t)(bus_addr >> 32));
2888 E1000_WRITE_REG(&adapter->hw, RDBAL, (uint32_t)bus_addr);
2890 /* Setup the Receive Control Register */
2891 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2892 E1000_RCTL_RDMTS_HALF |
2893 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
2895 if (adapter->hw.tbi_compatibility_on == TRUE)
2896 reg_rctl |= E1000_RCTL_SBP;
2898 switch (adapter->rx_buffer_len) {
2900 case EM_RXBUFFER_2048:
2901 reg_rctl |= E1000_RCTL_SZ_2048;
2903 case EM_RXBUFFER_4096:
2904 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX |
2907 case EM_RXBUFFER_8192:
2908 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX |
2911 case EM_RXBUFFER_16384:
2912 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX |
2917 if (ifp->if_mtu > ETHERMTU)
2918 reg_rctl |= E1000_RCTL_LPE;
2920 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
2921 if ((adapter->hw.mac_type >= em_82543) &&
2922 (ifp->if_capenable & IFCAP_RXCSUM)) {
2923 reg_rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
2924 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
2925 E1000_WRITE_REG(&adapter->hw, RXCSUM, reg_rxcsum);
2928 #ifdef EM_X60_WORKAROUND
2929 if (adapter->hw.mac_type == em_82573)
2930 E1000_WRITE_REG(&adapter->hw, RDTR, 32);
2933 /* Enable Receives */
2934 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
2936 /* Setup the HW Rx Head and Tail Descriptor Pointers */
2937 E1000_WRITE_REG(&adapter->hw, RDH, 0);
2938 E1000_WRITE_REG(&adapter->hw, RDT, adapter->num_rx_desc - 1);
2941 /*********************************************************************
2943 * Free receive related data structures.
2945 **********************************************************************/
2947 em_free_receive_structures(struct adapter *adapter)
2949 struct em_buffer *rx_buffer;
2952 INIT_DEBUGOUT("free_receive_structures: begin");
2954 if (adapter->rx_buffer_area != NULL) {
2955 rx_buffer = adapter->rx_buffer_area;
2956 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
2957 if (rx_buffer->m_head != NULL) {
2958 bus_dmamap_unload(adapter->rxtag,
2960 m_freem(rx_buffer->m_head);
2961 rx_buffer->m_head = NULL;
2963 if (rx_buffer->map != NULL) {
2964 bus_dmamap_destroy(adapter->rxtag,
2966 rx_buffer->map = NULL;
2970 if (adapter->rx_buffer_area != NULL) {
2971 kfree(adapter->rx_buffer_area, M_DEVBUF);
2972 adapter->rx_buffer_area = NULL;
2974 if (adapter->rxtag != NULL) {
2975 bus_dma_tag_destroy(adapter->rxtag);
2976 adapter->rxtag = NULL;
2980 /*********************************************************************
2982 * This routine executes in interrupt context. It replenishes
2983 * the mbufs in the descriptor and sends data which has been
2984 * dma'ed into host memory to upper layer.
2986 * We loop at most count times if count is > 0, or until done if
2989 *********************************************************************/
2991 em_rxeof(struct adapter *adapter, int count)
2995 uint8_t accept_frame = 0;
2997 uint16_t len, desc_len, prev_len_adj;
3000 /* Pointer to the receive descriptor being examined. */
3001 struct em_rx_desc *current_desc;
3003 ifp = &adapter->interface_data.ac_if;
3004 i = adapter->next_rx_desc_to_check;
3005 current_desc = &adapter->rx_desc_base[i];
3007 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
3008 BUS_DMASYNC_POSTREAD);
3010 if (!(current_desc->status & E1000_RXD_STAT_DD))
3013 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) {
3015 mp = adapter->rx_buffer_area[i].m_head;
3016 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map,
3017 BUS_DMASYNC_POSTREAD);
3018 bus_dmamap_unload(adapter->rxtag,
3019 adapter->rx_buffer_area[i].map);
3023 desc_len = le16toh(current_desc->length);
3024 if (current_desc->status & E1000_RXD_STAT_EOP) {
3027 if (desc_len < ETHER_CRC_LEN) {
3029 prev_len_adj = ETHER_CRC_LEN - desc_len;
3031 len = desc_len - ETHER_CRC_LEN;
3038 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
3040 uint32_t pkt_len = desc_len;
3042 if (adapter->fmp != NULL)
3043 pkt_len += adapter->fmp->m_pkthdr.len;
3045 last_byte = *(mtod(mp, caddr_t) + desc_len - 1);
3047 if (TBI_ACCEPT(&adapter->hw, current_desc->status,
3048 current_desc->errors,
3049 pkt_len, last_byte)) {
3050 em_tbi_adjust_stats(&adapter->hw,
3053 adapter->hw.mac_addr);
3062 if (em_get_buf(i, adapter, NULL, MB_DONTWAIT) == ENOBUFS) {
3063 adapter->dropped_pkts++;
3064 em_get_buf(i, adapter, mp, MB_DONTWAIT);
3065 if (adapter->fmp != NULL)
3066 m_freem(adapter->fmp);
3067 adapter->fmp = NULL;
3068 adapter->lmp = NULL;
3072 /* Assign correct length to the current fragment */
3075 if (adapter->fmp == NULL) {
3076 mp->m_pkthdr.len = len;
3077 adapter->fmp = mp; /* Store the first mbuf */
3080 /* Chain mbuf's together */
3082 * Adjust length of previous mbuf in chain if
3083 * we received less than 4 bytes in the last
3086 if (prev_len_adj > 0) {
3087 adapter->lmp->m_len -= prev_len_adj;
3088 adapter->fmp->m_pkthdr.len -= prev_len_adj;
3090 adapter->lmp->m_next = mp;
3091 adapter->lmp = adapter->lmp->m_next;
3092 adapter->fmp->m_pkthdr.len += len;
3096 adapter->fmp->m_pkthdr.rcvif = ifp;
3099 em_receive_checksum(adapter, current_desc,
3101 if (current_desc->status & E1000_RXD_STAT_VP) {
3102 VLAN_INPUT_TAG(adapter->fmp,
3103 (current_desc->special &
3104 E1000_RXD_SPC_VLAN_MASK));
3106 ifp->if_input(ifp, adapter->fmp);
3108 adapter->fmp = NULL;
3109 adapter->lmp = NULL;
3112 adapter->dropped_pkts++;
3113 em_get_buf(i, adapter, mp, MB_DONTWAIT);
3114 if (adapter->fmp != NULL)
3115 m_freem(adapter->fmp);
3116 adapter->fmp = NULL;
3117 adapter->lmp = NULL;
3121 /* Zero out the receive descriptors status. */
3122 current_desc->status = 0;
3124 /* Advance our pointers to the next descriptor. */
3125 if (++i == adapter->num_rx_desc) {
3127 current_desc = adapter->rx_desc_base;
3133 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
3134 BUS_DMASYNC_PREWRITE);
3136 adapter->next_rx_desc_to_check = i;
3138 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */
3140 i = adapter->num_rx_desc - 1;
3142 E1000_WRITE_REG(&adapter->hw, RDT, i);
3145 /*********************************************************************
3147 * Verify that the hardware indicated that the checksum is valid.
3148 * Inform the stack about the status of checksum so that stack
3149 * doesn't spend time verifying the checksum.
3151 *********************************************************************/
3153 em_receive_checksum(struct adapter *adapter,
3154 struct em_rx_desc *rx_desc,
3157 /* 82543 or newer only */
3158 if ((adapter->hw.mac_type < em_82543) ||
3159 /* Ignore Checksum bit is set */
3160 (rx_desc->status & E1000_RXD_STAT_IXSM)) {
3161 mp->m_pkthdr.csum_flags = 0;
3165 if (rx_desc->status & E1000_RXD_STAT_IPCS) {
3167 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) {
3168 /* IP Checksum Good */
3169 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
3170 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3172 mp->m_pkthdr.csum_flags = 0;
3176 if (rx_desc->status & E1000_RXD_STAT_TCPCS) {
3178 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
3179 mp->m_pkthdr.csum_flags |=
3180 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR |
3181 CSUM_FRAG_NOT_CHECKED);
3182 mp->m_pkthdr.csum_data = htons(0xffff);
3189 em_enable_vlans(struct adapter *adapter)
3193 E1000_WRITE_REG(&adapter->hw, VET, ETHERTYPE_VLAN);
3195 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3196 ctrl |= E1000_CTRL_VME;
3197 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3201 em_disable_vlans(struct adapter *adapter)
3205 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3206 ctrl &= ~E1000_CTRL_VME;
3207 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3211 * note: we must call bus_enable_intr() prior to enabling the hardware
3212 * interrupt and bus_disable_intr() after disabling the hardware interrupt
3213 * in order to avoid handler execution races from scheduled interrupt
3217 em_enable_intr(struct adapter *adapter)
3219 struct ifnet *ifp = &adapter->interface_data.ac_if;
3221 if ((ifp->if_flags & IFF_POLLING) == 0) {
3222 lwkt_serialize_handler_enable(ifp->if_serializer);
3223 E1000_WRITE_REG(&adapter->hw, IMS, (IMS_ENABLE_MASK));
3228 em_disable_intr(struct adapter *adapter)
3231 * The first version of 82542 had an errata where when link was forced
3232 * it would stay up even up even if the cable was disconnected.
3233 * Sequence errors were used to detect the disconnect and then the
3234 * driver would unforce the link. This code in the in the ISR. For
3235 * this to work correctly the Sequence error interrupt had to be
3236 * enabled all the time.
3238 if (adapter->hw.mac_type == em_82542_rev2_0) {
3239 E1000_WRITE_REG(&adapter->hw, IMC,
3240 (0xffffffff & ~E1000_IMC_RXSEQ));
3242 E1000_WRITE_REG(&adapter->hw, IMC, 0xffffffff);
3245 lwkt_serialize_handler_disable(adapter->interface_data.ac_if.if_serializer);
3249 em_is_valid_ether_addr(uint8_t *addr)
3251 static const char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3253 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3260 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3262 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2);
3266 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3268 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2);
3272 em_pci_set_mwi(struct em_hw *hw)
3274 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND,
3275 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2);
3279 em_pci_clear_mwi(struct em_hw *hw)
3281 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND,
3282 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2);
3286 em_io_read(struct em_hw *hw, unsigned long port)
3288 struct em_osdep *io = hw->back;
3290 return bus_space_read_4(io->io_bus_space_tag,
3291 io->io_bus_space_handle, port);
3295 em_io_write(struct em_hw *hw, unsigned long port, uint32_t value)
3297 struct em_osdep *io = hw->back;
3299 bus_space_write_4(io->io_bus_space_tag,
3300 io->io_bus_space_handle, port, value);
3304 * We may eventually really do this, but its unnecessary
3305 * for now so we just return unsupported.
3308 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3314 /*********************************************************************
3315 * 82544 Coexistence issue workaround.
3316 * There are 2 issues.
3317 * 1. Transmit Hang issue.
3318 * To detect this issue, following equation can be used...
3319 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3320 * If SUM[3:0] is in between 1 to 4, we will have this issue.
3323 * To detect this issue, following equation can be used...
3324 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3325 * If SUM[3:0] is in between 9 to c, we will have this issue.
3329 * Make sure we do not have ending address as 1,2,3,4(Hang) or
3332 *************************************************************************/
3334 em_fill_descriptors(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array)
3336 /* Since issue is sensitive to length and address.*/
3337 /* Let us first check the address...*/
3338 uint32_t safe_terminator;
3340 desc_array->descriptor[0].address = address;
3341 desc_array->descriptor[0].length = length;
3342 desc_array->elements = 1;
3343 return (desc_array->elements);
3345 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF);
3346 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */
3347 if (safe_terminator == 0 ||
3348 (safe_terminator > 4 && safe_terminator < 9) ||
3349 (safe_terminator > 0xC && safe_terminator <= 0xF)) {
3350 desc_array->descriptor[0].address = address;
3351 desc_array->descriptor[0].length = length;
3352 desc_array->elements = 1;
3353 return (desc_array->elements);
3356 desc_array->descriptor[0].address = address;
3357 desc_array->descriptor[0].length = length - 4;
3358 desc_array->descriptor[1].address = address + (length - 4);
3359 desc_array->descriptor[1].length = 4;
3360 desc_array->elements = 2;
3361 return (desc_array->elements);
3364 /**********************************************************************
3366 * Update the board statistics counters.
3368 **********************************************************************/
3370 em_update_stats_counters(struct adapter *adapter)
3374 if (adapter->hw.media_type == em_media_type_copper ||
3375 (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
3376 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, SYMERRS);
3377 adapter->stats.sec += E1000_READ_REG(&adapter->hw, SEC);
3379 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, CRCERRS);
3380 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, MPC);
3381 adapter->stats.scc += E1000_READ_REG(&adapter->hw, SCC);
3382 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, ECOL);
3384 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, MCC);
3385 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, LATECOL);
3386 adapter->stats.colc += E1000_READ_REG(&adapter->hw, COLC);
3387 adapter->stats.dc += E1000_READ_REG(&adapter->hw, DC);
3388 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, RLEC);
3389 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, XONRXC);
3390 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, XONTXC);
3391 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, XOFFRXC);
3392 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, XOFFTXC);
3393 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, FCRUC);
3394 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, PRC64);
3395 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, PRC127);
3396 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, PRC255);
3397 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, PRC511);
3398 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, PRC1023);
3399 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, PRC1522);
3400 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, GPRC);
3401 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, BPRC);
3402 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, MPRC);
3403 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, GPTC);
3405 /* For the 64-bit byte counters the low dword must be read first. */
3406 /* Both registers clear on the read of the high dword */
3408 adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, GORCL);
3409 adapter->stats.gorch += E1000_READ_REG(&adapter->hw, GORCH);
3410 adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, GOTCL);
3411 adapter->stats.gotch += E1000_READ_REG(&adapter->hw, GOTCH);
3413 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, RNBC);
3414 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, RUC);
3415 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, RFC);
3416 adapter->stats.roc += E1000_READ_REG(&adapter->hw, ROC);
3417 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, RJC);
3419 adapter->stats.torl += E1000_READ_REG(&adapter->hw, TORL);
3420 adapter->stats.torh += E1000_READ_REG(&adapter->hw, TORH);
3421 adapter->stats.totl += E1000_READ_REG(&adapter->hw, TOTL);
3422 adapter->stats.toth += E1000_READ_REG(&adapter->hw, TOTH);
3424 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, TPR);
3425 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, TPT);
3426 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, PTC64);
3427 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, PTC127);
3428 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, PTC255);
3429 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, PTC511);
3430 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, PTC1023);
3431 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, PTC1522);
3432 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, MPTC);
3433 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, BPTC);
3435 if (adapter->hw.mac_type >= em_82543) {
3436 adapter->stats.algnerrc +=
3437 E1000_READ_REG(&adapter->hw, ALGNERRC);
3438 adapter->stats.rxerrc +=
3439 E1000_READ_REG(&adapter->hw, RXERRC);
3440 adapter->stats.tncrs +=
3441 E1000_READ_REG(&adapter->hw, TNCRS);
3442 adapter->stats.cexterr +=
3443 E1000_READ_REG(&adapter->hw, CEXTERR);
3444 adapter->stats.tsctc +=
3445 E1000_READ_REG(&adapter->hw, TSCTC);
3446 adapter->stats.tsctfc +=
3447 E1000_READ_REG(&adapter->hw, TSCTFC);
3449 ifp = &adapter->interface_data.ac_if;
3451 /* Fill out the OS statistics structure */
3452 ifp->if_collisions = adapter->stats.colc;
3456 adapter->dropped_pkts +
3457 adapter->stats.rxerrc +
3458 adapter->stats.crcerrs +
3459 adapter->stats.algnerrc +
3460 adapter->stats.ruc + adapter->stats.roc +
3461 adapter->stats.mpc + adapter->stats.cexterr +
3462 adapter->rx_overruns;
3465 ifp->if_oerrors = adapter->stats.ecol + adapter->stats.latecol +
3466 adapter->watchdog_timeouts;
3470 /**********************************************************************
3472 * This routine is called only when em_display_debug_stats is enabled.
3473 * This routine provides a way to take a look at important statistics
3474 * maintained by the driver and hardware.
3476 **********************************************************************/
3478 em_print_debug_info(struct adapter *adapter)
3480 device_t dev= adapter->dev;
3481 uint8_t *hw_addr = adapter->hw.hw_addr;
3483 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3484 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x\n",
3485 E1000_READ_REG(&adapter->hw, CTRL),
3486 E1000_READ_REG(&adapter->hw, RCTL));
3487 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk\n",
3488 ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff0000) >> 16),
3489 (E1000_READ_REG(&adapter->hw, PBA) & 0xffff));
3490 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3491 adapter->hw.fc_high_water, adapter->hw.fc_low_water);
3492 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3493 E1000_READ_REG(&adapter->hw, TIDV),
3494 E1000_READ_REG(&adapter->hw, TADV));
3495 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3496 E1000_READ_REG(&adapter->hw, RDTR),
3497 E1000_READ_REG(&adapter->hw, RADV));
3498 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n",
3499 (long long)adapter->tx_fifo_wrk_cnt,
3500 (long long)adapter->tx_fifo_reset_cnt);
3501 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3502 E1000_READ_REG(&adapter->hw, TDH),
3503 E1000_READ_REG(&adapter->hw, TDT));
3504 device_printf(dev, "Num Tx descriptors avail = %d\n",
3505 adapter->num_tx_desc_avail);
3506 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3507 adapter->no_tx_desc_avail1);
3508 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3509 adapter->no_tx_desc_avail2);
3510 device_printf(dev, "Std mbuf failed = %ld\n",
3511 adapter->mbuf_alloc_failed);
3512 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3513 adapter->mbuf_cluster_failed);
3514 device_printf(dev, "Driver dropped packets = %ld\n",
3515 adapter->dropped_pkts);
3519 em_print_hw_stats(struct adapter *adapter)
3521 device_t dev= adapter->dev;
3523 device_printf(dev, "Excessive collisions = %lld\n",
3524 (long long)adapter->stats.ecol);
3525 device_printf(dev, "Symbol errors = %lld\n",
3526 (long long)adapter->stats.symerrs);
3527 device_printf(dev, "Sequence errors = %lld\n",
3528 (long long)adapter->stats.sec);
3529 device_printf(dev, "Defer count = %lld\n",
3530 (long long)adapter->stats.dc);
3532 device_printf(dev, "Missed Packets = %lld\n",
3533 (long long)adapter->stats.mpc);
3534 device_printf(dev, "Receive No Buffers = %lld\n",
3535 (long long)adapter->stats.rnbc);
3536 /* RLEC is inaccurate on some hardware, calculate our own. */
3537 device_printf(dev, "Receive Length errors = %lld\n",
3538 (long long)adapter->stats.roc +
3539 (long long)adapter->stats.ruc);
3540 device_printf(dev, "Receive errors = %lld\n",
3541 (long long)adapter->stats.rxerrc);
3542 device_printf(dev, "Crc errors = %lld\n",
3543 (long long)adapter->stats.crcerrs);
3544 device_printf(dev, "Alignment errors = %lld\n",
3545 (long long)adapter->stats.algnerrc);
3546 device_printf(dev, "Carrier extension errors = %lld\n",
3547 (long long)adapter->stats.cexterr);
3548 device_printf(dev, "RX overruns = %lu\n", adapter->rx_overruns);
3549 device_printf(dev, "Watchdog timeouts = %lu\n",
3550 adapter->watchdog_timeouts);
3552 device_printf(dev, "XON Rcvd = %lld\n",
3553 (long long)adapter->stats.xonrxc);
3554 device_printf(dev, "XON Xmtd = %lld\n",
3555 (long long)adapter->stats.xontxc);
3556 device_printf(dev, "XOFF Rcvd = %lld\n",
3557 (long long)adapter->stats.xoffrxc);
3558 device_printf(dev, "XOFF Xmtd = %lld\n",
3559 (long long)adapter->stats.xofftxc);
3561 device_printf(dev, "Good Packets Rcvd = %lld\n",
3562 (long long)adapter->stats.gprc);
3563 device_printf(dev, "Good Packets Xmtd = %lld\n",
3564 (long long)adapter->stats.gptc);
3568 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3572 struct adapter *adapter;
3575 error = sysctl_handle_int(oidp, &result, 0, req);
3577 if (error || !req->newptr)
3581 adapter = (struct adapter *)arg1;
3582 em_print_debug_info(adapter);
3589 em_sysctl_stats(SYSCTL_HANDLER_ARGS)
3593 struct adapter *adapter;
3596 error = sysctl_handle_int(oidp, &result, 0, req);
3598 if (error || !req->newptr)
3602 adapter = (struct adapter *)arg1;
3603 em_print_hw_stats(adapter);
3610 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3612 struct em_int_delay_info *info;
3613 struct adapter *adapter;
3619 info = (struct em_int_delay_info *)arg1;
3620 adapter = info->adapter;
3621 usecs = info->value;
3622 error = sysctl_handle_int(oidp, &usecs, 0, req);
3623 if (error != 0 || req->newptr == NULL)
3625 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535))
3627 info->value = usecs;
3628 ticks = E1000_USECS_TO_TICKS(usecs);
3630 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3631 regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
3632 regval = (regval & ~0xffff) | (ticks & 0xffff);
3633 /* Handle a few special cases. */
3634 switch (info->offset) {
3636 case E1000_82542_RDTR:
3637 regval |= E1000_RDT_FPDB;
3640 case E1000_82542_TIDV:
3642 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
3643 /* Don't write 0 into the TIDV register. */
3646 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3649 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
3650 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3655 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
3656 const char *description, struct em_int_delay_info *info,
3657 int offset, int value)
3659 info->adapter = adapter;
3660 info->offset = offset;
3661 info->value = value;
3662 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
3663 SYSCTL_CHILDREN(adapter->sysctl_tree),
3664 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
3665 info, 0, em_sysctl_int_delay, "I", description);
3669 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3671 struct adapter *adapter = (void *)arg1;
3675 throttle = em_int_throttle_ceil;
3676 error = sysctl_handle_int(oidp, &throttle, 0, req);
3677 if (error || req->newptr == NULL)
3679 if (throttle < 0 || throttle > 1000000000 / 256)
3683 * Set the interrupt throttling rate in 256ns increments,
3684 * recalculate sysctl value assignment to get exact frequency.
3686 throttle = 1000000000 / 256 / throttle;
3687 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3688 em_int_throttle_ceil = 1000000000 / 256 / throttle;
3689 E1000_WRITE_REG(&adapter->hw, ITR, throttle);
3690 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3692 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3693 em_int_throttle_ceil = 0;
3694 E1000_WRITE_REG(&adapter->hw, ITR, 0);
3695 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3697 device_printf(adapter->dev, "Interrupt moderation set to %d/sec\n",
3698 em_int_throttle_ceil);