1 @c Copyright (C) 1991-2014 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
7 @chapter MIPS Dependent Features
10 @node Machine Dependencies
11 @chapter MIPS Dependent Features
14 @cindex MIPS processor
15 @sc{gnu} @code{@value{AS}} for MIPS architectures supports several
16 different MIPS processors, and MIPS ISA levels I through V, MIPS32,
17 and MIPS64. For information about the MIPS instruction set, see
18 @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall).
19 For an overview of MIPS assembly conventions, see ``Appendix D:
20 Assembly Language Programming'' in the same work.
23 * MIPS Options:: Assembler options
24 * MIPS Macros:: High-level assembly macros
25 * MIPS Symbol Sizes:: Directives to override the size of symbols
26 * MIPS Small Data:: Controlling the use of small data accesses
27 * MIPS ISA:: Directives to override the ISA level
28 * MIPS assembly options:: Directives to control code generation
29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
30 * MIPS insn:: Directive to mark data as an instruction
31 * MIPS FP ABIs:: Marking which FP ABI is in use
32 * MIPS NaN Encodings:: Directives to record which NaN encoding is being used
33 * MIPS Option Stack:: Directives to save and restore options
34 * MIPS ASE Instruction Generation Overrides:: Directives to control
35 generation of MIPS ASE instructions
36 * MIPS Floating-Point:: Directives to override floating-point options
37 * MIPS Syntax:: MIPS specific syntactical considerations
41 @section Assembler options
43 The MIPS configurations of @sc{gnu} @code{@value{AS}} support these
47 @cindex @code{-G} option (MIPS)
49 Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes.
50 @xref{MIPS Small Data,, Controlling the use of small data accesses}.
52 @cindex @code{-EB} option (MIPS)
53 @cindex @code{-EL} option (MIPS)
54 @cindex MIPS big-endian output
55 @cindex MIPS little-endian output
56 @cindex big-endian output, MIPS
57 @cindex little-endian output, MIPS
60 Any MIPS configuration of @code{@value{AS}} can select big-endian or
61 little-endian output at run time (unlike the other @sc{gnu} development
62 tools, which must be configured for one or the other). Use @samp{-EB}
63 to select big-endian output, and @samp{-EL} for little-endian.
66 @cindex PIC selection, MIPS
67 @cindex @option{-KPIC} option, MIPS
68 Generate SVR4-style PIC. This option tells the assembler to generate
69 SVR4-style position-independent macro expansions. It also tells the
70 assembler to mark the output file as PIC.
73 @cindex @option{-mvxworks-pic} option, MIPS
74 Generate VxWorks PIC. This option tells the assembler to generate
75 VxWorks-style position-independent macro expansions.
77 @cindex MIPS architecture options
93 Generate code for a particular MIPS Instruction Set Architecture level.
94 @samp{-mips1} corresponds to the R2000 and R3000 processors,
95 @samp{-mips2} to the R6000 processor, @samp{-mips3} to the
96 R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors.
97 @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3},
98 @samp{-mips32r5}, @samp{-mips32r6}, @samp{-mips64}, @samp{-mips64r2},
99 @samp{-mips64r3}, @samp{-mips64r5}, and @samp{-mips64r6} correspond to
100 generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32
101 Release 5, MIPS32 Release 6, MIPS64, and MIPS64 Release 2, MIPS64
102 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors,
103 respectively. You can also switch instruction sets during the assembly;
104 see @ref{MIPS ISA, Directives to override the ISA level}.
108 Some macros have different expansions for 32-bit and 64-bit registers.
109 The register sizes are normally inferred from the ISA and ABI, but these
110 flags force a certain group of registers to be treated as 32 bits wide at
111 all times. @samp{-mgp32} controls the size of general-purpose registers
112 and @samp{-mfp32} controls the size of floating-point registers.
114 The @code{.set gp=32} and @code{.set fp=32} directives allow the size
115 of registers to be changed for parts of an object. The default value is
116 restored by @code{.set gp=default} and @code{.set fp=default}.
118 On some MIPS variants there is a 32-bit mode flag; when this flag is
119 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
120 save the 32-bit registers on a context switch, so it is essential never
121 to use the 64-bit registers.
125 Assume that 64-bit registers are available. This is provided in the
126 interests of symmetry with @samp{-mgp32} and @samp{-mfp32}.
128 The @code{.set gp=64} and @code{.set fp=64} directives allow the size
129 of registers to be changed for parts of an object. The default value is
130 restored by @code{.set gp=default} and @code{.set fp=default}.
133 Make no assumptions about whether 32-bit or 64-bit floating-point
134 registers are available. This is provided to support having modules
135 compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can
136 only be used with MIPS II and above.
138 The @code{.set fp=xx} directive allows a part of an object to be marked
139 as not making assumptions about 32-bit or 64-bit FP registers. The
140 default value is restored by @code{.set fp=default}.
143 @itemx -mno-odd-spreg
144 Enable use of floating-point operations on odd-numbered single-precision
145 registers when supported by the ISA. @samp{-mfpxx} implies
146 @samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg}
150 Generate code for the MIPS 16 processor. This is equivalent to putting
151 @code{.set mips16} at the start of the assembly file. @samp{-no-mips16}
152 turns off this option.
155 @itemx -mno-micromips
156 Generate code for the microMIPS processor. This is equivalent to putting
157 @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips}
158 turns off this option. This is equivalent to putting @code{.set nomicromips}
159 at the start of the assembly file.
162 @itemx -mno-smartmips
163 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
164 provides a number of new instructions which target smartcard and
165 cryptographic applications. This is equivalent to putting
166 @code{.set smartmips} at the start of the assembly file.
167 @samp{-mno-smartmips} turns off this option.
171 Generate code for the MIPS-3D Application Specific Extension.
172 This tells the assembler to accept MIPS-3D instructions.
173 @samp{-no-mips3d} turns off this option.
177 Generate code for the MDMX Application Specific Extension.
178 This tells the assembler to accept MDMX instructions.
179 @samp{-no-mdmx} turns off this option.
183 Generate code for the DSP Release 1 Application Specific Extension.
184 This tells the assembler to accept DSP Release 1 instructions.
185 @samp{-mno-dsp} turns off this option.
189 Generate code for the DSP Release 2 Application Specific Extension.
190 This option implies -mdsp.
191 This tells the assembler to accept DSP Release 2 instructions.
192 @samp{-mno-dspr2} turns off this option.
196 Generate code for the MT Application Specific Extension.
197 This tells the assembler to accept MT instructions.
198 @samp{-mno-mt} turns off this option.
202 Generate code for the MCU Application Specific Extension.
203 This tells the assembler to accept MCU instructions.
204 @samp{-mno-mcu} turns off this option.
208 Generate code for the MIPS SIMD Architecture Extension.
209 This tells the assembler to accept MSA instructions.
210 @samp{-mno-msa} turns off this option.
214 Generate code for the MIPS eXtended Physical Address (XPA) Extension.
215 This tells the assembler to accept XPA instructions.
216 @samp{-mno-xpa} turns off this option.
220 Generate code for the Virtualization Application Specific Extension.
221 This tells the assembler to accept Virtualization instructions.
222 @samp{-mno-virt} turns off this option.
226 Only use 32-bit instruction encodings when generating code for the
227 microMIPS processor. This option inhibits the use of any 16-bit
228 instructions. This is equivalent to putting @code{.set insn32} at
229 the start of the assembly file. @samp{-mno-insn32} turns off this
230 option. This is equivalent to putting @code{.set noinsn32} at the
231 start of the assembly file. By default @samp{-mno-insn32} is
232 selected, allowing all instructions to be used.
236 Cause nops to be inserted if the read of the destination register
237 of an mfhi or mflo instruction occurs in the following two instructions.
240 @itemx -mno-fix-rm7000
241 Cause nops to be inserted if a dmult or dmultu instruction is
242 followed by a load instruction.
244 @item -mfix-loongson2f-jump
245 @itemx -mno-fix-loongson2f-jump
246 Eliminate instruction fetch from outside 256M region to work around the
247 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
248 the kernel may crash. The issue has been solved in latest processor
249 batches, but this fix has no side effect to them.
251 @item -mfix-loongson2f-nop
252 @itemx -mno-fix-loongson2f-nop
253 Replace nops by @code{or at,at,zero} to work around the Loongson2F
254 @samp{nop} errata. Without it, under extreme cases, the CPU might
255 deadlock. The issue has been solved in later Loongson2F batches, but
256 this fix has no side effect to them.
259 @itemx -mno-fix-vr4120
260 Insert nops to work around certain VR4120 errata. This option is
261 intended to be used on GCC-generated code: it is not designed to catch
262 all problems in hand-written assembler code.
265 @itemx -mno-fix-vr4130
266 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
270 Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
273 @itemx -mno-fix-cn63xxp1
274 Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
275 certain CN63XXP1 errata.
279 Generate code for the LSI R4010 chip. This tells the assembler to
280 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
281 etc.), and to not schedule @samp{nop} instructions around accesses to
282 the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this
287 Generate code for the MIPS R4650 chip. This tells the assembler to accept
288 the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop}
289 instructions around accesses to the @samp{HI} and @samp{LO} registers.
290 @samp{-no-m4650} turns off this option.
296 For each option @samp{-m@var{nnnn}}, generate code for the MIPS
297 R@var{nnnn} chip. This tells the assembler to accept instructions
298 specific to that chip, and to schedule for that chip's hazards.
300 @item -march=@var{cpu}
301 Generate code for a particular MIPS CPU. It is exactly equivalent to
302 @samp{-m@var{cpu}}, except that there are more value of @var{cpu}
303 understood. Valid @var{cpu} value are:
389 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
390 accepted as synonyms for @samp{@var{n}f1_1}. These values are
393 @item -mtune=@var{cpu}
394 Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are
395 identical to @samp{-march=@var{cpu}}.
397 @item -mabi=@var{abi}
398 Record which ABI the source code uses. The recognized arguments
399 are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}.
405 Equivalent to adding @code{.set sym32} or @code{.set nosym32} to
406 the beginning of the assembler input. @xref{MIPS Symbol Sizes}.
408 @cindex @code{-nocpp} ignored (MIPS)
410 This option is ignored. It is accepted for command-line compatibility with
411 other assemblers, which use it to turn off C style preprocessing. With
412 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
413 @sc{gnu} assembler itself never runs the C preprocessor.
417 Disable or enable floating-point instructions. Note that by default
418 floating-point instructions are always allowed even with CPU targets
419 that don't have support for these instructions.
422 @itemx -mdouble-float
423 Disable or enable double-precision floating-point operations. Note
424 that by default double-precision floating-point operations are always
425 allowed even with CPU targets that don't have support for these
428 @item --construct-floats
429 @itemx --no-construct-floats
430 The @code{--no-construct-floats} option disables the construction of
431 double width floating point constants by loading the two halves of the
432 value into the two single width floating point registers that make up
433 the double width register. This feature is useful if the processor
434 support the FR bit in its status register, and this bit is known (by
435 the programmer) to be set. This bit prevents the aliasing of the double
436 width register by the single width registers.
438 By default @code{--construct-floats} is selected, allowing construction
439 of these floating point constants.
442 @itemx --no-relax-branch
443 The @samp{--relax-branch} option enables the relaxation of out-of-range
444 branches. Any branches whose target cannot be reached directly are
445 converted to a small instruction sequence including an inverse-condition
446 branch to the physically next instruction, and a jump to the original
447 target is inserted between the two instructions. In PIC code the jump
448 will involve further instructions for address calculation.
450 The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T},
451 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
452 relaxation, because they have no complementing counterparts. They could
453 be relaxed with the use of a longer sequence involving another branch,
454 however this has not been implemented and if their target turns out of
455 reach, they produce an error even if branch relaxation is enabled.
457 Also no MIPS16 branches are ever relaxed.
459 By default @samp{--no-relax-branch} is selected, causing any out-of-range
460 branches to produce an error.
462 @cindex @option{-mnan=} command line option, MIPS
463 @item -mnan=@var{encoding}
464 This option indicates whether the source code uses the IEEE 2008
465 NaN encoding (@option{-mnan=2008}) or the original MIPS encoding
466 (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan}
467 directive to the beginning of the source file. @xref{MIPS NaN Encodings}.
469 @option{-mnan=legacy} is the default if no @option{-mnan} option or
470 @code{.nan} directive is used.
474 @c FIXME! (1) reflect these options (next item too) in option summaries;
475 @c (2) stop teasing, say _which_ instructions expanded _how_.
476 @code{@value{AS}} automatically macro expands certain division and
477 multiplication instructions to check for overflow and division by zero. This
478 option causes @code{@value{AS}} to generate code to take a trap exception
479 rather than a break exception when an error is detected. The trap instructions
480 are only supported at Instruction Set Architecture level 2 and higher.
484 Generate code to take a break exception rather than a trap exception when an
485 error is detected. This is the default.
489 Control generation of @code{.pdr} sections. Off by default on IRIX, on
494 When generating code using the Unix calling conventions (selected by
495 @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code
496 which can go into a shared library. The @samp{-mno-shared} option
497 tells gas to generate code which uses the calling convention, but can
498 not go into a shared library. The resulting code is slightly more
499 efficient. This option only affects the handling of the
500 @samp{.cpload} and @samp{.cpsetup} pseudo-ops.
504 @section High-level assembly macros
506 MIPS assemblers have traditionally provided a wider range of
507 instructions than the MIPS architecture itself. These extra
508 instructions are usually referred to as ``macro'' instructions
509 @footnote{The term ``macro'' is somewhat overloaded here, since
510 these macros have no relation to those defined by @code{.macro},
511 @pxref{Macro,, @code{.macro}}.}.
513 Some MIPS macro instructions extend an underlying architectural instruction
514 while others are entirely new. An example of the former type is @code{and},
515 which allows the third operand to be either a register or an arbitrary
516 immediate value. Examples of the latter type include @code{bgt}, which
517 branches to the third operand when the first operand is greater than
518 the second operand, and @code{ulh}, which implements an unaligned
521 One of the most common extensions provided by macros is to expand
522 memory offsets to the full address range (32 or 64 bits) and to allow
523 symbolic offsets such as @samp{my_data + 4} to be used in place of
524 integer constants. For example, the architectural instruction
525 @code{lbu} allows only a signed 16-bit offset, whereas the macro
526 @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}.
527 The implementation of these symbolic offsets depends on several factors,
528 such as whether the assembler is generating SVR4-style PIC (selected by
529 @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols
530 (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}),
531 and the small data limit (@pxref{MIPS Small Data,, Controlling the use
532 of small data accesses}).
534 @kindex @code{.set macro}
535 @kindex @code{.set nomacro}
536 Sometimes it is undesirable to have one assembly instruction expand
537 to several machine instructions. The directive @code{.set nomacro}
538 tells the assembler to warn when this happens. @code{.set macro}
539 restores the default behavior.
541 @cindex @code{at} register, MIPS
542 @kindex @code{.set at=@var{reg}}
543 Some macro instructions need a temporary register to store intermediate
544 results. This register is usually @code{$1}, also known as @code{$at},
545 but it can be changed to any core register @var{reg} using
546 @code{.set at=@var{reg}}. Note that @code{$at} always refers
547 to @code{$1} regardless of which register is being used as the
550 @kindex @code{.set at}
551 @kindex @code{.set noat}
552 Implicit uses of the temporary register in macros could interfere with
553 explicit uses in the assembly code. The assembler therefore warns
554 whenever it sees an explicit use of the temporary register. The directive
555 @code{.set noat} silences this warning while @code{.set at} restores
556 the default behavior. It is safe to use @code{.set noat} while
557 @code{.set nomacro} is in effect since single-instruction macros
558 never need a temporary register.
560 Note that while the @sc{gnu} assembler provides these macros for compatibility,
561 it does not make any attempt to optimize them with the surrounding code.
563 @node MIPS Symbol Sizes
564 @section Directives to override the size of symbols
566 @kindex @code{.set sym32}
567 @kindex @code{.set nosym32}
568 The n64 ABI allows symbols to have any 64-bit value. Although this
569 provides a great deal of flexibility, it means that some macros have
570 much longer expansions than their 32-bit counterparts. For example,
571 the non-PIC expansion of @samp{dla $4,sym} is usually:
576 daddiu $4,$4,%higher(sym)
577 daddiu $1,$1,%lo(sym)
582 whereas the 32-bit expansion is simply:
586 daddiu $4,$4,%lo(sym)
589 n64 code is sometimes constructed in such a way that all symbolic
590 constants are known to have 32-bit values, and in such cases, it's
591 preferable to use the 32-bit expansion instead of the 64-bit
594 You can use the @code{.set sym32} directive to tell the assembler
595 that, from this point on, all expressions of the form
596 @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}}
597 have 32-bit values. For example:
606 will cause the assembler to treat @samp{sym}, @code{sym+16} and
607 @code{sym+0x8000} as 32-bit values. The handling of non-symbolic
608 addresses is not affected.
610 The directive @code{.set nosym32} ends a @code{.set sym32} block and
611 reverts to the normal behavior. It is also possible to change the
612 symbol size using the command-line options @option{-msym32} and
615 These options and directives are always accepted, but at present,
616 they have no effect for anything other than n64.
618 @node MIPS Small Data
619 @section Controlling the use of small data accesses
621 @c This section deliberately glosses over the possibility of using -G
622 @c in SVR4-style PIC, as could be done on IRIX. We don't support that.
623 @cindex small data, MIPS
624 @cindex @code{gp} register, MIPS
625 It often takes several instructions to load the address of a symbol.
626 For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion
627 of @samp{dla $4,addr} is usually:
631 daddiu $4,$4,%lo(addr)
634 The sequence is much longer when @samp{addr} is a 64-bit symbol.
635 @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}.
637 In order to cut down on this overhead, most embedded MIPS systems
638 set aside a 64-kilobyte ``small data'' area and guarantee that all
639 data of size @var{n} and smaller will be placed in that area.
640 The limit @var{n} is passed to both the assembler and the linker
641 using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,,
642 Assembler options}. Note that the same value of @var{n} must be used
643 when linking and when assembling all input files to the link; any
644 inconsistency could cause a relocation overflow error.
646 The size of an object in the @code{.bss} section is set by the
647 @code{.comm} or @code{.lcomm} directive that defines it. The size of
648 an external object may be set with the @code{.extern} directive. For
649 example, @samp{.extern sym,4} declares that the object at @code{sym}
650 is 4 bytes in length, while leaving @code{sym} otherwise undefined.
652 When no @option{-G} option is given, the default limit is 8 bytes.
653 The option @option{-G 0} prevents any data from being automatically
656 It is also possible to mark specific objects as small by putting them
657 in the special sections @code{.sdata} and @code{.sbss}, which are
658 ``small'' counterparts of @code{.data} and @code{.bss} respectively.
659 The toolchain will treat such data as small regardless of the
662 On startup, systems that support a small data area are expected to
663 initialize register @code{$28}, also known as @code{$gp}, in such a
664 way that small data can be accessed using a 16-bit offset from that
665 register. For example, when @samp{addr} is small data,
666 the @samp{dla $4,addr} instruction above is equivalent to:
669 daddiu $4,$28,%gp_rel(addr)
672 Small data is not supported for SVR4-style PIC.
675 @section Directives to override the ISA level
677 @cindex MIPS ISA override
678 @kindex @code{.set mips@var{n}}
679 @sc{gnu} @code{@value{AS}} supports an additional directive to change
680 the MIPS Instruction Set Architecture level on the fly: @code{.set
681 mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3,
682 32r5, 32r6, 64, 64r2, 64r3, 64r5 or 64r6.
683 The values other than 0 make the assembler accept instructions
684 for the corresponding ISA level, from that point on in the
685 assembly. @code{.set mips@var{n}} affects not only which instructions
686 are permitted, but also how certain macros are expanded. @code{.set
687 mips0} restores the ISA level to its original level: either the
688 level you selected with command line options, or the default for your
689 configuration. You can use this feature to permit specific MIPS III
690 instructions while assembling in 32 bit mode. Use this directive with
693 @cindex MIPS CPU override
694 @kindex @code{.set arch=@var{cpu}}
695 The @code{.set arch=@var{cpu}} directive provides even finer control.
696 It changes the effective CPU target and allows the assembler to use
697 instructions specific to a particular CPU. All CPUs supported by the
698 @samp{-march} command line option are also selectable by this directive.
699 The original value is restored by @code{.set arch=default}.
701 The directive @code{.set mips16} puts the assembler into MIPS 16 mode,
702 in which it will assemble instructions for the MIPS 16 processor. Use
703 @code{.set nomips16} to return to normal 32 bit mode.
705 Traditional MIPS assemblers do not support this directive.
707 The directive @code{.set micromips} puts the assembler into microMIPS mode,
708 in which it will assemble instructions for the microMIPS processor. Use
709 @code{.set nomicromips} to return to normal 32 bit mode.
711 Traditional MIPS assemblers do not support this directive.
713 @node MIPS assembly options
714 @section Directives to control code generation
716 @cindex MIPS directives to override command line options
717 @kindex @code{.module}
718 The @code{.module} directive allows command line options to be set directly
719 from assembly. The format of the directive matches the @code{.set}
720 directive but only those options which are relevant to a whole module are
721 supported. The effect of a @code{.module} directive is the same as the
722 corresponding command line option. Where @code{.set} directives support
723 returning to a default then the @code{.module} directives do not as they
726 These module-level directives must appear first in assembly.
728 Traditional MIPS assemblers do not support this directive.
730 @cindex MIPS 32-bit microMIPS instruction generation override
731 @kindex @code{.set insn32}
732 @kindex @code{.set noinsn32}
733 The directive @code{.set insn32} makes the assembler only use 32-bit
734 instruction encodings when generating code for the microMIPS processor.
735 This directive inhibits the use of any 16-bit instructions from that
736 point on in the assembly. The @code{.set noinsn32} directive allows
737 16-bit instructions to be accepted.
739 Traditional MIPS assemblers do not support this directive.
741 @node MIPS autoextend
742 @section Directives for extending MIPS 16 bit instructions
744 @kindex @code{.set autoextend}
745 @kindex @code{.set noautoextend}
746 By default, MIPS 16 instructions are automatically extended to 32 bits
747 when necessary. The directive @code{.set noautoextend} will turn this
748 off. When @code{.set noautoextend} is in effect, any 32 bit instruction
749 must be explicitly extended with the @code{.e} modifier (e.g.,
750 @code{li.e $4,1000}). The directive @code{.set autoextend} may be used
751 to once again automatically extend instructions when necessary.
753 This directive is only meaningful when in MIPS 16 mode. Traditional
754 MIPS assemblers do not support this directive.
757 @section Directive to mark data as an instruction
760 The @code{.insn} directive tells @code{@value{AS}} that the following
761 data is actually instructions. This makes a difference in MIPS 16 and
762 microMIPS modes: when loading the address of a label which precedes
763 instructions, @code{@value{AS}} automatically adds 1 to the value, so
764 that jumping to the loaded address will do the right thing.
766 @kindex @code{.global}
767 The @code{.global} and @code{.globl} directives supported by
768 @code{@value{AS}} will by default mark the symbol as pointing to a
769 region of data not code. This means that, for example, any
770 instructions following such a symbol will not be disassembled by
771 @code{objdump} as it will regard them as data. To change this
772 behavior an optional section name can be placed after the symbol name
773 in the @code{.global} directive. If this section exists and is known
774 to be a code section, then the symbol will be marked as pointing at
775 code not data. Ie the syntax for the directive is:
777 @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
779 Here is a short example:
782 .global foo .text, bar, baz .data
793 @section Directives to control the FP ABI
795 * MIPS FP ABI History:: History of FP ABIs
796 * MIPS FP ABI Variants:: Supported FP ABIs
797 * MIPS FP ABI Selection:: Automatic selection of FP ABI
798 * MIPS FP ABI Compatibility:: Linking different FP ABI variants
801 @node MIPS FP ABI History
802 @subsection History of FP ABIs
803 @cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS
804 @cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS
805 The MIPS ABIs support a variety of different floating-point extensions
806 where calling-convention and register sizes vary for floating-point data.
807 The extensions exist to support a wide variety of optional architecture
808 features. The resulting ABI variants are generally incompatible with each
809 other and must be tracked carefully.
811 Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}}
812 directive is used to indicate which ABI is in use by a specific module.
813 It was then left to the user to ensure that command line options and the
814 selected ABI were compatible with some potential for inconsistencies.
816 @node MIPS FP ABI Variants
817 @subsection Supported FP ABIs
818 The supported floating-point ABI variants are:
821 @item 0 - No floating-point
822 This variant is used to indicate that floating-point is not used within
823 the module at all and therefore has no impact on the ABI. This is the
826 @item 1 - Double-precision
827 This variant indicates that double-precision support is used. For 64-bit
828 ABIs this means that 64-bit wide floating-point registers are required.
829 For 32-bit ABIs this means that 32-bit wide floating-point registers are
830 required and double-precision operations use pairs of registers.
832 @item 2 - Single-precision
833 This variant indicates that single-precision support is used. Double
834 precision operations will be supported via soft-float routines.
837 This variant indicates that although floating-point support is used all
838 operations are emulated in software. This means the ABI is modified to
839 pass all floating-point data in general-purpose registers.
842 This variant existed as an initial attempt at supporting 64-bit wide
843 floating-point registers for O32 ABI on a MIPS32r2 CPU. This has been
844 superseded by 5, 6 and 7.
846 @item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU
847 This variant is used by 32-bit ABIs to indicate that the floating-point
848 code in the module has been designed to operate correctly with either
849 32-bit wide or 64-bit wide floating-point registers. Double-precision
850 support is used. Only O32 currently supports this variant and requires
851 a minimum architecture of MIPS II.
853 @item 6 - Double-precision 32-bit FPU, 64-bit FPU
854 This variant is used by 32-bit ABIs to indicate that the floating-point
855 code in the module requires 64-bit wide floating-point registers.
856 Double-precision support is used. Only O32 currently supports this
857 variant and requires a minimum architecture of MIPS32r2.
859 @item 7 - Double-precision compat 32-bit FPU, 64-bit FPU
860 This variant is used by 32-bit ABIs to indicate that the floating-point
861 code in the module requires 64-bit wide floating-point registers.
862 Double-precision support is used. This differs from the previous ABI
863 as it restricts use of odd-numbered single-precision registers. Only
864 O32 currently supports this variant and requires a minimum architecture
868 @node MIPS FP ABI Selection
869 @subsection Automatic selection of FP ABI
870 @cindex @code{.module fp=@var{nn}} directive, MIPS
871 In order to simplify and add safety to the process of selecting the
872 correct floating-point ABI, the assembler will automatically infer the
873 correct @code{.gnu_attribute 4, @var{n}} directive based on command line
874 options and @code{.module} overrides. Where an explicit
875 @code{.gnu_attribute 4, @var{n}} directive has been seen then a warning
876 will be raised if it does not match an inferred setting.
878 The floating-point ABI is inferred as follows. If @samp{-msoft-float}
879 has been used the module will be marked as soft-float. If
880 @samp{-msingle-float} has been used then the module will be marked as
881 single-precision. The remaining ABIs are then selected based
882 on the FP register width. Double-precision is selected if the width
883 of GP and FP registers match and the special double-precision variants
884 for 32-bit ABIs are then selected depending on @samp{-mfpxx},
885 @samp{-mfp64} and @samp{-mno-odd-spreg}.
887 @node MIPS FP ABI Compatibility
888 @subsection Linking different FP ABI variants
889 Modules using the default FP ABI (no floating-point) can be linked with
890 any other (singular) FP ABI variant.
892 Special compatibility support exists for O32 with the four
893 double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically
894 designed to be compatible with the standard double-precision ABI and the
895 @samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be
896 built as @samp{-mfpxx} to ensure the maximum compatibility with other
897 modules produced for more specific needs. The only FP ABIs which cannot
898 be linked together are the standard double-precision ABI and the full
899 @samp{-mfp64} ABI with @samp{-modd-spreg}.
901 @node MIPS NaN Encodings
902 @section Directives to record which NaN encoding is being used
904 @cindex MIPS IEEE 754 NaN data encoding selection
905 @cindex @code{.nan} directive, MIPS
906 The IEEE 754 floating-point standard defines two types of not-a-number
907 (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version
908 of the standard did not specify how these two types should be
909 distinguished. Most implementations followed the i387 model, in which
910 the first bit of the significand is set for quiet NaNs and clear for
911 signalling NaNs. However, the original MIPS implementation assigned the
912 opposite meaning to the bit, so that it was set for signalling NaNs and
913 clear for quiet NaNs.
915 The 2008 revision of the standard formally suggested the i387 choice
916 and as from Sep 2012 the current release of the MIPS architecture
917 therefore optionally supports that form. Code that uses one NaN encoding
918 would usually be incompatible with code that uses the other NaN encoding,
919 so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which
920 encoding is being used.
922 Assembly files can use the @code{.nan} directive to select between the
923 two encodings. @samp{.nan 2008} says that the assembly file uses the
924 IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses
925 the original MIPS encoding. If several @code{.nan} directives are given,
926 the final setting is the one that is used.
928 The command-line options @option{-mnan=legacy} and @option{-mnan=2008}
929 can be used instead of @samp{.nan legacy} and @samp{.nan 2008}
930 respectively. However, any @code{.nan} directive overrides the
931 command-line setting.
933 @samp{.nan legacy} is the default if no @code{.nan} directive or
934 @option{-mnan} option is given.
936 Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and
937 therefore these directives do not affect code generation. They simply
938 control the setting of the @code{EF_MIPS_NAN2008} flag.
940 Traditional MIPS assemblers do not support these directives.
942 @node MIPS Option Stack
943 @section Directives to save and restore options
945 @cindex MIPS option stack
946 @kindex @code{.set push}
947 @kindex @code{.set pop}
948 The directives @code{.set push} and @code{.set pop} may be used to save
949 and restore the current settings for all the options which are
950 controlled by @code{.set}. The @code{.set push} directive saves the
951 current settings on a stack. The @code{.set pop} directive pops the
952 stack and restores the settings.
954 These directives can be useful inside an macro which must change an
955 option such as the ISA level or instruction reordering but does not want
956 to change the state of the code which invoked the macro.
958 Traditional MIPS assemblers do not support these directives.
960 @node MIPS ASE Instruction Generation Overrides
961 @section Directives to control generation of MIPS ASE instructions
963 @cindex MIPS MIPS-3D instruction generation override
964 @kindex @code{.set mips3d}
965 @kindex @code{.set nomips3d}
966 The directive @code{.set mips3d} makes the assembler accept instructions
967 from the MIPS-3D Application Specific Extension from that point on
968 in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D
969 instructions from being accepted.
971 @cindex SmartMIPS instruction generation override
972 @kindex @code{.set smartmips}
973 @kindex @code{.set nosmartmips}
974 The directive @code{.set smartmips} makes the assembler accept
975 instructions from the SmartMIPS Application Specific Extension to the
976 MIPS32 ISA from that point on in the assembly. The
977 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
980 @cindex MIPS MDMX instruction generation override
981 @kindex @code{.set mdmx}
982 @kindex @code{.set nomdmx}
983 The directive @code{.set mdmx} makes the assembler accept instructions
984 from the MDMX Application Specific Extension from that point on
985 in the assembly. The @code{.set nomdmx} directive prevents MDMX
986 instructions from being accepted.
988 @cindex MIPS DSP Release 1 instruction generation override
989 @kindex @code{.set dsp}
990 @kindex @code{.set nodsp}
991 The directive @code{.set dsp} makes the assembler accept instructions
992 from the DSP Release 1 Application Specific Extension from that point
993 on in the assembly. The @code{.set nodsp} directive prevents DSP
994 Release 1 instructions from being accepted.
996 @cindex MIPS DSP Release 2 instruction generation override
997 @kindex @code{.set dspr2}
998 @kindex @code{.set nodspr2}
999 The directive @code{.set dspr2} makes the assembler accept instructions
1000 from the DSP Release 2 Application Specific Extension from that point
1001 on in the assembly. This directive implies @code{.set dsp}. The
1002 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
1005 @cindex MIPS MT instruction generation override
1006 @kindex @code{.set mt}
1007 @kindex @code{.set nomt}
1008 The directive @code{.set mt} makes the assembler accept instructions
1009 from the MT Application Specific Extension from that point on
1010 in the assembly. The @code{.set nomt} directive prevents MT
1011 instructions from being accepted.
1013 @cindex MIPS MCU instruction generation override
1014 @kindex @code{.set mcu}
1015 @kindex @code{.set nomcu}
1016 The directive @code{.set mcu} makes the assembler accept instructions
1017 from the MCU Application Specific Extension from that point on
1018 in the assembly. The @code{.set nomcu} directive prevents MCU
1019 instructions from being accepted.
1021 @cindex MIPS SIMD Architecture instruction generation override
1022 @kindex @code{.set msa}
1023 @kindex @code{.set nomsa}
1024 The directive @code{.set msa} makes the assembler accept instructions
1025 from the MIPS SIMD Architecture Extension from that point on
1026 in the assembly. The @code{.set nomsa} directive prevents MSA
1027 instructions from being accepted.
1029 @cindex Virtualization instruction generation override
1030 @kindex @code{.set virt}
1031 @kindex @code{.set novirt}
1032 The directive @code{.set virt} makes the assembler accept instructions
1033 from the Virtualization Application Specific Extension from that point
1034 on in the assembly. The @code{.set novirt} directive prevents Virtualization
1035 instructions from being accepted.
1037 @cindex MIPS eXtended Physical Address (XPA) instruction generation override
1038 @kindex @code{.set xpa}
1039 @kindex @code{.set noxpa}
1040 The directive @code{.set xpa} makes the assembler accept instructions
1041 from the XPA Extension from that point on in the assembly. The
1042 @code{.set noxpa} directive prevents XPA instructions from being accepted.
1044 Traditional MIPS assemblers do not support these directives.
1046 @node MIPS Floating-Point
1047 @section Directives to override floating-point options
1049 @cindex Disable floating-point instructions
1050 @kindex @code{.set softfloat}
1051 @kindex @code{.set hardfloat}
1052 The directives @code{.set softfloat} and @code{.set hardfloat} provide
1053 finer control of disabling and enabling float-point instructions.
1054 These directives always override the default (that hard-float
1055 instructions are accepted) or the command-line options
1056 (@samp{-msoft-float} and @samp{-mhard-float}).
1058 @cindex Disable single-precision floating-point operations
1059 @kindex @code{.set singlefloat}
1060 @kindex @code{.set doublefloat}
1061 The directives @code{.set singlefloat} and @code{.set doublefloat}
1062 provide finer control of disabling and enabling double-precision
1063 float-point operations. These directives always override the default
1064 (that double-precision operations are accepted) or the command-line
1065 options (@samp{-msingle-float} and @samp{-mdouble-float}).
1067 Traditional MIPS assemblers do not support these directives.
1070 @section Syntactical considerations for the MIPS assembler
1072 * MIPS-Chars:: Special Characters
1076 @subsection Special Characters
1078 @cindex line comment character, MIPS
1079 @cindex MIPS line comment character
1080 The presence of a @samp{#} on a line indicates the start of a comment
1081 that extends to the end of the current line.
1083 If a @samp{#} appears as the first character of a line, the whole line
1084 is treated as a comment, but in this case the line can also be a
1085 logical line number directive (@pxref{Comments}) or a
1086 preprocessor control command (@pxref{Preprocessing}).
1088 @cindex line separator, MIPS
1089 @cindex statement separator, MIPS
1090 @cindex MIPS line separator
1091 The @samp{;} character can be used to separate statements on the same
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