1 @c Copyright (C) 1996-2016 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
139 @code{cortex-m0plus},
142 @code{marvell-whitney},
146 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
147 @code{i80200} (Intel XScale processor)
148 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
151 The special name @code{all} may be used to allow the
152 assembler to accept instructions valid for any ARM processor.
154 In addition to the basic instruction set, the assembler can be told to
155 accept various extension mnemonics that extend the processor using the
156 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
157 is equivalent to specifying @code{-mcpu=ep9312}.
159 Multiple extensions may be specified, separated by a @code{+}. The
160 extensions should be specified in ascending alphabetical order.
162 Some extensions may be restricted to particular architectures; this is
163 documented in the list of extensions below.
165 Extension mnemonics may also be removed from those the assembler accepts.
166 This is done be prepending @code{no} to the option that adds the extension.
167 Extensions that are removed should be listed after all extensions which have
168 been added, again in ascending alphabetical order. For example,
169 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
172 The following extensions are currently supported:
174 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
175 @code{fp} (Floating Point Extensions for v8-A architecture),
176 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
181 @code{mp} (Multiprocessing Extensions for v7-A and v7-R
183 @code{os} (Operating System for v6M architecture),
184 @code{sec} (Security Extensions for v6K and v7-A architectures),
185 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
186 @code{virt} (Virtualization Extensions for v7-A architecture, implies
188 @code{pan} (Priviliged Access Never Extensions for v8-A architecture),
189 @code{ras} (Reliability, Availability and Serviceability extensions
190 for v8-A architecture),
191 @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
196 @cindex @code{-march=} command line option, ARM
197 @item -march=@var{architecture}[+@var{extension}@dots{}]
198 This option specifies the target architecture. The assembler will issue
199 an error message if an attempt is made to assemble an instruction which
200 will not execute on the target architecture. The following architecture
201 names are recognized:
237 If both @code{-mcpu} and
238 @code{-march} are specified, the assembler will use
239 the setting for @code{-mcpu}.
241 The architecture option can be extended with the same instruction set
242 extension options as the @code{-mcpu} option.
244 @cindex @code{-mfpu=} command line option, ARM
245 @item -mfpu=@var{floating-point-format}
247 This option specifies the floating point format to assemble for. The
248 assembler will issue an error message if an attempt is made to assemble
249 an instruction which will not execute on the target floating point unit.
250 The following format options are recognized:
270 @code{vfpv3-d16-fp16},
285 @code{neon-fp-armv8},
286 @code{crypto-neon-fp-armv8},
287 @code{neon-fp-armv8.1}
289 @code{crypto-neon-fp-armv8.1}.
291 In addition to determining which instructions are assembled, this option
292 also affects the way in which the @code{.double} assembler directive behaves
293 when assembling little-endian code.
295 The default is dependent on the processor selected. For Architecture 5 or
296 later, the default is to assembler for VFP instructions; for earlier
297 architectures the default is to assemble for FPA instructions.
299 @cindex @code{-mthumb} command line option, ARM
301 This option specifies that the assembler should start assembling Thumb
302 instructions; that is, it should behave as though the file starts with a
303 @code{.code 16} directive.
305 @cindex @code{-mthumb-interwork} command line option, ARM
306 @item -mthumb-interwork
307 This option specifies that the output generated by the assembler should
308 be marked as supporting interworking.
310 @cindex @code{-mimplicit-it} command line option, ARM
311 @item -mimplicit-it=never
312 @itemx -mimplicit-it=always
313 @itemx -mimplicit-it=arm
314 @itemx -mimplicit-it=thumb
315 The @code{-mimplicit-it} option controls the behavior of the assembler when
316 conditional instructions are not enclosed in IT blocks.
317 There are four possible behaviors.
318 If @code{never} is specified, such constructs cause a warning in ARM
319 code and an error in Thumb-2 code.
320 If @code{always} is specified, such constructs are accepted in both
321 ARM and Thumb-2 code, where the IT instruction is added implicitly.
322 If @code{arm} is specified, such constructs are accepted in ARM code
323 and cause an error in Thumb-2 code.
324 If @code{thumb} is specified, such constructs cause a warning in ARM
325 code and are accepted in Thumb-2 code. If you omit this option, the
326 behavior is equivalent to @code{-mimplicit-it=arm}.
328 @cindex @code{-mapcs-26} command line option, ARM
329 @cindex @code{-mapcs-32} command line option, ARM
332 These options specify that the output generated by the assembler should
333 be marked as supporting the indicated version of the Arm Procedure.
336 @cindex @code{-matpcs} command line option, ARM
338 This option specifies that the output generated by the assembler should
339 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
340 enabled this option will cause the assembler to create an empty
341 debugging section in the object file called .arm.atpcs. Debuggers can
342 use this to determine the ABI being used by.
344 @cindex @code{-mapcs-float} command line option, ARM
346 This indicates the floating point variant of the APCS should be
347 used. In this variant floating point arguments are passed in FP
348 registers rather than integer registers.
350 @cindex @code{-mapcs-reentrant} command line option, ARM
351 @item -mapcs-reentrant
352 This indicates that the reentrant variant of the APCS should be used.
353 This variant supports position independent code.
355 @cindex @code{-mfloat-abi=} command line option, ARM
356 @item -mfloat-abi=@var{abi}
357 This option specifies that the output generated by the assembler should be
358 marked as using specified floating point ABI.
359 The following values are recognized:
365 @cindex @code{-eabi=} command line option, ARM
366 @item -meabi=@var{ver}
367 This option specifies which EABI version the produced object files should
369 The following values are recognized:
375 @cindex @code{-EB} command line option, ARM
377 This option specifies that the output generated by the assembler should
378 be marked as being encoded for a big-endian processor.
380 Note: If a program is being built for a system with big-endian data
381 and little-endian instructions then it should be assembled with the
382 @option{-EB} option, (all of it, code and data) and then linked with
383 the @option{--be8} option. This will reverse the endianness of the
384 instructions back to little-endian, but leave the data as big-endian.
386 @cindex @code{-EL} command line option, ARM
388 This option specifies that the output generated by the assembler should
389 be marked as being encoded for a little-endian processor.
391 @cindex @code{-k} command line option, ARM
392 @cindex PIC code generation for ARM
394 This option specifies that the output of the assembler should be marked
395 as position-independent code (PIC).
397 @cindex @code{--fix-v4bx} command line option, ARM
399 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
400 the linker option of the same name.
402 @cindex @code{-mwarn-deprecated} command line option, ARM
403 @item -mwarn-deprecated
404 @itemx -mno-warn-deprecated
405 Enable or disable warnings about using deprecated options or
406 features. The default is to warn.
408 @cindex @code{-mccs} command line option, ARM
410 Turns on CodeComposer Studio assembly syntax compatibility mode.
412 @cindex @code{-mwarn-syms} command line option, ARM
414 @itemx -mno-warn-syms
415 Enable or disable warnings about symbols that match the names of ARM
416 instructions. The default is to warn.
424 * ARM-Instruction-Set:: Instruction Set
425 * ARM-Chars:: Special Characters
426 * ARM-Regs:: Register Names
427 * ARM-Relocations:: Relocations
428 * ARM-Neon-Alignment:: NEON Alignment Specifiers
431 @node ARM-Instruction-Set
432 @subsection Instruction Set Syntax
433 Two slightly different syntaxes are support for ARM and THUMB
434 instructions. The default, @code{divided}, uses the old style where
435 ARM and THUMB instructions had their own, separate syntaxes. The new,
436 @code{unified} syntax, which can be selected via the @code{.syntax}
437 directive, and has the following main features:
441 Immediate operands do not require a @code{#} prefix.
444 The @code{IT} instruction may appear, and if it does it is validated
445 against subsequent conditional affixes. In ARM mode it does not
446 generate machine code, in THUMB mode it does.
449 For ARM instructions the conditional affixes always appear at the end
450 of the instruction. For THUMB instructions conditional affixes can be
451 used, but only inside the scope of an @code{IT} instruction.
454 All of the instructions new to the V6T2 architecture (and later) are
455 available. (Only a few such instructions can be written in the
456 @code{divided} syntax).
459 The @code{.N} and @code{.W} suffixes are recognized and honored.
462 All instructions set the flags if and only if they have an @code{s}
467 @subsection Special Characters
469 @cindex line comment character, ARM
470 @cindex ARM line comment character
471 The presence of a @samp{@@} anywhere on a line indicates the start of
472 a comment that extends to the end of that line.
474 If a @samp{#} appears as the first character of a line then the whole
475 line is treated as a comment, but in this case the line could also be
476 a logical line number directive (@pxref{Comments}) or a preprocessor
477 control command (@pxref{Preprocessing}).
479 @cindex line separator, ARM
480 @cindex statement separator, ARM
481 @cindex ARM line separator
482 The @samp{;} character can be used instead of a newline to separate
485 @cindex immediate character, ARM
486 @cindex ARM immediate character
487 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
489 @cindex identifiers, ARM
490 @cindex ARM identifiers
491 *TODO* Explain about /data modifier on symbols.
494 @subsection Register Names
496 @cindex ARM register names
497 @cindex register names, ARM
498 *TODO* Explain about ARM register naming, and the predefined names.
500 @node ARM-Relocations
501 @subsection ARM relocation generation
503 @cindex data relocations, ARM
504 @cindex ARM data relocations
505 Specific data relocations can be generated by putting the relocation name
506 in parentheses after the symbol name. For example:
512 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
514 The following relocations are supported:
530 For compatibility with older toolchains the assembler also accepts
531 @code{(PLT)} after branch targets. On legacy targets this will
532 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
533 targets it will encode either the @samp{R_ARM_CALL} or
534 @samp{R_ARM_JUMP24} relocation, as appropriate.
536 @cindex MOVW and MOVT relocations, ARM
537 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
538 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
539 respectively. For example to load the 32-bit address of foo into r0:
542 MOVW r0, #:lower16:foo
543 MOVT r0, #:upper16:foo
546 Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC},
547 @samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be
548 generated by prefixing the value with @samp{#:lower0_7:#},
549 @samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#}
550 respectively. For example to load the 32-bit address of foo into r0:
553 MOVS r0, #:upper8_15:#foo
555 ADDS r0, #:upper0_7:#foo
557 ADDS r0, #:lower8_15:#foo
559 ADDS r0, #:lower0_7:#foo
562 @node ARM-Neon-Alignment
563 @subsection NEON Alignment Specifiers
565 @cindex alignment for NEON instructions
566 Some NEON load/store instructions allow an optional address
568 The ARM documentation specifies that this is indicated by
569 @samp{@@ @var{align}}. However GAS already interprets
570 the @samp{@@} character as a "line comment" start,
571 so @samp{: @var{align}} is used instead. For example:
574 vld1.8 @{q0@}, [r0, :128]
577 @node ARM Floating Point
578 @section Floating Point
580 @cindex floating point, ARM (@sc{ieee})
581 @cindex ARM floating point (@sc{ieee})
582 The ARM family uses @sc{ieee} floating-point numbers.
585 @section ARM Machine Directives
587 @cindex machine directives, ARM
588 @cindex ARM machine directives
591 @c AAAAAAAAAAAAAAAAAAAAAAAAA
593 @cindex @code{.2byte} directive, ARM
594 @cindex @code{.4byte} directive, ARM
595 @cindex @code{.8byte} directive, ARM
596 @item .2byte @var{expression} [, @var{expression}]*
597 @itemx .4byte @var{expression} [, @var{expression}]*
598 @itemx .8byte @var{expression} [, @var{expression}]*
599 These directives write 2, 4 or 8 byte values to the output section.
601 @cindex @code{.align} directive, ARM
602 @item .align @var{expression} [, @var{expression}]
603 This is the generic @var{.align} directive. For the ARM however if the
604 first argument is zero (ie no alignment is needed) the assembler will
605 behave as if the argument had been 2 (ie pad to the next four byte
606 boundary). This is for compatibility with ARM's own assembler.
608 @cindex @code{.arch} directive, ARM
609 @item .arch @var{name}
610 Select the target architecture. Valid values for @var{name} are the same as
611 for the @option{-march} commandline option.
613 Specifying @code{.arch} clears any previously selected architecture
616 @cindex @code{.arch_extension} directive, ARM
617 @item .arch_extension @var{name}
618 Add or remove an architecture extension to the target architecture. Valid
619 values for @var{name} are the same as those accepted as architectural
620 extensions by the @option{-mcpu} commandline option.
622 @code{.arch_extension} may be used multiple times to add or remove extensions
623 incrementally to the architecture being compiled for.
625 @cindex @code{.arm} directive, ARM
627 This performs the same action as @var{.code 32}.
629 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
631 @cindex @code{.bss} directive, ARM
633 This directive switches to the @code{.bss} section.
635 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
637 @cindex @code{.cantunwind} directive, ARM
639 Prevents unwinding through the current function. No personality routine
640 or exception table data is required or permitted.
642 @cindex @code{.code} directive, ARM
643 @item .code @code{[16|32]}
644 This directive selects the instruction set being generated. The value 16
645 selects Thumb, with the value 32 selecting ARM.
647 @cindex @code{.cpu} directive, ARM
648 @item .cpu @var{name}
649 Select the target processor. Valid values for @var{name} are the same as
650 for the @option{-mcpu} commandline option.
652 Specifying @code{.cpu} clears any previously selected architecture
655 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
657 @cindex @code{.dn} and @code{.qn} directives, ARM
658 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
659 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
661 The @code{dn} and @code{qn} directives are used to create typed
662 and/or indexed register aliases for use in Advanced SIMD Extension
663 (Neon) instructions. The former should be used to create aliases
664 of double-precision registers, and the latter to create aliases of
665 quad-precision registers.
667 If these directives are used to create typed aliases, those aliases can
668 be used in Neon instructions instead of writing types after the mnemonic
669 or after each operand. For example:
678 This is equivalent to writing the following:
684 Aliases created using @code{dn} or @code{qn} can be destroyed using
687 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
689 @cindex @code{.eabi_attribute} directive, ARM
690 @item .eabi_attribute @var{tag}, @var{value}
691 Set the EABI object attribute @var{tag} to @var{value}.
693 The @var{tag} is either an attribute number, or one of the following:
694 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
695 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
696 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
697 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
698 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
699 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
700 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
701 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
702 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
703 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
704 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
705 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
706 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
707 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
708 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
709 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
710 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
711 @code{Tag_conformance}, @code{Tag_T2EE_use},
712 @code{Tag_Virtualization_use}
714 The @var{value} is either a @code{number}, @code{"string"}, or
715 @code{number, "string"} depending on the tag.
717 Note - the following legacy values are also accepted by @var{tag}:
718 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
719 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
721 @cindex @code{.even} directive, ARM
723 This directive aligns to an even-numbered address.
725 @cindex @code{.extend} directive, ARM
726 @cindex @code{.ldouble} directive, ARM
727 @item .extend @var{expression} [, @var{expression}]*
728 @itemx .ldouble @var{expression} [, @var{expression}]*
729 These directives write 12byte long double floating-point values to the
730 output section. These are not compatible with current ARM processors
733 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
736 @cindex @code{.fnend} directive, ARM
738 Marks the end of a function with an unwind table entry. The unwind index
739 table entry is created when this directive is processed.
741 If no personality routine has been specified then standard personality
742 routine 0 or 1 will be used, depending on the number of unwind opcodes
746 @cindex @code{.fnstart} directive, ARM
748 Marks the start of a function with an unwind table entry.
750 @cindex @code{.force_thumb} directive, ARM
752 This directive forces the selection of Thumb instructions, even if the
753 target processor does not support those instructions
755 @cindex @code{.fpu} directive, ARM
756 @item .fpu @var{name}
757 Select the floating-point unit to assemble for. Valid values for @var{name}
758 are the same as for the @option{-mfpu} commandline option.
760 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
761 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
763 @cindex @code{.handlerdata} directive, ARM
765 Marks the end of the current function, and the start of the exception table
766 entry for that function. Anything between this directive and the
767 @code{.fnend} directive will be added to the exception table entry.
769 Must be preceded by a @code{.personality} or @code{.personalityindex}
772 @c IIIIIIIIIIIIIIIIIIIIIIIIII
774 @cindex @code{.inst} directive, ARM
775 @item .inst @var{opcode} [ , @dots{} ]
776 @itemx .inst.n @var{opcode} [ , @dots{} ]
777 @itemx .inst.w @var{opcode} [ , @dots{} ]
778 Generates the instruction corresponding to the numerical value @var{opcode}.
779 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
780 specified explicitly, overriding the normal encoding rules.
782 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
783 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
784 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
786 @item .ldouble @var{expression} [, @var{expression}]*
789 @cindex @code{.ltorg} directive, ARM
791 This directive causes the current contents of the literal pool to be
792 dumped into the current section (which is assumed to be the .text
793 section) at the current location (aligned to a word boundary).
794 @code{GAS} maintains a separate literal pool for each section and each
795 sub-section. The @code{.ltorg} directive will only affect the literal
796 pool of the current section and sub-section. At the end of assembly
797 all remaining, un-empty literal pools will automatically be dumped.
799 Note - older versions of @code{GAS} would dump the current literal
800 pool any time a section change occurred. This is no longer done, since
801 it prevents accurate control of the placement of literal pools.
803 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
805 @cindex @code{.movsp} directive, ARM
806 @item .movsp @var{reg} [, #@var{offset}]
807 Tell the unwinder that @var{reg} contains an offset from the current
808 stack pointer. If @var{offset} is not specified then it is assumed to be
811 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
812 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
814 @cindex @code{.object_arch} directive, ARM
815 @item .object_arch @var{name}
816 Override the architecture recorded in the EABI object attribute section.
817 Valid values for @var{name} are the same as for the @code{.arch} directive.
818 Typically this is useful when code uses runtime detection of CPU features.
820 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
822 @cindex @code{.packed} directive, ARM
823 @item .packed @var{expression} [, @var{expression}]*
824 This directive writes 12-byte packed floating-point values to the
825 output section. These are not compatible with current ARM processors
829 @cindex @code{.pad} directive, ARM
830 @item .pad #@var{count}
831 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
832 A positive value indicates the function prologue allocated stack space by
833 decrementing the stack pointer.
835 @cindex @code{.personality} directive, ARM
836 @item .personality @var{name}
837 Sets the personality routine for the current function to @var{name}.
839 @cindex @code{.personalityindex} directive, ARM
840 @item .personalityindex @var{index}
841 Sets the personality routine for the current function to the EABI standard
842 routine number @var{index}
844 @cindex @code{.pool} directive, ARM
846 This is a synonym for .ltorg.
848 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
849 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
851 @cindex @code{.req} directive, ARM
852 @item @var{name} .req @var{register name}
853 This creates an alias for @var{register name} called @var{name}. For
860 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
863 @cindex @code{.save} directive, ARM
864 @item .save @var{reglist}
865 Generate unwinder annotations to restore the registers in @var{reglist}.
866 The format of @var{reglist} is the same as the corresponding store-multiple
870 @exdent @emph{core registers}
871 .save @{r4, r5, r6, lr@}
872 stmfd sp!, @{r4, r5, r6, lr@}
873 @exdent @emph{FPA registers}
876 @exdent @emph{VFP registers}
877 .save @{d8, d9, d10@}
878 fstmdx sp!, @{d8, d9, d10@}
879 @exdent @emph{iWMMXt registers}
881 wstrd wr11, [sp, #-8]!
882 wstrd wr10, [sp, #-8]!
885 wstrd wr11, [sp, #-8]!
887 wstrd wr10, [sp, #-8]!
891 @cindex @code{.setfp} directive, ARM
892 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
893 Make all unwinder annotations relative to a frame pointer. Without this
894 the unwinder will use offsets from the stack pointer.
896 The syntax of this directive is the same as the @code{add} or @code{mov}
897 instruction used to set the frame pointer. @var{spreg} must be either
898 @code{sp} or mentioned in a previous @code{.movsp} directive.
908 @cindex @code{.secrel32} directive, ARM
909 @item .secrel32 @var{expression} [, @var{expression}]*
910 This directive emits relocations that evaluate to the section-relative
911 offset of each expression's symbol. This directive is only supported
914 @cindex @code{.syntax} directive, ARM
915 @item .syntax [@code{unified} | @code{divided}]
916 This directive sets the Instruction Set Syntax as described in the
917 @ref{ARM-Instruction-Set} section.
919 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
921 @cindex @code{.thumb} directive, ARM
923 This performs the same action as @var{.code 16}.
925 @cindex @code{.thumb_func} directive, ARM
927 This directive specifies that the following symbol is the name of a
928 Thumb encoded function. This information is necessary in order to allow
929 the assembler and linker to generate correct code for interworking
930 between Arm and Thumb instructions and should be used even if
931 interworking is not going to be performed. The presence of this
932 directive also implies @code{.thumb}
934 This directive is not neccessary when generating EABI objects. On these
935 targets the encoding is implicit when generating Thumb code.
937 @cindex @code{.thumb_set} directive, ARM
939 This performs the equivalent of a @code{.set} directive in that it
940 creates a symbol which is an alias for another symbol (possibly not yet
941 defined). This directive also has the added property in that it marks
942 the aliased symbol as being a thumb function entry point, in the same
943 way that the @code{.thumb_func} directive does.
945 @cindex @code{.tlsdescseq} directive, ARM
946 @item .tlsdescseq @var{tls-variable}
947 This directive is used to annotate parts of an inlined TLS descriptor
948 trampoline. Normally the trampoline is provided by the linker, and
949 this directive is not needed.
951 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
953 @cindex @code{.unreq} directive, ARM
954 @item .unreq @var{alias-name}
955 This undefines a register alias which was previously defined using the
956 @code{req}, @code{dn} or @code{qn} directives. For example:
963 An error occurs if the name is undefined. Note - this pseudo op can
964 be used to delete builtin in register name aliases (eg 'r0'). This
965 should only be done if it is really necessary.
967 @cindex @code{.unwind_raw} directive, ARM
968 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
969 Insert one of more arbitary unwind opcode bytes, which are known to adjust
970 the stack pointer by @var{offset} bytes.
972 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
975 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
977 @cindex @code{.vsave} directive, ARM
978 @item .vsave @var{vfp-reglist}
979 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
980 using FLDMD. Also works for VFPv3 registers
981 that are to be restored using VLDM.
982 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
986 @exdent @emph{VFP registers}
987 .vsave @{d8, d9, d10@}
988 fstmdd sp!, @{d8, d9, d10@}
989 @exdent @emph{VFPv3 registers}
990 .vsave @{d15, d16, d17@}
991 vstm sp!, @{d15, d16, d17@}
994 Since FLDMX and FSTMX are now deprecated, this directive should be
995 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
997 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
998 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
999 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
1000 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
1008 @cindex opcodes for ARM
1009 @code{@value{AS}} implements all the standard ARM opcodes. It also
1010 implements several pseudo opcodes, including several synthetic load
1015 @cindex @code{NOP} pseudo op, ARM
1021 This pseudo op will always evaluate to a legal ARM instruction that does
1022 nothing. Currently it will evaluate to MOV r0, r0.
1024 @cindex @code{LDR reg,=<label>} pseudo op, ARM
1027 ldr <register> , = <expression>
1030 If expression evaluates to a numeric constant then a MOV or MVN
1031 instruction will be used in place of the LDR instruction, if the
1032 constant can be generated by either of these instructions. Otherwise
1033 the constant will be placed into the nearest literal pool (if it not
1034 already there) and a PC relative LDR instruction will be generated.
1036 @cindex @code{ADR reg,<label>} pseudo op, ARM
1039 adr <register> <label>
1042 This instruction will load the address of @var{label} into the indicated
1043 register. The instruction will evaluate to a PC relative ADD or SUB
1044 instruction depending upon where the label is located. If the label is
1045 out of range, or if it is not defined in the same file (and section) as
1046 the ADR instruction, then an error will be generated. This instruction
1047 will not make use of the literal pool.
1049 @cindex @code{ADRL reg,<label>} pseudo op, ARM
1052 adrl <register> <label>
1055 This instruction will load the address of @var{label} into the indicated
1056 register. The instruction will evaluate to one or two PC relative ADD
1057 or SUB instructions depending upon where the label is located. If a
1058 second instruction is not needed a NOP instruction will be generated in
1059 its place, so that this instruction is always 8 bytes long.
1061 If the label is out of range, or if it is not defined in the same file
1062 (and section) as the ADRL instruction, then an error will be generated.
1063 This instruction will not make use of the literal pool.
1067 For information on the ARM or Thumb instruction sets, see @cite{ARM
1068 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1071 @node ARM Mapping Symbols
1072 @section Mapping Symbols
1074 The ARM ELF specification requires that special symbols be inserted
1075 into object files to mark certain features:
1081 At the start of a region of code containing ARM instructions.
1085 At the start of a region of code containing THUMB instructions.
1089 At the start of a region of data.
1093 The assembler will automatically insert these symbols for you - there
1094 is no need to code them yourself. Support for tagging symbols ($b,
1095 $f, $p and $m) which is also mentioned in the current ARM ELF
1096 specification is not implemented. This is because they have been
1097 dropped from the new EABI and so tools cannot rely upon their
1100 @node ARM Unwinding Tutorial
1103 The ABI for the ARM Architecture specifies a standard format for
1104 exception unwind information. This information is used when an
1105 exception is thrown to determine where control should be transferred.
1106 In particular, the unwind information is used to determine which
1107 function called the function that threw the exception, and which
1108 function called that one, and so forth. This information is also used
1109 to restore the values of callee-saved registers in the function
1110 catching the exception.
1112 If you are writing functions in assembly code, and those functions
1113 call other functions that throw exceptions, you must use assembly
1114 pseudo ops to ensure that appropriate exception unwind information is
1115 generated. Otherwise, if one of the functions called by your assembly
1116 code throws an exception, the run-time library will be unable to
1117 unwind the stack through your assembly code and your program will not
1120 To illustrate the use of these pseudo ops, we will examine the code
1121 that G++ generates for the following C++ input:
1124 void callee (int *);
1135 This example does not show how to throw or catch an exception from
1136 assembly code. That is a much more complex operation and should
1137 always be done in a high-level language, such as C++, that directly
1138 supports exceptions.
1140 The code generated by one particular version of G++ when compiling the
1147 @ Function supports interworking.
1148 @ args = 0, pretend = 0, frame = 8
1149 @ frame_needed = 1, uses_anonymous_args = 0
1171 Of course, the sequence of instructions varies based on the options
1172 you pass to GCC and on the version of GCC in use. The exact
1173 instructions are not important since we are focusing on the pseudo ops
1174 that are used to generate unwind information.
1176 An important assumption made by the unwinder is that the stack frame
1177 does not change during the body of the function. In particular, since
1178 we assume that the assembly code does not itself throw an exception,
1179 the only point where an exception can be thrown is from a call, such
1180 as the @code{bl} instruction above. At each call site, the same saved
1181 registers (including @code{lr}, which indicates the return address)
1182 must be located in the same locations relative to the frame pointer.
1184 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1185 op appears immediately before the first instruction of the function
1186 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1187 op appears immediately after the last instruction of the function.
1188 These pseudo ops specify the range of the function.
1190 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1191 @code{.pad}) matters; their exact locations are irrelevant. In the
1192 example above, the compiler emits the pseudo ops with particular
1193 instructions. That makes it easier to understand the code, but it is
1194 not required for correctness. It would work just as well to emit all
1195 of the pseudo ops other than @code{.fnend} in the same order, but
1196 immediately after @code{.fnstart}.
1198 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1199 indicates registers that have been saved to the stack so that they can
1200 be restored before the function returns. The argument to the
1201 @code{.save} pseudo op is a list of registers to save. If a register
1202 is ``callee-saved'' (as specified by the ABI) and is modified by the
1203 function you are writing, then your code must save the value before it
1204 is modified and restore the original value before the function
1205 returns. If an exception is thrown, the run-time library restores the
1206 values of these registers from their locations on the stack before
1207 returning control to the exception handler. (Of course, if an
1208 exception is not thrown, the function that contains the @code{.save}
1209 pseudo op restores these registers in the function epilogue, as is
1210 done with the @code{ldmfd} instruction above.)
1212 You do not have to save callee-saved registers at the very beginning
1213 of the function and you do not need to use the @code{.save} pseudo op
1214 immediately following the point at which the registers are saved.
1215 However, if you modify a callee-saved register, you must save it on
1216 the stack before modifying it and before calling any functions which
1217 might throw an exception. And, you must use the @code{.save} pseudo
1218 op to indicate that you have done so.
1220 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1221 modification of the stack pointer that does not save any registers.
1222 The argument is the number of bytes (in decimal) that are subtracted
1223 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1224 subtracting from the stack pointer increases the size of the stack.)
1226 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1227 indicates the register that contains the frame pointer. The first
1228 argument is the register that is set, which is typically @code{fp}.
1229 The second argument indicates the register from which the frame
1230 pointer takes its value. The third argument, if present, is the value
1231 (in decimal) added to the register specified by the second argument to
1232 compute the value of the frame pointer. You should not modify the
1233 frame pointer in the body of the function.
1235 If you do not use a frame pointer, then you should not use the
1236 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1237 should avoid modifying the stack pointer outside of the function
1238 prologue. Otherwise, the run-time library will be unable to find
1239 saved registers when it is unwinding the stack.
1241 The pseudo ops described above are sufficient for writing assembly
1242 code that calls functions which may throw exceptions. If you need to
1243 know more about the object-file format used to represent unwind
1244 information, you may consult the @cite{Exception Handling ABI for the
1245 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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