sys/dev/drm/i915/i915_cmd_parser.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Brad Volkin <bradley.d.volkin@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29
  30 /**
  31  * DOC: batch buffer command parser
  32  *
  33  * Motivation:
  34  * Certain OpenGL features (e.g. transform feedback, performance monitoring)
  35  * require userspace code to submit batches containing commands such as
  36  * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
  37  * generations of the hardware will noop these commands in "unsecure" batches
  38  * (which includes all userspace batches submitted via i915) even though the
  39  * commands may be safe and represent the intended programming model of the
  40  * device.
  41  *
  42  * The software command parser is similar in operation to the command parsing
  43  * done in hardware for unsecure batches. However, the software parser allows
  44  * some operations that would be noop'd by hardware, if the parser determines
  45  * the operation is safe, and submits the batch as "secure" to prevent hardware
  46  * parsing.
  47  *
  48  * Threats:
  49  * At a high level, the hardware (and software) checks attempt to prevent
  50  * granting userspace undue privileges. There are three categories of privilege.
  51  *
  52  * First, commands which are explicitly defined as privileged or which should
  53  * only be used by the kernel driver. The parser generally rejects such
  54  * commands, though it may allow some from the drm master process.
  55  *
  56  * Second, commands which access registers. To support correct/enhanced
  57  * userspace functionality, particularly certain OpenGL extensions, the parser
  58  * provides a whitelist of registers which userspace may safely access (for both
  59  * normal and drm master processes).
  60  *
  61  * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
  62  * The parser always rejects such commands.
  63  *
  64  * The majority of the problematic commands fall in the MI_* range, with only a
  65  * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
  66  *
  67  * Implementation:
  68  * Each ring maintains tables of commands and registers which the parser uses in
  69  * scanning batch buffers submitted to that ring.
  70  *
  71  * Since the set of commands that the parser must check for is significantly
  72  * smaller than the number of commands supported, the parser tables contain only
  73  * those commands required by the parser. This generally works because command
  74  * opcode ranges have standard command length encodings. So for commands that
  75  * the parser does not need to check, it can easily skip them. This is
  76  * implemented via a per-ring length decoding vfunc.
  77  *
  78  * Unfortunately, there are a number of commands that do not follow the standard
  79  * length encoding for their opcode range, primarily amongst the MI_* commands.
  80  * To handle this, the parser provides a way to define explicit "skip" entries
  81  * in the per-ring command tables.
  82  *
  83  * Other command table entries map fairly directly to high level categories
  84  * mentioned above: rejected, master-only, register whitelist. The parser
  85  * implements a number of checks, including the privileged memory checks, via a
  86  * general bitmasking mechanism.
  87  */
  88
  89 #define STD_MI_OPCODE_MASK  0xFF800000
  90 #define STD_3D_OPCODE_MASK  0xFFFF0000
  91 #define STD_2D_OPCODE_MASK  0xFFC00000
  92 #define STD_MFX_OPCODE_MASK 0xFFFF0000
  93
  94 #define CMD(op, opm, f, lm, fl, ...)                            \
  95         {                                                       \
  96                 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0),     \
  97                 .cmd = { (op), (opm) },                         \
  98                 .length = { (lm) },                             \
  99                 __VA_ARGS__                                     \
 100         }
 101
 102 /* Convenience macros to compress the tables */
 103 #define SMI STD_MI_OPCODE_MASK
 104 #define S3D STD_3D_OPCODE_MASK
 105 #define S2D STD_2D_OPCODE_MASK
 106 #define SMFX STD_MFX_OPCODE_MASK
 107 #define F true
 108 #define S CMD_DESC_SKIP
 109 #define R CMD_DESC_REJECT
 110 #define W CMD_DESC_REGISTER
 111 #define B CMD_DESC_BITMASK
 112 #define M CMD_DESC_MASTER
 113
 114 /*            Command                          Mask   Fixed Len   Action
 115               ---------------------------------------------------------- */
 116 static const struct drm_i915_cmd_descriptor common_cmds[] = {
 117         CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),
 118         CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      R  ),
 119         CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      M  ),
 120         CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),
 121         CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
 122         CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
 123         CMD(  MI_SEMAPHORE_MBOX,                SMI,   !F,  0xFF,   R  ),
 124         CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),
 125         CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
 126               .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 }    ),
 127         CMD(  MI_STORE_REGISTER_MEM,            SMI,    F,  3,     W | B,
 128               .reg = { .offset = 1, .mask = 0x007FFFFC },
 129               .bits = {{
 130                         .offset = 0,
 131                         .mask = MI_GLOBAL_GTT,
 132                         .expected = 0,
 133               }},                                                      ),
 134         CMD(  MI_LOAD_REGISTER_MEM,             SMI,    F,  3,     W | B,
 135               .reg = { .offset = 1, .mask = 0x007FFFFC },
 136               .bits = {{
 137                         .offset = 0,
 138                         .mask = MI_GLOBAL_GTT,
 139                         .expected = 0,
 140               }},                                                      ),
 141         /*
 142          * MI_BATCH_BUFFER_START requires some special handling. It's not
 143          * really a 'skip' action but it doesn't seem like it's worth adding
 144          * a new action. See i915_parse_cmds().
 145          */
 146         CMD(  MI_BATCH_BUFFER_START,            SMI,   !F,  0xFF,   S  ),
 147 };
 148
 149 static const struct drm_i915_cmd_descriptor render_cmds[] = {
 150         CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
 151         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 152         CMD(  MI_PREDICATE,                     SMI,    F,  1,      S  ),
 153         CMD(  MI_TOPOLOGY_FILTER,               SMI,    F,  1,      S  ),
 154         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 155         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 156         CMD(  MI_SET_CONTEXT,                   SMI,   !F,  0xFF,   R  ),
 157         CMD(  MI_URB_CLEAR,                     SMI,   !F,  0xFF,   S  ),
 158         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3F,   B,
 159               .bits = {{
 160                         .offset = 0,
 161                         .mask = MI_GLOBAL_GTT,
 162                         .expected = 0,
 163               }},                                                      ),
 164         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0xFF,   R  ),
 165         CMD(  MI_CLFLUSH,                       SMI,   !F,  0x3FF,  B,
 166               .bits = {{
 167                         .offset = 0,
 168                         .mask = MI_GLOBAL_GTT,
 169                         .expected = 0,
 170               }},                                                      ),
 171         CMD(  MI_REPORT_PERF_COUNT,             SMI,   !F,  0x3F,   B,
 172               .bits = {{
 173                         .offset = 1,
 174                         .mask = MI_REPORT_PERF_COUNT_GGTT,
 175                         .expected = 0,
 176               }},                                                      ),
 177         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 178               .bits = {{
 179                         .offset = 0,
 180                         .mask = MI_GLOBAL_GTT,
 181                         .expected = 0,
 182               }},                                                      ),
 183         CMD(  GFX_OP_3DSTATE_VF_STATISTICS,     S3D,    F,  1,      S  ),
 184         CMD(  PIPELINE_SELECT,                  S3D,    F,  1,      S  ),
 185         CMD(  MEDIA_VFE_STATE,                  S3D,   !F,  0xFFFF, B,
 186               .bits = {{
 187                         .offset = 2,
 188                         .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
 189                         .expected = 0,
 190               }},                                                      ),
 191         CMD(  GPGPU_OBJECT,                     S3D,   !F,  0xFF,   S  ),
 192         CMD(  GPGPU_WALKER,                     S3D,   !F,  0xFF,   S  ),
 193         CMD(  GFX_OP_3DSTATE_SO_DECL_LIST,      S3D,   !F,  0x1FF,  S  ),
 194         CMD(  GFX_OP_PIPE_CONTROL(5),           S3D,   !F,  0xFF,   B,
 195               .bits = {{
 196                         .offset = 1,
 197                         .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
 198                         .expected = 0,
 199               },
 200               {
 201                         .offset = 1,
 202                         .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
 203                                  PIPE_CONTROL_STORE_DATA_INDEX),
 204                         .expected = 0,
 205                         .condition_offset = 1,
 206                         .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
 207               }},                                                      ),
 208 };
 209
 210 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
 211         CMD(  MI_SET_PREDICATE,                 SMI,    F,  1,      S  ),
 212         CMD(  MI_RS_CONTROL,                    SMI,    F,  1,      S  ),
 213         CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
 214         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 215         CMD(  MI_RS_CONTEXT,                    SMI,    F,  1,      S  ),
 216         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 217         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 218         CMD(  MI_LOAD_REGISTER_REG,             SMI,   !F,  0xFF,   R  ),
 219         CMD(  MI_RS_STORE_DATA_IMM,             SMI,   !F,  0xFF,   S  ),
 220         CMD(  MI_LOAD_URB_MEM,                  SMI,   !F,  0xFF,   S  ),
 221         CMD(  MI_STORE_URB_MEM,                 SMI,   !F,  0xFF,   S  ),
 222         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_VS,  S3D,   !F,  0x7FF,  S  ),
 223         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_PS,  S3D,   !F,  0x7FF,  S  ),
 224
 225         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS,  S3D,   !F,  0x1FF,  S  ),
 226         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS,  S3D,   !F,  0x1FF,  S  ),
 227         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS,  S3D,   !F,  0x1FF,  S  ),
 228         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS,  S3D,   !F,  0x1FF,  S  ),
 229         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS,  S3D,   !F,  0x1FF,  S  ),
 230 };
 231
 232 static const struct drm_i915_cmd_descriptor video_cmds[] = {
 233         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 234         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 235         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 236               .bits = {{
 237                         .offset = 0,
 238                         .mask = MI_GLOBAL_GTT,
 239                         .expected = 0,
 240               }},                                                      ),
 241         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 242         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 243               .bits = {{
 244                         .offset = 0,
 245                         .mask = MI_FLUSH_DW_NOTIFY,
 246                         .expected = 0,
 247               },
 248               {
 249                         .offset = 1,
 250                         .mask = MI_FLUSH_DW_USE_GTT,
 251                         .expected = 0,
 252                         .condition_offset = 0,
 253                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 254               },
 255               {
 256                         .offset = 0,
 257                         .mask = MI_FLUSH_DW_STORE_INDEX,
 258                         .expected = 0,
 259                         .condition_offset = 0,
 260                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 261               }},                                                      ),
 262         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 263               .bits = {{
 264                         .offset = 0,
 265                         .mask = MI_GLOBAL_GTT,
 266                         .expected = 0,
 267               }},                                                      ),
 268         /*
 269          * MFX_WAIT doesn't fit the way we handle length for most commands.
 270          * It has a length field but it uses a non-standard length bias.
 271          * It is always 1 dword though, so just treat it as fixed length.
 272          */
 273         CMD(  MFX_WAIT,                         SMFX,   F,  1,      S  ),
 274 };
 275
 276 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
 277         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 278         CMD(  MI_SET_APPID,                     SMI,    F,  1,      S  ),
 279         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 280               .bits = {{
 281                         .offset = 0,
 282                         .mask = MI_GLOBAL_GTT,
 283                         .expected = 0,
 284               }},                                                      ),
 285         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 286         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 287               .bits = {{
 288                         .offset = 0,
 289                         .mask = MI_FLUSH_DW_NOTIFY,
 290                         .expected = 0,
 291               },
 292               {
 293                         .offset = 1,
 294                         .mask = MI_FLUSH_DW_USE_GTT,
 295                         .expected = 0,
 296                         .condition_offset = 0,
 297                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 298               },
 299               {
 300                         .offset = 0,
 301                         .mask = MI_FLUSH_DW_STORE_INDEX,
 302                         .expected = 0,
 303                         .condition_offset = 0,
 304                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 305               }},                                                      ),
 306         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 307               .bits = {{
 308                         .offset = 0,
 309                         .mask = MI_GLOBAL_GTT,
 310                         .expected = 0,
 311               }},                                                      ),
 312 };
 313
 314 static const struct drm_i915_cmd_descriptor blt_cmds[] = {
 315         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 316         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  B,
 317               .bits = {{
 318                         .offset = 0,
 319                         .mask = MI_GLOBAL_GTT,
 320                         .expected = 0,
 321               }},                                                      ),
 322         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 323         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 324               .bits = {{
 325                         .offset = 0,
 326                         .mask = MI_FLUSH_DW_NOTIFY,
 327                         .expected = 0,
 328               },
 329               {
 330                         .offset = 1,
 331                         .mask = MI_FLUSH_DW_USE_GTT,
 332                         .expected = 0,
 333                         .condition_offset = 0,
 334                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 335               },
 336               {
 337                         .offset = 0,
 338                         .mask = MI_FLUSH_DW_STORE_INDEX,
 339                         .expected = 0,
 340                         .condition_offset = 0,
 341                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 342               }},                                                      ),
 343         CMD(  COLOR_BLT,                        S2D,   !F,  0x3F,   S  ),
 344         CMD(  SRC_COPY_BLT,                     S2D,   !F,  0x3F,   S  ),
 345 };
 346
 347 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
 348         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 349         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 350 };
 351
 352 #undef CMD
 353 #undef SMI
 354 #undef S3D
 355 #undef S2D
 356 #undef SMFX
 357 #undef F
 358 #undef S
 359 #undef R
 360 #undef W
 361 #undef B
 362 #undef M
 363
 364 static const struct drm_i915_cmd_table gen7_render_cmds[] = {
 365         { common_cmds, ARRAY_SIZE(common_cmds) },
 366         { render_cmds, ARRAY_SIZE(render_cmds) },
 367 };
 368
 369 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
 370         { common_cmds, ARRAY_SIZE(common_cmds) },
 371         { render_cmds, ARRAY_SIZE(render_cmds) },
 372         { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
 373 };
 374
 375 static const struct drm_i915_cmd_table gen7_video_cmds[] = {
 376         { common_cmds, ARRAY_SIZE(common_cmds) },
 377         { video_cmds, ARRAY_SIZE(video_cmds) },
 378 };
 379
 380 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
 381         { common_cmds, ARRAY_SIZE(common_cmds) },
 382         { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
 383 };
 384
 385 static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
 386         { common_cmds, ARRAY_SIZE(common_cmds) },
 387         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 388 };
 389
 390 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
 391         { common_cmds, ARRAY_SIZE(common_cmds) },
 392         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 393         { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
 394 };
 395
 396 /*
 397  * Register whitelists, sorted by increasing register offset.
 398  */
 399
 400 /*
 401  * An individual whitelist entry granting access to register addr.  If
 402  * mask is non-zero the argument of immediate register writes will be
 403  * AND-ed with mask, and the command will be rejected if the result
 404  * doesn't match value.
 405  *
 406  * Registers with non-zero mask are only allowed to be written using
 407  * LRI.
 408  */
 409 struct drm_i915_reg_descriptor {
 410         i915_reg_t addr;
 411         u32 mask;
 412         u32 value;
 413 };
 414
 415 /* Convenience macro for adding 32-bit registers. */
 416 #define REG32(_reg, ...) \
 417         { .addr = (_reg), __VA_ARGS__ }
 418
 419 /*
 420  * Convenience macro for adding 64-bit registers.
 421  *
 422  * Some registers that userspace accesses are 64 bits. The register
 423  * access commands only allow 32-bit accesses. Hence, we have to include
 424  * entries for both halves of the 64-bit registers.
 425  */
 426 #define REG64(_reg) \
 427         { .addr = _reg }, \
 428         { .addr = _reg ## _UDW }
 429
 430 #define REG64_IDX(_reg, idx) \
 431         { .addr = _reg(idx) }, \
 432         { .addr = _reg ## _UDW(idx) }
 433
 434 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
 435         REG64(GPGPU_THREADS_DISPATCHED),
 436         REG64(HS_INVOCATION_COUNT),
 437         REG64(DS_INVOCATION_COUNT),
 438         REG64(IA_VERTICES_COUNT),
 439         REG64(IA_PRIMITIVES_COUNT),
 440         REG64(VS_INVOCATION_COUNT),
 441         REG64(GS_INVOCATION_COUNT),
 442         REG64(GS_PRIMITIVES_COUNT),
 443         REG64(CL_INVOCATION_COUNT),
 444         REG64(CL_PRIMITIVES_COUNT),
 445         REG64(PS_INVOCATION_COUNT),
 446         REG64(PS_DEPTH_COUNT),
 447         REG64_IDX(RING_TIMESTAMP, RENDER_RING_BASE),
 448         REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */
 449         REG64(MI_PREDICATE_SRC0),
 450         REG64(MI_PREDICATE_SRC1),
 451         REG32(GEN7_3DPRIM_END_OFFSET),
 452         REG32(GEN7_3DPRIM_START_VERTEX),
 453         REG32(GEN7_3DPRIM_VERTEX_COUNT),
 454         REG32(GEN7_3DPRIM_INSTANCE_COUNT),
 455         REG32(GEN7_3DPRIM_START_INSTANCE),
 456         REG32(GEN7_3DPRIM_BASE_VERTEX),
 457         REG32(GEN7_GPGPU_DISPATCHDIMX),
 458         REG32(GEN7_GPGPU_DISPATCHDIMY),
 459         REG32(GEN7_GPGPU_DISPATCHDIMZ),
 460         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 0),
 461         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 1),
 462         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 2),
 463         REG64_IDX(GEN7_SO_NUM_PRIMS_WRITTEN, 3),
 464         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 0),
 465         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 1),
 466         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 2),
 467         REG64_IDX(GEN7_SO_PRIM_STORAGE_NEEDED, 3),
 468         REG32(GEN7_SO_WRITE_OFFSET(0)),
 469         REG32(GEN7_SO_WRITE_OFFSET(1)),
 470         REG32(GEN7_SO_WRITE_OFFSET(2)),
 471         REG32(GEN7_SO_WRITE_OFFSET(3)),
 472         REG32(GEN7_L3SQCREG1),
 473         REG32(GEN7_L3CNTLREG2),
 474         REG32(GEN7_L3CNTLREG3),
 475 };
 476
 477 static const struct drm_i915_reg_descriptor hsw_render_regs[] = {
 478         REG64_IDX(HSW_CS_GPR, 0),
 479         REG64_IDX(HSW_CS_GPR, 1),
 480         REG64_IDX(HSW_CS_GPR, 2),
 481         REG64_IDX(HSW_CS_GPR, 3),
 482         REG64_IDX(HSW_CS_GPR, 4),
 483         REG64_IDX(HSW_CS_GPR, 5),
 484         REG64_IDX(HSW_CS_GPR, 6),
 485         REG64_IDX(HSW_CS_GPR, 7),
 486         REG64_IDX(HSW_CS_GPR, 8),
 487         REG64_IDX(HSW_CS_GPR, 9),
 488         REG64_IDX(HSW_CS_GPR, 10),
 489         REG64_IDX(HSW_CS_GPR, 11),
 490         REG64_IDX(HSW_CS_GPR, 12),
 491         REG64_IDX(HSW_CS_GPR, 13),
 492         REG64_IDX(HSW_CS_GPR, 14),
 493         REG64_IDX(HSW_CS_GPR, 15),
 494         REG32(HSW_SCRATCH1,
 495               .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
 496               .value = 0),
 497         REG32(HSW_ROW_CHICKEN3,
 498               .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
 499                         HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE),
 500               .value = 0),
 501 };
 502
 503 static const struct drm_i915_reg_descriptor gen7_blt_regs[] = {
 504         REG32(BCS_SWCTRL),
 505 };
 506
 507 static const struct drm_i915_reg_descriptor ivb_master_regs[] = {
 508         REG32(FORCEWAKE_MT),
 509         REG32(DERRMR),
 510         REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
 511         REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_B)),
 512         REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_C)),
 513 };
 514
 515 static const struct drm_i915_reg_descriptor hsw_master_regs[] = {
 516         REG32(FORCEWAKE_MT),
 517         REG32(DERRMR),
 518 };
 519
 520 #undef REG64
 521 #undef REG32
 522
 523 struct drm_i915_reg_table {
 524         const struct drm_i915_reg_descriptor *regs;
 525         int num_regs;
 526         bool master;
 527 };
 528
 529 static const struct drm_i915_reg_table ivb_render_reg_tables[] = {
 530         { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
 531         { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
 532 };
 533
 534 static const struct drm_i915_reg_table ivb_blt_reg_tables[] = {
 535         { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
 536         { ivb_master_regs, ARRAY_SIZE(ivb_master_regs), true },
 537 };
 538
 539 static const struct drm_i915_reg_table hsw_render_reg_tables[] = {
 540         { gen7_render_regs, ARRAY_SIZE(gen7_render_regs), false },
 541         { hsw_render_regs, ARRAY_SIZE(hsw_render_regs), false },
 542         { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
 543 };
 544
 545 static const struct drm_i915_reg_table hsw_blt_reg_tables[] = {
 546         { gen7_blt_regs, ARRAY_SIZE(gen7_blt_regs), false },
 547         { hsw_master_regs, ARRAY_SIZE(hsw_master_regs), true },
 548 };
 549
 550 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
 551 {
 552         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 553         u32 subclient =
 554                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 555
 556         if (client == INSTR_MI_CLIENT)
 557                 return 0x3F;
 558         else if (client == INSTR_RC_CLIENT) {
 559                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 560                         return 0xFFFF;
 561                 else
 562                         return 0xFF;
 563         }
 564
 565         DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
 566         return 0;
 567 }
 568
 569 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
 570 {
 571         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 572         u32 subclient =
 573                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 574         u32 op = (cmd_header & INSTR_26_TO_24_MASK) >> INSTR_26_TO_24_SHIFT;
 575
 576         if (client == INSTR_MI_CLIENT)
 577                 return 0x3F;
 578         else if (client == INSTR_RC_CLIENT) {
 579                 if (subclient == INSTR_MEDIA_SUBCLIENT) {
 580                         if (op == 6)
 581                                 return 0xFFFF;
 582                         else
 583                                 return 0xFFF;
 584                 } else
 585                         return 0xFF;
 586         }
 587
 588         DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
 589         return 0;
 590 }
 591
 592 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
 593 {
 594         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 595
 596         if (client == INSTR_MI_CLIENT)
 597                 return 0x3F;
 598         else if (client == INSTR_BC_CLIENT)
 599                 return 0xFF;
 600
 601         DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
 602         return 0;
 603 }
 604
 605 static bool validate_cmds_sorted(struct intel_engine_cs *engine,
 606                                  const struct drm_i915_cmd_table *cmd_tables,
 607                                  int cmd_table_count)
 608 {
 609         int i;
 610         bool ret = true;
 611
 612         if (!cmd_tables || cmd_table_count == 0)
 613                 return true;
 614
 615         for (i = 0; i < cmd_table_count; i++) {
 616                 const struct drm_i915_cmd_table *table = &cmd_tables[i];
 617                 u32 previous = 0;
 618                 int j;
 619
 620                 for (j = 0; j < table->count; j++) {
 621                         const struct drm_i915_cmd_descriptor *desc =
 622                                 &table->table[j];
 623                         u32 curr = desc->cmd.value & desc->cmd.mask;
 624
 625                         if (curr < previous) {
 626                                 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
 627                                           engine->id, i, j, curr, previous);
 628                                 ret = false;
 629                         }
 630
 631                         previous = curr;
 632                 }
 633         }
 634
 635         return ret;
 636 }
 637
 638 static bool check_sorted(int ring_id,
 639                          const struct drm_i915_reg_descriptor *reg_table,
 640                          int reg_count)
 641 {
 642         int i;
 643         u32 previous = 0;
 644         bool ret = true;
 645
 646         for (i = 0; i < reg_count; i++) {
 647                 u32 curr = i915_mmio_reg_offset(reg_table[i].addr);
 648
 649                 if (curr < previous) {
 650                         DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
 651                                   ring_id, i, curr, previous);
 652                         ret = false;
 653                 }
 654
 655                 previous = curr;
 656         }
 657
 658         return ret;
 659 }
 660
 661 static bool validate_regs_sorted(struct intel_engine_cs *engine)
 662 {
 663         int i;
 664         const struct drm_i915_reg_table *table;
 665
 666         for (i = 0; i < engine->reg_table_count; i++) {
 667                 table = &engine->reg_tables[i];
 668                 if (!check_sorted(engine->id, table->regs, table->num_regs))
 669                         return false;
 670         }
 671
 672         return true;
 673 }
 674
 675 struct cmd_node {
 676         const struct drm_i915_cmd_descriptor *desc;
 677         struct hlist_node node;
 678 };
 679
 680 /*
 681  * Different command ranges have different numbers of bits for the opcode. For
 682  * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
 683  * problem is that, for example, MI commands use bits 22:16 for other fields
 684  * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
 685  * we mask a command from a batch it could hash to the wrong bucket due to
 686  * non-opcode bits being set. But if we don't include those bits, some 3D
 687  * commands may hash to the same bucket due to not including opcode bits that
 688  * make the command unique. For now, we will risk hashing to the same bucket.
 689  *
 690  * If we attempt to generate a perfect hash, we should be able to look at bits
 691  * 31:29 of a command from a batch buffer and use the full mask for that
 692  * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this.
 693  */
 694 #define CMD_HASH_MASK STD_MI_OPCODE_MASK
 695
 696 static int init_hash_table(struct intel_engine_cs *engine,
 697                            const struct drm_i915_cmd_table *cmd_tables,
 698                            int cmd_table_count)
 699 {
 700 #if 0
 701         int i, j;
 702
 703         hash_init(engine->cmd_hash);
 704
 705         for (i = 0; i < cmd_table_count; i++) {
 706                 const struct drm_i915_cmd_table *table = &cmd_tables[i];
 707
 708                 for (j = 0; j < table->count; j++) {
 709                         const struct drm_i915_cmd_descriptor *desc =
 710                                 &table->table[j];
 711                         struct cmd_node *desc_node =
 712                                 kmalloc(sizeof(*desc_node), GFP_KERNEL);
 713
 714                         if (!desc_node)
 715                                 return -ENOMEM;
 716
 717                         desc_node->desc = desc;
 718                         hash_add(engine->cmd_hash, &desc_node->node,
 719                                  desc->cmd.value & CMD_HASH_MASK);
 720                 }
 721         }
 722 #endif
 723
 724         return 0;
 725 }
 726
 727 static void fini_hash_table(struct intel_engine_cs *engine)
 728 {
 729 #if 0
 730         struct hlist_node *tmp;
 731         struct cmd_node *desc_node;
 732         int i;
 733
 734         hash_for_each_safe(engine->cmd_hash, i, tmp, desc_node, node) {
 735                 hash_del(&desc_node->node);
 736                 kfree(desc_node);
 737         }
 738 #endif
 739 }
 740
 741 /**
 742  * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
 743  * @ring: the ringbuffer to initialize
 744  *
 745  * Optionally initializes fields related to batch buffer command parsing in the
 746  * struct intel_engine_cs based on whether the platform requires software
 747  * command parsing.
 748  *
 749  * Return: non-zero if initialization fails
 750  */
 751 int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
 752 {
 753         const struct drm_i915_cmd_table *cmd_tables;
 754         int cmd_table_count;
 755         int ret;
 756
 757         if (!IS_GEN7(engine->dev))
 758                 return 0;
 759
 760         switch (engine->id) {
 761         case RCS:
 762                 if (IS_HASWELL(engine->dev)) {
 763                         cmd_tables = hsw_render_ring_cmds;
 764                         cmd_table_count =
 765                                 ARRAY_SIZE(hsw_render_ring_cmds);
 766                 } else {
 767                         cmd_tables = gen7_render_cmds;
 768                         cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
 769                 }
 770
 771                 if (IS_HASWELL(engine->dev)) {
 772                         engine->reg_tables = hsw_render_reg_tables;
 773                         engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
 774                 } else {
 775                         engine->reg_tables = ivb_render_reg_tables;
 776                         engine->reg_table_count = ARRAY_SIZE(ivb_render_reg_tables);
 777                 }
 778
 779                 engine->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
 780                 break;
 781         case VCS:
 782                 cmd_tables = gen7_video_cmds;
 783                 cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
 784                 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 785                 break;
 786         case BCS:
 787                 if (IS_HASWELL(engine->dev)) {
 788                         cmd_tables = hsw_blt_ring_cmds;
 789                         cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
 790                 } else {
 791                         cmd_tables = gen7_blt_cmds;
 792                         cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
 793                 }
 794
 795                 if (IS_HASWELL(engine->dev)) {
 796                         engine->reg_tables = hsw_blt_reg_tables;
 797                         engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
 798                 } else {
 799                         engine->reg_tables = ivb_blt_reg_tables;
 800                         engine->reg_table_count = ARRAY_SIZE(ivb_blt_reg_tables);
 801                 }
 802
 803                 engine->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
 804                 break;
 805         case VECS:
 806                 cmd_tables = hsw_vebox_cmds;
 807                 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
 808                 /* VECS can use the same length_mask function as VCS */
 809                 engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 810                 break;
 811         default:
 812                 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
 813                           engine->id);
 814                 BUG();
 815         }
 816
 817         BUG_ON(!validate_cmds_sorted(engine, cmd_tables, cmd_table_count));
 818         BUG_ON(!validate_regs_sorted(engine));
 819
 820 #if 0
 821         WARN_ON(!hash_empty(engine->cmd_hash));
 822 #endif
 823
 824         ret = init_hash_table(engine, cmd_tables, cmd_table_count);
 825         if (ret) {
 826                 DRM_ERROR("CMD: cmd_parser_init failed!\n");
 827                 fini_hash_table(engine);
 828                 return ret;
 829         }
 830
 831         engine->needs_cmd_parser = true;
 832
 833         return 0;
 834 }
 835
 836 /**
 837  * i915_cmd_parser_fini_ring() - clean up cmd parser related fields
 838  * @ring: the ringbuffer to clean up
 839  *
 840  * Releases any resources related to command parsing that may have been
 841  * initialized for the specified ring.
 842  */
 843 void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine)
 844 {
 845         if (!engine->needs_cmd_parser)
 846                 return;
 847
 848         fini_hash_table(engine);
 849 }
 850
 851 static const struct drm_i915_cmd_descriptor*
 852 find_cmd_in_table(struct intel_engine_cs *engine,
 853                   u32 cmd_header)
 854 {
 855 #if 0
 856         struct cmd_node *desc_node;
 857
 858         hash_for_each_possible(engine->cmd_hash, desc_node, node,
 859                                cmd_header & CMD_HASH_MASK) {
 860                 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
 861                 u32 masked_cmd = desc->cmd.mask & cmd_header;
 862                 u32 masked_value = desc->cmd.value & desc->cmd.mask;
 863
 864                 if (masked_cmd == masked_value)
 865                         return desc;
 866         }
 867 #endif
 868
 869         return NULL;
 870 }
 871
 872 /*
 873  * Returns a pointer to a descriptor for the command specified by cmd_header.
 874  *
 875  * The caller must supply space for a default descriptor via the default_desc
 876  * parameter. If no descriptor for the specified command exists in the ring's
 877  * command parser tables, this function fills in default_desc based on the
 878  * ring's default length encoding and returns default_desc.
 879  */
 880 static const struct drm_i915_cmd_descriptor*
 881 find_cmd(struct intel_engine_cs *engine,
 882          u32 cmd_header,
 883          struct drm_i915_cmd_descriptor *default_desc)
 884 {
 885         const struct drm_i915_cmd_descriptor *desc;
 886         u32 mask;
 887
 888         desc = find_cmd_in_table(engine, cmd_header);
 889         if (desc)
 890                 return desc;
 891
 892         mask = engine->get_cmd_length_mask(cmd_header);
 893         if (!mask)
 894                 return NULL;
 895
 896         BUG_ON(!default_desc);
 897         default_desc->flags = CMD_DESC_SKIP;
 898         default_desc->length.mask = mask;
 899
 900         return default_desc;
 901 }
 902
 903 static const struct drm_i915_reg_descriptor *
 904 find_reg(const struct drm_i915_reg_descriptor *table,
 905          int count, u32 addr)
 906 {
 907         int i;
 908
 909         for (i = 0; i < count; i++) {
 910                 if (i915_mmio_reg_offset(table[i].addr) == addr)
 911                         return &table[i];
 912         }
 913
 914         return NULL;
 915 }
 916
 917 static const struct drm_i915_reg_descriptor *
 918 find_reg_in_tables(const struct drm_i915_reg_table *tables,
 919                    int count, bool is_master, u32 addr)
 920 {
 921         int i;
 922         const struct drm_i915_reg_table *table;
 923         const struct drm_i915_reg_descriptor *reg;
 924
 925         for (i = 0; i < count; i++) {
 926                 table = &tables[i];
 927                 if (!table->master || is_master) {
 928                         reg = find_reg(table->regs, table->num_regs,
 929                                        addr);
 930                         if (reg != NULL)
 931                                 return reg;
 932                 }
 933         }
 934
 935         return NULL;
 936 }
 937
 938 static u32 *vmap_batch(struct drm_i915_gem_object *obj,
 939                        unsigned start, unsigned len)
 940 {
 941         int i;
 942         void *addr = NULL;
 943         struct sg_page_iter sg_iter;
 944         int first_page = start >> PAGE_SHIFT;
 945         int last_page = (len + start + 4095) >> PAGE_SHIFT;
 946         int npages = last_page - first_page;
 947         struct page **pages;
 948
 949         pages = drm_malloc_ab(npages, sizeof(*pages));
 950         if (pages == NULL) {
 951                 DRM_DEBUG_DRIVER("Failed to get space for pages\n");
 952                 goto finish;
 953         }
 954
 955         i = 0;
 956         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, first_page) {
 957                 pages[i++] = sg_page_iter_page(&sg_iter);
 958                 if (i == npages)
 959                         break;
 960         }
 961
 962 #if 0
 963         addr = vmap(pages, i, 0, PAGE_KERNEL);
 964         if (addr == NULL) {
 965                 DRM_DEBUG_DRIVER("Failed to vmap pages\n");
 966                 goto finish;
 967         }
 968 #endif
 969
 970 finish:
 971         if (pages)
 972                 drm_free_large(pages);
 973         return (u32*)addr;
 974 }
 975
 976 /* Returns a vmap'd pointer to dest_obj, which the caller must unmap */
 977 static u32 *copy_batch(struct drm_i915_gem_object *dest_obj,
 978                        struct drm_i915_gem_object *src_obj,
 979                        u32 batch_start_offset,
 980                        u32 batch_len)
 981 {
 982         int needs_clflush = 0;
 983         char *src_base, *src;
 984         void *dst = NULL;
 985         int ret;
 986
 987         if (batch_len > dest_obj->base.size ||
 988             batch_len + batch_start_offset > src_obj->base.size)
 989                 return ERR_PTR(-E2BIG);
 990
 991         if (WARN_ON(dest_obj->pages_pin_count == 0))
 992                 return ERR_PTR(-ENODEV);
 993
 994         ret = i915_gem_obj_prepare_shmem_read(src_obj, &needs_clflush);
 995         if (ret) {
 996                 DRM_DEBUG_DRIVER("CMD: failed to prepare shadow batch\n");
 997                 return ERR_PTR(ret);
 998         }
 999
1000         src_base = (char *)vmap_batch(src_obj, batch_start_offset, batch_len);
1001         if (!src_base) {
1002                 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
1003                 ret = -ENOMEM;
1004                 goto unpin_src;
1005         }
1006
1007         ret = i915_gem_object_set_to_cpu_domain(dest_obj, true);
1008         if (ret) {
1009                 DRM_DEBUG_DRIVER("CMD: Failed to set shadow batch to CPU\n");
1010                 goto unmap_src;
1011         }
1012
1013         dst = vmap_batch(dest_obj, 0, batch_len);
1014         if (!dst) {
1015                 DRM_DEBUG_DRIVER("CMD: Failed to vmap shadow batch\n");
1016                 ret = -ENOMEM;
1017                 goto unmap_src;
1018         }
1019
1020         src = src_base + offset_in_page(batch_start_offset);
1021         if (needs_clflush)
1022                 drm_clflush_virt_range(src, batch_len);
1023
1024         memcpy(dst, src, batch_len);
1025
1026 unmap_src:
1027         vunmap(src_base);
1028 unpin_src:
1029         i915_gem_object_unpin_pages(src_obj);
1030
1031         return ret ? ERR_PTR(ret) : dst;
1032 }
1033
1034 /**
1035  * i915_needs_cmd_parser() - should a given ring use software command parsing?
1036  * @ring: the ring in question
1037  *
1038  * Only certain platforms require software batch buffer command parsing, and
1039  * only when enabled via module parameter.
1040  *
1041  * Return: true if the ring requires software command parsing
1042  */
1043 bool i915_needs_cmd_parser(struct intel_engine_cs *engine)
1044 {
1045         if (!engine->needs_cmd_parser)
1046                 return false;
1047
1048         if (!USES_PPGTT(engine->dev))
1049                 return false;
1050
1051         return (i915.enable_cmd_parser == 1);
1052 }
1053
1054 static bool check_cmd(const struct intel_engine_cs *engine,
1055                       const struct drm_i915_cmd_descriptor *desc,
1056                       const u32 *cmd, u32 length,
1057                       const bool is_master,
1058                       bool *oacontrol_set)
1059 {
1060         if (desc->flags & CMD_DESC_REJECT) {
1061                 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
1062                 return false;
1063         }
1064
1065         if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
1066                 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
1067                                  *cmd);
1068                 return false;
1069         }
1070
1071         if (desc->flags & CMD_DESC_REGISTER) {
1072                 /*
1073                  * Get the distance between individual register offset
1074                  * fields if the command can perform more than one
1075                  * access at a time.
1076                  */
1077                 const u32 step = desc->reg.step ? desc->reg.step : length;
1078                 u32 offset;
1079
1080                 for (offset = desc->reg.offset; offset < length;
1081                      offset += step) {
1082                         const u32 reg_addr = cmd[offset] & desc->reg.mask;
1083                         const struct drm_i915_reg_descriptor *reg =
1084                                 find_reg_in_tables(engine->reg_tables,
1085                                                    engine->reg_table_count,
1086                                                    is_master,
1087                                                    reg_addr);
1088
1089                         if (!reg) {
1090                                 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
1091                                                  reg_addr, *cmd, engine->id);
1092                                 return false;
1093                         }
1094
1095                         /*
1096                          * OACONTROL requires some special handling for
1097                          * writes. We want to make sure that any batch which
1098                          * enables OA also disables it before the end of the
1099                          * batch. The goal is to prevent one process from
1100                          * snooping on the perf data from another process. To do
1101                          * that, we need to check the value that will be written
1102                          * to the register. Hence, limit OACONTROL writes to
1103                          * only MI_LOAD_REGISTER_IMM commands.
1104                          */
1105                         if (reg_addr == i915_mmio_reg_offset(OACONTROL)) {
1106                                 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1107                                         DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
1108                                         return false;
1109                                 }
1110
1111                                 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
1112                                         *oacontrol_set = (cmd[offset + 1] != 0);
1113                         }
1114
1115                         /*
1116                          * Check the value written to the register against the
1117                          * allowed mask/value pair given in the whitelist entry.
1118                          */
1119                         if (reg->mask) {
1120                                 if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
1121                                         DRM_DEBUG_DRIVER("CMD: Rejected LRM to masked register 0x%08X\n",
1122                                                          reg_addr);
1123                                         return false;
1124                                 }
1125
1126                                 if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
1127                                     (offset + 2 > length ||
1128                                      (cmd[offset + 1] & reg->mask) != reg->value)) {
1129                                         DRM_DEBUG_DRIVER("CMD: Rejected LRI to masked register 0x%08X\n",
1130                                                          reg_addr);
1131                                         return false;
1132                                 }
1133                         }
1134                 }
1135         }
1136
1137         if (desc->flags & CMD_DESC_BITMASK) {
1138                 int i;
1139
1140                 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
1141                         u32 dword;
1142
1143                         if (desc->bits[i].mask == 0)
1144                                 break;
1145
1146                         if (desc->bits[i].condition_mask != 0) {
1147                                 u32 offset =
1148                                         desc->bits[i].condition_offset;
1149                                 u32 condition = cmd[offset] &
1150                                         desc->bits[i].condition_mask;
1151
1152                                 if (condition == 0)
1153                                         continue;
1154                         }
1155
1156                         dword = cmd[desc->bits[i].offset] &
1157                                 desc->bits[i].mask;
1158
1159                         if (dword != desc->bits[i].expected) {
1160                                 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
1161                                                  *cmd,
1162                                                  desc->bits[i].mask,
1163                                                  desc->bits[i].expected,
1164                                                  dword, engine->id);
1165                                 return false;
1166                         }
1167                 }
1168         }
1169
1170         return true;
1171 }
1172
1173 #define LENGTH_BIAS 2
1174
1175 /**
1176  * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
1177  * @ring: the ring on which the batch is to execute
1178  * @batch_obj: the batch buffer in question
1179  * @shadow_batch_obj: copy of the batch buffer in question
1180  * @batch_start_offset: byte offset in the batch at which execution starts
1181  * @batch_len: length of the commands in batch_obj
1182  * @is_master: is the submitting process the drm master?
1183  *
1184  * Parses the specified batch buffer looking for privilege violations as
1185  * described in the overview.
1186  *
1187  * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
1188  * if the batch appears legal but should use hardware parsing
1189  */
1190 int i915_parse_cmds(struct intel_engine_cs *engine,
1191                     struct drm_i915_gem_object *batch_obj,
1192                     struct drm_i915_gem_object *shadow_batch_obj,
1193                     u32 batch_start_offset,
1194                     u32 batch_len,
1195                     bool is_master)
1196 {
1197         u32 *cmd, *batch_base, *batch_end;
1198         struct drm_i915_cmd_descriptor default_desc = { 0 };
1199         bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
1200         int ret = 0;
1201
1202         batch_base = copy_batch(shadow_batch_obj, batch_obj,
1203                                 batch_start_offset, batch_len);
1204         if (IS_ERR(batch_base)) {
1205                 DRM_DEBUG_DRIVER("CMD: Failed to copy batch\n");
1206                 return PTR_ERR(batch_base);
1207         }
1208
1209         /*
1210          * We use the batch length as size because the shadow object is as
1211          * large or larger and copy_batch() will write MI_NOPs to the extra
1212          * space. Parsing should be faster in some cases this way.
1213          */
1214         batch_end = batch_base + (batch_len / sizeof(*batch_end));
1215
1216         cmd = batch_base;
1217         while (cmd < batch_end) {
1218                 const struct drm_i915_cmd_descriptor *desc;
1219                 u32 length;
1220
1221                 if (*cmd == MI_BATCH_BUFFER_END)
1222                         break;
1223
1224                 desc = find_cmd(engine, *cmd, &default_desc);
1225                 if (!desc) {
1226                         DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
1227                                          *cmd);
1228                         ret = -EINVAL;
1229                         break;
1230                 }
1231
1232                 /*
1233                  * If the batch buffer contains a chained batch, return an
1234                  * error that tells the caller to abort and dispatch the
1235                  * workload as a non-secure batch.
1236                  */
1237                 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1238                         ret = -EACCES;
1239                         break;
1240                 }
1241
1242                 if (desc->flags & CMD_DESC_FIXED)
1243                         length = desc->length.fixed;
1244                 else
1245                         length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
1246
1247                 if ((batch_end - cmd) < length) {
1248                         DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1249                                          *cmd,
1250                                          length,
1251                                          batch_end - cmd);
1252                         ret = -EINVAL;
1253                         break;
1254                 }
1255
1256                 if (!check_cmd(engine, desc, cmd, length, is_master,
1257                                &oacontrol_set)) {
1258                         ret = -EINVAL;
1259                         break;
1260                 }
1261
1262                 cmd += length;
1263         }
1264
1265         if (oacontrol_set) {
1266                 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n");
1267                 ret = -EINVAL;
1268         }
1269
1270         if (cmd >= batch_end) {
1271                 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1272                 ret = -EINVAL;
1273         }
1274
1275         vunmap(batch_base);
1276
1277         return ret;
1278 }
1279
1280 /**
1281  * i915_cmd_parser_get_version() - get the cmd parser version number
1282  *
1283  * The cmd parser maintains a simple increasing integer version number suitable
1284  * for passing to userspace clients to determine what operations are permitted.
1285  *
1286  * Return: the current version number of the cmd parser
1287  */
1288 int i915_cmd_parser_get_version(void)
1289 {
1290         /*
1291          * Command parser version history
1292          *
1293          * 1. Initial version. Checks batches and reports violations, but leaves
1294          *    hardware parsing enabled (so does not allow new use cases).
1295          * 2. Allow access to the MI_PREDICATE_SRC0 and
1296          *    MI_PREDICATE_SRC1 registers.
1297          * 3. Allow access to the GPGPU_THREADS_DISPATCHED register.
1298          * 4. L3 atomic chicken bits of HSW_SCRATCH1 and HSW_ROW_CHICKEN3.
1299          * 5. GPGPU dispatch compute indirect registers.
1300          * 6. TIMESTAMP register and Haswell CS GPR registers
1301          */
1302         return 6;
1303 }