2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <william.paul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
34 * $DragonFly: src/sys/dev/netif/lge/if_lge.c,v 1.18 2005/02/18 23:40:10 joerg Exp $
36 * $FreeBSD: src/sys/dev/lge/if_lge.c,v 1.5.2.2 2001/12/14 19:49:23 jlemon Exp $
40 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public
41 * documentation not available, but ask me nicely.
43 * Written by Bill Paul <william.paul@windriver.com>
48 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs.
49 * It's a 64-bit PCI part that supports TCP/IP checksum offload,
50 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There
51 * are three supported methods for data transfer between host and
52 * NIC: programmed I/O, traditional scatter/gather DMA and Packet
53 * Propulsion Technology (tm) DMA. The latter mechanism is a form
54 * of double buffer DMA where the packet data is copied to a
55 * pre-allocated DMA buffer who's physical address has been loaded
56 * into a table at device initialization time. The rationale is that
57 * the virtual to physical address translation needed for normal
58 * scatter/gather DMA is more expensive than the data copy needed
59 * for double buffering. This may be true in Windows NT and the like,
60 * but it isn't true for us, at least on the x86 arch. This driver
61 * uses the scatter/gather I/O method for both TX and RX.
63 * The LXT1001 only supports TCP/IP checksum offload on receive.
64 * Also, the VLAN tagging is done using a 16-entry table which allows
65 * the chip to perform hardware filtering based on VLAN tags. Sadly,
66 * our vlan support doesn't currently play well with this kind of
70 * - Jeff James at Intel, for arranging to have the LXT1001 manual
71 * released (at long last)
72 * - Beny Chen at D-Link, for actually sending it to me
73 * - Brad Short and Keith Alexis at SMC, for sending me sample
74 * SMC9462SX and SMC9462TX adapters for testing
75 * - Paul Saab at Y!, for not killing me (though it remains to be seen
76 * if in fact he did me much of a favor)
79 #include <sys/param.h>
80 #include <sys/systm.h>
81 #include <sys/sockio.h>
83 #include <sys/malloc.h>
84 #include <sys/kernel.h>
85 #include <sys/socket.h>
88 #include <net/ifq_var.h>
89 #include <net/if_arp.h>
90 #include <net/ethernet.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
96 #include <vm/vm.h> /* for vtophys */
97 #include <vm/pmap.h> /* for vtophys */
98 #include <machine/clock.h> /* for DELAY */
99 #include <machine/bus_pio.h>
100 #include <machine/bus_memio.h>
101 #include <machine/bus.h>
102 #include <machine/resource.h>
104 #include <sys/rman.h>
106 #include "../mii_layer/mii.h"
107 #include "../mii_layer/miivar.h"
109 #include <bus/pci/pcireg.h>
110 #include <bus/pci/pcivar.h>
112 #define LGE_USEIOSPACE
114 #include "if_lgereg.h"
116 /* "controller miibus0" required. See GENERIC if you get errors here. */
117 #include "miibus_if.h"
120 * Various supported device vendors/types and their names.
122 static struct lge_type lge_devs[] = {
123 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" },
127 static int lge_probe (device_t);
128 static int lge_attach (device_t);
129 static int lge_detach (device_t);
131 static int lge_alloc_jumbo_mem (struct lge_softc *);
132 static void lge_free_jumbo_mem (struct lge_softc *);
133 static void *lge_jalloc (struct lge_softc *);
134 static void lge_jfree (caddr_t, u_int);
135 static void lge_jref (caddr_t, u_int);
137 static int lge_newbuf (struct lge_softc *,
138 struct lge_rx_desc *,
140 static int lge_encap (struct lge_softc *,
141 struct mbuf *, u_int32_t *);
142 static void lge_rxeof (struct lge_softc *, int);
143 static void lge_rxeoc (struct lge_softc *);
144 static void lge_txeof (struct lge_softc *);
145 static void lge_intr (void *);
146 static void lge_tick (void *);
147 static void lge_start (struct ifnet *);
148 static int lge_ioctl (struct ifnet *, u_long, caddr_t,
150 static void lge_init (void *);
151 static void lge_stop (struct lge_softc *);
152 static void lge_watchdog (struct ifnet *);
153 static void lge_shutdown (device_t);
154 static int lge_ifmedia_upd (struct ifnet *);
155 static void lge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
157 static void lge_eeprom_getword (struct lge_softc *, int, u_int16_t *);
158 static void lge_read_eeprom (struct lge_softc *, caddr_t, int,
161 static int lge_miibus_readreg (device_t, int, int);
162 static int lge_miibus_writereg (device_t, int, int, int);
163 static void lge_miibus_statchg (device_t);
165 static void lge_setmulti (struct lge_softc *);
166 static u_int32_t lge_crc (struct lge_softc *, caddr_t);
167 static void lge_reset (struct lge_softc *);
168 static int lge_list_rx_init (struct lge_softc *);
169 static int lge_list_tx_init (struct lge_softc *);
171 #ifdef LGE_USEIOSPACE
172 #define LGE_RES SYS_RES_IOPORT
173 #define LGE_RID LGE_PCI_LOIO
175 #define LGE_RES SYS_RES_MEMORY
176 #define LGE_RID LGE_PCI_LOMEM
179 static device_method_t lge_methods[] = {
180 /* Device interface */
181 DEVMETHOD(device_probe, lge_probe),
182 DEVMETHOD(device_attach, lge_attach),
183 DEVMETHOD(device_detach, lge_detach),
184 DEVMETHOD(device_shutdown, lge_shutdown),
187 DEVMETHOD(bus_print_child, bus_generic_print_child),
188 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
191 DEVMETHOD(miibus_readreg, lge_miibus_readreg),
192 DEVMETHOD(miibus_writereg, lge_miibus_writereg),
193 DEVMETHOD(miibus_statchg, lge_miibus_statchg),
198 static driver_t lge_driver = {
201 sizeof(struct lge_softc)
204 static devclass_t lge_devclass;
206 DECLARE_DUMMY_MODULE(if_lge);
207 DRIVER_MODULE(if_lge, pci, lge_driver, lge_devclass, 0, 0);
208 DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0);
210 #define LGE_SETBIT(sc, reg, x) \
211 CSR_WRITE_4(sc, reg, \
212 CSR_READ_4(sc, reg) | (x))
214 #define LGE_CLRBIT(sc, reg, x) \
215 CSR_WRITE_4(sc, reg, \
216 CSR_READ_4(sc, reg) & ~(x))
219 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x)
222 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x)
225 * Read a word of data stored in the EEPROM at address 'addr.'
227 static void lge_eeprom_getword(sc, addr, dest)
228 struct lge_softc *sc;
235 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ|
236 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8));
238 for (i = 0; i < LGE_TIMEOUT; i++)
239 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ))
242 if (i == LGE_TIMEOUT) {
243 printf("lge%d: EEPROM read timed out\n", sc->lge_unit);
247 val = CSR_READ_4(sc, LGE_EEDATA);
250 *dest = (val >> 16) & 0xFFFF;
252 *dest = val & 0xFFFF;
258 * Read a sequence of words from the EEPROM.
260 static void lge_read_eeprom(sc, dest, off, cnt, swap)
261 struct lge_softc *sc;
268 u_int16_t word = 0, *ptr;
270 for (i = 0; i < cnt; i++) {
271 lge_eeprom_getword(sc, off + i, &word);
272 ptr = (u_int16_t *)(dest + (i * 2));
282 static int lge_miibus_readreg(dev, phy, reg)
286 struct lge_softc *sc;
289 sc = device_get_softc(dev);
292 * If we have a non-PCS PHY, pretend that the internal
293 * autoneg stuff at PHY address 0 isn't there so that
294 * the miibus code will find only the GMII PHY.
296 if (sc->lge_pcs == 0 && phy == 0)
299 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ);
301 for (i = 0; i < LGE_TIMEOUT; i++)
302 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
305 if (i == LGE_TIMEOUT) {
306 printf("lge%d: PHY read timed out\n", sc->lge_unit);
310 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16);
313 static int lge_miibus_writereg(dev, phy, reg, data)
317 struct lge_softc *sc;
320 sc = device_get_softc(dev);
322 CSR_WRITE_4(sc, LGE_GMIICTL,
323 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE);
325 for (i = 0; i < LGE_TIMEOUT; i++)
326 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY))
329 if (i == LGE_TIMEOUT) {
330 printf("lge%d: PHY write timed out\n", sc->lge_unit);
337 static void lge_miibus_statchg(dev)
340 struct lge_softc *sc;
341 struct mii_data *mii;
343 sc = device_get_softc(dev);
344 mii = device_get_softc(sc->lge_miibus);
346 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED);
347 switch (IFM_SUBTYPE(mii->mii_media_active)) {
350 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
353 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100);
356 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10);
360 * Choose something, even if it's wrong. Clearing
361 * all the bits will hose autoneg on the internal
364 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000);
368 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
369 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
371 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX);
377 static u_int32_t lge_crc(sc, addr)
378 struct lge_softc *sc;
381 u_int32_t crc, carry;
385 /* Compute CRC for the address value. */
386 crc = 0xFFFFFFFF; /* initial value */
388 for (i = 0; i < 6; i++) {
390 for (j = 0; j < 8; j++) {
391 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
395 crc = (crc ^ 0x04c11db6) | carry;
400 * return the filter bit position
402 return((crc >> 26) & 0x0000003F);
405 static void lge_setmulti(sc)
406 struct lge_softc *sc;
409 struct ifmultiaddr *ifma;
410 u_int32_t h = 0, hashes[2] = { 0, 0 };
412 ifp = &sc->arpcom.ac_if;
414 /* Make sure multicast hash table is enabled. */
415 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST);
417 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
418 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF);
419 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF);
423 /* first, zot all the existing hash bits */
424 CSR_WRITE_4(sc, LGE_MAR0, 0);
425 CSR_WRITE_4(sc, LGE_MAR1, 0);
427 /* now program new ones */
428 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
429 ifma = ifma->ifma_link.le_next) {
430 if (ifma->ifma_addr->sa_family != AF_LINK)
432 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
434 hashes[0] |= (1 << h);
436 hashes[1] |= (1 << (h - 32));
439 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]);
440 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]);
445 static void lge_reset(sc)
446 struct lge_softc *sc;
450 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST);
452 for (i = 0; i < LGE_TIMEOUT; i++) {
453 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST))
457 if (i == LGE_TIMEOUT)
458 printf("lge%d: reset never completed\n", sc->lge_unit);
460 /* Wait a little while for the chip to get its brains in order. */
467 * Probe for a Level 1 chip. Check the PCI vendor and device
468 * IDs against our list and return a device name if we find a match.
470 static int lge_probe(dev)
477 while(t->lge_name != NULL) {
478 if ((pci_get_vendor(dev) == t->lge_vid) &&
479 (pci_get_device(dev) == t->lge_did)) {
480 device_set_desc(dev, t->lge_name);
490 * Attach the interface. Allocate softc structures, do ifmedia
491 * setup and ethernet/BPF attach.
493 static int lge_attach(dev)
497 u_char eaddr[ETHER_ADDR_LEN];
499 struct lge_softc *sc;
501 int unit, error = 0, rid;
505 sc = device_get_softc(dev);
506 unit = device_get_unit(dev);
507 bzero(sc, sizeof(struct lge_softc));
508 callout_init(&sc->lge_stat_timer);
511 * Handle power management nonsense.
513 command = pci_read_config(dev, LGE_PCI_CAPID, 4) & 0x000000FF;
514 if (command == 0x01) {
516 command = pci_read_config(dev, LGE_PCI_PWRMGMTCTRL, 4);
517 if (command & LGE_PSTATE_MASK) {
518 u_int32_t iobase, membase, irq;
520 /* Save important PCI config data. */
521 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4);
522 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4);
523 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4);
525 /* Reset the power state. */
526 printf("lge%d: chip is in D%d power mode "
527 "-- setting to D0\n", unit, command & LGE_PSTATE_MASK);
528 command &= 0xFFFFFFFC;
529 pci_write_config(dev, LGE_PCI_PWRMGMTCTRL, command, 4);
531 /* Restore PCI config data. */
532 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4);
533 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4);
534 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4);
539 * Map control/status registers.
541 command = pci_read_config(dev, PCIR_COMMAND, 4);
542 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
543 pci_write_config(dev, PCIR_COMMAND, command, 4);
544 command = pci_read_config(dev, PCIR_COMMAND, 4);
546 #ifdef LGE_USEIOSPACE
547 if (!(command & PCIM_CMD_PORTEN)) {
548 printf("lge%d: failed to enable I/O ports!\n", unit);
553 if (!(command & PCIM_CMD_MEMEN)) {
554 printf("lge%d: failed to enable memory mapping!\n", unit);
561 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid,
562 0, ~0, 1, RF_ACTIVE);
564 if (sc->lge_res == NULL) {
565 printf("lge%d: couldn't map ports/memory\n", unit);
570 sc->lge_btag = rman_get_bustag(sc->lge_res);
571 sc->lge_bhandle = rman_get_bushandle(sc->lge_res);
573 /* Allocate interrupt */
575 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
576 RF_SHAREABLE | RF_ACTIVE);
578 if (sc->lge_irq == NULL) {
579 printf("lge%d: couldn't map interrupt\n", unit);
580 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
585 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET,
586 lge_intr, sc, &sc->lge_intrhand);
589 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
590 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
591 printf("lge%d: couldn't set up irq\n", unit);
595 /* Reset the adapter. */
599 * Get station address from the EEPROM.
601 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0);
602 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0);
603 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0);
607 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF,
608 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
610 if (sc->lge_ldata == NULL) {
611 printf("lge%d: no memory for list buffers!\n", unit);
612 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
613 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
614 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
618 bzero(sc->lge_ldata, sizeof(struct lge_list_data));
620 /* Try to allocate memory for jumbo buffers. */
621 if (lge_alloc_jumbo_mem(sc)) {
622 printf("lge%d: jumbo buffer allocation failed\n",
624 contigfree(sc->lge_ldata,
625 sizeof(struct lge_list_data), M_DEVBUF);
626 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
627 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
628 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
633 ifp = &sc->arpcom.ac_if;
635 if_initname(ifp, "lge", unit);
636 ifp->if_mtu = ETHERMTU;
637 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
638 ifp->if_ioctl = lge_ioctl;
639 ifp->if_start = lge_start;
640 ifp->if_watchdog = lge_watchdog;
641 ifp->if_init = lge_init;
642 ifp->if_baudrate = 1000000000;
643 ifq_set_maxlen(&ifp->if_snd, LGE_TX_LIST_CNT - 1);
644 ifq_set_ready(&ifp->if_snd);
645 ifp->if_capabilities = IFCAP_RXCSUM;
646 ifp->if_capenable = ifp->if_capabilities;
648 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH)
656 if (mii_phy_probe(dev, &sc->lge_miibus,
657 lge_ifmedia_upd, lge_ifmedia_sts)) {
658 printf("lge%d: MII without any PHY!\n", sc->lge_unit);
659 contigfree(sc->lge_ldata,
660 sizeof(struct lge_list_data), M_DEVBUF);
661 lge_free_jumbo_mem(sc);
662 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
663 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
664 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
670 * Call MI attach routine.
672 ether_ifattach(ifp, eaddr);
679 static int lge_detach(dev)
682 struct lge_softc *sc;
688 sc = device_get_softc(dev);
689 ifp = &sc->arpcom.ac_if;
695 bus_generic_detach(dev);
696 device_delete_child(dev, sc->lge_miibus);
698 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand);
699 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq);
700 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res);
702 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF);
703 lge_free_jumbo_mem(sc);
711 * Initialize the transmit descriptors.
713 static int lge_list_tx_init(sc)
714 struct lge_softc *sc;
716 struct lge_list_data *ld;
717 struct lge_ring_data *cd;
722 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
723 ld->lge_tx_list[i].lge_mbuf = NULL;
724 ld->lge_tx_list[i].lge_ctl = 0;
727 cd->lge_tx_prod = cd->lge_tx_cons = 0;
734 * Initialize the RX descriptors and allocate mbufs for them. Note that
735 * we arralge the descriptors in a closed ring, so that the last descriptor
736 * points back to the first.
738 static int lge_list_rx_init(sc)
739 struct lge_softc *sc;
741 struct lge_list_data *ld;
742 struct lge_ring_data *cd;
748 cd->lge_rx_prod = cd->lge_rx_cons = 0;
750 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
752 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
753 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0)
755 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS)
759 /* Clear possible 'rx command queue empty' interrupt. */
760 CSR_READ_4(sc, LGE_ISR);
766 * Initialize an RX descriptor and attach an MBUF cluster.
768 static int lge_newbuf(sc, c, m)
769 struct lge_softc *sc;
770 struct lge_rx_desc *c;
773 struct mbuf *m_new = NULL;
777 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
779 printf("lge%d: no memory for rx list "
780 "-- packet dropped!\n", sc->lge_unit);
784 /* Allocate the jumbo buffer */
785 buf = lge_jalloc(sc);
788 printf("lge%d: jumbo allocation failed "
789 "-- packet dropped!\n", sc->lge_unit);
794 /* Attach the buffer to the mbuf */
795 m_new->m_data = m_new->m_ext.ext_buf = (void *)buf;
796 m_new->m_flags |= M_EXT | M_EXT_OLD;
797 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
798 m_new->m_len = LGE_MCLBYTES;
799 m_new->m_ext.ext_nfree.old = lge_jfree;
800 m_new->m_ext.ext_nref.old = lge_jref;
803 m_new->m_len = m_new->m_pkthdr.len = LGE_MCLBYTES;
804 m_new->m_data = m_new->m_ext.ext_buf;
808 * Adjust alignment so packet payload begins on a
809 * longword boundary. Mandatory for Alpha, useful on
812 m_adj(m_new, ETHER_ALIGN);
815 c->lge_fragptr_hi = 0;
816 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t));
817 c->lge_fraglen = m_new->m_len;
818 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1);
822 * Put this buffer in the RX command FIFO. To do this,
823 * we just write the physical address of the descriptor
824 * into the RX descriptor address registers. Note that
825 * there are two registers, one high DWORD and one low
826 * DWORD, which lets us specify a 64-bit address if
827 * desired. We only use a 32-bit address for now.
828 * Writing to the low DWORD register is what actually
829 * causes the command to be issued, so we do that
832 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c));
833 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT);
838 static int lge_alloc_jumbo_mem(sc)
839 struct lge_softc *sc;
843 struct lge_jpool_entry *entry;
845 /* Grab a big chunk o' storage. */
846 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF,
847 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
849 if (sc->lge_cdata.lge_jumbo_buf == NULL) {
850 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit);
854 SLIST_INIT(&sc->lge_jfree_listhead);
855 SLIST_INIT(&sc->lge_jinuse_listhead);
858 * Now divide it up into 9K pieces and save the addresses
861 ptr = sc->lge_cdata.lge_jumbo_buf;
862 for (i = 0; i < LGE_JSLOTS; i++) {
864 aptr = (u_int64_t **)ptr;
865 aptr[0] = (u_int64_t *)sc;
866 ptr += sizeof(u_int64_t);
867 sc->lge_cdata.lge_jslots[i].lge_buf = ptr;
868 sc->lge_cdata.lge_jslots[i].lge_inuse = 0;
870 entry = malloc(sizeof(struct lge_jpool_entry),
873 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
874 entry, jpool_entries);
880 static void lge_free_jumbo_mem(sc)
881 struct lge_softc *sc;
884 struct lge_jpool_entry *entry;
886 for (i = 0; i < LGE_JSLOTS; i++) {
887 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
888 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
889 free(entry, M_DEVBUF);
892 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF);
898 * Allocate a jumbo buffer.
900 static void *lge_jalloc(sc)
901 struct lge_softc *sc;
903 struct lge_jpool_entry *entry;
905 entry = SLIST_FIRST(&sc->lge_jfree_listhead);
909 printf("lge%d: no free jumbo buffers\n", sc->lge_unit);
914 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries);
915 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries);
916 sc->lge_cdata.lge_jslots[entry->slot].lge_inuse = 1;
917 return(sc->lge_cdata.lge_jslots[entry->slot].lge_buf);
921 * Adjust usage count on a jumbo buffer. In general this doesn't
922 * get used much because our jumbo buffers don't get passed around
923 * a lot, but it's implemented for correctness.
925 static void lge_jref(buf, size)
929 struct lge_softc *sc;
933 /* Extract the softc struct pointer. */
934 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
935 sc = (struct lge_softc *)(aptr[0]);
938 panic("lge_jref: can't find softc pointer!");
940 if (size != LGE_MCLBYTES)
941 panic("lge_jref: adjusting refcount of buf of wrong size!");
943 /* calculate the slot this buffer belongs to */
945 i = ((vm_offset_t)aptr
946 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
948 if ((i < 0) || (i >= LGE_JSLOTS))
949 panic("lge_jref: asked to reference buffer "
950 "that we don't manage!");
951 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
952 panic("lge_jref: buffer already free!");
954 sc->lge_cdata.lge_jslots[i].lge_inuse++;
960 * Release a jumbo buffer.
962 static void lge_jfree(buf, size)
966 struct lge_softc *sc;
969 struct lge_jpool_entry *entry;
971 /* Extract the softc struct pointer. */
972 aptr = (u_int64_t **)(buf - sizeof(u_int64_t));
973 sc = (struct lge_softc *)(aptr[0]);
976 panic("lge_jfree: can't find softc pointer!");
978 if (size != LGE_MCLBYTES)
979 panic("lge_jfree: freeing buffer of wrong size!");
981 /* calculate the slot this buffer belongs to */
982 i = ((vm_offset_t)aptr
983 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN;
985 if ((i < 0) || (i >= LGE_JSLOTS))
986 panic("lge_jfree: asked to free buffer that we don't manage!");
987 else if (sc->lge_cdata.lge_jslots[i].lge_inuse == 0)
988 panic("lge_jfree: buffer already free!");
990 sc->lge_cdata.lge_jslots[i].lge_inuse--;
991 if(sc->lge_cdata.lge_jslots[i].lge_inuse == 0) {
992 entry = SLIST_FIRST(&sc->lge_jinuse_listhead);
994 panic("lge_jfree: buffer not in use!");
996 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead,
998 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead,
999 entry, jpool_entries);
1007 * A frame has been uploaded: pass the resulting mbuf chain up to
1008 * the higher level protocols.
1010 static void lge_rxeof(sc, cnt)
1011 struct lge_softc *sc;
1016 struct lge_rx_desc *cur_rx;
1017 int c, i, total_len = 0;
1018 u_int32_t rxsts, rxctl;
1020 ifp = &sc->arpcom.ac_if;
1022 /* Find out how many frames were processed. */
1024 i = sc->lge_cdata.lge_rx_cons;
1028 struct mbuf *m0 = NULL;
1030 cur_rx = &sc->lge_ldata->lge_rx_list[i];
1031 rxctl = cur_rx->lge_ctl;
1032 rxsts = cur_rx->lge_sts;
1033 m = cur_rx->lge_mbuf;
1034 cur_rx->lge_mbuf = NULL;
1035 total_len = LGE_RXBYTES(cur_rx);
1036 LGE_INC(i, LGE_RX_LIST_CNT);
1040 * If an error occurs, update stats, clear the
1041 * status word and leave the mbuf cluster in place:
1042 * it should simply get re-used next time this descriptor
1043 * comes up in the ring.
1045 if (rxctl & LGE_RXCTL_ERRMASK) {
1047 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1051 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) {
1052 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1053 total_len + ETHER_ALIGN, 0, ifp, NULL);
1054 lge_newbuf(sc, &LGE_RXTAIL(sc), m);
1056 printf("lge%d: no receive buffers "
1057 "available -- packet dropped!\n",
1062 m_adj(m0, ETHER_ALIGN);
1065 m->m_pkthdr.rcvif = ifp;
1066 m->m_pkthdr.len = m->m_len = total_len;
1071 /* Do IP checksum checking. */
1072 if (rxsts & LGE_RXSTS_ISIP)
1073 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1074 if (!(rxsts & LGE_RXSTS_IPCSUMERR))
1075 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1076 if ((rxsts & LGE_RXSTS_ISTCP &&
1077 !(rxsts & LGE_RXSTS_TCPCSUMERR)) ||
1078 (rxsts & LGE_RXSTS_ISUDP &&
1079 !(rxsts & LGE_RXSTS_UDPCSUMERR))) {
1080 m->m_pkthdr.csum_flags |=
1081 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1082 m->m_pkthdr.csum_data = 0xffff;
1085 (*ifp->if_input)(ifp, m);
1088 sc->lge_cdata.lge_rx_cons = i;
1094 struct lge_softc *sc;
1098 ifp = &sc->arpcom.ac_if;
1099 ifp->if_flags &= ~IFF_RUNNING;
1105 * A frame was downloaded to the chip. It's safe for us to clean up
1109 static void lge_txeof(sc)
1110 struct lge_softc *sc;
1112 struct lge_tx_desc *cur_tx = NULL;
1114 u_int32_t idx, txdone;
1116 ifp = &sc->arpcom.ac_if;
1118 /* Clear the timeout timer. */
1122 * Go through our tx list and free mbufs for those
1123 * frames that have been transmitted.
1125 idx = sc->lge_cdata.lge_tx_cons;
1126 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT);
1128 while (idx != sc->lge_cdata.lge_tx_prod && txdone) {
1129 cur_tx = &sc->lge_ldata->lge_tx_list[idx];
1132 if (cur_tx->lge_mbuf != NULL) {
1133 m_freem(cur_tx->lge_mbuf);
1134 cur_tx->lge_mbuf = NULL;
1136 cur_tx->lge_ctl = 0;
1139 LGE_INC(idx, LGE_TX_LIST_CNT);
1143 sc->lge_cdata.lge_tx_cons = idx;
1146 ifp->if_flags &= ~IFF_OACTIVE;
1151 static void lge_tick(xsc)
1154 struct lge_softc *sc;
1155 struct mii_data *mii;
1162 ifp = &sc->arpcom.ac_if;
1164 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS);
1165 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1166 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS);
1167 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL);
1169 if (!sc->lge_link) {
1170 mii = device_get_softc(sc->lge_miibus);
1173 if (mii->mii_media_status & IFM_ACTIVE &&
1174 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1176 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX||
1177 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
1178 printf("lge%d: gigabit link up\n",
1180 if (!ifq_is_empty(&ifp->if_snd))
1185 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
1192 static void lge_intr(arg)
1195 struct lge_softc *sc;
1200 ifp = &sc->arpcom.ac_if;
1202 /* Supress unwanted interrupts */
1203 if (!(ifp->if_flags & IFF_UP)) {
1210 * Reading the ISR register clears all interrupts, and
1211 * clears the 'interrupts enabled' bit in the IMR
1214 status = CSR_READ_4(sc, LGE_ISR);
1216 if ((status & LGE_INTRS) == 0)
1219 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE)))
1222 if (status & LGE_ISR_RXDMA_DONE)
1223 lge_rxeof(sc, LGE_RX_DMACNT(status));
1225 if (status & LGE_ISR_RXCMDFIFO_EMPTY)
1228 if (status & LGE_ISR_PHY_INTR) {
1230 callout_stop(&sc->lge_stat_timer);
1235 /* Re-enable interrupts. */
1236 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB);
1238 if (!ifq_is_empty(&ifp->if_snd))
1245 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1246 * pointers to the fragment pointers.
1248 static int lge_encap(sc, m_head, txidx)
1249 struct lge_softc *sc;
1250 struct mbuf *m_head;
1253 struct lge_frag *f = NULL;
1254 struct lge_tx_desc *cur_tx;
1256 int frag = 0, tot_len = 0;
1259 * Start packing the mbufs in this chain into
1260 * the fragment pointers. Stop when we run out
1261 * of fragments or hit the end of the mbuf chain.
1264 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx];
1267 for (m = m_head; m != NULL; m = m->m_next) {
1268 if (m->m_len != 0) {
1269 tot_len += m->m_len;
1270 f = &cur_tx->lge_frags[frag];
1271 f->lge_fraglen = m->m_len;
1272 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t));
1273 f->lge_fragptr_hi = 0;
1281 cur_tx->lge_mbuf = m_head;
1282 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len;
1283 LGE_INC((*txidx), LGE_TX_LIST_CNT);
1285 /* Queue for transmit */
1286 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx));
1292 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1293 * to the mbuf data regions directly in the transmit lists. We also save a
1294 * copy of the pointers since the transmit list fragment pointers are
1295 * physical addresses.
1298 static void lge_start(ifp)
1301 struct lge_softc *sc;
1302 struct mbuf *m_head = NULL;
1310 idx = sc->lge_cdata.lge_tx_prod;
1312 if (ifp->if_flags & IFF_OACTIVE)
1315 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) {
1316 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0)
1319 m_head = ifq_poll(&ifp->if_snd);
1323 if (lge_encap(sc, m_head, &idx)) {
1324 ifp->if_flags |= IFF_OACTIVE;
1327 m_head = ifq_dequeue(&ifp->if_snd);
1329 BPF_MTAP(ifp, m_head);
1332 sc->lge_cdata.lge_tx_prod = idx;
1335 * Set a timeout in case the chip goes out to lunch.
1342 static void lge_init(xsc)
1345 struct lge_softc *sc = xsc;
1346 struct ifnet *ifp = &sc->arpcom.ac_if;
1347 struct mii_data *mii;
1350 if (ifp->if_flags & IFF_RUNNING)
1356 * Cancel pending I/O and free all RX/TX buffers.
1361 mii = device_get_softc(sc->lge_miibus);
1363 /* Set MAC address */
1364 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
1365 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
1367 /* Init circular RX list. */
1368 if (lge_list_rx_init(sc) == ENOBUFS) {
1369 printf("lge%d: initialization failed: no "
1370 "memory for rx buffers\n", sc->lge_unit);
1377 * Init tx descriptors.
1379 lge_list_tx_init(sc);
1381 /* Set initial value for MODE1 register. */
1382 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST|
1383 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD|
1384 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0|
1385 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2);
1387 /* If we want promiscuous mode, set the allframes bit. */
1388 if (ifp->if_flags & IFF_PROMISC) {
1389 CSR_WRITE_4(sc, LGE_MODE1,
1390 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC);
1392 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC);
1396 * Set the capture broadcast bit to capture broadcast frames.
1398 if (ifp->if_flags & IFF_BROADCAST) {
1399 CSR_WRITE_4(sc, LGE_MODE1,
1400 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST);
1402 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST);
1405 /* Packet padding workaround? */
1406 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD);
1408 /* No error frames */
1409 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS);
1411 /* Receive large frames */
1412 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS);
1414 /* Workaround: disable RX/TX flow control */
1415 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL);
1416 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL);
1418 /* Make sure to strip CRC from received frames */
1419 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC);
1421 /* Turn off magic packet mode */
1422 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB);
1424 /* Turn off all VLAN stuff */
1425 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX|
1426 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT);
1428 /* Workarond: FIFO overflow */
1429 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF);
1430 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT);
1433 * Load the multicast filter.
1438 * Enable hardware checksum validation for all received IPv4
1439 * packets, do not reject packets with bad checksums.
1441 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM|
1442 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM|
1443 LGE_MODE2_RX_ERRCSUM);
1446 * Enable the delivery of PHY interrupts based on
1447 * link/speed/duplex status chalges.
1449 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL);
1451 /* Enable receiver and transmitter. */
1452 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0);
1453 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB);
1455 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0);
1456 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB);
1459 * Enable interrupts.
1461 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|
1462 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS);
1464 lge_ifmedia_upd(ifp);
1466 ifp->if_flags |= IFF_RUNNING;
1467 ifp->if_flags &= ~IFF_OACTIVE;
1471 callout_reset(&sc->lge_stat_timer, hz, lge_tick, sc);
1477 * Set media options.
1479 static int lge_ifmedia_upd(ifp)
1482 struct lge_softc *sc;
1483 struct mii_data *mii;
1487 mii = device_get_softc(sc->lge_miibus);
1489 if (mii->mii_instance) {
1490 struct mii_softc *miisc;
1491 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1492 miisc = LIST_NEXT(miisc, mii_list))
1493 mii_phy_reset(miisc);
1501 * Report current media status.
1503 static void lge_ifmedia_sts(ifp, ifmr)
1505 struct ifmediareq *ifmr;
1507 struct lge_softc *sc;
1508 struct mii_data *mii;
1512 mii = device_get_softc(sc->lge_miibus);
1514 ifmr->ifm_active = mii->mii_media_active;
1515 ifmr->ifm_status = mii->mii_media_status;
1520 static int lge_ioctl(ifp, command, data, cr)
1526 struct lge_softc *sc = ifp->if_softc;
1527 struct ifreq *ifr = (struct ifreq *) data;
1528 struct mii_data *mii;
1536 error = ether_ioctl(ifp, command, data);
1539 if (ifr->ifr_mtu > LGE_JUMBO_MTU)
1542 ifp->if_mtu = ifr->ifr_mtu;
1545 if (ifp->if_flags & IFF_UP) {
1546 if (ifp->if_flags & IFF_RUNNING &&
1547 ifp->if_flags & IFF_PROMISC &&
1548 !(sc->lge_if_flags & IFF_PROMISC)) {
1549 CSR_WRITE_4(sc, LGE_MODE1,
1550 LGE_MODE1_SETRST_CTL1|
1551 LGE_MODE1_RX_PROMISC);
1552 } else if (ifp->if_flags & IFF_RUNNING &&
1553 !(ifp->if_flags & IFF_PROMISC) &&
1554 sc->lge_if_flags & IFF_PROMISC) {
1555 CSR_WRITE_4(sc, LGE_MODE1,
1556 LGE_MODE1_RX_PROMISC);
1558 ifp->if_flags &= ~IFF_RUNNING;
1562 if (ifp->if_flags & IFF_RUNNING)
1565 sc->lge_if_flags = ifp->if_flags;
1575 mii = device_get_softc(sc->lge_miibus);
1576 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1588 static void lge_watchdog(ifp)
1591 struct lge_softc *sc;
1596 printf("lge%d: watchdog timeout\n", sc->lge_unit);
1600 ifp->if_flags &= ~IFF_RUNNING;
1603 if (!ifq_is_empty(&ifp->if_snd))
1610 * Stop the adapter and free any mbufs allocated to the
1613 static void lge_stop(sc)
1614 struct lge_softc *sc;
1619 ifp = &sc->arpcom.ac_if;
1621 callout_stop(&sc->lge_stat_timer);
1622 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB);
1624 /* Disable receiver and transmitter. */
1625 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB);
1629 * Free data in the RX lists.
1631 for (i = 0; i < LGE_RX_LIST_CNT; i++) {
1632 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) {
1633 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf);
1634 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL;
1637 bzero((char *)&sc->lge_ldata->lge_rx_list,
1638 sizeof(sc->lge_ldata->lge_rx_list));
1641 * Free the TX list buffers.
1643 for (i = 0; i < LGE_TX_LIST_CNT; i++) {
1644 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) {
1645 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf);
1646 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL;
1650 bzero((char *)&sc->lge_ldata->lge_tx_list,
1651 sizeof(sc->lge_ldata->lge_tx_list));
1653 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1659 * Stop all chip I/O so that the kernel's probe routines don't
1660 * get confused by errant DMAs when rebooting.
1662 static void lge_shutdown(dev)
1665 struct lge_softc *sc;
1667 sc = device_get_softc(dev);