2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.47 2006/10/25 20:55:57 dillon Exp $
33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
36 #include "opt_polling.h"
38 #include <sys/param.h>
39 #include <sys/systm.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
43 #include <sys/socket.h>
44 #include <sys/sysctl.h>
45 #include <sys/thread2.h>
48 #include <net/ifq_var.h>
49 #include <net/if_dl.h>
50 #include <net/if_media.h>
54 #include <netns/ns_if.h>
58 #include <sys/sockio.h>
62 #include <net/ethernet.h>
63 #include <net/if_arp.h>
65 #include <vm/vm.h> /* for vtophys */
66 #include <vm/pmap.h> /* for vtophys */
68 #include <net/if_types.h>
69 #include <net/vlan/if_vlan_var.h>
71 #include <bus/pci/pcivar.h>
72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */
74 #include "../mii_layer/mii.h"
75 #include "../mii_layer/miivar.h"
77 #include "if_fxpreg.h"
78 #include "if_fxpvar.h"
81 #include "miibus_if.h"
84 * NOTE! On the Alpha, we have an alignment constraint. The
85 * card DMAs the packet immediately following the RFA. However,
86 * the first thing in the packet is a 14-byte Ethernet header.
87 * This means that the packet is misaligned. To compensate,
88 * we actually offset the RFA 2 bytes into the cluster. This
89 * alignes the packet after the Ethernet header at a 32-bit
90 * boundary. HOWEVER! This means that the RFA is misaligned!
92 #define RFA_ALIGNMENT_FUDGE 2
95 * Set initial transmit threshold at 64 (512 bytes). This is
96 * increased by 64 (512 bytes) at a time, to maximum of 192
97 * (1536 bytes), if an underrun occurs.
99 static int tx_threshold = 64;
102 * The configuration byte map has several undefined fields which
103 * must be one or must be zero. Set up a template for these bits
104 * only, (assuming a 82557 chip) leaving the actual configuration
107 * See struct fxp_cb_config for the bit definitions.
109 static u_char fxp_cb_config_template[] = {
110 0x0, 0x0, /* cb_status */
111 0x0, 0x0, /* cb_command */
112 0x0, 0x0, 0x0, 0x0, /* link_addr */
139 int16_t revid; /* -1 matches anything */
144 * Claim various Intel PCI device identifiers for this driver. The
145 * sub-vendor and sub-device field are extensively used to identify
146 * particular variants, but we don't currently differentiate between
149 static struct fxp_ident fxp_ident_table[] = {
150 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
151 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
152 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
153 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
154 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
155 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
156 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
157 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
158 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
159 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
160 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
161 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
162 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
163 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
164 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
165 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
166 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
167 { 0x1051, -1, "Intel 82562ET (ICH5/ICH5R) Pro/100 VE Ethernet" },
168 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
169 { 0x1064, -1, "Intel 82562ET/EZ/GT/GZ (ICH6/ICH6R) Pro/100 VE Ethernet" },
170 { 0x1068, -1, "Intel 82801FBM (ICH6-M) Pro/100 VE Ethernet" },
171 { 0x1069, -1, "Intel 82562EM/EX/GX Pro/100 Ethernet" },
172 { 0x1092, -1, "Intel Pro/100 VE Network Connection" },
173 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
174 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
175 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
176 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
177 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
178 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
179 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
180 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
181 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
182 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
183 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
184 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
185 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
186 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
187 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
188 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
189 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
190 { 0x27dc, -1, "Intel 82801GB (ICH7) 10/100 Ethernet" },
194 static int fxp_probe(device_t dev);
195 static int fxp_attach(device_t dev);
196 static int fxp_detach(device_t dev);
197 static int fxp_shutdown(device_t dev);
198 static int fxp_suspend(device_t dev);
199 static int fxp_resume(device_t dev);
201 static void fxp_intr(void *xsc);
202 static void fxp_intr_body(struct fxp_softc *sc,
203 u_int8_t statack, int count);
205 static void fxp_init(void *xsc);
206 static void fxp_tick(void *xsc);
207 static void fxp_powerstate_d0(device_t dev);
208 static void fxp_start(struct ifnet *ifp);
209 static void fxp_stop(struct fxp_softc *sc);
210 static void fxp_release(device_t dev);
211 static int fxp_ioctl(struct ifnet *ifp, u_long command,
212 caddr_t data, struct ucred *);
213 static void fxp_watchdog(struct ifnet *ifp);
214 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
215 static int fxp_mc_addrs(struct fxp_softc *sc);
216 static void fxp_mc_setup(struct fxp_softc *sc);
217 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
219 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
221 static void fxp_autosize_eeprom(struct fxp_softc *sc);
222 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
223 int offset, int words);
224 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
225 int offset, int words);
226 static int fxp_ifmedia_upd(struct ifnet *ifp);
227 static void fxp_ifmedia_sts(struct ifnet *ifp,
228 struct ifmediareq *ifmr);
229 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
230 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
231 struct ifmediareq *ifmr);
232 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
233 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
235 static void fxp_load_ucode(struct fxp_softc *sc);
236 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
238 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
239 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
240 #ifdef DEVICE_POLLING
241 static poll_handler_t fxp_poll;
244 static void fxp_lwcopy(volatile u_int32_t *src,
245 volatile u_int32_t *dst);
246 static void fxp_scb_wait(struct fxp_softc *sc);
247 static void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
248 static void fxp_dma_wait(volatile u_int16_t *status,
249 struct fxp_softc *sc);
251 static device_method_t fxp_methods[] = {
252 /* Device interface */
253 DEVMETHOD(device_probe, fxp_probe),
254 DEVMETHOD(device_attach, fxp_attach),
255 DEVMETHOD(device_detach, fxp_detach),
256 DEVMETHOD(device_shutdown, fxp_shutdown),
257 DEVMETHOD(device_suspend, fxp_suspend),
258 DEVMETHOD(device_resume, fxp_resume),
261 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
262 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
267 static driver_t fxp_driver = {
270 sizeof(struct fxp_softc),
273 static devclass_t fxp_devclass;
275 DECLARE_DUMMY_MODULE(if_fxp);
276 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1);
277 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
278 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
279 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
282 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
285 * Copy a 16-bit aligned 32-bit quantity.
288 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
293 volatile u_int16_t *a = (volatile u_int16_t *)src;
294 volatile u_int16_t *b = (volatile u_int16_t *)dst;
302 * Wait for the previous command to be accepted (but not necessarily
306 fxp_scb_wait(struct fxp_softc *sc)
310 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
313 if_printf(&sc->arpcom.ac_if,
314 "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
315 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
316 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
317 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
318 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
323 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
326 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
327 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
330 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
334 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
338 while (!(*status & FXP_CB_STATUS_C) && --i)
341 if_printf(&sc->arpcom.ac_if, "DMA timeout\n");
345 * Return identification string if this is device is ours.
348 fxp_probe(device_t dev)
352 struct fxp_ident *ident;
354 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
355 devid = pci_get_device(dev);
356 revid = pci_get_revid(dev);
357 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
358 if (ident->devid == devid &&
359 (ident->revid == revid || ident->revid == -1)) {
360 device_set_desc(dev, ident->name);
369 fxp_powerstate_d0(device_t dev)
371 u_int32_t iobase, membase, irq;
373 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
374 /* Save important PCI config data. */
375 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
376 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
377 irq = pci_read_config(dev, PCIR_INTLINE, 4);
379 /* Reset the power state. */
380 device_printf(dev, "chip is in D%d power mode "
381 "-- setting to D0\n", pci_get_powerstate(dev));
383 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
385 /* Restore PCI config data. */
386 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
387 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
388 pci_write_config(dev, PCIR_INTLINE, irq, 4);
393 fxp_attach(device_t dev)
396 struct fxp_softc *sc = device_get_softc(dev);
400 int i, rid, m1, m2, prefer_iomap;
402 callout_init(&sc->fxp_stat_timer);
403 sysctl_ctx_init(&sc->sysctl_ctx);
406 * Enable bus mastering. Enable memory space too, in case
407 * BIOS/Prom forgot about it.
409 pci_enable_busmaster(dev);
410 pci_enable_io(dev, SYS_RES_MEMORY);
411 val = pci_read_config(dev, PCIR_COMMAND, 2);
413 fxp_powerstate_d0(dev);
416 * Figure out which we should try first - memory mapping or i/o mapping?
417 * We default to memory mapping. Then we accept an override from the
418 * command line. Then we check to see which one is enabled.
421 m2 = PCIM_CMD_PORTEN;
423 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
424 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
425 m1 = PCIM_CMD_PORTEN;
431 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
432 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
433 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
436 if (sc->mem == NULL && (val & m2)) {
438 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
439 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
440 sc->mem = bus_alloc_resource_any(dev, sc->rtp, &sc->rgd,
445 device_printf(dev, "could not map device registers\n");
450 device_printf(dev, "using %s space register mapping\n",
451 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
454 sc->sc_st = rman_get_bustag(sc->mem);
455 sc->sc_sh = rman_get_bushandle(sc->mem);
458 * Allocate our interrupt.
461 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
462 RF_SHAREABLE | RF_ACTIVE);
463 if (sc->irq == NULL) {
464 device_printf(dev, "could not map interrupt\n");
470 * Reset to a stable state.
472 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
475 sc->cbl_base = kmalloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
476 M_DEVBUF, M_WAITOK | M_ZERO);
478 sc->fxp_stats = kmalloc(sizeof(struct fxp_stats), M_DEVBUF,
481 sc->mcsp = kmalloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK);
484 * Pre-allocate our receive buffers.
486 for (i = 0; i < FXP_NRFABUFS; i++) {
487 if (fxp_add_rfabuf(sc, NULL) != 0) {
493 * Find out how large of an SEEPROM we have.
495 fxp_autosize_eeprom(sc);
498 * Determine whether we must use the 503 serial interface.
500 fxp_read_eeprom(sc, &data, 6, 1);
501 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
502 (data & FXP_PHY_SERIAL_ONLY))
503 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
506 * Create the sysctl tree
508 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
509 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
510 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
511 if (sc->sysctl_tree == NULL)
513 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
514 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
515 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
516 "FXP driver receive interrupt microcode bundling delay");
517 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
518 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
519 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
520 "FXP driver receive interrupt microcode bundle size limit");
523 * Pull in device tunables.
525 sc->tunable_int_delay = TUNABLE_INT_DELAY;
526 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
527 resource_int_value(device_get_name(dev), device_get_unit(dev),
528 "int_delay", &sc->tunable_int_delay);
529 resource_int_value(device_get_name(dev), device_get_unit(dev),
530 "bundle_max", &sc->tunable_bundle_max);
533 * Find out the chip revision; lump all 82557 revs together.
535 fxp_read_eeprom(sc, &data, 5, 1);
536 if ((data >> 8) == 1)
537 sc->revision = FXP_REV_82557;
539 sc->revision = pci_get_revid(dev);
542 * Enable workarounds for certain chip revision deficiencies.
544 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
545 * some systems based a normal 82559 design, have a defect where
546 * the chip can cause a PCI protocol violation if it receives
547 * a CU_RESUME command when it is entering the IDLE state. The
548 * workaround is to disable Dynamic Standby Mode, so the chip never
549 * deasserts CLKRUN#, and always remains in an active state.
551 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
553 i = pci_get_device(dev);
554 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
555 sc->revision >= FXP_REV_82559_A0) {
556 fxp_read_eeprom(sc, &data, 10, 1);
557 if (data & 0x02) { /* STB enable */
562 "Disabling dynamic standby mode in EEPROM\n");
564 fxp_write_eeprom(sc, &data, 10, 1);
565 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
567 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
568 fxp_read_eeprom(sc, &data, i, 1);
571 i = (1 << sc->eeprom_size) - 1;
572 cksum = 0xBABA - cksum;
573 fxp_read_eeprom(sc, &data, i, 1);
574 fxp_write_eeprom(sc, &cksum, i, 1);
576 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
580 * If the user elects to continue, try the software
581 * workaround, as it is better than nothing.
583 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
589 * If we are not a 82557 chip, we can enable extended features.
591 if (sc->revision != FXP_REV_82557) {
593 * If MWI is enabled in the PCI configuration, and there
594 * is a valid cacheline size (8 or 16 dwords), then tell
595 * the board to turn on MWI.
597 if (val & PCIM_CMD_MWRICEN &&
598 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
599 sc->flags |= FXP_FLAG_MWI_ENABLE;
601 /* turn on the extended TxCB feature */
602 sc->flags |= FXP_FLAG_EXT_TXCB;
604 /* enable reception of long frames for VLAN */
605 sc->flags |= FXP_FLAG_LONG_PKT_EN;
611 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
612 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
613 device_printf(dev, "10Mbps\n");
615 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
616 pci_get_vendor(dev), pci_get_device(dev),
617 pci_get_subvendor(dev), pci_get_subdevice(dev),
619 fxp_read_eeprom(sc, &data, 10, 1);
620 device_printf(dev, "Dynamic Standby mode is %s\n",
621 data & 0x02 ? "enabled" : "disabled");
625 * If this is only a 10Mbps device, then there is no MII, and
626 * the PHY will use a serial interface instead.
628 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
629 * doesn't have a programming interface of any sort. The
630 * media is sensed automatically based on how the link partner
631 * is configured. This is, in essence, manual configuration.
633 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
634 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
635 fxp_serial_ifmedia_sts);
636 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
637 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
639 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
641 device_printf(dev, "MII without any PHY!\n");
647 ifp = &sc->arpcom.ac_if;
648 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
649 ifp->if_baudrate = 100000000;
650 ifp->if_init = fxp_init;
652 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
653 ifp->if_ioctl = fxp_ioctl;
654 ifp->if_start = fxp_start;
655 #ifdef DEVICE_POLLING
656 ifp->if_poll = fxp_poll;
658 ifp->if_watchdog = fxp_watchdog;
661 * Attach the interface.
663 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
666 * Tell the upper layer(s) we support long frames.
668 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
671 * Let the system queue as many packets as we have available
674 ifq_set_maxlen(&ifp->if_snd, FXP_NTXCB - 1);
675 ifq_set_ready(&ifp->if_snd);
677 error = bus_setup_intr(dev, sc->irq, INTR_NETSAFE,
678 fxp_intr, sc, &sc->ih,
682 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
683 ifmedia_removeall(&sc->sc_media);
684 device_printf(dev, "could not setup irq\n");
691 device_printf(dev, "Failed to malloc memory\n");
699 * release all resources
702 fxp_release(device_t dev)
704 struct fxp_softc *sc = device_get_softc(dev);
707 device_delete_child(dev, sc->miibus);
708 bus_generic_detach(dev);
711 kfree(sc->cbl_base, M_DEVBUF);
713 kfree(sc->fxp_stats, M_DEVBUF);
715 kfree(sc->mcsp, M_DEVBUF);
717 m_freem(sc->rfa_headm);
720 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
722 bus_release_resource(dev, sc->rtp, sc->rgd, sc->mem);
724 sysctl_ctx_free(&sc->sysctl_ctx);
731 fxp_detach(device_t dev)
733 struct fxp_softc *sc = device_get_softc(dev);
735 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
738 * Stop DMA and drop transmit queue.
743 * Disable interrupts.
745 * NOTE: This should be done after fxp_stop(), because software
746 * resetting in fxp_stop() may leave interrupts turned on.
748 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
751 * Free all media structures.
753 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
754 ifmedia_removeall(&sc->sc_media);
757 bus_teardown_intr(dev, sc->irq, sc->ih);
759 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
762 * Close down routes etc.
764 ether_ifdetach(&sc->arpcom.ac_if);
766 /* Release our allocated resources. */
773 * Device shutdown routine. Called at system shutdown after sync. The
774 * main purpose of this routine is to shut off receiver DMA so that
775 * kernel memory doesn't get clobbered during warmboot.
778 fxp_shutdown(device_t dev)
781 * Make sure that DMA is disabled prior to reboot. Not doing
782 * do could allow DMA to corrupt kernel memory during the
783 * reboot before the driver initializes.
785 fxp_stop((struct fxp_softc *) device_get_softc(dev));
790 * Device suspend routine. Stop the interface and save some PCI
791 * settings in case the BIOS doesn't restore them properly on
795 fxp_suspend(device_t dev)
797 struct fxp_softc *sc = device_get_softc(dev);
800 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
804 for (i = 0; i < 5; i++)
805 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
806 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
807 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
808 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
809 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
813 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
818 * Device resume routine. Restore some PCI settings in case the BIOS
819 * doesn't, re-enable busmastering, and restart the interface if
823 fxp_resume(device_t dev)
825 struct fxp_softc *sc = device_get_softc(dev);
826 struct ifnet *ifp = &sc->arpcom.ac_if;
829 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
831 fxp_powerstate_d0(dev);
833 /* better way to do this? */
834 for (i = 0; i < 5; i++)
835 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
836 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
837 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
838 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
839 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
841 /* reenable busmastering and memory space */
842 pci_enable_busmaster(dev);
843 pci_enable_io(dev, SYS_RES_MEMORY);
845 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
848 /* reinitialize interface if necessary */
849 if (ifp->if_flags & IFF_UP)
854 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
859 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
867 for (x = 1 << (length - 1); x; x >>= 1) {
869 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
871 reg = FXP_EEPROM_EECS;
872 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
874 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
876 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
882 * Read from the serial EEPROM. Basically, you manually shift in
883 * the read opcode (one bit at a time) and then shift in the address,
884 * and then you shift out the data (all of this one bit at a time).
885 * The word size is 16 bits, so you have to provide the address for
886 * every 16 bits of data.
889 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
894 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
896 * Shift in read opcode.
898 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
903 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
905 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
907 reg = FXP_EEPROM_EECS;
908 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
910 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
912 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
914 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
916 if (autosize && reg == 0) {
917 sc->eeprom_size = data;
925 reg = FXP_EEPROM_EECS;
926 for (x = 1 << 15; x; x >>= 1) {
927 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
929 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
931 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
934 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
941 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
946 * Erase/write enable.
948 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
949 fxp_eeprom_shiftin(sc, 0x4, 3);
950 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
951 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
954 * Shift in write opcode, address, data.
956 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
957 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
958 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
959 fxp_eeprom_shiftin(sc, data, 16);
960 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
963 * Wait for EEPROM to finish up.
965 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
967 for (i = 0; i < 1000; i++) {
968 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
972 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
975 * Erase/write disable.
977 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
978 fxp_eeprom_shiftin(sc, 0x4, 3);
979 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
980 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
987 * Figure out EEPROM size.
989 * 559's can have either 64-word or 256-word EEPROMs, the 558
990 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
991 * talks about the existance of 16 to 256 word EEPROMs.
993 * The only known sizes are 64 and 256, where the 256 version is used
994 * by CardBus cards to store CIS information.
996 * The address is shifted in msb-to-lsb, and after the last
997 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
998 * after which follows the actual data. We try to detect this zero, by
999 * probing the data-out bit in the EEPROM control register just after
1000 * having shifted in a bit. If the bit is zero, we assume we've
1001 * shifted enough address bits. The data-out should be tri-state,
1002 * before this, which should translate to a logical one.
1005 fxp_autosize_eeprom(struct fxp_softc *sc)
1008 /* guess maximum size of 256 words */
1009 sc->eeprom_size = 8;
1012 fxp_eeprom_getword(sc, 0, 1);
1016 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1020 for (i = 0; i < words; i++)
1021 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1025 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1029 for (i = 0; i < words; i++)
1030 fxp_eeprom_putword(sc, offset + i, data[i]);
1034 * Start packet transmission on the interface.
1037 fxp_start(struct ifnet *ifp)
1039 struct fxp_softc *sc = ifp->if_softc;
1040 struct fxp_cb_tx *txp;
1043 * See if we need to suspend xmit until the multicast filter
1044 * has been reprogrammed (which can only be done at the head
1045 * of the command chain).
1047 if (sc->need_mcsetup) {
1054 * We're finished if there is nothing more to add to the list or if
1055 * we're all filled up with buffers to transmit.
1056 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1057 * a NOP command when needed.
1059 while (!ifq_is_empty(&ifp->if_snd) && sc->tx_queued < FXP_NTXCB - 1) {
1060 struct mbuf *m, *mb_head;
1061 int segment, ntries = 0;
1064 * Grab a packet to transmit. The packet is dequeued,
1065 * once we are sure that we have enough free descriptors.
1067 mb_head = ifq_poll(&ifp->if_snd);
1068 if (mb_head == NULL)
1072 * Get pointer to next available tx desc.
1074 txp = sc->cbl_last->next;
1077 * Go through each of the mbufs in the chain and initialize
1078 * the transmit buffer descriptors with the physical address
1079 * and size of the mbuf.
1082 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1083 if (m->m_len != 0) {
1084 if (segment == FXP_NTXSEG)
1086 txp->tbd[segment].tb_addr =
1087 vtophys(mtod(m, vm_offset_t));
1088 txp->tbd[segment].tb_size = m->m_len;
1096 * We ran out of segments. We have to recopy this
1097 * mbuf chain first. Bail out if we can't get the
1102 mn = m_dup(mb_head, MB_DONTWAIT);
1105 /* We can transmit the packet, dequeue it. */
1106 ifq_dequeue(&ifp->if_snd, mb_head);
1112 /* Nothing to worry about, just dequeue. */
1113 ifq_dequeue(&ifp->if_snd, mb_head);
1116 txp->tbd_number = segment;
1117 txp->mb_head = mb_head;
1119 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1121 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1125 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1126 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1128 * Set a 5 second timer just in case we don't hear
1129 * from the card again.
1133 txp->tx_threshold = tx_threshold;
1136 * Advance the end of list forward.
1139 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1143 * Advance the beginning of the list forward if there are
1144 * no other packets queued (when nothing is queued, cbl_first
1145 * sits on the last TxCB that was sent out).
1147 if (sc->tx_queued == 0)
1148 sc->cbl_first = txp;
1152 BPF_MTAP(ifp, mb_head);
1156 * We're finished. If we added to the list, issue a RESUME to get DMA
1157 * going again if suspended.
1161 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1165 #ifdef DEVICE_POLLING
1168 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1170 struct fxp_softc *sc = ifp->if_softc;
1175 /* disable interrupts */
1176 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1178 case POLL_DEREGISTER:
1179 /* enable interrupts */
1180 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1183 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1185 if (cmd == POLL_AND_CHECK_STATUS) {
1188 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1189 if (tmp == 0xff || tmp == 0)
1190 return; /* nothing to do */
1192 /* ack what we can */
1194 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1197 fxp_intr_body(sc, statack, count);
1202 #endif /* DEVICE_POLLING */
1205 * Process interface interrupts.
1210 struct fxp_softc *sc = xsc;
1213 if (sc->suspended) {
1217 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1219 * It should not be possible to have all bits set; the
1220 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1221 * all bits are set, this may indicate that the card has
1222 * been physically ejected, so ignore it.
1224 if (statack == 0xff)
1228 * First ACK all the interrupts in this pass.
1230 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1231 fxp_intr_body(sc, statack, -1);
1236 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1238 struct ifnet *ifp = &sc->arpcom.ac_if;
1240 struct fxp_rfa *rfa;
1241 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1245 #ifdef DEVICE_POLLING
1246 /* Pick up a deferred RNR condition if `count' ran out last time. */
1247 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1248 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1254 * Free any finished transmit mbuf chains.
1256 * Handle the CNA event likt a CXTNO event. It used to
1257 * be that this event (control unit not ready) was not
1258 * encountered, but it is now with the SMPng modifications.
1259 * The exact sequence of events that occur when the interface
1260 * is brought up are different now, and if this event
1261 * goes unhandled, the configuration/rxfilter setup sequence
1262 * can stall for several seconds. The result is that no
1263 * packets go out onto the wire for about 5 to 10 seconds
1264 * after the interface is ifconfig'ed for the first time.
1266 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1267 struct fxp_cb_tx *txp;
1269 for (txp = sc->cbl_first; sc->tx_queued &&
1270 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1272 if ((m = txp->mb_head) != NULL) {
1273 txp->mb_head = NULL;
1280 sc->cbl_first = txp;
1282 if (sc->tx_queued == 0) {
1283 if (sc->need_mcsetup)
1287 * Try to start more packets transmitting.
1289 if (!ifq_is_empty(&ifp->if_snd))
1290 (*ifp->if_start)(ifp);
1294 * Just return if nothing happened on the receive side.
1296 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1300 * Process receiver interrupts. If a no-resource (RNR)
1301 * condition exists, get whatever packets we can and
1302 * re-start the receiver.
1304 * When using polling, we do not process the list to completion,
1305 * so when we get an RNR interrupt we must defer the restart
1306 * until we hit the last buffer with the C bit set.
1307 * If we run out of cycles and rfa_headm has the C bit set,
1308 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1309 * that the info will be used in the subsequent polling cycle.
1313 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1314 RFA_ALIGNMENT_FUDGE);
1316 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1317 if (count >= 0 && count-- == 0) {
1319 /* Defer RNR processing until the next time. */
1320 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1325 #endif /* DEVICE_POLLING */
1327 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1331 * Remove first packet from the chain.
1333 sc->rfa_headm = m->m_next;
1337 * Add a new buffer to the receive chain.
1338 * If this fails, the old buffer is recycled
1341 if (fxp_add_rfabuf(sc, m) == 0) {
1345 * Fetch packet length (the top 2 bits of
1346 * actual_size are flags set by the controller
1347 * upon completion), and drop the packet in case
1348 * of bogus length or CRC errors.
1350 total_len = rfa->actual_size & 0x3fff;
1351 if (total_len < sizeof(struct ether_header) ||
1352 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1353 sizeof(struct fxp_rfa) ||
1354 rfa->rfa_status & FXP_RFA_STATUS_CRC) {
1358 m->m_pkthdr.len = m->m_len = total_len;
1359 ifp->if_input(ifp, m);
1364 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1365 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1366 RFA_ALIGNMENT_FUDGE);
1367 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1372 * Update packet in/out/collision statistics. The i82557 doesn't
1373 * allow you to access these counters without doing a fairly
1374 * expensive DMA to get _all_ of the statistics it maintains, so
1375 * we do this operation here only once per second. The statistics
1376 * counters in the kernel are updated from the previous dump-stats
1377 * DMA and then a new dump-stats DMA is started. The on-chip
1378 * counters are zeroed when the DMA completes. If we can't start
1379 * the DMA immediately, we don't wait - we just prepare to read
1380 * them again next time.
1385 struct fxp_softc *sc = xsc;
1386 struct ifnet *ifp = &sc->arpcom.ac_if;
1387 struct fxp_stats *sp = sc->fxp_stats;
1388 struct fxp_cb_tx *txp;
1391 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1393 ifp->if_opackets += sp->tx_good;
1394 ifp->if_collisions += sp->tx_total_collisions;
1396 ifp->if_ipackets += sp->rx_good;
1397 sc->rx_idle_secs = 0;
1400 * Receiver's been idle for another second.
1406 sp->rx_alignment_errors +
1408 sp->rx_overrun_errors;
1410 * If any transmit underruns occured, bump up the transmit
1411 * threshold by another 512 bytes (64 * 8).
1413 if (sp->tx_underruns) {
1414 ifp->if_oerrors += sp->tx_underruns;
1415 if (tx_threshold < 192)
1420 * Release any xmit buffers that have completed DMA. This isn't
1421 * strictly necessary to do here, but it's advantagous for mbufs
1422 * with external storage to be released in a timely manner rather
1423 * than being defered for a potentially long time. This limits
1424 * the delay to a maximum of one second.
1426 for (txp = sc->cbl_first; sc->tx_queued &&
1427 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1429 if ((m = txp->mb_head) != NULL) {
1430 txp->mb_head = NULL;
1437 sc->cbl_first = txp;
1439 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1440 * then assume the receiver has locked up and attempt to clear
1441 * the condition by reprogramming the multicast filter. This is
1442 * a work-around for a bug in the 82557 where the receiver locks
1443 * up if it gets certain types of garbage in the syncronization
1444 * bits prior to the packet header. This bug is supposed to only
1445 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1446 * mode as well (perhaps due to a 10/100 speed transition).
1448 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1449 sc->rx_idle_secs = 0;
1453 * If there is no pending command, start another stats
1454 * dump. Otherwise punt for now.
1456 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1458 * Start another stats dump.
1460 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1463 * A previous command is still waiting to be accepted.
1464 * Just zero our copy of the stats and wait for the
1465 * next timer event to update them.
1468 sp->tx_underruns = 0;
1469 sp->tx_total_collisions = 0;
1472 sp->rx_crc_errors = 0;
1473 sp->rx_alignment_errors = 0;
1474 sp->rx_rnr_errors = 0;
1475 sp->rx_overrun_errors = 0;
1477 if (sc->miibus != NULL)
1478 mii_tick(device_get_softc(sc->miibus));
1480 * Schedule another timeout one second from now.
1482 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1484 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1488 * Stop the interface. Cancels the statistics updater and resets
1492 fxp_stop(struct fxp_softc *sc)
1494 struct ifnet *ifp = &sc->arpcom.ac_if;
1495 struct fxp_cb_tx *txp;
1498 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1502 * Cancel stats updater.
1504 callout_stop(&sc->fxp_stat_timer);
1507 * Issue software reset, which also unloads the microcode.
1509 sc->flags &= ~FXP_FLAG_UCODE;
1510 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1514 * Release any xmit buffers.
1518 for (i = 0; i < FXP_NTXCB; i++) {
1519 if (txp[i].mb_head != NULL) {
1520 m_freem(txp[i].mb_head);
1521 txp[i].mb_head = NULL;
1528 * Free all the receive buffers then reallocate/reinitialize
1530 if (sc->rfa_headm != NULL)
1531 m_freem(sc->rfa_headm);
1532 sc->rfa_headm = NULL;
1533 sc->rfa_tailm = NULL;
1534 for (i = 0; i < FXP_NRFABUFS; i++) {
1535 if (fxp_add_rfabuf(sc, NULL) != 0) {
1537 * This "can't happen" - we're at splimp()
1538 * and we just freed all the buffers we need
1541 panic("fxp_stop: no buffers!");
1547 * Watchdog/transmission transmit timeout handler. Called when a
1548 * transmission is started on the interface, but no interrupt is
1549 * received before the timeout. This usually indicates that the
1550 * card has wedged for some reason.
1553 fxp_watchdog(struct ifnet *ifp)
1555 if_printf(ifp, "device timeout\n");
1557 fxp_init(ifp->if_softc);
1563 struct fxp_softc *sc = xsc;
1564 struct ifnet *ifp = &sc->arpcom.ac_if;
1565 struct fxp_cb_config *cbp;
1566 struct fxp_cb_ias *cb_ias;
1567 struct fxp_cb_tx *txp;
1568 struct fxp_cb_mcs *mcsp;
1572 * Cancel any pending I/O
1576 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1579 * Initialize base of CBL and RFA memory. Loading with zero
1580 * sets it up for regular linear addressing.
1582 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1583 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1586 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1589 * Initialize base of dump-stats buffer.
1592 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1593 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1596 * Attempt to load microcode if requested.
1598 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1602 * Initialize the multicast address list.
1604 if (fxp_mc_addrs(sc)) {
1606 mcsp->cb_status = 0;
1607 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1608 mcsp->link_addr = -1;
1610 * Start the multicast setup command.
1613 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1614 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1615 /* ...and wait for it to complete. */
1616 fxp_dma_wait(&mcsp->cb_status, sc);
1620 * We temporarily use memory that contains the TxCB list to
1621 * construct the config CB. The TxCB list memory is rebuilt
1624 cbp = (struct fxp_cb_config *) sc->cbl_base;
1627 * This bcopy is kind of disgusting, but there are a bunch of must be
1628 * zero and must be one bits in this structure and this is the easiest
1629 * way to initialize them all to proper values.
1631 bcopy(fxp_cb_config_template,
1632 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1633 sizeof(fxp_cb_config_template));
1636 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1637 cbp->link_addr = -1; /* (no) next command */
1638 cbp->byte_count = 22; /* (22) bytes to config */
1639 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1640 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1641 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1642 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1643 cbp->type_enable = 0; /* actually reserved */
1644 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1645 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1646 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1647 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1648 cbp->dma_mbce = 0; /* (disable) dma max counters */
1649 cbp->late_scb = 0; /* (don't) defer SCB update */
1650 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1651 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1652 cbp->ci_int = 1; /* interrupt on CU idle */
1653 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1654 cbp->ext_stats_dis = 1; /* disable extended counters */
1655 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1656 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1657 cbp->disc_short_rx = !prm; /* discard short packets */
1658 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1659 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1660 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1661 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1662 cbp->csma_dis = 0; /* (don't) disable link */
1663 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1664 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1665 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1666 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1667 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1668 cbp->nsai = 1; /* (don't) disable source addr insert */
1669 cbp->preamble_length = 2; /* (7 byte) preamble */
1670 cbp->loopback = 0; /* (don't) loopback */
1671 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1672 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1673 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1674 cbp->promiscuous = prm; /* promiscuous mode */
1675 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1676 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1677 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1678 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1679 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1681 cbp->stripping = !prm; /* truncate rx packet to byte count */
1682 cbp->padding = 1; /* (do) pad short tx packets */
1683 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1684 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1685 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1686 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1687 /* must set wake_en in PMCSR also */
1688 cbp->force_fdx = 0; /* (don't) force full duplex */
1689 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1690 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1691 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1693 if (sc->revision == FXP_REV_82557) {
1695 * The 82557 has no hardware flow control, the values
1696 * below are the defaults for the chip.
1698 cbp->fc_delay_lsb = 0;
1699 cbp->fc_delay_msb = 0x40;
1700 cbp->pri_fc_thresh = 3;
1702 cbp->rx_fc_restop = 0;
1703 cbp->rx_fc_restart = 0;
1705 cbp->pri_fc_loc = 1;
1707 cbp->fc_delay_lsb = 0x1f;
1708 cbp->fc_delay_msb = 0x01;
1709 cbp->pri_fc_thresh = 3;
1710 cbp->tx_fc_dis = 0; /* enable transmit FC */
1711 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1712 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1713 cbp->fc_filter = !prm; /* drop FC frames to host */
1714 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1718 * Start the config command/DMA.
1721 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1722 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1723 /* ...and wait for it to complete. */
1724 fxp_dma_wait(&cbp->cb_status, sc);
1727 * Now initialize the station address. Temporarily use the TxCB
1728 * memory area like we did above for the config CB.
1730 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1731 cb_ias->cb_status = 0;
1732 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1733 cb_ias->link_addr = -1;
1734 bcopy(sc->arpcom.ac_enaddr,
1735 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1736 sizeof(sc->arpcom.ac_enaddr));
1739 * Start the IAS (Individual Address Setup) command/DMA.
1742 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1743 /* ...and wait for it to complete. */
1744 fxp_dma_wait(&cb_ias->cb_status, sc);
1747 * Initialize transmit control block (TxCB) list.
1751 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1752 for (i = 0; i < FXP_NTXCB; i++) {
1753 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1754 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1756 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1757 if (sc->flags & FXP_FLAG_EXT_TXCB)
1758 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1760 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1761 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1764 * Set the suspend flag on the first TxCB and start the control
1765 * unit. It will execute the NOP and then suspend.
1767 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1768 sc->cbl_first = sc->cbl_last = txp;
1772 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1775 * Initialize receiver buffer area - RFA.
1778 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1779 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1780 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1783 * Set current media.
1785 if (sc->miibus != NULL)
1786 mii_mediachg(device_get_softc(sc->miibus));
1788 ifp->if_flags |= IFF_RUNNING;
1789 ifp->if_flags &= ~IFF_OACTIVE;
1792 * Enable interrupts.
1794 #ifdef DEVICE_POLLING
1796 * ... but only do that if we are not polling. And because (presumably)
1797 * the default is interrupts on, we need to disable them explicitly!
1799 if ( ifp->if_flags & IFF_POLLING )
1800 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1802 #endif /* DEVICE_POLLING */
1803 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1806 * Start stats updater.
1808 callout_reset(&sc->fxp_stat_timer, hz, fxp_tick, sc);
1812 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1819 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1822 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1826 * Change media according to request.
1829 fxp_ifmedia_upd(struct ifnet *ifp)
1831 struct fxp_softc *sc = ifp->if_softc;
1832 struct mii_data *mii;
1834 mii = device_get_softc(sc->miibus);
1840 * Notify the world which media we're using.
1843 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1845 struct fxp_softc *sc = ifp->if_softc;
1846 struct mii_data *mii;
1848 mii = device_get_softc(sc->miibus);
1850 ifmr->ifm_active = mii->mii_media_active;
1851 ifmr->ifm_status = mii->mii_media_status;
1853 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1854 sc->cu_resume_bug = 1;
1856 sc->cu_resume_bug = 0;
1860 * Add a buffer to the end of the RFA buffer list.
1861 * Return 0 if successful, 1 for failure. A failure results in
1862 * adding the 'oldm' (if non-NULL) on to the end of the list -
1863 * tossing out its old contents and recycling it.
1864 * The RFA struct is stuck at the beginning of mbuf cluster and the
1865 * data pointer is fixed up to point just past it.
1868 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1872 struct fxp_rfa *rfa, *p_rfa;
1874 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1875 if (m == NULL) { /* try to recycle the old mbuf instead */
1879 m->m_data = m->m_ext.ext_buf;
1883 * Move the data pointer up so that the incoming data packet
1884 * will be 32-bit aligned.
1886 m->m_data += RFA_ALIGNMENT_FUDGE;
1889 * Get a pointer to the base of the mbuf cluster and move
1890 * data start past it.
1892 rfa = mtod(m, struct fxp_rfa *);
1893 m->m_data += sizeof(struct fxp_rfa);
1894 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1897 * Initialize the rest of the RFA. Note that since the RFA
1898 * is misaligned, we cannot store values directly. Instead,
1899 * we use an optimized, inline copy.
1902 rfa->rfa_status = 0;
1903 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1904 rfa->actual_size = 0;
1907 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1908 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1911 * If there are other buffers already on the list, attach this
1912 * one to the end by fixing up the tail to point to this one.
1914 if (sc->rfa_headm != NULL) {
1915 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
1916 RFA_ALIGNMENT_FUDGE);
1917 sc->rfa_tailm->m_next = m;
1919 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1920 p_rfa->rfa_control = 0;
1930 fxp_miibus_readreg(device_t dev, int phy, int reg)
1932 struct fxp_softc *sc = device_get_softc(dev);
1936 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1937 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
1939 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
1944 device_printf(dev, "fxp_miibus_readreg: timed out\n");
1946 return (value & 0xffff);
1950 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
1952 struct fxp_softc *sc = device_get_softc(dev);
1955 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1956 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
1959 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
1964 device_printf(dev, "fxp_miibus_writereg: timed out\n");
1968 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1970 struct fxp_softc *sc = ifp->if_softc;
1971 struct ifreq *ifr = (struct ifreq *)data;
1972 struct mii_data *mii;
1978 if (ifp->if_flags & IFF_ALLMULTI)
1979 sc->flags |= FXP_FLAG_ALL_MCAST;
1981 sc->flags &= ~FXP_FLAG_ALL_MCAST;
1984 * If interface is marked up and not running, then start it.
1985 * If it is marked down and running, stop it.
1986 * XXX If it's up then re-initialize it. This is so flags
1987 * such as IFF_PROMISC are handled.
1989 if (ifp->if_flags & IFF_UP) {
1992 if (ifp->if_flags & IFF_RUNNING)
1999 if (ifp->if_flags & IFF_ALLMULTI)
2000 sc->flags |= FXP_FLAG_ALL_MCAST;
2002 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2004 * Multicast list has changed; set the hardware filter
2007 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2010 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2011 * again rather than else {}.
2013 if (sc->flags & FXP_FLAG_ALL_MCAST)
2020 if (sc->miibus != NULL) {
2021 mii = device_get_softc(sc->miibus);
2022 error = ifmedia_ioctl(ifp, ifr,
2023 &mii->mii_media, command);
2025 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2030 error = ether_ioctl(ifp, command, data);
2037 * Fill in the multicast address list and return number of entries.
2040 fxp_mc_addrs(struct fxp_softc *sc)
2042 struct fxp_cb_mcs *mcsp = sc->mcsp;
2043 struct ifnet *ifp = &sc->arpcom.ac_if;
2044 struct ifmultiaddr *ifma;
2048 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2049 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2050 if (ifma->ifma_addr->sa_family != AF_LINK)
2052 if (nmcasts >= MAXMCADDR) {
2053 sc->flags |= FXP_FLAG_ALL_MCAST;
2057 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2058 (void *)(uintptr_t)(volatile void *)
2059 &sc->mcsp->mc_addr[nmcasts][0], 6);
2063 mcsp->mc_cnt = nmcasts * 6;
2068 * Program the multicast filter.
2070 * We have an artificial restriction that the multicast setup command
2071 * must be the first command in the chain, so we take steps to ensure
2072 * this. By requiring this, it allows us to keep up the performance of
2073 * the pre-initialized command ring (esp. link pointers) by not actually
2074 * inserting the mcsetup command in the ring - i.e. its link pointer
2075 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2076 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2077 * lead into the regular TxCB ring when it completes.
2079 * This function must be called at splimp.
2082 fxp_mc_setup(struct fxp_softc *sc)
2084 struct fxp_cb_mcs *mcsp = sc->mcsp;
2085 struct ifnet *ifp = &sc->arpcom.ac_if;
2089 * If there are queued commands, we must wait until they are all
2090 * completed. If we are already waiting, then add a NOP command
2091 * with interrupt option so that we're notified when all commands
2092 * have been completed - fxp_start() ensures that no additional
2093 * TX commands will be added when need_mcsetup is true.
2095 if (sc->tx_queued) {
2096 struct fxp_cb_tx *txp;
2099 * need_mcsetup will be true if we are already waiting for the
2100 * NOP command to be completed (see below). In this case, bail.
2102 if (sc->need_mcsetup)
2104 sc->need_mcsetup = 1;
2107 * Add a NOP command with interrupt so that we are notified
2108 * when all TX commands have been processed.
2110 txp = sc->cbl_last->next;
2111 txp->mb_head = NULL;
2113 txp->cb_command = FXP_CB_COMMAND_NOP |
2114 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2116 * Advance the end of list forward.
2118 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2122 * Issue a resume in case the CU has just suspended.
2125 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2127 * Set a 5 second timer just in case we don't hear from the
2134 sc->need_mcsetup = 0;
2137 * Initialize multicast setup descriptor.
2139 mcsp->next = sc->cbl_base;
2140 mcsp->mb_head = NULL;
2141 mcsp->cb_status = 0;
2142 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2143 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2144 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2146 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2150 * Wait until command unit is not active. This should never
2151 * be the case when nothing is queued, but make sure anyway.
2154 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2155 FXP_SCB_CUS_ACTIVE && --count)
2158 if_printf(&sc->arpcom.ac_if, "command queue timeout\n");
2163 * Start the multicast setup command.
2166 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2167 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2173 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2174 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2175 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2176 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2177 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2178 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2180 #define UCODE(x) x, sizeof(x)
2186 u_short int_delay_offset;
2187 u_short bundle_max_offset;
2189 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2190 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2191 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2192 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2193 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2194 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2195 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2196 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2197 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2198 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2199 { 0, NULL, 0, 0, 0 }
2203 fxp_load_ucode(struct fxp_softc *sc)
2206 struct fxp_cb_ucode *cbp;
2208 for (uc = ucode_table; uc->ucode != NULL; uc++)
2209 if (sc->revision == uc->revision)
2211 if (uc->ucode == NULL)
2213 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2215 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2216 cbp->link_addr = -1; /* (no) next command */
2217 memcpy(cbp->ucode, uc->ucode, uc->length);
2218 if (uc->int_delay_offset)
2219 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2220 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2221 if (uc->bundle_max_offset)
2222 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2223 sc->tunable_bundle_max;
2225 * Download the ucode to the chip.
2228 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2229 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2230 /* ...and wait for it to complete. */
2231 fxp_dma_wait(&cbp->cb_status, sc);
2232 if_printf(&sc->arpcom.ac_if,
2233 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2234 sc->tunable_int_delay,
2235 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2236 sc->flags |= FXP_FLAG_UCODE;
2240 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2244 value = *(int *)arg1;
2245 error = sysctl_handle_int(oidp, &value, 0, req);
2246 if (error || !req->newptr)
2248 if (value < low || value > high)
2250 *(int *)arg1 = value;
2255 * Interrupt delay is expressed in microseconds, a multiplier is used
2256 * to convert this to the appropriate clock ticks before using.
2259 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2261 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2265 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2267 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));