sys/i386/i386/exception.s

   1 /*-
   2  * Copyright (c) 1990 The Regents of the University of California.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *      This product includes software developed by the University of
  16  *      California, Berkeley and its contributors.
  17  * 4. Neither the name of the University nor the names of its contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/i386/i386/exception.s,v 1.65.2.3 2001/08/15 01:23:49 peter Exp $
  34  * $DragonFly: src/sys/i386/i386/Attic/exception.s,v 1.20 2003/10/25 17:36:22 dillon Exp $
  35  */
  36
  37 #include "use_npx.h"
  38
  39 #include <machine/asmacros.h>
  40 #include <machine/ipl.h>
  41 #include <machine/lock.h>
  42 #include <machine/psl.h>
  43 #include <machine/trap.h>
  44 #ifdef SMP
  45 #include <machine/smptests.h>           /** various SMP options */
  46 #endif
  47
  48 #include "assym.s"
  49
  50 #define SEL_RPL_MASK    0x0003
  51
  52         .text
  53
  54 #ifdef DEBUG_INTERRUPTS
  55         .globl  Xrsvdary
  56
  57 Xrsvdary:
  58  .long  Xrsvd0
  59  .long  Xrsvd1  , Xrsvd2  , Xrsvd3  , Xrsvd4  , Xrsvd5  , Xrsvd6  , Xrsvd7  , Xrsvd8
  60  .long  Xrsvd9  , Xrsvd10 , Xrsvd11 , Xrsvd12 , Xrsvd13 , Xrsvd14 , Xrsvd15 , Xrsvd16
  61  .long  Xrsvd17 , Xrsvd18 , Xrsvd19 , Xrsvd20 , Xrsvd21 , Xrsvd22 , Xrsvd23 , Xrsvd24
  62  .long  Xrsvd25 , Xrsvd26 , Xrsvd27 , Xrsvd28 , Xrsvd29 , Xrsvd30 , Xrsvd31 , Xrsvd32
  63  .long  Xrsvd33 , Xrsvd34 , Xrsvd35 , Xrsvd36 , Xrsvd37 , Xrsvd38 , Xrsvd39 , Xrsvd40
  64  .long  Xrsvd41 , Xrsvd42 , Xrsvd43 , Xrsvd44 , Xrsvd45 , Xrsvd46 , Xrsvd47 , Xrsvd48
  65  .long  Xrsvd49 , Xrsvd50 , Xrsvd51 , Xrsvd52 , Xrsvd53 , Xrsvd54 , Xrsvd55 , Xrsvd56
  66  .long  Xrsvd57 , Xrsvd58 , Xrsvd59 , Xrsvd60 , Xrsvd61 , Xrsvd62 , Xrsvd63 , Xrsvd64
  67  .long  Xrsvd65 , Xrsvd66 , Xrsvd67 , Xrsvd68 , Xrsvd69 , Xrsvd70 , Xrsvd71 , Xrsvd72
  68  .long  Xrsvd73 , Xrsvd74 , Xrsvd75 , Xrsvd76 , Xrsvd77 , Xrsvd78 , Xrsvd79 , Xrsvd80
  69  .long  Xrsvd81 , Xrsvd82 , Xrsvd83 , Xrsvd84 , Xrsvd85 , Xrsvd86 , Xrsvd87 , Xrsvd88
  70  .long  Xrsvd89 , Xrsvd90 , Xrsvd91 , Xrsvd92 , Xrsvd93 , Xrsvd94 , Xrsvd95 , Xrsvd96
  71  .long  Xrsvd97 , Xrsvd98 , Xrsvd99 , Xrsvd100, Xrsvd101, Xrsvd102, Xrsvd103, Xrsvd104
  72  .long  Xrsvd105, Xrsvd106, Xrsvd107, Xrsvd108, Xrsvd109, Xrsvd110, Xrsvd111, Xrsvd112
  73  .long  Xrsvd113, Xrsvd114, Xrsvd115, Xrsvd116, Xrsvd117, Xrsvd118, Xrsvd119, Xrsvd120
  74  .long  Xrsvd121, Xrsvd122, Xrsvd123, Xrsvd124, Xrsvd125, Xrsvd126, Xrsvd127, Xrsvd128
  75  .long  Xrsvd129, Xrsvd130, Xrsvd131, Xrsvd132, Xrsvd133, Xrsvd134, Xrsvd135, Xrsvd136
  76  .long  Xrsvd137, Xrsvd138, Xrsvd139, Xrsvd140, Xrsvd141, Xrsvd142, Xrsvd143, Xrsvd144
  77  .long  Xrsvd145, Xrsvd146, Xrsvd147, Xrsvd148, Xrsvd149, Xrsvd150, Xrsvd151, Xrsvd152
  78  .long  Xrsvd153, Xrsvd154, Xrsvd155, Xrsvd156, Xrsvd157, Xrsvd158, Xrsvd159, Xrsvd160
  79  .long  Xrsvd161, Xrsvd162, Xrsvd163, Xrsvd164, Xrsvd165, Xrsvd166, Xrsvd167, Xrsvd168
  80  .long  Xrsvd169, Xrsvd170, Xrsvd171, Xrsvd172, Xrsvd173, Xrsvd174, Xrsvd175, Xrsvd176
  81  .long  Xrsvd177, Xrsvd178, Xrsvd179, Xrsvd180, Xrsvd181, Xrsvd182, Xrsvd183, Xrsvd184
  82  .long  Xrsvd185, Xrsvd186, Xrsvd187, Xrsvd188, Xrsvd189, Xrsvd190, Xrsvd191, Xrsvd192
  83  .long  Xrsvd193, Xrsvd194, Xrsvd195, Xrsvd196, Xrsvd197, Xrsvd198, Xrsvd199, Xrsvd200
  84  .long  Xrsvd201, Xrsvd202, Xrsvd203, Xrsvd204, Xrsvd205, Xrsvd206, Xrsvd207, Xrsvd208
  85  .long  Xrsvd209, Xrsvd210, Xrsvd211, Xrsvd212, Xrsvd213, Xrsvd214, Xrsvd215, Xrsvd216
  86  .long  Xrsvd217, Xrsvd218, Xrsvd219, Xrsvd220, Xrsvd221, Xrsvd222, Xrsvd223, Xrsvd224
  87  .long  Xrsvd225, Xrsvd226, Xrsvd227, Xrsvd228, Xrsvd229, Xrsvd230, Xrsvd231, Xrsvd232
  88  .long  Xrsvd233, Xrsvd234, Xrsvd235, Xrsvd236, Xrsvd237, Xrsvd238, Xrsvd239, Xrsvd240
  89  .long  Xrsvd241, Xrsvd242, Xrsvd243, Xrsvd244, Xrsvd245, Xrsvd246, Xrsvd247, Xrsvd248
  90  .long  Xrsvd249, Xrsvd250, Xrsvd251, Xrsvd252, Xrsvd253, Xrsvd254, Xrsvd255
  91
  92 #endif
  93
  94 /*****************************************************************************/
  95 /* Trap handling                                                             */
  96 /*****************************************************************************/
  97 /*
  98  * Trap and fault vector routines.
  99  *
 100  * Most traps are 'trap gates', SDT_SYS386TGT.  A trap gate pushes state on
 101  * the stack that mostly looks like an interrupt, but does not disable
 102  * interrupts.  A few of the traps we are use are interrupt gates,
 103  * SDT_SYS386IGT, which are nearly the same thing except interrupts are
 104  * disabled on entry.
 105  *
 106  * The cpu will push a certain amount of state onto the kernel stack for
 107  * the current process.  The amount of state depends on the type of trap
 108  * and whether the trap crossed rings or not.  See i386/include/frame.h.
 109  * At the very least the current EFLAGS (status register, which includes
 110  * the interrupt disable state prior to the trap), the code segment register,
 111  * and the return instruction pointer are pushed by the cpu.  The cpu
 112  * will also push an 'error' code for certain traps.  We push a dummy
 113  * error code for those traps where the cpu doesn't in order to maintain
 114  * a consistent frame.  We also push a contrived 'trap number'.
 115  *
 116  * The cpu does not push the general registers, we must do that, and we
 117  * must restore them prior to calling 'iret'.  The cpu adjusts the %cs and
 118  * %ss segment registers, but does not mess with %ds, %es, or %fs.  Thus we
 119  * must load them with appropriate values for supervisor mode operation.
 120  *
 121  * On entry to a trap or interrupt WE DO NOT OWN THE MP LOCK.  This means
 122  * that we must be careful in regards to accessing global variables.  We
 123  * save (push) the current cpl (our software interrupt disable mask), call
 124  * the trap function, then jump to doreti to restore the cpl and deal with
 125  * ASTs (software interrupts).  doreti will determine if the restoration
 126  * of the cpl unmasked any pending interrupts and will issue those interrupts
 127  * synchronously prior to doing the iret.
 128  */
 129 #define IDTVEC(name)    ALIGN_TEXT; .globl __CONCAT(X,name); \
 130                         .type __CONCAT(X,name),@function; __CONCAT(X,name):
 131 #define TRAP(a)         pushl $(a) ; jmp alltraps
 132
 133 #ifdef BDE_DEBUGGER
 134 #define BDBTRAP(name) \
 135         ss ; \
 136         cmpb    $0,bdb_exists ; \
 137         je      1f ; \
 138         testb   $SEL_RPL_MASK,4(%esp) ; \
 139         jne     1f ; \
 140         ss ; \
 141         .globl  __CONCAT(__CONCAT(bdb_,name),_ljmp); \
 142 __CONCAT(__CONCAT(bdb_,name),_ljmp): \
 143         ljmp    $0,$0 ; \
 144 1:
 145 #else
 146 #define BDBTRAP(name)
 147 #endif
 148
 149 #define BPTTRAP(a)      testl $PSL_I,4+8(%esp) ; je 1f ; sti ; 1: ; TRAP(a)
 150
 151 MCOUNT_LABEL(user)
 152 MCOUNT_LABEL(btrap)
 153
 154 IDTVEC(div)
 155         pushl $0; TRAP(T_DIVIDE)
 156 IDTVEC(dbg)
 157         BDBTRAP(dbg)
 158         pushl $0; BPTTRAP(T_TRCTRAP)
 159 IDTVEC(nmi)
 160         pushl $0; TRAP(T_NMI)
 161 IDTVEC(bpt)
 162         BDBTRAP(bpt)
 163         pushl $0; BPTTRAP(T_BPTFLT)
 164 IDTVEC(ofl)
 165         pushl $0; TRAP(T_OFLOW)
 166 IDTVEC(bnd)
 167         pushl $0; TRAP(T_BOUND)
 168 IDTVEC(ill)
 169         pushl $0; TRAP(T_PRIVINFLT)
 170 IDTVEC(dna)
 171         pushl $0; TRAP(T_DNA)
 172 IDTVEC(fpusegm)
 173         pushl $0; TRAP(T_FPOPFLT)
 174 IDTVEC(tss)
 175         TRAP(T_TSSFLT)
 176 IDTVEC(missing)
 177         TRAP(T_SEGNPFLT)
 178 IDTVEC(stk)
 179         TRAP(T_STKFLT)
 180 IDTVEC(prot)
 181         TRAP(T_PROTFLT)
 182 IDTVEC(page)
 183         TRAP(T_PAGEFLT)
 184 IDTVEC(mchk)
 185         pushl $0; TRAP(T_MCHK)
 186
 187 IDTVEC(rsvd0)
 188         pushl $0; TRAP(T_RESERVED)
 189
 190 #ifdef DEBUG_INTERRUPTS
 191
 192 IDTVEC(rsvd1)
 193         pushl $1; TRAP(T_RESERVED)
 194 IDTVEC(rsvd2)
 195         pushl $2; TRAP(T_RESERVED)
 196 IDTVEC(rsvd3)
 197         pushl $3; TRAP(T_RESERVED)
 198 IDTVEC(rsvd4)
 199         pushl $4; TRAP(T_RESERVED)
 200 IDTVEC(rsvd5)
 201         pushl $5; TRAP(T_RESERVED)
 202 IDTVEC(rsvd6)
 203         pushl $6; TRAP(T_RESERVED)
 204 IDTVEC(rsvd7)
 205         pushl $7; TRAP(T_RESERVED)
 206 IDTVEC(rsvd8)
 207         pushl $8; TRAP(T_RESERVED)
 208 IDTVEC(rsvd9)
 209         pushl $9; TRAP(T_RESERVED)
 210 IDTVEC(rsvd10)
 211         pushl $10; TRAP(T_RESERVED)
 212 IDTVEC(rsvd11)
 213         pushl $11; TRAP(T_RESERVED)
 214 IDTVEC(rsvd12)
 215         pushl $12; TRAP(T_RESERVED)
 216 IDTVEC(rsvd13)
 217         pushl $13; TRAP(T_RESERVED)
 218 IDTVEC(rsvd14)
 219         pushl $14; TRAP(T_RESERVED)
 220 IDTVEC(rsvd15)
 221         pushl $15; TRAP(T_RESERVED)
 222 IDTVEC(rsvd16)
 223         pushl $16; TRAP(T_RESERVED)
 224 IDTVEC(rsvd17)
 225         pushl $17; TRAP(T_RESERVED)
 226 IDTVEC(rsvd18)
 227         pushl $18; TRAP(T_RESERVED)
 228 IDTVEC(rsvd19)
 229         pushl $19; TRAP(T_RESERVED)
 230 IDTVEC(rsvd20)
 231         pushl $20; TRAP(T_RESERVED)
 232 IDTVEC(rsvd21)
 233         pushl $21; TRAP(T_RESERVED)
 234 IDTVEC(rsvd22)
 235         pushl $22; TRAP(T_RESERVED)
 236 IDTVEC(rsvd23)
 237         pushl $23; TRAP(T_RESERVED)
 238 IDTVEC(rsvd24)
 239         pushl $24; TRAP(T_RESERVED)
 240 IDTVEC(rsvd25)
 241         pushl $25; TRAP(T_RESERVED)
 242 IDTVEC(rsvd26)
 243         pushl $26; TRAP(T_RESERVED)
 244 IDTVEC(rsvd27)
 245         pushl $27; TRAP(T_RESERVED)
 246 IDTVEC(rsvd28)
 247         pushl $28; TRAP(T_RESERVED)
 248 IDTVEC(rsvd29)
 249         pushl $29; TRAP(T_RESERVED)
 250 IDTVEC(rsvd30)
 251         pushl $30; TRAP(T_RESERVED)
 252 IDTVEC(rsvd31)
 253         pushl $31; TRAP(T_RESERVED)
 254 IDTVEC(rsvd32)
 255         pushl $32; TRAP(T_RESERVED)
 256 IDTVEC(rsvd33)
 257         pushl $33; TRAP(T_RESERVED)
 258 IDTVEC(rsvd34)
 259         pushl $34; TRAP(T_RESERVED)
 260 IDTVEC(rsvd35)
 261         pushl $35; TRAP(T_RESERVED)
 262 IDTVEC(rsvd36)
 263         pushl $36; TRAP(T_RESERVED)
 264 IDTVEC(rsvd37)
 265         pushl $37; TRAP(T_RESERVED)
 266 IDTVEC(rsvd38)
 267         pushl $38; TRAP(T_RESERVED)
 268 IDTVEC(rsvd39)
 269         pushl $39; TRAP(T_RESERVED)
 270 IDTVEC(rsvd40)
 271         pushl $40; TRAP(T_RESERVED)
 272 IDTVEC(rsvd41)
 273         pushl $41; TRAP(T_RESERVED)
 274 IDTVEC(rsvd42)
 275         pushl $42; TRAP(T_RESERVED)
 276 IDTVEC(rsvd43)
 277         pushl $43; TRAP(T_RESERVED)
 278 IDTVEC(rsvd44)
 279         pushl $44; TRAP(T_RESERVED)
 280 IDTVEC(rsvd45)
 281         pushl $45; TRAP(T_RESERVED)
 282 IDTVEC(rsvd46)
 283         pushl $46; TRAP(T_RESERVED)
 284 IDTVEC(rsvd47)
 285         pushl $47; TRAP(T_RESERVED)
 286 IDTVEC(rsvd48)
 287         pushl $48; TRAP(T_RESERVED)
 288 IDTVEC(rsvd49)
 289         pushl $49; TRAP(T_RESERVED)
 290 IDTVEC(rsvd50)
 291         pushl $50; TRAP(T_RESERVED)
 292 IDTVEC(rsvd51)
 293         pushl $51; TRAP(T_RESERVED)
 294 IDTVEC(rsvd52)
 295         pushl $52; TRAP(T_RESERVED)
 296 IDTVEC(rsvd53)
 297         pushl $53; TRAP(T_RESERVED)
 298 IDTVEC(rsvd54)
 299         pushl $54; TRAP(T_RESERVED)
 300 IDTVEC(rsvd55)
 301         pushl $55; TRAP(T_RESERVED)
 302 IDTVEC(rsvd56)
 303         pushl $56; TRAP(T_RESERVED)
 304 IDTVEC(rsvd57)
 305         pushl $57; TRAP(T_RESERVED)
 306 IDTVEC(rsvd58)
 307         pushl $58; TRAP(T_RESERVED)
 308 IDTVEC(rsvd59)
 309         pushl $59; TRAP(T_RESERVED)
 310 IDTVEC(rsvd60)
 311         pushl $60; TRAP(T_RESERVED)
 312 IDTVEC(rsvd61)
 313         pushl $61; TRAP(T_RESERVED)
 314 IDTVEC(rsvd62)
 315         pushl $62; TRAP(T_RESERVED)
 316 IDTVEC(rsvd63)
 317         pushl $63; TRAP(T_RESERVED)
 318 IDTVEC(rsvd64)
 319         pushl $64; TRAP(T_RESERVED)
 320 IDTVEC(rsvd65)
 321         pushl $65; TRAP(T_RESERVED)
 322 IDTVEC(rsvd66)
 323         pushl $66; TRAP(T_RESERVED)
 324 IDTVEC(rsvd67)
 325         pushl $67; TRAP(T_RESERVED)
 326 IDTVEC(rsvd68)
 327         pushl $68; TRAP(T_RESERVED)
 328 IDTVEC(rsvd69)
 329         pushl $69; TRAP(T_RESERVED)
 330 IDTVEC(rsvd70)
 331         pushl $70; TRAP(T_RESERVED)
 332 IDTVEC(rsvd71)
 333         pushl $71; TRAP(T_RESERVED)
 334 IDTVEC(rsvd72)
 335         pushl $72; TRAP(T_RESERVED)
 336 IDTVEC(rsvd73)
 337         pushl $73; TRAP(T_RESERVED)
 338 IDTVEC(rsvd74)
 339         pushl $74; TRAP(T_RESERVED)
 340 IDTVEC(rsvd75)
 341         pushl $75; TRAP(T_RESERVED)
 342 IDTVEC(rsvd76)
 343         pushl $76; TRAP(T_RESERVED)
 344 IDTVEC(rsvd77)
 345         pushl $77; TRAP(T_RESERVED)
 346 IDTVEC(rsvd78)
 347         pushl $78; TRAP(T_RESERVED)
 348 IDTVEC(rsvd79)
 349         pushl $79; TRAP(T_RESERVED)
 350 IDTVEC(rsvd80)
 351         pushl $80; TRAP(T_RESERVED)
 352 IDTVEC(rsvd81)
 353         pushl $81; TRAP(T_RESERVED)
 354 IDTVEC(rsvd82)
 355         pushl $82; TRAP(T_RESERVED)
 356 IDTVEC(rsvd83)
 357         pushl $83; TRAP(T_RESERVED)
 358 IDTVEC(rsvd84)
 359         pushl $84; TRAP(T_RESERVED)
 360 IDTVEC(rsvd85)
 361         pushl $85; TRAP(T_RESERVED)
 362 IDTVEC(rsvd86)
 363         pushl $86; TRAP(T_RESERVED)
 364 IDTVEC(rsvd87)
 365         pushl $87; TRAP(T_RESERVED)
 366 IDTVEC(rsvd88)
 367         pushl $88; TRAP(T_RESERVED)
 368 IDTVEC(rsvd89)
 369         pushl $89; TRAP(T_RESERVED)
 370 IDTVEC(rsvd90)
 371         pushl $90; TRAP(T_RESERVED)
 372 IDTVEC(rsvd91)
 373         pushl $91; TRAP(T_RESERVED)
 374 IDTVEC(rsvd92)
 375         pushl $92; TRAP(T_RESERVED)
 376 IDTVEC(rsvd93)
 377         pushl $93; TRAP(T_RESERVED)
 378 IDTVEC(rsvd94)
 379         pushl $94; TRAP(T_RESERVED)
 380 IDTVEC(rsvd95)
 381         pushl $95; TRAP(T_RESERVED)
 382 IDTVEC(rsvd96)
 383         pushl $96; TRAP(T_RESERVED)
 384 IDTVEC(rsvd97)
 385         pushl $97; TRAP(T_RESERVED)
 386 IDTVEC(rsvd98)
 387         pushl $98; TRAP(T_RESERVED)
 388 IDTVEC(rsvd99)
 389         pushl $99; TRAP(T_RESERVED)
 390 IDTVEC(rsvd100)
 391         pushl $100; TRAP(T_RESERVED)
 392 IDTVEC(rsvd101)
 393         pushl $101; TRAP(T_RESERVED)
 394 IDTVEC(rsvd102)
 395         pushl $102; TRAP(T_RESERVED)
 396 IDTVEC(rsvd103)
 397         pushl $103; TRAP(T_RESERVED)
 398 IDTVEC(rsvd104)
 399         pushl $104; TRAP(T_RESERVED)
 400 IDTVEC(rsvd105)
 401         pushl $105; TRAP(T_RESERVED)
 402 IDTVEC(rsvd106)
 403         pushl $106; TRAP(T_RESERVED)
 404 IDTVEC(rsvd107)
 405         pushl $107; TRAP(T_RESERVED)
 406 IDTVEC(rsvd108)
 407         pushl $108; TRAP(T_RESERVED)
 408 IDTVEC(rsvd109)
 409         pushl $109; TRAP(T_RESERVED)
 410 IDTVEC(rsvd110)
 411         pushl $110; TRAP(T_RESERVED)
 412 IDTVEC(rsvd111)
 413         pushl $111; TRAP(T_RESERVED)
 414 IDTVEC(rsvd112)
 415         pushl $112; TRAP(T_RESERVED)
 416 IDTVEC(rsvd113)
 417         pushl $113; TRAP(T_RESERVED)
 418 IDTVEC(rsvd114)
 419         pushl $114; TRAP(T_RESERVED)
 420 IDTVEC(rsvd115)
 421         pushl $115; TRAP(T_RESERVED)
 422 IDTVEC(rsvd116)
 423         pushl $116; TRAP(T_RESERVED)
 424 IDTVEC(rsvd117)
 425         pushl $117; TRAP(T_RESERVED)
 426 IDTVEC(rsvd118)
 427         pushl $118; TRAP(T_RESERVED)
 428 IDTVEC(rsvd119)
 429         pushl $119; TRAP(T_RESERVED)
 430 IDTVEC(rsvd120)
 431         pushl $120; TRAP(T_RESERVED)
 432 IDTVEC(rsvd121)
 433         pushl $121; TRAP(T_RESERVED)
 434 IDTVEC(rsvd122)
 435         pushl $122; TRAP(T_RESERVED)
 436 IDTVEC(rsvd123)
 437         pushl $123; TRAP(T_RESERVED)
 438 IDTVEC(rsvd124)
 439         pushl $124; TRAP(T_RESERVED)
 440 IDTVEC(rsvd125)
 441         pushl $125; TRAP(T_RESERVED)
 442 IDTVEC(rsvd126)
 443         pushl $126; TRAP(T_RESERVED)
 444 IDTVEC(rsvd127)
 445         pushl $127; TRAP(T_RESERVED)
 446 IDTVEC(rsvd128)
 447         pushl $128; TRAP(T_RESERVED)
 448 IDTVEC(rsvd129)
 449         pushl $129; TRAP(T_RESERVED)
 450 IDTVEC(rsvd130)
 451         pushl $130; TRAP(T_RESERVED)
 452 IDTVEC(rsvd131)
 453         pushl $131; TRAP(T_RESERVED)
 454 IDTVEC(rsvd132)
 455         pushl $132; TRAP(T_RESERVED)
 456 IDTVEC(rsvd133)
 457         pushl $133; TRAP(T_RESERVED)
 458 IDTVEC(rsvd134)
 459         pushl $134; TRAP(T_RESERVED)
 460 IDTVEC(rsvd135)
 461         pushl $135; TRAP(T_RESERVED)
 462 IDTVEC(rsvd136)
 463         pushl $136; TRAP(T_RESERVED)
 464 IDTVEC(rsvd137)
 465         pushl $137; TRAP(T_RESERVED)
 466 IDTVEC(rsvd138)
 467         pushl $138; TRAP(T_RESERVED)
 468 IDTVEC(rsvd139)
 469         pushl $139; TRAP(T_RESERVED)
 470 IDTVEC(rsvd140)
 471         pushl $140; TRAP(T_RESERVED)
 472 IDTVEC(rsvd141)
 473         pushl $141; TRAP(T_RESERVED)
 474 IDTVEC(rsvd142)
 475         pushl $142; TRAP(T_RESERVED)
 476 IDTVEC(rsvd143)
 477         pushl $143; TRAP(T_RESERVED)
 478 IDTVEC(rsvd144)
 479         pushl $144; TRAP(T_RESERVED)
 480 IDTVEC(rsvd145)
 481         pushl $145; TRAP(T_RESERVED)
 482 IDTVEC(rsvd146)
 483         pushl $146; TRAP(T_RESERVED)
 484 IDTVEC(rsvd147)
 485         pushl $147; TRAP(T_RESERVED)
 486 IDTVEC(rsvd148)
 487         pushl $148; TRAP(T_RESERVED)
 488 IDTVEC(rsvd149)
 489         pushl $149; TRAP(T_RESERVED)
 490 IDTVEC(rsvd150)
 491         pushl $150; TRAP(T_RESERVED)
 492 IDTVEC(rsvd151)
 493         pushl $151; TRAP(T_RESERVED)
 494 IDTVEC(rsvd152)
 495         pushl $152; TRAP(T_RESERVED)
 496 IDTVEC(rsvd153)
 497         pushl $153; TRAP(T_RESERVED)
 498 IDTVEC(rsvd154)
 499         pushl $154; TRAP(T_RESERVED)
 500 IDTVEC(rsvd155)
 501         pushl $155; TRAP(T_RESERVED)
 502 IDTVEC(rsvd156)
 503         pushl $156; TRAP(T_RESERVED)
 504 IDTVEC(rsvd157)
 505         pushl $157; TRAP(T_RESERVED)
 506 IDTVEC(rsvd158)
 507         pushl $158; TRAP(T_RESERVED)
 508 IDTVEC(rsvd159)
 509         pushl $159; TRAP(T_RESERVED)
 510 IDTVEC(rsvd160)
 511         pushl $160; TRAP(T_RESERVED)
 512 IDTVEC(rsvd161)
 513         pushl $161; TRAP(T_RESERVED)
 514 IDTVEC(rsvd162)
 515         pushl $162; TRAP(T_RESERVED)
 516 IDTVEC(rsvd163)
 517         pushl $163; TRAP(T_RESERVED)
 518 IDTVEC(rsvd164)
 519         pushl $164; TRAP(T_RESERVED)
 520 IDTVEC(rsvd165)
 521         pushl $165; TRAP(T_RESERVED)
 522 IDTVEC(rsvd166)
 523         pushl $166; TRAP(T_RESERVED)
 524 IDTVEC(rsvd167)
 525         pushl $167; TRAP(T_RESERVED)
 526 IDTVEC(rsvd168)
 527         pushl $168; TRAP(T_RESERVED)
 528 IDTVEC(rsvd169)
 529         pushl $169; TRAP(T_RESERVED)
 530 IDTVEC(rsvd170)
 531         pushl $170; TRAP(T_RESERVED)
 532 IDTVEC(rsvd171)
 533         pushl $171; TRAP(T_RESERVED)
 534 IDTVEC(rsvd172)
 535         pushl $172; TRAP(T_RESERVED)
 536 IDTVEC(rsvd173)
 537         pushl $173; TRAP(T_RESERVED)
 538 IDTVEC(rsvd174)
 539         pushl $174; TRAP(T_RESERVED)
 540 IDTVEC(rsvd175)
 541         pushl $175; TRAP(T_RESERVED)
 542 IDTVEC(rsvd176)
 543         pushl $176; TRAP(T_RESERVED)
 544 IDTVEC(rsvd177)
 545         pushl $177; TRAP(T_RESERVED)
 546 IDTVEC(rsvd178)
 547         pushl $178; TRAP(T_RESERVED)
 548 IDTVEC(rsvd179)
 549         pushl $179; TRAP(T_RESERVED)
 550 IDTVEC(rsvd180)
 551         pushl $180; TRAP(T_RESERVED)
 552 IDTVEC(rsvd181)
 553         pushl $181; TRAP(T_RESERVED)
 554 IDTVEC(rsvd182)
 555         pushl $182; TRAP(T_RESERVED)
 556 IDTVEC(rsvd183)
 557         pushl $183; TRAP(T_RESERVED)
 558 IDTVEC(rsvd184)
 559         pushl $184; TRAP(T_RESERVED)
 560 IDTVEC(rsvd185)
 561         pushl $185; TRAP(T_RESERVED)
 562 IDTVEC(rsvd186)
 563         pushl $186; TRAP(T_RESERVED)
 564 IDTVEC(rsvd187)
 565         pushl $187; TRAP(T_RESERVED)
 566 IDTVEC(rsvd188)
 567         pushl $188; TRAP(T_RESERVED)
 568 IDTVEC(rsvd189)
 569         pushl $189; TRAP(T_RESERVED)
 570 IDTVEC(rsvd190)
 571         pushl $190; TRAP(T_RESERVED)
 572 IDTVEC(rsvd191)
 573         pushl $191; TRAP(T_RESERVED)
 574 IDTVEC(rsvd192)
 575         pushl $192; TRAP(T_RESERVED)
 576 IDTVEC(rsvd193)
 577         pushl $193; TRAP(T_RESERVED)
 578 IDTVEC(rsvd194)
 579         pushl $194; TRAP(T_RESERVED)
 580 IDTVEC(rsvd195)
 581         pushl $195; TRAP(T_RESERVED)
 582 IDTVEC(rsvd196)
 583         pushl $196; TRAP(T_RESERVED)
 584 IDTVEC(rsvd197)
 585         pushl $197; TRAP(T_RESERVED)
 586 IDTVEC(rsvd198)
 587         pushl $198; TRAP(T_RESERVED)
 588 IDTVEC(rsvd199)
 589         pushl $199; TRAP(T_RESERVED)
 590 IDTVEC(rsvd200)
 591         pushl $200; TRAP(T_RESERVED)
 592 IDTVEC(rsvd201)
 593         pushl $201; TRAP(T_RESERVED)
 594 IDTVEC(rsvd202)
 595         pushl $202; TRAP(T_RESERVED)
 596 IDTVEC(rsvd203)
 597         pushl $203; TRAP(T_RESERVED)
 598 IDTVEC(rsvd204)
 599         pushl $204; TRAP(T_RESERVED)
 600 IDTVEC(rsvd205)
 601         pushl $205; TRAP(T_RESERVED)
 602 IDTVEC(rsvd206)
 603         pushl $206; TRAP(T_RESERVED)
 604 IDTVEC(rsvd207)
 605         pushl $207; TRAP(T_RESERVED)
 606 IDTVEC(rsvd208)
 607         pushl $208; TRAP(T_RESERVED)
 608 IDTVEC(rsvd209)
 609         pushl $209; TRAP(T_RESERVED)
 610 IDTVEC(rsvd210)
 611         pushl $210; TRAP(T_RESERVED)
 612 IDTVEC(rsvd211)
 613         pushl $211; TRAP(T_RESERVED)
 614 IDTVEC(rsvd212)
 615         pushl $212; TRAP(T_RESERVED)
 616 IDTVEC(rsvd213)
 617         pushl $213; TRAP(T_RESERVED)
 618 IDTVEC(rsvd214)
 619         pushl $214; TRAP(T_RESERVED)
 620 IDTVEC(rsvd215)
 621         pushl $215; TRAP(T_RESERVED)
 622 IDTVEC(rsvd216)
 623         pushl $216; TRAP(T_RESERVED)
 624 IDTVEC(rsvd217)
 625         pushl $217; TRAP(T_RESERVED)
 626 IDTVEC(rsvd218)
 627         pushl $218; TRAP(T_RESERVED)
 628 IDTVEC(rsvd219)
 629         pushl $219; TRAP(T_RESERVED)
 630 IDTVEC(rsvd220)
 631         pushl $220; TRAP(T_RESERVED)
 632 IDTVEC(rsvd221)
 633         pushl $221; TRAP(T_RESERVED)
 634 IDTVEC(rsvd222)
 635         pushl $222; TRAP(T_RESERVED)
 636 IDTVEC(rsvd223)
 637         pushl $223; TRAP(T_RESERVED)
 638 IDTVEC(rsvd224)
 639         pushl $224; TRAP(T_RESERVED)
 640 IDTVEC(rsvd225)
 641         pushl $225; TRAP(T_RESERVED)
 642 IDTVEC(rsvd226)
 643         pushl $226; TRAP(T_RESERVED)
 644 IDTVEC(rsvd227)
 645         pushl $227; TRAP(T_RESERVED)
 646 IDTVEC(rsvd228)
 647         pushl $228; TRAP(T_RESERVED)
 648 IDTVEC(rsvd229)
 649         pushl $229; TRAP(T_RESERVED)
 650 IDTVEC(rsvd230)
 651         pushl $230; TRAP(T_RESERVED)
 652 IDTVEC(rsvd231)
 653         pushl $231; TRAP(T_RESERVED)
 654 IDTVEC(rsvd232)
 655         pushl $232; TRAP(T_RESERVED)
 656 IDTVEC(rsvd233)
 657         pushl $233; TRAP(T_RESERVED)
 658 IDTVEC(rsvd234)
 659         pushl $234; TRAP(T_RESERVED)
 660 IDTVEC(rsvd235)
 661         pushl $235; TRAP(T_RESERVED)
 662 IDTVEC(rsvd236)
 663         pushl $236; TRAP(T_RESERVED)
 664 IDTVEC(rsvd237)
 665         pushl $237; TRAP(T_RESERVED)
 666 IDTVEC(rsvd238)
 667         pushl $238; TRAP(T_RESERVED)
 668 IDTVEC(rsvd239)
 669         pushl $239; TRAP(T_RESERVED)
 670 IDTVEC(rsvd240)
 671         pushl $240; TRAP(T_RESERVED)
 672 IDTVEC(rsvd241)
 673         pushl $241; TRAP(T_RESERVED)
 674 IDTVEC(rsvd242)
 675         pushl $242; TRAP(T_RESERVED)
 676 IDTVEC(rsvd243)
 677         pushl $243; TRAP(T_RESERVED)
 678 IDTVEC(rsvd244)
 679         pushl $244; TRAP(T_RESERVED)
 680 IDTVEC(rsvd245)
 681         pushl $245; TRAP(T_RESERVED)
 682 IDTVEC(rsvd246)
 683         pushl $246; TRAP(T_RESERVED)
 684 IDTVEC(rsvd247)
 685         pushl $247; TRAP(T_RESERVED)
 686 IDTVEC(rsvd248)
 687         pushl $248; TRAP(T_RESERVED)
 688 IDTVEC(rsvd249)
 689         pushl $249; TRAP(T_RESERVED)
 690 IDTVEC(rsvd250)
 691         pushl $250; TRAP(T_RESERVED)
 692 IDTVEC(rsvd251)
 693         pushl $251; TRAP(T_RESERVED)
 694 IDTVEC(rsvd252)
 695         pushl $252; TRAP(T_RESERVED)
 696 IDTVEC(rsvd253)
 697         pushl $253; TRAP(T_RESERVED)
 698 IDTVEC(rsvd254)
 699         pushl $254; TRAP(T_RESERVED)
 700 IDTVEC(rsvd255)
 701         pushl $255; TRAP(T_RESERVED)
 702
 703 #endif
 704
 705 IDTVEC(fpu)
 706 #if NNPX > 0
 707         /*
 708          * Handle like an interrupt (except for accounting) so that we can
 709          * call npx_intr to clear the error.  It would be better to handle
 710          * npx interrupts as traps.  Nested interrupts would probably have
 711          * to be converted to ASTs.
 712          */
 713         pushl   $0                      /* dummy error code */
 714         pushl   $0                      /* dummy trap type */
 715         pushal
 716         pushl   %ds
 717         pushl   %es                     /* now stack frame is a trap frame */
 718         pushl   %fs
 719         mov     $KDSEL,%ax
 720         mov     %ax,%ds
 721         mov     %ax,%es
 722         mov     $KPSEL,%ax
 723         mov     %ax,%fs
 724         FAKE_MCOUNT(13*4(%esp))
 725
 726         movl    PCPU(curthread),%ebx            /* save original cpl */
 727         movl    TD_CPL(%ebx), %ebx
 728         pushl   %ebx
 729         incl    PCPU(cnt)+V_TRAP
 730
 731         call    npx_intr                /* note: call might mess w/ argument */
 732
 733         movl    %ebx, (%esp)            /* save cpl for doreti */
 734         MEXITCOUNT
 735         jmp     doreti
 736 #else   /* NNPX > 0 */
 737         pushl $0; TRAP(T_ARITHTRAP)
 738 #endif  /* NNPX > 0 */
 739
 740 IDTVEC(align)
 741         TRAP(T_ALIGNFLT)
 742
 743 IDTVEC(xmm)
 744         pushl $0; TRAP(T_XMMFLT)
 745
 746         /*
 747          * _alltraps entry point.  Interrupts are enabled if this was a trap
 748          * gate (TGT), else disabled if this was an interrupt gate (IGT).
 749          * Note that int0x80_syscall is a trap gate.  Only page faults
 750          * use an interrupt gate.
 751          *
 752          * Note that we are MP through to the call to trap().
 753          */
 754
 755         SUPERALIGN_TEXT
 756         .globl  alltraps
 757         .type   alltraps,@function
 758 alltraps:
 759         pushal
 760         pushl   %ds
 761         pushl   %es
 762         pushl   %fs
 763 alltraps_with_regs_pushed:
 764         mov     $KDSEL,%ax
 765         mov     %ax,%ds
 766         mov     %ax,%es
 767         mov     $KPSEL,%ax
 768         mov     %ax,%fs
 769         FAKE_MCOUNT(13*4(%esp))
 770 calltrap:
 771         FAKE_MCOUNT(btrap)              /* init "from" _btrap -> calltrap */
 772         incl    PCPU(cnt)+V_TRAP
 773         movl    PCPU(curthread),%eax    /* keep orig cpl here during call */
 774         movl    TD_CPL(%eax),%ebx
 775         call    trap
 776
 777         /*
 778          * Return via doreti to handle ASTs.  Have to change trap frame
 779          * to interrupt frame.
 780          */
 781         pushl   %ebx                    /* cpl to restore */
 782         MEXITCOUNT
 783         jmp     doreti
 784
 785 /*
 786  * SYSCALL CALL GATE (old entry point for a.out binaries)
 787  *
 788  * The intersegment call has been set up to specify one dummy parameter.
 789  *
 790  * This leaves a place to put eflags so that the call frame can be
 791  * converted to a trap frame. Note that the eflags is (semi-)bogusly
 792  * pushed into (what will be) tf_err and then copied later into the
 793  * final spot. It has to be done this way because esp can't be just
 794  * temporarily altered for the pushfl - an interrupt might come in
 795  * and clobber the saved cs/eip.
 796  *
 797  * We do not obtain the MP lock, but the call to syscall2 might.  If it
 798  * does it will release the lock prior to returning.
 799  */
 800         SUPERALIGN_TEXT
 801 IDTVEC(syscall)
 802         pushfl                          /* save eflags in tf_err for now */
 803         subl    $4,%esp                 /* skip over tf_trapno */
 804         pushal
 805         pushl   %ds
 806         pushl   %es
 807         pushl   %fs
 808         mov     $KDSEL,%ax              /* switch to kernel segments */
 809         mov     %ax,%ds
 810         mov     %ax,%es
 811         mov     $KPSEL,%ax
 812         mov     %ax,%fs
 813         movl    TF_ERR(%esp),%eax       /* copy saved eflags to final spot */
 814         movl    %eax,TF_EFLAGS(%esp)
 815         movl    $7,TF_ERR(%esp)         /* sizeof "lcall 7,0" */
 816         FAKE_MCOUNT(13*4(%esp))
 817         incl    PCPU(cnt)+V_SYSCALL     /* YYY per-cpu */
 818         call    syscall2
 819         MEXITCOUNT
 820         cli                             /* atomic reqflags interlock w/iret */
 821         cmpl    $0,PCPU(reqflags)
 822         je      doreti_syscall_ret
 823         pushl   $0                      /* cpl to restore */
 824         jmp     doreti
 825
 826 /*
 827  * Trap gate entry for FreeBSD ELF and Linux/NetBSD syscall (int 0x80)
 828  *
 829  * Even though the name says 'int0x80', this is actually a TGT (trap gate)
 830  * rather then an IGT (interrupt gate).  Thus interrupts are enabled on
 831  * entry just as they are for a normal syscall.
 832  *
 833  * We do not obtain the MP lock, but the call to syscall2 might.  If it
 834  * does it will release the lock prior to returning.
 835  */
 836         SUPERALIGN_TEXT
 837 IDTVEC(int0x80_syscall)
 838         subl    $8,%esp                 /* skip over tf_trapno and tf_err */
 839         pushal
 840         pushl   %ds
 841         pushl   %es
 842         pushl   %fs
 843         mov     $KDSEL,%ax              /* switch to kernel segments */
 844         mov     %ax,%ds
 845         mov     %ax,%es
 846         mov     $KPSEL,%ax
 847         mov     %ax,%fs
 848         movl    $2,TF_ERR(%esp)         /* sizeof "int 0x80" */
 849         FAKE_MCOUNT(13*4(%esp))
 850         incl    PCPU(cnt)+V_SYSCALL
 851         call    syscall2
 852         MEXITCOUNT
 853         cli                             /* atomic reqflags interlock w/irq */
 854         cmpl    $0,PCPU(reqflags)
 855         je      doreti_syscall_ret
 856         pushl   $0                      /* cpl to restore */
 857         jmp     doreti
 858
 859 /*
 860  * Trap gate entry for FreeBSD syscall messaging interface (int 0x81).
 861  * Arguments are passed in registers, the return value is placed in %eax.
 862  *
 863  *      eax:error = int0x81(eax:port, ecx:msg, edx:msgsize)
 864  *
 865  *      Performs message sending, message and port waiting, and flushing
 866  *      functinos.
 867  */
 868         SUPERALIGN_TEXT
 869 IDTVEC(int0x81_syscall)
 870         subl    $8,%esp                 /* skip over tf_trapno and tf_err */
 871         pushal
 872         pushl   %ds
 873         pushl   %es
 874         pushl   %fs
 875         mov     $KDSEL,%ax              /* switch to kernel segments */
 876         mov     %ax,%ds
 877         mov     %ax,%es
 878         mov     $KPSEL,%ax
 879         mov     %ax,%fs
 880                                         /* note: tf_err is not used */
 881         FAKE_MCOUNT(13*4(%esp))
 882         incl    PCPU(cnt)+V_SENDSYS
 883         call    sendsys2
 884         MEXITCOUNT
 885         cli                             /* atomic reqflags interlock w/irq */
 886         cmpl    $0,PCPU(reqflags)
 887         je      doreti_syscall_ret
 888         pushl   $0                      /* cpl to restore */
 889         jmp     doreti
 890
 891 /*
 892  * This function is what cpu_heavy_restore jumps to after a new process
 893  * is created.  The LWKT subsystem switches while holding a critical
 894  * section and we maintain that abstraction here (e.g. because
 895  * cpu_heavy_restore needs it due to PCB_*() manipulation), then get out of
 896  * it before calling the initial function (typically fork_return()) and/or
 897  * returning to user mode.
 898  *
 899  * The MP lock is held on entry, but for processes fork_return(esi)
 900  * releases it.  'doreti' always runs without the MP lock.
 901  */
 902 ENTRY(fork_trampoline)
 903         movl    PCPU(curthread),%eax
 904         subl    $TDPRI_CRIT,TD_PRI(%eax)
 905
 906         /*
 907          * cpu_set_fork_handler intercepts this function call to
 908          * have this call a non-return function to stay in kernel mode.
 909          *
 910          * initproc has its own fork handler, start_init(), which DOES
 911          * return.
 912          */
 913         pushl   %ebx                    /* arg1 */
 914         call    *%esi                   /* function */
 915         addl    $4,%esp
 916         /* cut from syscall */
 917
 918         sti
 919         call    spl0
 920         call    splz
 921
 922 #if defined(INVARIANTS) && defined(SMP)
 923         movl    PCPU(curthread),%eax
 924         cmpl    $0,TD_MPCOUNT(%eax)
 925         je      1f
 926         pushl   %esi
 927         pushl   TD_MPCOUNT(%eax)
 928         pushl   $pmsg4
 929         call    panic
 930 pmsg4:  .asciz  "fork_trampoline mpcount %d after calling %p"
 931         .p2align 2
 932 1:
 933 #endif
 934         /*
 935          * Return via doreti to handle ASTs.
 936          */
 937         pushl   $0                      /* cpl to restore */
 938         MEXITCOUNT
 939         jmp     doreti
 940
 941
 942 /*
 943  * Include vm86 call routines, which want to call doreti.
 944  */
 945 #include "i386/i386/vm86bios.s"
 946
 947 /*
 948  * Include what was once config+isa-dependent code.
 949  * XXX it should be in a stand-alone file.  It's still icu-dependent and
 950  * belongs in i386/isa.
 951  */
 952 #include "i386/isa/vector.s"
 953
 954 /*
 955  * Include what was once icu-dependent code.
 956  * XXX it should be merged into this file (also move the definition of
 957  * imen to vector.s or isa.c).
 958  * Before including it, set up a normal asm environment so that vector.s
 959  * doesn't have to know that stuff is included after it.
 960  */
 961         .data
 962         ALIGN_DATA
 963         .text
 964         SUPERALIGN_TEXT
 965 #include "i386/isa/ipl.s"