sys/dev/netif/bnx/if_bnx.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 #include "opt_bnx.h"
  37 #include "opt_ifpoll.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/bus.h>
  41 #include <sys/endian.h>
  42 #include <sys/kernel.h>
  43 #include <sys/interrupt.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/malloc.h>
  46 #include <sys/queue.h>
  47 #include <sys/rman.h>
  48 #include <sys/serialize.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <netinet/ip.h>
  54 #include <netinet/tcp.h>
  55
  56 #include <net/bpf.h>
  57 #include <net/ethernet.h>
  58 #include <net/if.h>
  59 #include <net/if_arp.h>
  60 #include <net/if_dl.h>
  61 #include <net/if_media.h>
  62 #include <net/if_poll.h>
  63 #include <net/if_types.h>
  64 #include <net/ifq_var.h>
  65 #include <net/vlan/if_vlan_var.h>
  66 #include <net/vlan/if_vlan_ether.h>
  67
  68 #include <dev/netif/mii_layer/mii.h>
  69 #include <dev/netif/mii_layer/miivar.h>
  70 #include <dev/netif/mii_layer/brgphyreg.h>
  71
  72 #include <bus/pci/pcidevs.h>
  73 #include <bus/pci/pcireg.h>
  74 #include <bus/pci/pcivar.h>
  75
  76 #include <dev/netif/bge/if_bgereg.h>
  77 #include <dev/netif/bnx/if_bnxvar.h>
  78
  79 /* "device miibus" required.  See GENERIC if you get errors here. */
  80 #include "miibus_if.h"
  81
  82 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  83
  84 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
  85
  86 static const struct bnx_type {
  87         uint16_t                bnx_vid;
  88         uint16_t                bnx_did;
  89         char                    *bnx_name;
  90 } bnx_devs[] = {
  91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
  92                 "Broadcom BCM5717 Gigabit Ethernet" },
  93         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
  94                 "Broadcom BCM5718 Gigabit Ethernet" },
  95         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
  96                 "Broadcom BCM5719 Gigabit Ethernet" },
  97         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
  98                 "Broadcom BCM5720 Gigabit Ethernet" },
  99
 100         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
 101                 "Broadcom BCM57761 Gigabit Ethernet" },
 102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
 103                 "Broadcom BCM57762 Gigabit Ethernet" },
 104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
 105                 "Broadcom BCM57765 Gigabit Ethernet" },
 106         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
 107                 "Broadcom BCM57766 Gigabit Ethernet" },
 108         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
 109                 "Broadcom BCM57781 Gigabit Ethernet" },
 110         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
 111                 "Broadcom BCM57782 Gigabit Ethernet" },
 112         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
 113                 "Broadcom BCM57785 Gigabit Ethernet" },
 114         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
 115                 "Broadcom BCM57786 Gigabit Ethernet" },
 116         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
 117                 "Broadcom BCM57791 Fast Ethernet" },
 118         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
 119                 "Broadcom BCM57795 Fast Ethernet" },
 120
 121         { 0, 0, NULL }
 122 };
 123
 124 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
 125 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
 126 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
 127 #define BNX_IS_57765_FAMILY(sc)  \
 128         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
 129
 130 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
 131
 132 static int      bnx_probe(device_t);
 133 static int      bnx_attach(device_t);
 134 static int      bnx_detach(device_t);
 135 static void     bnx_shutdown(device_t);
 136 static int      bnx_suspend(device_t);
 137 static int      bnx_resume(device_t);
 138 static int      bnx_miibus_readreg(device_t, int, int);
 139 static int      bnx_miibus_writereg(device_t, int, int, int);
 140 static void     bnx_miibus_statchg(device_t);
 141
 142 #ifdef IFPOLL_ENABLE
 143 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
 144 static void     bnx_npoll_compat(struct ifnet *, void *, int);
 145 #endif
 146 static void     bnx_intr_legacy(void *);
 147 static void     bnx_msi(void *);
 148 static void     bnx_msi_oneshot(void *);
 149 static void     bnx_intr(struct bnx_softc *);
 150 static void     bnx_enable_intr(struct bnx_softc *);
 151 static void     bnx_disable_intr(struct bnx_softc *);
 152 static void     bnx_txeof(struct bnx_softc *, uint16_t);
 153 static void     bnx_rxeof(struct bnx_softc *, uint16_t, int);
 154
 155 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
 156 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 157 static void     bnx_init(void *);
 158 static void     bnx_stop(struct bnx_softc *);
 159 static void     bnx_watchdog(struct ifnet *);
 160 static int      bnx_ifmedia_upd(struct ifnet *);
 161 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 162 static void     bnx_tick(void *);
 163
 164 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
 165 static void     bnx_free_jumbo_mem(struct bnx_softc *);
 166 static struct bnx_jslot
 167                 *bnx_jalloc(struct bnx_softc *);
 168 static void     bnx_jfree(void *);
 169 static void     bnx_jref(void *);
 170 static int      bnx_newbuf_std(struct bnx_softc *, int, int);
 171 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
 172 static void     bnx_setup_rxdesc_std(struct bnx_softc *, int);
 173 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
 174 static int      bnx_init_rx_ring_std(struct bnx_softc *);
 175 static void     bnx_free_rx_ring_std(struct bnx_softc *);
 176 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
 177 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
 178 static void     bnx_free_tx_ring(struct bnx_softc *);
 179 static int      bnx_init_tx_ring(struct bnx_softc *);
 180 static int      bnx_dma_alloc(struct bnx_softc *);
 181 static void     bnx_dma_free(struct bnx_softc *);
 182 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
 183                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
 184 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 185 static struct mbuf *
 186                 bnx_defrag_shortdma(struct mbuf *);
 187 static int      bnx_encap(struct bnx_softc *, struct mbuf **,
 188                         uint32_t *, int *);
 189 static int      bnx_setup_tso(struct bnx_softc *, struct mbuf **,
 190                     uint16_t *, uint16_t *);
 191
 192 static void     bnx_reset(struct bnx_softc *);
 193 static int      bnx_chipinit(struct bnx_softc *);
 194 static int      bnx_blockinit(struct bnx_softc *);
 195 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
 196 static void     bnx_enable_msi(struct bnx_softc *sc);
 197 static void     bnx_setmulti(struct bnx_softc *);
 198 static void     bnx_setpromisc(struct bnx_softc *);
 199 static void     bnx_stats_update_regs(struct bnx_softc *);
 200 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
 201
 202 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
 203 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
 204 #ifdef notdef
 205 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
 206 #endif
 207 static void     bnx_writereg_ind(struct bnx_softc *, uint32_t, uint32_t);
 208 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
 209 static void     bnx_writembx(struct bnx_softc *, int, int);
 210 static uint8_t  bnx_nvram_getbyte(struct bnx_softc *, int, uint8_t *);
 211 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
 212 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
 213 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
 214
 215 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
 216 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
 217 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
 218 static void     bnx_link_poll(struct bnx_softc *);
 219
 220 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
 221 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
 222 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
 223 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
 224
 225 static void     bnx_coal_change(struct bnx_softc *);
 226 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 227 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 228 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 229 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 230 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 231 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 232 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 233                     int, int, uint32_t);
 234
 235 static int      bnx_msi_enable = 1;
 236 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
 237
 238 static device_method_t bnx_methods[] = {
 239         /* Device interface */
 240         DEVMETHOD(device_probe,         bnx_probe),
 241         DEVMETHOD(device_attach,        bnx_attach),
 242         DEVMETHOD(device_detach,        bnx_detach),
 243         DEVMETHOD(device_shutdown,      bnx_shutdown),
 244         DEVMETHOD(device_suspend,       bnx_suspend),
 245         DEVMETHOD(device_resume,        bnx_resume),
 246
 247         /* bus interface */
 248         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 249         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 250
 251         /* MII interface */
 252         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
 253         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
 254         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
 255
 256         { 0, 0 }
 257 };
 258
 259 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
 260 static devclass_t bnx_devclass;
 261
 262 DECLARE_DUMMY_MODULE(if_bnx);
 263 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
 264 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
 265
 266 static uint32_t
 267 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
 268 {
 269         device_t dev = sc->bnx_dev;
 270         uint32_t val;
 271
 272         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 273             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 274                 return 0;
 275
 276         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 277         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 278         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 279         return (val);
 280 }
 281
 282 static void
 283 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 284 {
 285         device_t dev = sc->bnx_dev;
 286
 287         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 288             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 289                 return;
 290
 291         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 292         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 293         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 294 }
 295
 296 #ifdef notdef
 297 static uint32_t
 298 bnx_readreg_ind(struct bnx_softc *sc, uin32_t off)
 299 {
 300         device_t dev = sc->bnx_dev;
 301
 302         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 303         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 304 }
 305 #endif
 306
 307 static void
 308 bnx_writereg_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 309 {
 310         device_t dev = sc->bnx_dev;
 311
 312         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 313         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 314 }
 315
 316 static void
 317 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
 318 {
 319         CSR_WRITE_4(sc, off, val);
 320 }
 321
 322 static void
 323 bnx_writembx(struct bnx_softc *sc, int off, int val)
 324 {
 325         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906)
 326                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 327
 328         CSR_WRITE_4(sc, off, val);
 329 }
 330
 331 static uint8_t
 332 bnx_nvram_getbyte(struct bnx_softc *sc, int addr, uint8_t *dest)
 333 {
 334         uint32_t access, byte = 0;
 335         int i;
 336
 337         /* Lock. */
 338         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 339         for (i = 0; i < 8000; i++) {
 340                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 341                         break;
 342                 DELAY(20);
 343         }
 344         if (i == 8000)
 345                 return (1);
 346
 347         /* Enable access. */
 348         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 349         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 350
 351         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 352         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 353         for (i = 0; i < BNX_TIMEOUT * 10; i++) {
 354                 DELAY(10);
 355                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 356                         DELAY(10);
 357                         break;
 358                 }
 359         }
 360
 361         if (i == BNX_TIMEOUT * 10) {
 362                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 363                 return (1);
 364         }
 365
 366         /* Get result. */
 367         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 368
 369         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 370
 371         /* Disable access. */
 372         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 373
 374         /* Unlock. */
 375         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 376         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 377
 378         return (0);
 379 }
 380
 381 /*
 382  * Read a sequence of bytes from NVRAM.
 383  */
 384 static int
 385 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
 386 {
 387         int err = 0, i;
 388         uint8_t byte = 0;
 389
 390         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 391                 return (1);
 392
 393         for (i = 0; i < cnt; i++) {
 394                 err = bnx_nvram_getbyte(sc, off + i, &byte);
 395                 if (err)
 396                         break;
 397                 *(dest + i) = byte;
 398         }
 399
 400         return (err ? 1 : 0);
 401 }
 402
 403 /*
 404  * Read a byte of data stored in the EEPROM at address 'addr.' The
 405  * BCM570x supports both the traditional bitbang interface and an
 406  * auto access interface for reading the EEPROM. We use the auto
 407  * access method.
 408  */
 409 static uint8_t
 410 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
 411 {
 412         int i;
 413         uint32_t byte = 0;
 414
 415         /*
 416          * Enable use of auto EEPROM access so we can avoid
 417          * having to use the bitbang method.
 418          */
 419         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 420
 421         /* Reset the EEPROM, load the clock period. */
 422         CSR_WRITE_4(sc, BGE_EE_ADDR,
 423             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 424         DELAY(20);
 425
 426         /* Issue the read EEPROM command. */
 427         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 428
 429         /* Wait for completion */
 430         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
 431                 DELAY(10);
 432                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 433                         break;
 434         }
 435
 436         if (i == BNX_TIMEOUT) {
 437                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 438                 return(1);
 439         }
 440
 441         /* Get result. */
 442         byte = CSR_READ_4(sc, BGE_EE_DATA);
 443
 444         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 445
 446         return(0);
 447 }
 448
 449 /*
 450  * Read a sequence of bytes from the EEPROM.
 451  */
 452 static int
 453 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
 454 {
 455         size_t i;
 456         int err;
 457         uint8_t byte;
 458
 459         for (byte = 0, err = 0, i = 0; i < len; i++) {
 460                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
 461                 if (err)
 462                         break;
 463                 *(dest + i) = byte;
 464         }
 465
 466         return(err ? 1 : 0);
 467 }
 468
 469 static int
 470 bnx_miibus_readreg(device_t dev, int phy, int reg)
 471 {
 472         struct bnx_softc *sc = device_get_softc(dev);
 473         uint32_t val;
 474         int i;
 475
 476         KASSERT(phy == sc->bnx_phyno,
 477             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 478
 479         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 480         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 481                 CSR_WRITE_4(sc, BGE_MI_MODE,
 482                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 483                 DELAY(80);
 484         }
 485
 486         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 487             BGE_MIPHY(phy) | BGE_MIREG(reg));
 488
 489         /* Poll for the PHY register access to complete. */
 490         for (i = 0; i < BNX_TIMEOUT; i++) {
 491                 DELAY(10);
 492                 val = CSR_READ_4(sc, BGE_MI_COMM);
 493                 if ((val & BGE_MICOMM_BUSY) == 0) {
 494                         DELAY(5);
 495                         val = CSR_READ_4(sc, BGE_MI_COMM);
 496                         break;
 497                 }
 498         }
 499         if (i == BNX_TIMEOUT) {
 500                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 501                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 502                 val = 0;
 503         }
 504
 505         /* Restore the autopoll bit if necessary. */
 506         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 507                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 508                 DELAY(80);
 509         }
 510
 511         if (val & BGE_MICOMM_READFAIL)
 512                 return 0;
 513
 514         return (val & 0xFFFF);
 515 }
 516
 517 static int
 518 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
 519 {
 520         struct bnx_softc *sc = device_get_softc(dev);
 521         int i;
 522
 523         KASSERT(phy == sc->bnx_phyno,
 524             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 525
 526         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 527             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 528                return 0;
 529
 530         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 531         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 532                 CSR_WRITE_4(sc, BGE_MI_MODE,
 533                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 534                 DELAY(80);
 535         }
 536
 537         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 538             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 539
 540         for (i = 0; i < BNX_TIMEOUT; i++) {
 541                 DELAY(10);
 542                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 543                         DELAY(5);
 544                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 545                         break;
 546                 }
 547         }
 548         if (i == BNX_TIMEOUT) {
 549                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 550                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 551         }
 552
 553         /* Restore the autopoll bit if necessary. */
 554         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 555                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 556                 DELAY(80);
 557         }
 558
 559         return 0;
 560 }
 561
 562 static void
 563 bnx_miibus_statchg(device_t dev)
 564 {
 565         struct bnx_softc *sc;
 566         struct mii_data *mii;
 567
 568         sc = device_get_softc(dev);
 569         mii = device_get_softc(sc->bnx_miibus);
 570
 571         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 572             (IFM_ACTIVE | IFM_AVALID)) {
 573                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 574                 case IFM_10_T:
 575                 case IFM_100_TX:
 576                         sc->bnx_link = 1;
 577                         break;
 578                 case IFM_1000_T:
 579                 case IFM_1000_SX:
 580                 case IFM_2500_SX:
 581                         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 582                                 sc->bnx_link = 1;
 583                         else
 584                                 sc->bnx_link = 0;
 585                         break;
 586                 default:
 587                         sc->bnx_link = 0;
 588                         break;
 589                 }
 590         } else {
 591                 sc->bnx_link = 0;
 592         }
 593         if (sc->bnx_link == 0)
 594                 return;
 595
 596         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 597         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 598             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 599                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 600         } else {
 601                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 602         }
 603
 604         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 605                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 606         } else {
 607                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 608         }
 609 }
 610
 611 /*
 612  * Memory management for jumbo frames.
 613  */
 614 static int
 615 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
 616 {
 617         struct ifnet *ifp = &sc->arpcom.ac_if;
 618         struct bnx_jslot *entry;
 619         uint8_t *ptr;
 620         bus_addr_t paddr;
 621         int i, error;
 622
 623         /*
 624          * Create tag for jumbo mbufs.
 625          * This is really a bit of a kludge. We allocate a special
 626          * jumbo buffer pool which (thanks to the way our DMA
 627          * memory allocation works) will consist of contiguous
 628          * pages. This means that even though a jumbo buffer might
 629          * be larger than a page size, we don't really need to
 630          * map it into more than one DMA segment. However, the
 631          * default mbuf tag will result in multi-segment mappings,
 632          * so we have to create a special jumbo mbuf tag that
 633          * lets us get away with mapping the jumbo buffers as
 634          * a single segment. I think eventually the driver should
 635          * be changed so that it uses ordinary mbufs and cluster
 636          * buffers, i.e. jumbo frames can span multiple DMA
 637          * descriptors. But that's a project for another day.
 638          */
 639
 640         /*
 641          * Create DMA stuffs for jumbo RX ring.
 642          */
 643         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 644                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 645                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 646                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
 647                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
 648         if (error) {
 649                 if_printf(ifp, "could not create jumbo RX ring\n");
 650                 return error;
 651         }
 652
 653         /*
 654          * Create DMA stuffs for jumbo buffer block.
 655          */
 656         error = bnx_dma_block_alloc(sc, BNX_JMEM,
 657                                     &sc->bnx_cdata.bnx_jumbo_tag,
 658                                     &sc->bnx_cdata.bnx_jumbo_map,
 659                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
 660                                     &paddr);
 661         if (error) {
 662                 if_printf(ifp, "could not create jumbo buffer\n");
 663                 return error;
 664         }
 665
 666         SLIST_INIT(&sc->bnx_jfree_listhead);
 667
 668         /*
 669          * Now divide it up into 9K pieces and save the addresses
 670          * in an array. Note that we play an evil trick here by using
 671          * the first few bytes in the buffer to hold the the address
 672          * of the softc structure for this interface. This is because
 673          * bnx_jfree() needs it, but it is called by the mbuf management
 674          * code which will not pass it to us explicitly.
 675          */
 676         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
 677                 entry = &sc->bnx_cdata.bnx_jslots[i];
 678                 entry->bnx_sc = sc;
 679                 entry->bnx_buf = ptr;
 680                 entry->bnx_paddr = paddr;
 681                 entry->bnx_inuse = 0;
 682                 entry->bnx_slot = i;
 683                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
 684
 685                 ptr += BNX_JLEN;
 686                 paddr += BNX_JLEN;
 687         }
 688         return 0;
 689 }
 690
 691 static void
 692 bnx_free_jumbo_mem(struct bnx_softc *sc)
 693 {
 694         /* Destroy jumbo RX ring. */
 695         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 696                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 697                            sc->bnx_ldata.bnx_rx_jumbo_ring);
 698
 699         /* Destroy jumbo buffer block. */
 700         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
 701                            sc->bnx_cdata.bnx_jumbo_map,
 702                            sc->bnx_ldata.bnx_jumbo_buf);
 703 }
 704
 705 /*
 706  * Allocate a jumbo buffer.
 707  */
 708 static struct bnx_jslot *
 709 bnx_jalloc(struct bnx_softc *sc)
 710 {
 711         struct bnx_jslot *entry;
 712
 713         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 714         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
 715         if (entry) {
 716                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
 717                 entry->bnx_inuse = 1;
 718         } else {
 719                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 720         }
 721         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 722         return(entry);
 723 }
 724
 725 /*
 726  * Adjust usage count on a jumbo buffer.
 727  */
 728 static void
 729 bnx_jref(void *arg)
 730 {
 731         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 732         struct bnx_softc *sc = entry->bnx_sc;
 733
 734         if (sc == NULL)
 735                 panic("bnx_jref: can't find softc pointer!");
 736
 737         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 738                 panic("bnx_jref: asked to reference buffer "
 739                     "that we don't manage!");
 740         } else if (entry->bnx_inuse == 0) {
 741                 panic("bnx_jref: buffer already free!");
 742         } else {
 743                 atomic_add_int(&entry->bnx_inuse, 1);
 744         }
 745 }
 746
 747 /*
 748  * Release a jumbo buffer.
 749  */
 750 static void
 751 bnx_jfree(void *arg)
 752 {
 753         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 754         struct bnx_softc *sc = entry->bnx_sc;
 755
 756         if (sc == NULL)
 757                 panic("bnx_jfree: can't find softc pointer!");
 758
 759         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 760                 panic("bnx_jfree: asked to free buffer that we don't manage!");
 761         } else if (entry->bnx_inuse == 0) {
 762                 panic("bnx_jfree: buffer already free!");
 763         } else {
 764                 /*
 765                  * Possible MP race to 0, use the serializer.  The atomic insn
 766                  * is still needed for races against bnx_jref().
 767                  */
 768                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 769                 atomic_subtract_int(&entry->bnx_inuse, 1);
 770                 if (entry->bnx_inuse == 0) {
 771                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
 772                                           entry, jslot_link);
 773                 }
 774                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 775         }
 776 }
 777
 778
 779 /*
 780  * Intialize a standard receive ring descriptor.
 781  */
 782 static int
 783 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
 784 {
 785         struct mbuf *m_new = NULL;
 786         bus_dma_segment_t seg;
 787         bus_dmamap_t map;
 788         int error, nsegs;
 789
 790         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 791         if (m_new == NULL)
 792                 return ENOBUFS;
 793         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 794         m_adj(m_new, ETHER_ALIGN);
 795
 796         error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
 797                         sc->bnx_cdata.bnx_rx_tmpmap, m_new,
 798                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 799         if (error) {
 800                 m_freem(m_new);
 801                 return error;
 802         }
 803
 804         if (!init) {
 805                 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
 806                                 sc->bnx_cdata.bnx_rx_std_dmamap[i],
 807                                 BUS_DMASYNC_POSTREAD);
 808                 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 809                         sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 810         }
 811
 812         map = sc->bnx_cdata.bnx_rx_tmpmap;
 813         sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
 814         sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
 815
 816         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
 817         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
 818
 819         bnx_setup_rxdesc_std(sc, i);
 820         return 0;
 821 }
 822
 823 static void
 824 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
 825 {
 826         struct bnx_rxchain *rc;
 827         struct bge_rx_bd *r;
 828
 829         rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 830         r = &sc->bnx_ldata.bnx_rx_std_ring[i];
 831
 832         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 833         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 834         r->bge_len = rc->bnx_mbuf->m_len;
 835         r->bge_idx = i;
 836         r->bge_flags = BGE_RXBDFLAG_END;
 837 }
 838
 839 /*
 840  * Initialize a jumbo receive ring descriptor. This allocates
 841  * a jumbo buffer from the pool managed internally by the driver.
 842  */
 843 static int
 844 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
 845 {
 846         struct mbuf *m_new = NULL;
 847         struct bnx_jslot *buf;
 848         bus_addr_t paddr;
 849
 850         /* Allocate the mbuf. */
 851         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 852         if (m_new == NULL)
 853                 return ENOBUFS;
 854
 855         /* Allocate the jumbo buffer */
 856         buf = bnx_jalloc(sc);
 857         if (buf == NULL) {
 858                 m_freem(m_new);
 859                 return ENOBUFS;
 860         }
 861
 862         /* Attach the buffer to the mbuf. */
 863         m_new->m_ext.ext_arg = buf;
 864         m_new->m_ext.ext_buf = buf->bnx_buf;
 865         m_new->m_ext.ext_free = bnx_jfree;
 866         m_new->m_ext.ext_ref = bnx_jref;
 867         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
 868
 869         m_new->m_flags |= M_EXT;
 870
 871         m_new->m_data = m_new->m_ext.ext_buf;
 872         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 873
 874         paddr = buf->bnx_paddr;
 875         m_adj(m_new, ETHER_ALIGN);
 876         paddr += ETHER_ALIGN;
 877
 878         /* Save necessary information */
 879         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
 880         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
 881
 882         /* Set up the descriptor. */
 883         bnx_setup_rxdesc_jumbo(sc, i);
 884         return 0;
 885 }
 886
 887 static void
 888 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
 889 {
 890         struct bge_rx_bd *r;
 891         struct bnx_rxchain *rc;
 892
 893         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
 894         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 895
 896         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 897         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 898         r->bge_len = rc->bnx_mbuf->m_len;
 899         r->bge_idx = i;
 900         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 901 }
 902
 903 static int
 904 bnx_init_rx_ring_std(struct bnx_softc *sc)
 905 {
 906         int i, error;
 907
 908         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 909                 error = bnx_newbuf_std(sc, i, 1);
 910                 if (error)
 911                         return error;
 912         }
 913
 914         sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
 915         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
 916
 917         return(0);
 918 }
 919
 920 static void
 921 bnx_free_rx_ring_std(struct bnx_softc *sc)
 922 {
 923         int i;
 924
 925         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 926                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 927
 928                 if (rc->bnx_mbuf != NULL) {
 929                         bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 930                                           sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 931                         m_freem(rc->bnx_mbuf);
 932                         rc->bnx_mbuf = NULL;
 933                 }
 934                 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
 935                     sizeof(struct bge_rx_bd));
 936         }
 937 }
 938
 939 static int
 940 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
 941 {
 942         struct bge_rcb *rcb;
 943         int i, error;
 944
 945         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 946                 error = bnx_newbuf_jumbo(sc, i, 1);
 947                 if (error)
 948                         return error;
 949         }
 950
 951         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 952
 953         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
 954         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 955         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 956
 957         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
 958
 959         return(0);
 960 }
 961
 962 static void
 963 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
 964 {
 965         int i;
 966
 967         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 968                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 969
 970                 if (rc->bnx_mbuf != NULL) {
 971                         m_freem(rc->bnx_mbuf);
 972                         rc->bnx_mbuf = NULL;
 973                 }
 974                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
 975                     sizeof(struct bge_rx_bd));
 976         }
 977 }
 978
 979 static void
 980 bnx_free_tx_ring(struct bnx_softc *sc)
 981 {
 982         int i;
 983
 984         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 985                 if (sc->bnx_cdata.bnx_tx_chain[i] != NULL) {
 986                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
 987                                           sc->bnx_cdata.bnx_tx_dmamap[i]);
 988                         m_freem(sc->bnx_cdata.bnx_tx_chain[i]);
 989                         sc->bnx_cdata.bnx_tx_chain[i] = NULL;
 990                 }
 991                 bzero(&sc->bnx_ldata.bnx_tx_ring[i],
 992                     sizeof(struct bge_tx_bd));
 993         }
 994 }
 995
 996 static int
 997 bnx_init_tx_ring(struct bnx_softc *sc)
 998 {
 999         sc->bnx_txcnt = 0;
1000         sc->bnx_tx_saved_considx = 0;
1001         sc->bnx_tx_prodidx = 0;
1002
1003         /* Initialize transmit producer index for host-memory send ring. */
1004         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bnx_tx_prodidx);
1005         bnx_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1006
1007         return(0);
1008 }
1009
1010 static void
1011 bnx_setmulti(struct bnx_softc *sc)
1012 {
1013         struct ifnet *ifp;
1014         struct ifmultiaddr *ifma;
1015         uint32_t hashes[4] = { 0, 0, 0, 0 };
1016         int h, i;
1017
1018         ifp = &sc->arpcom.ac_if;
1019
1020         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1021                 for (i = 0; i < 4; i++)
1022                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1023                 return;
1024         }
1025
1026         /* First, zot all the existing filters. */
1027         for (i = 0; i < 4; i++)
1028                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1029
1030         /* Now program new ones. */
1031         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1032                 if (ifma->ifma_addr->sa_family != AF_LINK)
1033                         continue;
1034                 h = ether_crc32_le(
1035                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1036                     ETHER_ADDR_LEN) & 0x7f;
1037                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1038         }
1039
1040         for (i = 0; i < 4; i++)
1041                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1042 }
1043
1044 /*
1045  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1046  * self-test results.
1047  */
1048 static int
1049 bnx_chipinit(struct bnx_softc *sc)
1050 {
1051         uint32_t dma_rw_ctl, mode_ctl;
1052         int i;
1053
1054         /* Set endian type before we access any non-PCI registers. */
1055         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1056             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1057
1058         /* Clear the MAC control register */
1059         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1060
1061         /*
1062          * Clear the MAC statistics block in the NIC's
1063          * internal memory.
1064          */
1065         for (i = BGE_STATS_BLOCK;
1066             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1067                 BNX_MEMWIN_WRITE(sc, i, 0);
1068
1069         for (i = BGE_STATUS_BLOCK;
1070             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1071                 BNX_MEMWIN_WRITE(sc, i, 0);
1072
1073         if (BNX_IS_57765_FAMILY(sc)) {
1074                 uint32_t val;
1075
1076                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1077                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1078                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1079
1080                         /* Access the lower 1K of PL PCI-E block registers. */
1081                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1082                             val | BGE_MODECTL_PCIE_PL_SEL);
1083
1084                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1085                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1086                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1087
1088                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1089                 }
1090                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1091                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1092                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1093
1094                         /* Access the lower 1K of DL PCI-E block registers. */
1095                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1096                             val | BGE_MODECTL_PCIE_DL_SEL);
1097
1098                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1099                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1100                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1101                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1102
1103                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1104                 }
1105
1106                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1107                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1108                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1109                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1110         }
1111
1112         /*
1113          * Set up the PCI DMA control register.
1114          */
1115         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1116         /*
1117          * Disable 32bytes cache alignment for DMA write to host memory
1118          *
1119          * NOTE:
1120          * 64bytes cache alignment for DMA write to host memory is still
1121          * enabled.
1122          */
1123         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1124         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1125                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1126         /*
1127          * Enable HW workaround for controllers that misinterpret
1128          * a status tag update and leave interrupts permanently
1129          * disabled.
1130          */
1131         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1132             !BNX_IS_57765_FAMILY(sc))
1133                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1134         if (bootverbose) {
1135                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1136                     dma_rw_ctl);
1137         }
1138         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1139
1140         /*
1141          * Set up general mode register.
1142          */
1143         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1144             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1145         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1146
1147         /*
1148          * Disable memory write invalidate.  Apparently it is not supported
1149          * properly by these devices.  Also ensure that INTx isn't disabled,
1150          * as these chips need it even when using MSI.
1151          */
1152         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1153             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1154
1155         /* Set the timer prescaler (always 66Mhz) */
1156         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1157
1158         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1159                 DELAY(40);      /* XXX */
1160
1161                 /* Put PHY into ready state */
1162                 BNX_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1163                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1164                 DELAY(40);
1165         }
1166
1167         return(0);
1168 }
1169
1170 static int
1171 bnx_blockinit(struct bnx_softc *sc)
1172 {
1173         struct bge_rcb *rcb;
1174         bus_size_t vrcb;
1175         bge_hostaddr taddr;
1176         uint32_t val;
1177         int i, limit;
1178
1179         /*
1180          * Initialize the memory window pointer register so that
1181          * we can access the first 32K of internal NIC RAM. This will
1182          * allow us to set up the TX send ring RCBs and the RX return
1183          * ring RCBs, plus other things which live in NIC memory.
1184          */
1185         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1186
1187         /* Configure mbuf pool watermarks */
1188         if (BNX_IS_57765_PLUS(sc)) {
1189                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1190                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1191                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1192                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1193                 } else {
1194                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1195                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1196                 }
1197         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1198                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1199                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1200                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1201         } else {
1202                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1203                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1204                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1205         }
1206
1207         /* Configure DMA resource watermarks */
1208         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1209         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1210
1211         /* Enable buffer manager */
1212         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1213         /*
1214          * Change the arbitration algorithm of TXMBUF read request to
1215          * round-robin instead of priority based for BCM5719.  When
1216          * TXFIFO is almost empty, RDMA will hold its request until
1217          * TXFIFO is not almost empty.
1218          */
1219         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1220                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1221         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1222             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1223             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1224                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1225         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1226
1227         /* Poll for buffer manager start indication */
1228         for (i = 0; i < BNX_TIMEOUT; i++) {
1229                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1230                         break;
1231                 DELAY(10);
1232         }
1233
1234         if (i == BNX_TIMEOUT) {
1235                 if_printf(&sc->arpcom.ac_if,
1236                           "buffer manager failed to start\n");
1237                 return(ENXIO);
1238         }
1239
1240         /* Enable flow-through queues */
1241         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1242         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1243
1244         /* Wait until queue initialization is complete */
1245         for (i = 0; i < BNX_TIMEOUT; i++) {
1246                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1247                         break;
1248                 DELAY(10);
1249         }
1250
1251         if (i == BNX_TIMEOUT) {
1252                 if_printf(&sc->arpcom.ac_if,
1253                           "flow-through queue init failed\n");
1254                 return(ENXIO);
1255         }
1256
1257         /*
1258          * Summary of rings supported by the controller:
1259          *
1260          * Standard Receive Producer Ring
1261          * - This ring is used to feed receive buffers for "standard"
1262          *   sized frames (typically 1536 bytes) to the controller.
1263          *
1264          * Jumbo Receive Producer Ring
1265          * - This ring is used to feed receive buffers for jumbo sized
1266          *   frames (i.e. anything bigger than the "standard" frames)
1267          *   to the controller.
1268          *
1269          * Mini Receive Producer Ring
1270          * - This ring is used to feed receive buffers for "mini"
1271          *   sized frames to the controller.
1272          * - This feature required external memory for the controller
1273          *   but was never used in a production system.  Should always
1274          *   be disabled.
1275          *
1276          * Receive Return Ring
1277          * - After the controller has placed an incoming frame into a
1278          *   receive buffer that buffer is moved into a receive return
1279          *   ring.  The driver is then responsible to passing the
1280          *   buffer up to the stack.  Many versions of the controller
1281          *   support multiple RR rings.
1282          *
1283          * Send Ring
1284          * - This ring is used for outgoing frames.  Many versions of
1285          *   the controller support multiple send rings.
1286          */
1287
1288         /* Initialize the standard receive producer ring control block. */
1289         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1290         rcb->bge_hostaddr.bge_addr_lo =
1291             BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1292         rcb->bge_hostaddr.bge_addr_hi =
1293             BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1294         if (BNX_IS_57765_PLUS(sc)) {
1295                 /*
1296                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1297                  * Bits 15-2 : Maximum RX frame size
1298                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1299                  * Bit 0     : Reserved
1300                  */
1301                 rcb->bge_maxlen_flags =
1302                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1303         } else {
1304                 /*
1305                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1306                  * Bits 15-2 : Reserved (should be 0)
1307                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1308                  * Bit 0     : Reserved
1309                  */
1310                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1311         }
1312         if (BNX_IS_5717_PLUS(sc))
1313                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1314         else
1315                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1316         /* Write the standard receive producer ring control block. */
1317         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1318         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1319         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1320         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1321         /* Reset the standard receive producer ring producer index. */
1322         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1323
1324         /*
1325          * Initialize the jumbo RX producer ring control
1326          * block.  We set the 'ring disabled' bit in the
1327          * flags field until we're actually ready to start
1328          * using this ring (i.e. once we set the MTU
1329          * high enough to require it).
1330          */
1331         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1332                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1333                 /* Get the jumbo receive producer ring RCB parameters. */
1334                 rcb->bge_hostaddr.bge_addr_lo =
1335                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1336                 rcb->bge_hostaddr.bge_addr_hi =
1337                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1338                 rcb->bge_maxlen_flags =
1339                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1340                     BGE_RCB_FLAG_RING_DISABLED);
1341                 if (BNX_IS_5717_PLUS(sc))
1342                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1343                 else
1344                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1345                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1346                     rcb->bge_hostaddr.bge_addr_hi);
1347                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1348                     rcb->bge_hostaddr.bge_addr_lo);
1349                 /* Program the jumbo receive producer ring RCB parameters. */
1350                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1351                     rcb->bge_maxlen_flags);
1352                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1353                 /* Reset the jumbo receive producer ring producer index. */
1354                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1355         }
1356
1357         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1358         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
1359             (sc->bnx_chipid == BGE_CHIPID_BCM5906_A0 ||
1360              sc->bnx_chipid == BGE_CHIPID_BCM5906_A1 ||
1361              sc->bnx_chipid == BGE_CHIPID_BCM5906_A2)) {
1362                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1363                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1364         }
1365
1366         /*
1367          * The BD ring replenish thresholds control how often the
1368          * hardware fetches new BD's from the producer rings in host
1369          * memory.  Setting the value too low on a busy system can
1370          * starve the hardware and recue the throughpout.
1371          *
1372          * Set the BD ring replentish thresholds. The recommended
1373          * values are 1/8th the number of descriptors allocated to
1374          * each ring.
1375          */
1376         val = 8;
1377         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1378         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1379                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1380                     BGE_JUMBO_RX_RING_CNT/8);
1381         }
1382         if (BNX_IS_57765_PLUS(sc)) {
1383                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1384                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1385         }
1386
1387         /*
1388          * Disable all send rings by setting the 'ring disabled' bit
1389          * in the flags field of all the TX send ring control blocks,
1390          * located in NIC memory.
1391          */
1392         if (BNX_IS_5717_PLUS(sc))
1393                 limit = 4;
1394         else if (BNX_IS_57765_FAMILY(sc))
1395                 limit = 2;
1396         else
1397                 limit = 1;
1398         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1399         for (i = 0; i < limit; i++) {
1400                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1401                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1402                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1403                 vrcb += sizeof(struct bge_rcb);
1404         }
1405
1406         /* Configure send ring RCB 0 (we use only the first ring) */
1407         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1408         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_tx_ring_paddr);
1409         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1410         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1411         if (BNX_IS_5717_PLUS(sc)) {
1412                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1413         } else {
1414                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1415                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1416         }
1417         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1418             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1419
1420         /*
1421          * Disable all receive return rings by setting the
1422          * 'ring disabled' bit in the flags field of all the receive
1423          * return ring control blocks, located in NIC memory.
1424          */
1425         if (BNX_IS_5717_PLUS(sc)) {
1426                 /* Should be 17, use 16 until we get an SRAM map. */
1427                 limit = 16;
1428         } else if (BNX_IS_57765_FAMILY(sc)) {
1429                 limit = 4;
1430         } else {
1431                 limit = 1;
1432         }
1433         /* Disable all receive return rings. */
1434         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1435         for (i = 0; i < limit; i++) {
1436                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1437                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1438                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1439                     BGE_RCB_FLAG_RING_DISABLED);
1440                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1441                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1442                     (i * (sizeof(uint64_t))), 0);
1443                 vrcb += sizeof(struct bge_rcb);
1444         }
1445
1446         /*
1447          * Set up receive return ring 0.  Note that the NIC address
1448          * for RX return rings is 0x0.  The return rings live entirely
1449          * within the host, so the nicaddr field in the RCB isn't used.
1450          */
1451         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1452         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1453         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1454         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1455         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1456         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1457             BGE_RCB_MAXLEN_FLAGS(sc->bnx_return_ring_cnt, 0));
1458
1459         /* Set random backoff seed for TX */
1460         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1461             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1462             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1463             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1464             BGE_TX_BACKOFF_SEED_MASK);
1465
1466         /* Set inter-packet gap */
1467         val = 0x2620;
1468         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1469                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1470                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1471         }
1472         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1473
1474         /*
1475          * Specify which ring to use for packets that don't match
1476          * any RX rules.
1477          */
1478         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1479
1480         /*
1481          * Configure number of RX lists. One interrupt distribution
1482          * list, sixteen active lists, one bad frames class.
1483          */
1484         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1485
1486         /* Inialize RX list placement stats mask. */
1487         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1488         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1489
1490         /* Disable host coalescing until we get it set up */
1491         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1492
1493         /* Poll to make sure it's shut down. */
1494         for (i = 0; i < BNX_TIMEOUT; i++) {
1495                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1496                         break;
1497                 DELAY(10);
1498         }
1499
1500         if (i == BNX_TIMEOUT) {
1501                 if_printf(&sc->arpcom.ac_if,
1502                           "host coalescing engine failed to idle\n");
1503                 return(ENXIO);
1504         }
1505
1506         /* Set up host coalescing defaults */
1507         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1508         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1509         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1510         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1511         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1512         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1513
1514         /* Set up address of status block */
1515         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1516         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1517             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1518         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1519             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1520
1521         /* Set up status block partail update size. */
1522         val = BGE_STATBLKSZ_32BYTE;
1523 #if 0
1524         /*
1525          * Does not seem to have visible effect in both
1526          * bulk data (1472B UDP datagram) and tiny data
1527          * (18B UDP datagram) TX tests.
1528          */
1529         val |= BGE_HCCMODE_CLRTICK_TX;
1530 #endif
1531         /* Turn on host coalescing state machine */
1532         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1533
1534         /* Turn on RX BD completion state machine and enable attentions */
1535         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1536             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1537
1538         /* Turn on RX list placement state machine */
1539         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1540
1541         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1542             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1543             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1544             BGE_MACMODE_FRMHDR_DMA_ENB;
1545
1546         if (sc->bnx_flags & BNX_FLAG_TBI)
1547                 val |= BGE_PORTMODE_TBI;
1548         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1549                 val |= BGE_PORTMODE_GMII;
1550         else
1551                 val |= BGE_PORTMODE_MII;
1552
1553         /* Turn on DMA, clear stats */
1554         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1555
1556         /* Set misc. local control, enable interrupts on attentions */
1557         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1558
1559 #ifdef notdef
1560         /* Assert GPIO pins for PHY reset */
1561         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1562             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1563         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1564             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1565 #endif
1566
1567         /* Turn on write DMA state machine */
1568         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1569         /* Enable host coalescing bug fix. */
1570         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1571         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1572                 /* Request larger DMA burst size to get better performance. */
1573                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1574         }
1575         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1576         DELAY(40);
1577
1578         if (BNX_IS_57765_PLUS(sc)) {
1579                 uint32_t dmactl;
1580
1581                 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1582                 /*
1583                  * Adjust tx margin to prevent TX data corruption and
1584                  * fix internal FIFO overflow.
1585                  */
1586                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1587                     sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1588                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1589                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1590                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1591                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1592                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1593                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1594                 }
1595                 /*
1596                  * Enable fix for read DMA FIFO overruns.
1597                  * The fix is to limit the number of RX BDs
1598                  * the hardware would fetch at a fime.
1599                  */
1600                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1601                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1602         }
1603
1604         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1605                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1606                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1607                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1608                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1609         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1610                 /*
1611                  * Allow 4KB burst length reads for non-LSO frames.
1612                  * Enable 512B burst length reads for buffer descriptors.
1613                  */
1614                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1615                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1616                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1617                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1618         }
1619
1620         /* Turn on read DMA state machine */
1621         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1622         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1623                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1624         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1625             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1626             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1627                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1628                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1629                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1630         }
1631         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1632                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1633                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1634                 /*
1635                  * Allow multiple outstanding read requests from
1636                  * non-LSO read DMA engine.
1637                  */
1638                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1639         }
1640         if (sc->bnx_flags & BNX_FLAG_TSO)
1641                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1642         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1643         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1644         DELAY(40);
1645
1646         /* Turn on RX data completion state machine */
1647         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1648
1649         /* Turn on RX BD initiator state machine */
1650         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1651
1652         /* Turn on RX data and RX BD initiator state machine */
1653         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1654
1655         /* Turn on send BD completion state machine */
1656         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1657
1658         /* Turn on send data completion state machine */
1659         val = BGE_SDCMODE_ENABLE;
1660         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1661                 val |= BGE_SDCMODE_CDELAY;
1662         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1663
1664         /* Turn on send data initiator state machine */
1665         if (sc->bnx_flags & BNX_FLAG_TSO) {
1666                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1667                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1668         } else {
1669                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1670         }
1671
1672         /* Turn on send BD initiator state machine */
1673         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1674
1675         /* Turn on send BD selector state machine */
1676         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1677
1678         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1679         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1680             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1681
1682         /* ack/clear link change events */
1683         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1684             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1685             BGE_MACSTAT_LINK_CHANGED);
1686         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1687
1688         /*
1689          * Enable attention when the link has changed state for
1690          * devices that use auto polling.
1691          */
1692         if (sc->bnx_flags & BNX_FLAG_TBI) {
1693                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1694         } else {
1695                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1696                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1697                         DELAY(80);
1698                 }
1699         }
1700
1701         /*
1702          * Clear any pending link state attention.
1703          * Otherwise some link state change events may be lost until attention
1704          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1705          * It's not necessary on newer BCM chips - perhaps enabling link
1706          * state change attentions implies clearing pending attention.
1707          */
1708         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1709             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1710             BGE_MACSTAT_LINK_CHANGED);
1711
1712         /* Enable link state change attentions. */
1713         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1714
1715         return(0);
1716 }
1717
1718 /*
1719  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1720  * against our list and return its name if we find a match. Note
1721  * that since the Broadcom controller contains VPD support, we
1722  * can get the device name string from the controller itself instead
1723  * of the compiled-in string. This is a little slow, but it guarantees
1724  * we'll always announce the right product name.
1725  */
1726 static int
1727 bnx_probe(device_t dev)
1728 {
1729         const struct bnx_type *t;
1730         uint16_t product, vendor;
1731
1732         if (!pci_is_pcie(dev))
1733                 return ENXIO;
1734
1735         product = pci_get_device(dev);
1736         vendor = pci_get_vendor(dev);
1737
1738         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1739                 if (vendor == t->bnx_vid && product == t->bnx_did)
1740                         break;
1741         }
1742         if (t->bnx_name == NULL)
1743                 return ENXIO;
1744
1745         device_set_desc(dev, t->bnx_name);
1746         return 0;
1747 }
1748
1749 static int
1750 bnx_attach(device_t dev)
1751 {
1752         struct ifnet *ifp;
1753         struct bnx_softc *sc;
1754         uint32_t hwcfg = 0;
1755         int error = 0, rid, capmask;
1756         uint8_t ether_addr[ETHER_ADDR_LEN];
1757         uint16_t product;
1758         driver_intr_t *intr_func;
1759         uintptr_t mii_priv = 0;
1760         u_int intr_flags;
1761 #ifdef BNX_TSO_DEBUG
1762         char desc[32];
1763         int i;
1764 #endif
1765
1766         sc = device_get_softc(dev);
1767         sc->bnx_dev = dev;
1768         callout_init_mp(&sc->bnx_stat_timer);
1769         callout_init_mp(&sc->bnx_intr_timer);
1770         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1771
1772         product = pci_get_device(dev);
1773
1774 #ifndef BURN_BRIDGES
1775         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1776                 uint32_t irq, mem;
1777
1778                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1779                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1780
1781                 device_printf(dev, "chip is in D%d power mode "
1782                     "-- setting to D0\n", pci_get_powerstate(dev));
1783
1784                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1785
1786                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1787                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1788         }
1789 #endif  /* !BURN_BRIDGE */
1790
1791         /*
1792          * Map control/status registers.
1793          */
1794         pci_enable_busmaster(dev);
1795
1796         rid = BGE_PCI_BAR0;
1797         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1798             RF_ACTIVE);
1799
1800         if (sc->bnx_res == NULL) {
1801                 device_printf(dev, "couldn't map memory\n");
1802                 return ENXIO;
1803         }
1804
1805         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1806         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1807
1808         /* Save various chip information */
1809         sc->bnx_chipid =
1810             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1811             BGE_PCIMISCCTL_ASICREV_SHIFT;
1812         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1813                 /* All chips having dedicated ASICREV register have CPMU */
1814                 sc->bnx_flags |= BNX_FLAG_CPMU;
1815
1816                 switch (product) {
1817                 case PCI_PRODUCT_BROADCOM_BCM5717:
1818                 case PCI_PRODUCT_BROADCOM_BCM5718:
1819                 case PCI_PRODUCT_BROADCOM_BCM5719:
1820                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1821                         sc->bnx_chipid = pci_read_config(dev,
1822                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1823                         break;
1824
1825                 case PCI_PRODUCT_BROADCOM_BCM57761:
1826                 case PCI_PRODUCT_BROADCOM_BCM57762:
1827                 case PCI_PRODUCT_BROADCOM_BCM57765:
1828                 case PCI_PRODUCT_BROADCOM_BCM57766:
1829                 case PCI_PRODUCT_BROADCOM_BCM57781:
1830                 case PCI_PRODUCT_BROADCOM_BCM57782:
1831                 case PCI_PRODUCT_BROADCOM_BCM57785:
1832                 case PCI_PRODUCT_BROADCOM_BCM57786:
1833                 case PCI_PRODUCT_BROADCOM_BCM57791:
1834                 case PCI_PRODUCT_BROADCOM_BCM57795:
1835                         sc->bnx_chipid = pci_read_config(dev,
1836                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1837                         break;
1838
1839                 default:
1840                         sc->bnx_chipid = pci_read_config(dev,
1841                             BGE_PCI_PRODID_ASICREV, 4);
1842                         break;
1843                 }
1844         }
1845         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1846         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1847
1848         switch (sc->bnx_asicrev) {
1849         case BGE_ASICREV_BCM5717:
1850         case BGE_ASICREV_BCM5719:
1851         case BGE_ASICREV_BCM5720:
1852                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1853                 break;
1854
1855         case BGE_ASICREV_BCM57765:
1856         case BGE_ASICREV_BCM57766:
1857                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1858                 break;
1859         }
1860         sc->bnx_flags |= BNX_FLAG_SHORTDMA;
1861
1862         sc->bnx_flags |= BNX_FLAG_TSO;
1863         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1864             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1865                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1866
1867         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1868             BNX_IS_57765_FAMILY(sc)) {
1869                 /*
1870                  * All BCM57785 and BCM5718 families chips have a bug that
1871                  * under certain situation interrupt will not be enabled
1872                  * even if status tag is written to BGE_MBX_IRQ0_LO mailbox.
1873                  *
1874                  * While BCM5719 and BCM5720 have a hardware workaround
1875                  * which could fix the above bug.
1876                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1877                  * bnx_chipinit().
1878                  *
1879                  * For the rest of the chips in these two families, we will
1880                  * have to poll the status block at high rate (10ms currently)
1881                  * to check whether the interrupt is hosed or not.
1882                  * See bnx_intr_check() for details.
1883                  */
1884                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1885         }
1886
1887         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1888         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1889             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1890                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1891         else
1892                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1893         device_printf(dev, "CHIP ID 0x%08x; "
1894                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1895                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1896
1897         /*
1898          * Set various PHY quirk flags.
1899          */
1900
1901         capmask = MII_CAPMASK_DEFAULT;
1902         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1903             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1904                 /* 10/100 only */
1905                 capmask &= ~BMSR_EXTSTAT;
1906         }
1907
1908         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1909
1910         /*
1911          * Allocate interrupt
1912          */
1913         sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1914             &intr_flags);
1915
1916         sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1917             intr_flags);
1918         if (sc->bnx_irq == NULL) {
1919                 device_printf(dev, "couldn't map interrupt\n");
1920                 error = ENXIO;
1921                 goto fail;
1922         }
1923
1924         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1925                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1926                 bnx_enable_msi(sc);
1927         }
1928
1929         /* Initialize if_name earlier, so if_printf could be used */
1930         ifp = &sc->arpcom.ac_if;
1931         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1932
1933         /* Try to reset the chip. */
1934         bnx_reset(sc);
1935
1936         if (bnx_chipinit(sc)) {
1937                 device_printf(dev, "chip initialization failed\n");
1938                 error = ENXIO;
1939                 goto fail;
1940         }
1941
1942         /*
1943          * Get station address
1944          */
1945         error = bnx_get_eaddr(sc, ether_addr);
1946         if (error) {
1947                 device_printf(dev, "failed to read station address\n");
1948                 goto fail;
1949         }
1950
1951         if (BNX_IS_57765_PLUS(sc)) {
1952                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT;
1953         } else {
1954                 /* 5705/5750 limits RX return ring to 512 entries. */
1955                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1956         }
1957
1958         error = bnx_dma_alloc(sc);
1959         if (error)
1960                 goto fail;
1961
1962         /* Set default tuneable values. */
1963         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1964         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1965         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1966         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1967         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
1968         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
1969         sc->bnx_tx_wreg = 8;
1970
1971         /* Set up ifnet structure */
1972         ifp->if_softc = sc;
1973         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1974         ifp->if_ioctl = bnx_ioctl;
1975         ifp->if_start = bnx_start;
1976 #ifdef IFPOLL_ENABLE
1977         ifp->if_npoll = bnx_npoll;
1978 #endif
1979         ifp->if_watchdog = bnx_watchdog;
1980         ifp->if_init = bnx_init;
1981         ifp->if_mtu = ETHERMTU;
1982         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1983         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1984         ifq_set_ready(&ifp->if_snd);
1985
1986         ifp->if_capabilities |= IFCAP_HWCSUM;
1987         ifp->if_hwassist = BNX_CSUM_FEATURES;
1988         if (sc->bnx_flags & BNX_FLAG_TSO) {
1989                 ifp->if_capabilities |= IFCAP_TSO;
1990                 ifp->if_hwassist |= CSUM_TSO;
1991         }
1992         ifp->if_capenable = ifp->if_capabilities;
1993
1994         /*
1995          * Figure out what sort of media we have by checking the
1996          * hardware config word in the first 32k of NIC internal memory,
1997          * or fall back to examining the EEPROM if necessary.
1998          * Note: on some BCM5700 cards, this value appears to be unset.
1999          * If that's the case, we have to rely on identifying the NIC
2000          * by its PCI subsystem ID, as we do below for the SysKonnect
2001          * SK-9D41.
2002          */
2003         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2004                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2005         } else {
2006                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2007                                     sizeof(hwcfg))) {
2008                         device_printf(dev, "failed to read EEPROM\n");
2009                         error = ENXIO;
2010                         goto fail;
2011                 }
2012                 hwcfg = ntohl(hwcfg);
2013         }
2014
2015         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2016         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2017             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2018                 sc->bnx_flags |= BNX_FLAG_TBI;
2019
2020         /* Setup MI MODE */
2021         if (sc->bnx_flags & BNX_FLAG_CPMU)
2022                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
2023         else
2024                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
2025
2026         /* Setup link status update stuffs */
2027         if (sc->bnx_flags & BNX_FLAG_TBI) {
2028                 sc->bnx_link_upd = bnx_tbi_link_upd;
2029                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2030         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
2031                 sc->bnx_link_upd = bnx_autopoll_link_upd;
2032                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2033         } else {
2034                 sc->bnx_link_upd = bnx_copper_link_upd;
2035                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2036         }
2037
2038         /* Set default PHY address */
2039         sc->bnx_phyno = 1;
2040
2041         /*
2042          * PHY address mapping for various devices.
2043          *
2044          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2045          * ---------+-------+-------+-------+-------+
2046          * BCM57XX  |   1   |   X   |   X   |   X   |
2047          * BCM5704  |   1   |   X   |   1   |   X   |
2048          * BCM5717  |   1   |   8   |   2   |   9   |
2049          * BCM5719  |   1   |   8   |   2   |   9   |
2050          * BCM5720  |   1   |   8   |   2   |   9   |
2051          *
2052          * Other addresses may respond but they are not
2053          * IEEE compliant PHYs and should be ignored.
2054          */
2055         if (BNX_IS_5717_PLUS(sc)) {
2056                 int f;
2057
2058                 f = pci_get_function(dev);
2059                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2060                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2061                             BGE_SGDIGSTS_IS_SERDES)
2062                                 sc->bnx_phyno = f + 8;
2063                         else
2064                                 sc->bnx_phyno = f + 1;
2065                 } else {
2066                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2067                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2068                                 sc->bnx_phyno = f + 8;
2069                         else
2070                                 sc->bnx_phyno = f + 1;
2071                 }
2072         }
2073
2074         if (sc->bnx_flags & BNX_FLAG_TBI) {
2075                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2076                     bnx_ifmedia_upd, bnx_ifmedia_sts);
2077                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2078                 ifmedia_add(&sc->bnx_ifmedia,
2079                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2080                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2081                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2082                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2083         } else {
2084                 struct mii_probe_args mii_args;
2085
2086                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2087                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2088                 mii_args.mii_capmask = capmask;
2089                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2090                 mii_args.mii_priv = mii_priv;
2091
2092                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2093                 if (error) {
2094                         device_printf(dev, "MII without any PHY!\n");
2095                         goto fail;
2096                 }
2097         }
2098
2099         /*
2100          * Create sysctl nodes.
2101          */
2102         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2103         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2104                                               SYSCTL_STATIC_CHILDREN(_hw),
2105                                               OID_AUTO,
2106                                               device_get_nameunit(dev),
2107                                               CTLFLAG_RD, 0, "");
2108         if (sc->bnx_sysctl_tree == NULL) {
2109                 device_printf(dev, "can't add sysctl node\n");
2110                 error = ENXIO;
2111                 goto fail;
2112         }
2113
2114         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2115                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2116                         OID_AUTO, "rx_coal_ticks",
2117                         CTLTYPE_INT | CTLFLAG_RW,
2118                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2119                         "Receive coalescing ticks (usec).");
2120         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2121                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2122                         OID_AUTO, "tx_coal_ticks",
2123                         CTLTYPE_INT | CTLFLAG_RW,
2124                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2125                         "Transmit coalescing ticks (usec).");
2126         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2127                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2128                         OID_AUTO, "rx_coal_bds",
2129                         CTLTYPE_INT | CTLFLAG_RW,
2130                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2131                         "Receive max coalesced BD count.");
2132         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2133                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2134                         OID_AUTO, "tx_coal_bds",
2135                         CTLTYPE_INT | CTLFLAG_RW,
2136                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2137                         "Transmit max coalesced BD count.");
2138         /*
2139          * A common design characteristic for many Broadcom
2140          * client controllers is that they only support a
2141          * single outstanding DMA read operation on the PCIe
2142          * bus. This means that it will take twice as long to
2143          * fetch a TX frame that is split into header and
2144          * payload buffers as it does to fetch a single,
2145          * contiguous TX frame (2 reads vs. 1 read). For these
2146          * controllers, coalescing buffers to reduce the number
2147          * of memory reads is effective way to get maximum
2148          * performance(about 940Mbps).  Without collapsing TX
2149          * buffers the maximum TCP bulk transfer performance
2150          * is about 850Mbps. However forcing coalescing mbufs
2151          * consumes a lot of CPU cycles, so leave it off by
2152          * default.
2153          */
2154         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2155             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2156             "force_defrag", CTLFLAG_RW, &sc->bnx_force_defrag, 0,
2157             "Force defragment on TX path");
2158
2159         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2160             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2161             "tx_wreg", CTLFLAG_RW, &sc->bnx_tx_wreg, 0,
2162             "# of segments before writing to hardware register");
2163
2164         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2165             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2166             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2167             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2168             "Receive max coalesced BD count during interrupt.");
2169         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2170             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2171             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2172             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2173             "Transmit max coalesced BD count during interrupt.");
2174
2175 #ifdef BNX_TSO_DEBUG
2176         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2177                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2178                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2179                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2180                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2181         }
2182 #endif
2183
2184         /*
2185          * Call MI attach routine.
2186          */
2187         ether_ifattach(ifp, ether_addr, NULL);
2188
2189 #ifdef IFPOLL_ENABLE
2190         ifpoll_compat_setup(&sc->bnx_npoll,
2191             &sc->bnx_sysctl_ctx, sc->bnx_sysctl_tree,
2192             device_get_unit(dev), ifp->if_serializer);
2193 #endif
2194
2195         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2196                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2197                         intr_func = bnx_msi_oneshot;
2198                         if (bootverbose)
2199                                 device_printf(dev, "oneshot MSI\n");
2200                 } else {
2201                         intr_func = bnx_msi;
2202                 }
2203         } else {
2204                 intr_func = bnx_intr_legacy;
2205         }
2206         error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2207             &sc->bnx_intrhand, ifp->if_serializer);
2208         if (error) {
2209                 ether_ifdetach(ifp);
2210                 device_printf(dev, "couldn't set up irq\n");
2211                 goto fail;
2212         }
2213
2214         sc->bnx_intr_cpuid = rman_get_cpuid(sc->bnx_irq);
2215         sc->bnx_stat_cpuid = sc->bnx_intr_cpuid;
2216         ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2217
2218         return(0);
2219 fail:
2220         bnx_detach(dev);
2221         return(error);
2222 }
2223
2224 static int
2225 bnx_detach(device_t dev)
2226 {
2227         struct bnx_softc *sc = device_get_softc(dev);
2228
2229         if (device_is_attached(dev)) {
2230                 struct ifnet *ifp = &sc->arpcom.ac_if;
2231
2232                 lwkt_serialize_enter(ifp->if_serializer);
2233                 bnx_stop(sc);
2234                 bnx_reset(sc);
2235                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2236                 lwkt_serialize_exit(ifp->if_serializer);
2237
2238                 ether_ifdetach(ifp);
2239         }
2240
2241         if (sc->bnx_flags & BNX_FLAG_TBI)
2242                 ifmedia_removeall(&sc->bnx_ifmedia);
2243         if (sc->bnx_miibus)
2244                 device_delete_child(dev, sc->bnx_miibus);
2245         bus_generic_detach(dev);
2246
2247         if (sc->bnx_irq != NULL) {
2248                 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2249                     sc->bnx_irq);
2250         }
2251         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2252                 pci_release_msi(dev);
2253
2254         if (sc->bnx_res != NULL) {
2255                 bus_release_resource(dev, SYS_RES_MEMORY,
2256                     BGE_PCI_BAR0, sc->bnx_res);
2257         }
2258
2259         if (sc->bnx_sysctl_tree != NULL)
2260                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2261
2262         bnx_dma_free(sc);
2263
2264         return 0;
2265 }
2266
2267 static void
2268 bnx_reset(struct bnx_softc *sc)
2269 {
2270         device_t dev;
2271         uint32_t cachesize, command, pcistate, reset;
2272         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2273         int i, val = 0;
2274         uint16_t devctl;
2275
2276         dev = sc->bnx_dev;
2277
2278         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
2279                 write_op = bnx_writemem_direct;
2280         else
2281                 write_op = bnx_writereg_ind;
2282
2283         /* Save some important PCI state. */
2284         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2285         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2286         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2287
2288         pci_write_config(dev, BGE_PCI_MISC_CTL,
2289             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2290             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2291             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2292
2293         /* Disable fastboot on controllers that support it. */
2294         if (bootverbose)
2295                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2296         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2297
2298         /*
2299          * Write the magic number to SRAM at offset 0xB50.
2300          * When firmware finishes its initialization it will
2301          * write ~BGE_MAGIC_NUMBER to the same location.
2302          */
2303         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2304
2305         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2306
2307         /* XXX: Broadcom Linux driver. */
2308         /* Force PCI-E 1.0a mode */
2309         if (!BNX_IS_57765_PLUS(sc) &&
2310             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2311             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2312              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2313                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2314                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2315         }
2316         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2317                 /* Prevent PCIE link training during global reset */
2318                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2319                 reset |= (1<<29);
2320         }
2321
2322         /*
2323          * Set GPHY Power Down Override to leave GPHY
2324          * powered up in D0 uninitialized.
2325          */
2326         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2327                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2328
2329         /* Issue global reset */
2330         write_op(sc, BGE_MISC_CFG, reset);
2331
2332         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2333                 uint32_t status, ctrl;
2334
2335                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2336                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2337                     status | BGE_VCPU_STATUS_DRV_RESET);
2338                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2339                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2340                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2341         }
2342
2343         DELAY(1000);
2344
2345         /* XXX: Broadcom Linux driver. */
2346         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2347                 uint32_t v;
2348
2349                 DELAY(500000); /* wait for link training to complete */
2350                 v = pci_read_config(dev, 0xc4, 4);
2351                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2352         }
2353
2354         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2355
2356         /* Disable no snoop and disable relaxed ordering. */
2357         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2358
2359         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2360         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2361                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2362                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2363         }
2364
2365         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2366             devctl, 2);
2367
2368         /* Clear error status. */
2369         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2370             PCIEM_DEVSTS_CORR_ERR |
2371             PCIEM_DEVSTS_NFATAL_ERR |
2372             PCIEM_DEVSTS_FATAL_ERR |
2373             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2374
2375         /* Reset some of the PCI state that got zapped by reset */
2376         pci_write_config(dev, BGE_PCI_MISC_CTL,
2377             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2378             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2379             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2380         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2381         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2382         write_op(sc, BGE_MISC_CFG, (65 << 1));
2383
2384         /* Enable memory arbiter */
2385         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2386
2387         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2388                 for (i = 0; i < BNX_TIMEOUT; i++) {
2389                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2390                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2391                                 break;
2392                         DELAY(100);
2393                 }
2394                 if (i == BNX_TIMEOUT) {
2395                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2396                         return;
2397                 }
2398         } else {
2399                 /*
2400                  * Poll until we see the 1's complement of the magic number.
2401                  * This indicates that the firmware initialization
2402                  * is complete.
2403                  */
2404                 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2405                         val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2406                         if (val == ~BGE_MAGIC_NUMBER)
2407                                 break;
2408                         DELAY(10);
2409                 }
2410                 if (i == BNX_FIRMWARE_TIMEOUT) {
2411                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2412                                   "timed out, found 0x%08x\n", val);
2413                 }
2414
2415                 /* BCM57765 A0 needs additional time before accessing. */
2416                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2417                         DELAY(10 * 1000);
2418         }
2419
2420         /*
2421          * XXX Wait for the value of the PCISTATE register to
2422          * return to its original pre-reset state. This is a
2423          * fairly good indicator of reset completion. If we don't
2424          * wait for the reset to fully complete, trying to read
2425          * from the device's non-PCI registers may yield garbage
2426          * results.
2427          */
2428         for (i = 0; i < BNX_TIMEOUT; i++) {
2429                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2430                         break;
2431                 DELAY(10);
2432         }
2433
2434         /* Fix up byte swapping */
2435         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2436
2437         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2438
2439         /*
2440          * The 5704 in TBI mode apparently needs some special
2441          * adjustment to insure the SERDES drive level is set
2442          * to 1.2V.
2443          */
2444         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2445             (sc->bnx_flags & BNX_FLAG_TBI)) {
2446                 uint32_t serdescfg;
2447
2448                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2449                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2450                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2451         }
2452
2453         CSR_WRITE_4(sc, BGE_MI_MODE,
2454             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2455         DELAY(80);
2456
2457         /* XXX: Broadcom Linux driver. */
2458         if (!BNX_IS_57765_PLUS(sc)) {
2459                 uint32_t v;
2460
2461                 /* Enable Data FIFO protection. */
2462                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2463                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2464         }
2465
2466         DELAY(10000);
2467
2468         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2469                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2470                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2471         }
2472 }
2473
2474 /*
2475  * Frame reception handling. This is called if there's a frame
2476  * on the receive return list.
2477  *
2478  * Note: we have to be able to handle two possibilities here:
2479  * 1) the frame is from the jumbo recieve ring
2480  * 2) the frame is from the standard receive ring
2481  */
2482
2483 static void
2484 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod, int count)
2485 {
2486         struct ifnet *ifp;
2487         int stdcnt = 0, jumbocnt = 0;
2488
2489         ifp = &sc->arpcom.ac_if;
2490
2491         while (sc->bnx_rx_saved_considx != rx_prod && count != 0) {
2492                 struct bge_rx_bd        *cur_rx;
2493                 uint32_t                rxidx;
2494                 struct mbuf             *m = NULL;
2495                 uint16_t                vlan_tag = 0;
2496                 int                     have_tag = 0;
2497
2498                 --count;
2499
2500                 cur_rx =
2501             &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2502
2503                 rxidx = cur_rx->bge_idx;
2504                 BNX_INC(sc->bnx_rx_saved_considx, sc->bnx_return_ring_cnt);
2505
2506                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2507                         have_tag = 1;
2508                         vlan_tag = cur_rx->bge_vlan_tag;
2509                 }
2510
2511                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2512                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2513                         jumbocnt++;
2514
2515                         if (rxidx != sc->bnx_jumbo) {
2516                                 IFNET_STAT_INC(ifp, ierrors, 1);
2517                                 if_printf(ifp, "sw jumbo index(%d) "
2518                                     "and hw jumbo index(%d) mismatch, drop!\n",
2519                                     sc->bnx_jumbo, rxidx);
2520                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2521                                 continue;
2522                         }
2523
2524                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2525                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2526                                 IFNET_STAT_INC(ifp, ierrors, 1);
2527                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2528                                 continue;
2529                         }
2530                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2531                                 IFNET_STAT_INC(ifp, ierrors, 1);
2532                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2533                                 continue;
2534                         }
2535                 } else {
2536                         BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2537                         stdcnt++;
2538
2539                         if (rxidx != sc->bnx_std) {
2540                                 IFNET_STAT_INC(ifp, ierrors, 1);
2541                                 if_printf(ifp, "sw std index(%d) "
2542                                     "and hw std index(%d) mismatch, drop!\n",
2543                                     sc->bnx_std, rxidx);
2544                                 bnx_setup_rxdesc_std(sc, rxidx);
2545                                 continue;
2546                         }
2547
2548                         m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2549                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2550                                 IFNET_STAT_INC(ifp, ierrors, 1);
2551                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2552                                 continue;
2553                         }
2554                         if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2555                                 IFNET_STAT_INC(ifp, ierrors, 1);
2556                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2557                                 continue;
2558                         }
2559                 }
2560
2561                 IFNET_STAT_INC(ifp, ipackets, 1);
2562                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2563                 m->m_pkthdr.rcvif = ifp;
2564
2565                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2566                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2567                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2568                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2569                                 if ((cur_rx->bge_error_flag &
2570                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2571                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2572                         }
2573                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2574                                 m->m_pkthdr.csum_data =
2575                                     cur_rx->bge_tcp_udp_csum;
2576                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2577                                     CSUM_PSEUDO_HDR;
2578                         }
2579                 }
2580
2581                 /*
2582                  * If we received a packet with a vlan tag, pass it
2583                  * to vlan_input() instead of ether_input().
2584                  */
2585                 if (have_tag) {
2586                         m->m_flags |= M_VLANTAG;
2587                         m->m_pkthdr.ether_vlantag = vlan_tag;
2588                 }
2589                 ifp->if_input(ifp, m);
2590         }
2591
2592         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2593         if (stdcnt)
2594                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2595         if (jumbocnt)
2596                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2597 }
2598
2599 static void
2600 bnx_txeof(struct bnx_softc *sc, uint16_t tx_cons)
2601 {
2602         struct ifnet *ifp;
2603
2604         ifp = &sc->arpcom.ac_if;
2605
2606         /*
2607          * Go through our tx ring and free mbufs for those
2608          * frames that have been sent.
2609          */
2610         while (sc->bnx_tx_saved_considx != tx_cons) {
2611                 uint32_t idx = 0;
2612
2613                 idx = sc->bnx_tx_saved_considx;
2614                 if (sc->bnx_cdata.bnx_tx_chain[idx] != NULL) {
2615                         IFNET_STAT_INC(ifp, opackets, 1);
2616                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
2617                             sc->bnx_cdata.bnx_tx_dmamap[idx]);
2618                         m_freem(sc->bnx_cdata.bnx_tx_chain[idx]);
2619                         sc->bnx_cdata.bnx_tx_chain[idx] = NULL;
2620                 }
2621                 sc->bnx_txcnt--;
2622                 BNX_INC(sc->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2623         }
2624
2625         if ((BGE_TX_RING_CNT - sc->bnx_txcnt) >=
2626             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2627                 ifq_clr_oactive(&ifp->if_snd);
2628
2629         if (sc->bnx_txcnt == 0)
2630                 ifp->if_timer = 0;
2631
2632         if (!ifq_is_empty(&ifp->if_snd))
2633                 if_devstart(ifp);
2634 }
2635
2636 #ifdef IFPOLL_ENABLE
2637
2638 static void
2639 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2640 {
2641         struct bnx_softc *sc = ifp->if_softc;
2642
2643         ASSERT_SERIALIZED(ifp->if_serializer);
2644
2645         if (info != NULL) {
2646                 int cpuid = sc->bnx_npoll.ifpc_cpuid;
2647
2648                 info->ifpi_rx[cpuid].poll_func = bnx_npoll_compat;
2649                 info->ifpi_rx[cpuid].arg = NULL;
2650                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2651
2652                 if (ifp->if_flags & IFF_RUNNING)
2653                         bnx_disable_intr(sc);
2654                 ifq_set_cpuid(&ifp->if_snd, cpuid);
2655         } else {
2656                 if (ifp->if_flags & IFF_RUNNING)
2657                         bnx_enable_intr(sc);
2658                 ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2659         }
2660 }
2661
2662 static void
2663 bnx_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycle)
2664 {
2665         struct bnx_softc *sc = ifp->if_softc;
2666         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2667         uint16_t rx_prod, tx_cons;
2668
2669         ASSERT_SERIALIZED(ifp->if_serializer);
2670
2671         if (sc->bnx_npoll.ifpc_stcount-- == 0) {
2672                 sc->bnx_npoll.ifpc_stcount = sc->bnx_npoll.ifpc_stfrac;
2673                 /*
2674                  * Process link state changes.
2675                  */
2676                 bnx_link_poll(sc);
2677         }
2678
2679         sc->bnx_status_tag = sblk->bge_status_tag;
2680
2681         /*
2682          * Use a load fence to ensure that status_tag is saved
2683          * before rx_prod and tx_cons.
2684          */
2685         cpu_lfence();
2686
2687         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2688         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2689
2690         if (sc->bnx_rx_saved_considx != rx_prod)
2691                 bnx_rxeof(sc, rx_prod, cycle);
2692
2693         if (sc->bnx_tx_saved_considx != tx_cons)
2694                 bnx_txeof(sc, tx_cons);
2695
2696         if (sc->bnx_coal_chg)
2697                 bnx_coal_change(sc);
2698 }
2699
2700 #endif  /* IFPOLL_ENABLE */
2701
2702 static void
2703 bnx_intr_legacy(void *xsc)
2704 {
2705         struct bnx_softc *sc = xsc;
2706         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2707
2708         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2709                 uint32_t val;
2710
2711                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2712                 if (val & BGE_PCISTAT_INTR_NOTACT)
2713                         return;
2714         }
2715
2716         /*
2717          * NOTE:
2718          * Interrupt will have to be disabled if tagged status
2719          * is used, else interrupt will always be asserted on
2720          * certain chips (at least on BCM5750 AX/BX).
2721          */
2722         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2723
2724         bnx_intr(sc);
2725 }
2726
2727 static void
2728 bnx_msi(void *xsc)
2729 {
2730         struct bnx_softc *sc = xsc;
2731
2732         /* Disable interrupt first */
2733         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2734         bnx_intr(sc);
2735 }
2736
2737 static void
2738 bnx_msi_oneshot(void *xsc)
2739 {
2740         bnx_intr(xsc);
2741 }
2742
2743 static void
2744 bnx_intr(struct bnx_softc *sc)
2745 {
2746         struct ifnet *ifp = &sc->arpcom.ac_if;
2747         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2748         uint16_t rx_prod, tx_cons;
2749         uint32_t status;
2750
2751         sc->bnx_status_tag = sblk->bge_status_tag;
2752         /*
2753          * Use a load fence to ensure that status_tag is saved
2754          * before rx_prod, tx_cons and status.
2755          */
2756         cpu_lfence();
2757
2758         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2759         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2760         status = sblk->bge_status;
2761
2762         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2763                 bnx_link_poll(sc);
2764
2765         if (ifp->if_flags & IFF_RUNNING) {
2766                 if (sc->bnx_rx_saved_considx != rx_prod)
2767                         bnx_rxeof(sc, rx_prod, -1);
2768
2769                 if (sc->bnx_tx_saved_considx != tx_cons)
2770                         bnx_txeof(sc, tx_cons);
2771         }
2772
2773         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2774
2775         if (sc->bnx_coal_chg)
2776                 bnx_coal_change(sc);
2777 }
2778
2779 static void
2780 bnx_tick(void *xsc)
2781 {
2782         struct bnx_softc *sc = xsc;
2783         struct ifnet *ifp = &sc->arpcom.ac_if;
2784
2785         lwkt_serialize_enter(ifp->if_serializer);
2786
2787         KKASSERT(mycpuid == sc->bnx_stat_cpuid);
2788
2789         bnx_stats_update_regs(sc);
2790
2791         if (sc->bnx_flags & BNX_FLAG_TBI) {
2792                 /*
2793                  * Since in TBI mode auto-polling can't be used we should poll
2794                  * link status manually. Here we register pending link event
2795                  * and trigger interrupt.
2796                  */
2797                 sc->bnx_link_evt++;
2798                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2799         } else if (!sc->bnx_link) {
2800                 mii_tick(device_get_softc(sc->bnx_miibus));
2801         }
2802
2803         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2804
2805         lwkt_serialize_exit(ifp->if_serializer);
2806 }
2807
2808 static void
2809 bnx_stats_update_regs(struct bnx_softc *sc)
2810 {
2811         struct ifnet *ifp = &sc->arpcom.ac_if;
2812         struct bge_mac_stats_regs stats;
2813         uint32_t *s;
2814         int i;
2815
2816         s = (uint32_t *)&stats;
2817         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2818                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2819                 s++;
2820         }
2821
2822         IFNET_STAT_SET(ifp, collisions,
2823            (stats.dot3StatsSingleCollisionFrames +
2824            stats.dot3StatsMultipleCollisionFrames +
2825            stats.dot3StatsExcessiveCollisions +
2826            stats.dot3StatsLateCollisions));
2827 }
2828
2829 /*
2830  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2831  * pointers to descriptors.
2832  */
2833 static int
2834 bnx_encap(struct bnx_softc *sc, struct mbuf **m_head0, uint32_t *txidx,
2835     int *segs_used)
2836 {
2837         struct bge_tx_bd *d = NULL;
2838         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
2839         bus_dma_segment_t segs[BNX_NSEG_NEW];
2840         bus_dmamap_t map;
2841         int error, maxsegs, nsegs, idx, i;
2842         struct mbuf *m_head = *m_head0, *m_new;
2843
2844         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2845 #ifdef BNX_TSO_DEBUG
2846                 int tso_nsegs;
2847 #endif
2848
2849                 error = bnx_setup_tso(sc, m_head0, &mss, &csum_flags);
2850                 if (error)
2851                         return error;
2852                 m_head = *m_head0;
2853
2854 #ifdef BNX_TSO_DEBUG
2855                 tso_nsegs = (m_head->m_pkthdr.len /
2856                     m_head->m_pkthdr.tso_segsz) - 1;
2857                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
2858                         tso_nsegs = BNX_TSO_NSTATS - 1;
2859                 else if (tso_nsegs < 0)
2860                         tso_nsegs = 0;
2861                 sc->bnx_tsosegs[tso_nsegs]++;
2862 #endif
2863         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
2864                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2865                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2866                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2867                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2868                 if (m_head->m_flags & M_LASTFRAG)
2869                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2870                 else if (m_head->m_flags & M_FRAG)
2871                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2872         }
2873         if (m_head->m_flags & M_VLANTAG) {
2874                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
2875                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
2876         }
2877
2878         idx = *txidx;
2879         map = sc->bnx_cdata.bnx_tx_dmamap[idx];
2880
2881         maxsegs = (BGE_TX_RING_CNT - sc->bnx_txcnt) - BNX_NSEG_RSVD;
2882         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2883                 ("not enough segments %d", maxsegs));
2884
2885         if (maxsegs > BNX_NSEG_NEW)
2886                 maxsegs = BNX_NSEG_NEW;
2887
2888         /*
2889          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2890          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2891          * but when such padded frames employ the bge IP/TCP checksum
2892          * offload, the hardware checksum assist gives incorrect results
2893          * (possibly from incorporating its own padding into the UDP/TCP
2894          * checksum; who knows).  If we pad such runts with zeros, the
2895          * onboard checksum comes out correct.
2896          */
2897         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2898             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2899                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2900                 if (error)
2901                         goto back;
2902         }
2903
2904         if ((sc->bnx_flags & BNX_FLAG_SHORTDMA) && m_head->m_next != NULL) {
2905                 m_new = bnx_defrag_shortdma(m_head);
2906                 if (m_new == NULL) {
2907                         error = ENOBUFS;
2908                         goto back;
2909                 }
2910                 *m_head0 = m_head = m_new;
2911         }
2912         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
2913             sc->bnx_force_defrag && m_head->m_next != NULL) {
2914                 /*
2915                  * Forcefully defragment mbuf chain to overcome hardware
2916                  * limitation which only support a single outstanding
2917                  * DMA read operation.  If it fails, keep moving on using
2918                  * the original mbuf chain.
2919                  */
2920                 m_new = m_defrag(m_head, MB_DONTWAIT);
2921                 if (m_new != NULL)
2922                         *m_head0 = m_head = m_new;
2923         }
2924
2925         error = bus_dmamap_load_mbuf_defrag(sc->bnx_cdata.bnx_tx_mtag, map,
2926                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2927         if (error)
2928                 goto back;
2929         *segs_used += nsegs;
2930
2931         m_head = *m_head0;
2932         bus_dmamap_sync(sc->bnx_cdata.bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2933
2934         for (i = 0; ; i++) {
2935                 d = &sc->bnx_ldata.bnx_tx_ring[idx];
2936
2937                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2938                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2939                 d->bge_len = segs[i].ds_len;
2940                 d->bge_flags = csum_flags;
2941                 d->bge_vlan_tag = vlan_tag;
2942                 d->bge_mss = mss;
2943
2944                 if (i == nsegs - 1)
2945                         break;
2946                 BNX_INC(idx, BGE_TX_RING_CNT);
2947         }
2948         /* Mark the last segment as end of packet... */
2949         d->bge_flags |= BGE_TXBDFLAG_END;
2950
2951         /*
2952          * Insure that the map for this transmission is placed at
2953          * the array index of the last descriptor in this chain.
2954          */
2955         sc->bnx_cdata.bnx_tx_dmamap[*txidx] = sc->bnx_cdata.bnx_tx_dmamap[idx];
2956         sc->bnx_cdata.bnx_tx_dmamap[idx] = map;
2957         sc->bnx_cdata.bnx_tx_chain[idx] = m_head;
2958         sc->bnx_txcnt += nsegs;
2959
2960         BNX_INC(idx, BGE_TX_RING_CNT);
2961         *txidx = idx;
2962 back:
2963         if (error) {
2964                 m_freem(*m_head0);
2965                 *m_head0 = NULL;
2966         }
2967         return error;
2968 }
2969
2970 /*
2971  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2972  * to the mbuf data regions directly in the transmit descriptors.
2973  */
2974 static void
2975 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2976 {
2977         struct bnx_softc *sc = ifp->if_softc;
2978         struct mbuf *m_head = NULL;
2979         uint32_t prodidx;
2980         int nsegs = 0;
2981
2982         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2983
2984         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
2985                 return;
2986
2987         prodidx = sc->bnx_tx_prodidx;
2988
2989         while (sc->bnx_cdata.bnx_tx_chain[prodidx] == NULL) {
2990                 /*
2991                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2992                  * descriptors of the end of the ring.  Also make
2993                  * sure there are BGE_NSEG_SPARE descriptors for
2994                  * jumbo buffers' or TSO segments' defragmentation.
2995                  */
2996                 if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
2997                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
2998                         ifq_set_oactive(&ifp->if_snd);
2999                         break;
3000                 }
3001
3002                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3003                 if (m_head == NULL)
3004                         break;
3005
3006                 /*
3007                  * Pack the data into the transmit ring. If we
3008                  * don't have room, set the OACTIVE flag and wait
3009                  * for the NIC to drain the ring.
3010                  */
3011                 if (bnx_encap(sc, &m_head, &prodidx, &nsegs)) {
3012                         ifq_set_oactive(&ifp->if_snd);
3013                         IFNET_STAT_INC(ifp, oerrors, 1);
3014                         break;
3015                 }
3016
3017                 if (nsegs >= sc->bnx_tx_wreg) {
3018                         /* Transmit */
3019                         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3020                         nsegs = 0;
3021                 }
3022
3023                 ETHER_BPF_MTAP(ifp, m_head);
3024
3025                 /*
3026                  * Set a timeout in case the chip goes out to lunch.
3027                  */
3028                 ifp->if_timer = 5;
3029         }
3030
3031         if (nsegs > 0) {
3032                 /* Transmit */
3033                 bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3034         }
3035         sc->bnx_tx_prodidx = prodidx;
3036 }
3037
3038 static void
3039 bnx_init(void *xsc)
3040 {
3041         struct bnx_softc *sc = xsc;
3042         struct ifnet *ifp = &sc->arpcom.ac_if;
3043         uint16_t *m;
3044         uint32_t mode;
3045
3046         ASSERT_SERIALIZED(ifp->if_serializer);
3047
3048         /* Cancel pending I/O and flush buffers. */
3049         bnx_stop(sc);
3050         bnx_reset(sc);
3051         bnx_chipinit(sc);
3052
3053         /*
3054          * Init the various state machines, ring
3055          * control blocks and firmware.
3056          */
3057         if (bnx_blockinit(sc)) {
3058                 if_printf(ifp, "initialization failure\n");
3059                 bnx_stop(sc);
3060                 return;
3061         }
3062
3063         /* Specify MTU. */
3064         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3065             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3066
3067         /* Load our MAC address. */
3068         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3069         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3070         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3071
3072         /* Enable or disable promiscuous mode as needed. */
3073         bnx_setpromisc(sc);
3074
3075         /* Program multicast filter. */
3076         bnx_setmulti(sc);
3077
3078         /* Init RX ring. */
3079         if (bnx_init_rx_ring_std(sc)) {
3080                 if_printf(ifp, "RX ring initialization failed\n");
3081                 bnx_stop(sc);
3082                 return;
3083         }
3084
3085         /* Init jumbo RX ring. */
3086         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3087                 if (bnx_init_rx_ring_jumbo(sc)) {
3088                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3089                         bnx_stop(sc);
3090                         return;
3091                 }
3092         }
3093
3094         /* Init our RX return ring index */
3095         sc->bnx_rx_saved_considx = 0;
3096
3097         /* Init TX ring. */
3098         bnx_init_tx_ring(sc);
3099
3100         /* Enable TX MAC state machine lockup fix. */
3101         mode = CSR_READ_4(sc, BGE_TX_MODE);
3102         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3103         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
3104                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3105                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3106                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3107         }
3108         /* Turn on transmitter */
3109         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3110
3111         /* Turn on receiver */
3112         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3113
3114         /*
3115          * Set the number of good frames to receive after RX MBUF
3116          * Low Watermark has been reached.  After the RX MAC receives
3117          * this number of frames, it will drop subsequent incoming
3118          * frames until the MBUF High Watermark is reached.
3119          */
3120         if (BNX_IS_57765_FAMILY(sc))
3121                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3122         else
3123                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3124
3125         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3126                 if (bootverbose) {
3127                         if_printf(ifp, "MSI_MODE: %#x\n",
3128                             CSR_READ_4(sc, BGE_MSI_MODE));
3129                 }
3130         }
3131
3132         /* Tell firmware we're alive. */
3133         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3134
3135         /* Enable host interrupts if polling(4) is not enabled. */
3136         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3137 #ifdef IFPOLL_ENABLE
3138         if (ifp->if_flags & IFF_NPOLLING)
3139                 bnx_disable_intr(sc);
3140         else
3141 #endif
3142         bnx_enable_intr(sc);
3143
3144         bnx_ifmedia_upd(ifp);
3145
3146         ifp->if_flags |= IFF_RUNNING;
3147         ifq_clr_oactive(&ifp->if_snd);
3148
3149         callout_reset_bycpu(&sc->bnx_stat_timer, hz, bnx_tick, sc,
3150             sc->bnx_stat_cpuid);
3151 }
3152
3153 /*
3154  * Set media options.
3155  */
3156 static int
3157 bnx_ifmedia_upd(struct ifnet *ifp)
3158 {
3159         struct bnx_softc *sc = ifp->if_softc;
3160
3161         /* If this is a 1000baseX NIC, enable the TBI port. */
3162         if (sc->bnx_flags & BNX_FLAG_TBI) {
3163                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3164
3165                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3166                         return(EINVAL);
3167
3168                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3169                 case IFM_AUTO:
3170                         break;
3171
3172                 case IFM_1000_SX:
3173                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3174                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3175                                     BGE_MACMODE_HALF_DUPLEX);
3176                         } else {
3177                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3178                                     BGE_MACMODE_HALF_DUPLEX);
3179                         }
3180                         break;
3181                 default:
3182                         return(EINVAL);
3183                 }
3184         } else {
3185                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3186
3187                 sc->bnx_link_evt++;
3188                 sc->bnx_link = 0;
3189                 if (mii->mii_instance) {
3190                         struct mii_softc *miisc;
3191
3192                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3193                                 mii_phy_reset(miisc);
3194                 }
3195                 mii_mediachg(mii);
3196
3197                 /*
3198                  * Force an interrupt so that we will call bnx_link_upd
3199                  * if needed and clear any pending link state attention.
3200                  * Without this we are not getting any further interrupts
3201                  * for link state changes and thus will not UP the link and
3202                  * not be able to send in bnx_start.  The only way to get
3203                  * things working was to receive a packet and get an RX
3204                  * intr.
3205                  *
3206                  * bnx_tick should help for fiber cards and we might not
3207                  * need to do this here if BNX_FLAG_TBI is set but as
3208                  * we poll for fiber anyway it should not harm.
3209                  */
3210                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3211         }
3212         return(0);
3213 }
3214
3215 /*
3216  * Report current media status.
3217  */
3218 static void
3219 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3220 {
3221         struct bnx_softc *sc = ifp->if_softc;
3222
3223         if (sc->bnx_flags & BNX_FLAG_TBI) {
3224                 ifmr->ifm_status = IFM_AVALID;
3225                 ifmr->ifm_active = IFM_ETHER;
3226                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3227                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3228                         ifmr->ifm_status |= IFM_ACTIVE;
3229                 } else {
3230                         ifmr->ifm_active |= IFM_NONE;
3231                         return;
3232                 }
3233
3234                 ifmr->ifm_active |= IFM_1000_SX;
3235                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3236                         ifmr->ifm_active |= IFM_HDX;
3237                 else
3238                         ifmr->ifm_active |= IFM_FDX;
3239         } else {
3240                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3241
3242                 mii_pollstat(mii);
3243                 ifmr->ifm_active = mii->mii_media_active;
3244                 ifmr->ifm_status = mii->mii_media_status;
3245         }
3246 }
3247
3248 static int
3249 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3250 {
3251         struct bnx_softc *sc = ifp->if_softc;
3252         struct ifreq *ifr = (struct ifreq *)data;
3253         int mask, error = 0;
3254
3255         ASSERT_SERIALIZED(ifp->if_serializer);
3256
3257         switch (command) {
3258         case SIOCSIFMTU:
3259                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3260                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3261                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3262                         error = EINVAL;
3263                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3264                         ifp->if_mtu = ifr->ifr_mtu;
3265                         if (ifp->if_flags & IFF_RUNNING)
3266                                 bnx_init(sc);
3267                 }
3268                 break;
3269         case SIOCSIFFLAGS:
3270                 if (ifp->if_flags & IFF_UP) {
3271                         if (ifp->if_flags & IFF_RUNNING) {
3272                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3273
3274                                 /*
3275                                  * If only the state of the PROMISC flag
3276                                  * changed, then just use the 'set promisc
3277                                  * mode' command instead of reinitializing
3278                                  * the entire NIC. Doing a full re-init
3279                                  * means reloading the firmware and waiting
3280                                  * for it to start up, which may take a
3281                                  * second or two.  Similarly for ALLMULTI.
3282                                  */
3283                                 if (mask & IFF_PROMISC)
3284                                         bnx_setpromisc(sc);
3285                                 if (mask & IFF_ALLMULTI)
3286                                         bnx_setmulti(sc);
3287                         } else {
3288                                 bnx_init(sc);
3289                         }
3290                 } else if (ifp->if_flags & IFF_RUNNING) {
3291                         bnx_stop(sc);
3292                 }
3293                 sc->bnx_if_flags = ifp->if_flags;
3294                 break;
3295         case SIOCADDMULTI:
3296         case SIOCDELMULTI:
3297                 if (ifp->if_flags & IFF_RUNNING)
3298                         bnx_setmulti(sc);
3299                 break;
3300         case SIOCSIFMEDIA:
3301         case SIOCGIFMEDIA:
3302                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3303                         error = ifmedia_ioctl(ifp, ifr,
3304                             &sc->bnx_ifmedia, command);
3305                 } else {
3306                         struct mii_data *mii;
3307
3308                         mii = device_get_softc(sc->bnx_miibus);
3309                         error = ifmedia_ioctl(ifp, ifr,
3310                                               &mii->mii_media, command);
3311                 }
3312                 break;
3313         case SIOCSIFCAP:
3314                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3315                 if (mask & IFCAP_HWCSUM) {
3316                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3317                         if (ifp->if_capenable & IFCAP_TXCSUM)
3318                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3319                         else
3320                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3321                 }
3322                 if (mask & IFCAP_TSO) {
3323                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3324                         if (ifp->if_capenable & IFCAP_TSO)
3325                                 ifp->if_hwassist |= CSUM_TSO;
3326                         else
3327                                 ifp->if_hwassist &= ~CSUM_TSO;
3328                 }
3329                 break;
3330         default:
3331                 error = ether_ioctl(ifp, command, data);
3332                 break;
3333         }
3334         return error;
3335 }
3336
3337 static void
3338 bnx_watchdog(struct ifnet *ifp)
3339 {
3340         struct bnx_softc *sc = ifp->if_softc;
3341
3342         if_printf(ifp, "watchdog timeout -- resetting\n");
3343
3344         bnx_init(sc);
3345
3346         IFNET_STAT_INC(ifp, oerrors, 1);
3347
3348         if (!ifq_is_empty(&ifp->if_snd))
3349                 if_devstart(ifp);
3350 }
3351
3352 /*
3353  * Stop the adapter and free any mbufs allocated to the
3354  * RX and TX lists.
3355  */
3356 static void
3357 bnx_stop(struct bnx_softc *sc)
3358 {
3359         struct ifnet *ifp = &sc->arpcom.ac_if;
3360
3361         ASSERT_SERIALIZED(ifp->if_serializer);
3362
3363         callout_stop(&sc->bnx_stat_timer);
3364
3365         /*
3366          * Disable all of the receiver blocks
3367          */
3368         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3369         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3370         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3371         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3372         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3373         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3374
3375         /*
3376          * Disable all of the transmit blocks
3377          */
3378         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3379         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3380         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3381         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3382         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3383         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3384
3385         /*
3386          * Shut down all of the memory managers and related
3387          * state machines.
3388          */
3389         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3390         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3391         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3392         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3393
3394         /* Disable host interrupts. */
3395         bnx_disable_intr(sc);
3396
3397         /*
3398          * Tell firmware we're shutting down.
3399          */
3400         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3401
3402         /* Free the RX lists. */
3403         bnx_free_rx_ring_std(sc);
3404
3405         /* Free jumbo RX list. */
3406         if (BNX_IS_JUMBO_CAPABLE(sc))
3407                 bnx_free_rx_ring_jumbo(sc);
3408
3409         /* Free TX buffers. */
3410         bnx_free_tx_ring(sc);
3411
3412         sc->bnx_status_tag = 0;
3413         sc->bnx_link = 0;
3414         sc->bnx_coal_chg = 0;
3415
3416         sc->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
3417
3418         ifp->if_flags &= ~IFF_RUNNING;
3419         ifq_clr_oactive(&ifp->if_snd);
3420         ifp->if_timer = 0;
3421 }
3422
3423 /*
3424  * Stop all chip I/O so that the kernel's probe routines don't
3425  * get confused by errant DMAs when rebooting.
3426  */
3427 static void
3428 bnx_shutdown(device_t dev)
3429 {
3430         struct bnx_softc *sc = device_get_softc(dev);
3431         struct ifnet *ifp = &sc->arpcom.ac_if;
3432
3433         lwkt_serialize_enter(ifp->if_serializer);
3434         bnx_stop(sc);
3435         bnx_reset(sc);
3436         lwkt_serialize_exit(ifp->if_serializer);
3437 }
3438
3439 static int
3440 bnx_suspend(device_t dev)
3441 {
3442         struct bnx_softc *sc = device_get_softc(dev);
3443         struct ifnet *ifp = &sc->arpcom.ac_if;
3444
3445         lwkt_serialize_enter(ifp->if_serializer);
3446         bnx_stop(sc);
3447         lwkt_serialize_exit(ifp->if_serializer);
3448
3449         return 0;
3450 }
3451
3452 static int
3453 bnx_resume(device_t dev)
3454 {
3455         struct bnx_softc *sc = device_get_softc(dev);
3456         struct ifnet *ifp = &sc->arpcom.ac_if;
3457
3458         lwkt_serialize_enter(ifp->if_serializer);
3459
3460         if (ifp->if_flags & IFF_UP) {
3461                 bnx_init(sc);
3462
3463                 if (!ifq_is_empty(&ifp->if_snd))
3464                         if_devstart(ifp);
3465         }
3466
3467         lwkt_serialize_exit(ifp->if_serializer);
3468
3469         return 0;
3470 }
3471
3472 static void
3473 bnx_setpromisc(struct bnx_softc *sc)
3474 {
3475         struct ifnet *ifp = &sc->arpcom.ac_if;
3476
3477         if (ifp->if_flags & IFF_PROMISC)
3478                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3479         else
3480                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3481 }
3482
3483 static void
3484 bnx_dma_free(struct bnx_softc *sc)
3485 {
3486         int i;
3487
3488         /* Destroy RX mbuf DMA stuffs. */
3489         if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3490                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3491                         bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3492                             sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3493                 }
3494                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3495                                    sc->bnx_cdata.bnx_rx_tmpmap);
3496                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3497         }
3498
3499         /* Destroy TX mbuf DMA stuffs. */
3500         if (sc->bnx_cdata.bnx_tx_mtag != NULL) {
3501                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3502                         bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3503                             sc->bnx_cdata.bnx_tx_dmamap[i]);
3504                 }
3505                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3506         }
3507
3508         /* Destroy standard RX ring */
3509         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3510                            sc->bnx_cdata.bnx_rx_std_ring_map,
3511                            sc->bnx_ldata.bnx_rx_std_ring);
3512
3513         if (BNX_IS_JUMBO_CAPABLE(sc))
3514                 bnx_free_jumbo_mem(sc);
3515
3516         /* Destroy RX return ring */
3517         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3518                            sc->bnx_cdata.bnx_rx_return_ring_map,
3519                            sc->bnx_ldata.bnx_rx_return_ring);
3520
3521         /* Destroy TX ring */
3522         bnx_dma_block_free(sc->bnx_cdata.bnx_tx_ring_tag,
3523                            sc->bnx_cdata.bnx_tx_ring_map,
3524                            sc->bnx_ldata.bnx_tx_ring);
3525
3526         /* Destroy status block */
3527         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3528                            sc->bnx_cdata.bnx_status_map,
3529                            sc->bnx_ldata.bnx_status_block);
3530
3531         /* Destroy the parent tag */
3532         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3533                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3534 }
3535
3536 static int
3537 bnx_dma_alloc(struct bnx_softc *sc)
3538 {
3539         struct ifnet *ifp = &sc->arpcom.ac_if;
3540         bus_size_t txmaxsz;
3541         int i, error;
3542
3543         /*
3544          * Allocate the parent bus DMA tag appropriate for PCI.
3545          *
3546          * All of the NetExtreme/NetLink controllers have 4GB boundary
3547          * DMA bug.
3548          * Whenever an address crosses a multiple of the 4GB boundary
3549          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3550          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3551          * state machine will lockup and cause the device to hang.
3552          */
3553         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3554                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3555                                    NULL, NULL,
3556                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3557                                    BUS_SPACE_MAXSIZE_32BIT,
3558                                    0, &sc->bnx_cdata.bnx_parent_tag);
3559         if (error) {
3560                 if_printf(ifp, "could not allocate parent dma tag\n");
3561                 return error;
3562         }
3563
3564         /*
3565          * Create DMA tag and maps for RX mbufs.
3566          */
3567         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3568                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3569                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3570                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3571                                    &sc->bnx_cdata.bnx_rx_mtag);
3572         if (error) {
3573                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3574                 return error;
3575         }
3576
3577         error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3578                                   BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3579         if (error) {
3580                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3581                 sc->bnx_cdata.bnx_rx_mtag = NULL;
3582                 return error;
3583         }
3584
3585         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3586                 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3587                                           BUS_DMA_WAITOK,
3588                                           &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3589                 if (error) {
3590                         int j;
3591
3592                         for (j = 0; j < i; ++j) {
3593                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3594                                         sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3595                         }
3596                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3597                         sc->bnx_cdata.bnx_rx_mtag = NULL;
3598
3599                         if_printf(ifp, "could not create DMA map for RX\n");
3600                         return error;
3601                 }
3602         }
3603
3604         /*
3605          * Create DMA tag and maps for TX mbufs.
3606          */
3607         if (sc->bnx_flags & BNX_FLAG_TSO)
3608                 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
3609         else
3610                 txmaxsz = BNX_JUMBO_FRAMELEN;
3611         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3612                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3613                                    NULL, NULL,
3614                                    txmaxsz, BNX_NSEG_NEW, PAGE_SIZE,
3615                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3616                                    BUS_DMA_ONEBPAGE,
3617                                    &sc->bnx_cdata.bnx_tx_mtag);
3618         if (error) {
3619                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3620                 return error;
3621         }
3622
3623         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3624                 error = bus_dmamap_create(sc->bnx_cdata.bnx_tx_mtag,
3625                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3626                                           &sc->bnx_cdata.bnx_tx_dmamap[i]);
3627                 if (error) {
3628                         int j;
3629
3630                         for (j = 0; j < i; ++j) {
3631                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3632                                         sc->bnx_cdata.bnx_tx_dmamap[j]);
3633                         }
3634                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3635                         sc->bnx_cdata.bnx_tx_mtag = NULL;
3636
3637                         if_printf(ifp, "could not create DMA map for TX\n");
3638                         return error;
3639                 }
3640         }
3641
3642         /*
3643          * Create DMA stuffs for standard RX ring.
3644          */
3645         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3646                                     &sc->bnx_cdata.bnx_rx_std_ring_tag,
3647                                     &sc->bnx_cdata.bnx_rx_std_ring_map,
3648                                     (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3649                                     &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3650         if (error) {
3651                 if_printf(ifp, "could not create std RX ring\n");
3652                 return error;
3653         }
3654
3655         /*
3656          * Create jumbo buffer pool.
3657          */
3658         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3659                 error = bnx_alloc_jumbo_mem(sc);
3660                 if (error) {
3661                         if_printf(ifp, "could not create jumbo buffer pool\n");
3662                         return error;
3663                 }
3664         }
3665
3666         /*
3667          * Create DMA stuffs for RX return ring.
3668          */
3669         error = bnx_dma_block_alloc(sc,
3670             BGE_RX_RTN_RING_SZ(sc->bnx_return_ring_cnt),
3671             &sc->bnx_cdata.bnx_rx_return_ring_tag,
3672             &sc->bnx_cdata.bnx_rx_return_ring_map,
3673             (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3674             &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3675         if (error) {
3676                 if_printf(ifp, "could not create RX ret ring\n");
3677                 return error;
3678         }
3679
3680         /*
3681          * Create DMA stuffs for TX ring.
3682          */
3683         error = bnx_dma_block_alloc(sc, BGE_TX_RING_SZ,
3684                                     &sc->bnx_cdata.bnx_tx_ring_tag,
3685                                     &sc->bnx_cdata.bnx_tx_ring_map,
3686                                     (void *)&sc->bnx_ldata.bnx_tx_ring,
3687                                     &sc->bnx_ldata.bnx_tx_ring_paddr);
3688         if (error) {
3689                 if_printf(ifp, "could not create TX ring\n");
3690                 return error;
3691         }
3692
3693         /*
3694          * Create DMA stuffs for status block.
3695          */
3696         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3697                                     &sc->bnx_cdata.bnx_status_tag,
3698                                     &sc->bnx_cdata.bnx_status_map,
3699                                     (void *)&sc->bnx_ldata.bnx_status_block,
3700                                     &sc->bnx_ldata.bnx_status_block_paddr);
3701         if (error) {
3702                 if_printf(ifp, "could not create status block\n");
3703                 return error;
3704         }
3705
3706         return 0;
3707 }
3708
3709 static int
3710 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3711                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3712 {
3713         bus_dmamem_t dmem;
3714         int error;
3715
3716         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3717                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3718                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3719         if (error)
3720                 return error;
3721
3722         *tag = dmem.dmem_tag;
3723         *map = dmem.dmem_map;
3724         *addr = dmem.dmem_addr;
3725         *paddr = dmem.dmem_busaddr;
3726
3727         return 0;
3728 }
3729
3730 static void
3731 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3732 {
3733         if (tag != NULL) {
3734                 bus_dmamap_unload(tag, map);
3735                 bus_dmamem_free(tag, addr, map);
3736                 bus_dma_tag_destroy(tag);
3737         }
3738 }
3739
3740 static void
3741 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3742 {
3743         struct ifnet *ifp = &sc->arpcom.ac_if;
3744
3745 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3746
3747         /*
3748          * Sometimes PCS encoding errors are detected in
3749          * TBI mode (on fiber NICs), and for some reason
3750          * the chip will signal them as link changes.
3751          * If we get a link change event, but the 'PCS
3752          * encoding error' bit in the MAC status register
3753          * is set, don't bother doing a link check.
3754          * This avoids spurious "gigabit link up" messages
3755          * that sometimes appear on fiber NICs during
3756          * periods of heavy traffic.
3757          */
3758         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3759                 if (!sc->bnx_link) {
3760                         sc->bnx_link++;
3761                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3762                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3763                                     BGE_MACMODE_TBI_SEND_CFGS);
3764                         }
3765                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3766
3767                         if (bootverbose)
3768                                 if_printf(ifp, "link UP\n");
3769
3770                         ifp->if_link_state = LINK_STATE_UP;
3771                         if_link_state_change(ifp);
3772                 }
3773         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3774                 if (sc->bnx_link) {
3775                         sc->bnx_link = 0;
3776
3777                         if (bootverbose)
3778                                 if_printf(ifp, "link DOWN\n");
3779
3780                         ifp->if_link_state = LINK_STATE_DOWN;
3781                         if_link_state_change(ifp);
3782                 }
3783         }
3784
3785 #undef PCS_ENCODE_ERR
3786
3787         /* Clear the attention. */
3788         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3789             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3790             BGE_MACSTAT_LINK_CHANGED);
3791 }
3792
3793 static void
3794 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3795 {
3796         struct ifnet *ifp = &sc->arpcom.ac_if;
3797         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3798
3799         mii_pollstat(mii);
3800         bnx_miibus_statchg(sc->bnx_dev);
3801
3802         if (bootverbose) {
3803                 if (sc->bnx_link)
3804                         if_printf(ifp, "link UP\n");
3805                 else
3806                         if_printf(ifp, "link DOWN\n");
3807         }
3808
3809         /* Clear the attention. */
3810         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3811             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3812             BGE_MACSTAT_LINK_CHANGED);
3813 }
3814
3815 static void
3816 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3817 {
3818         struct ifnet *ifp = &sc->arpcom.ac_if;
3819         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3820
3821         mii_pollstat(mii);
3822
3823         if (!sc->bnx_link &&
3824             (mii->mii_media_status & IFM_ACTIVE) &&
3825             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3826                 sc->bnx_link++;
3827                 if (bootverbose)
3828                         if_printf(ifp, "link UP\n");
3829         } else if (sc->bnx_link &&
3830             (!(mii->mii_media_status & IFM_ACTIVE) ||
3831             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3832                 sc->bnx_link = 0;
3833                 if (bootverbose)
3834                         if_printf(ifp, "link DOWN\n");
3835         }
3836
3837         /* Clear the attention. */
3838         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3839             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3840             BGE_MACSTAT_LINK_CHANGED);
3841 }
3842
3843 static int
3844 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3845 {
3846         struct bnx_softc *sc = arg1;
3847
3848         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3849             &sc->bnx_rx_coal_ticks,
3850             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3851             BNX_RX_COAL_TICKS_CHG);
3852 }
3853
3854 static int
3855 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3856 {
3857         struct bnx_softc *sc = arg1;
3858
3859         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3860             &sc->bnx_tx_coal_ticks,
3861             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3862             BNX_TX_COAL_TICKS_CHG);
3863 }
3864
3865 static int
3866 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3867 {
3868         struct bnx_softc *sc = arg1;
3869
3870         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3871             &sc->bnx_rx_coal_bds,
3872             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3873             BNX_RX_COAL_BDS_CHG);
3874 }
3875
3876 static int
3877 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3878 {
3879         struct bnx_softc *sc = arg1;
3880
3881         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3882             &sc->bnx_tx_coal_bds,
3883             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3884             BNX_TX_COAL_BDS_CHG);
3885 }
3886
3887 static int
3888 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3889 {
3890         struct bnx_softc *sc = arg1;
3891
3892         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3893             &sc->bnx_rx_coal_bds_int,
3894             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3895             BNX_RX_COAL_BDS_INT_CHG);
3896 }
3897
3898 static int
3899 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3900 {
3901         struct bnx_softc *sc = arg1;
3902
3903         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3904             &sc->bnx_tx_coal_bds_int,
3905             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3906             BNX_TX_COAL_BDS_INT_CHG);
3907 }
3908
3909 static int
3910 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3911     int coal_min, int coal_max, uint32_t coal_chg_mask)
3912 {
3913         struct bnx_softc *sc = arg1;
3914         struct ifnet *ifp = &sc->arpcom.ac_if;
3915         int error = 0, v;
3916
3917         lwkt_serialize_enter(ifp->if_serializer);
3918
3919         v = *coal;
3920         error = sysctl_handle_int(oidp, &v, 0, req);
3921         if (!error && req->newptr != NULL) {
3922                 if (v < coal_min || v > coal_max) {
3923                         error = EINVAL;
3924                 } else {
3925                         *coal = v;
3926                         sc->bnx_coal_chg |= coal_chg_mask;
3927                 }
3928         }
3929
3930         lwkt_serialize_exit(ifp->if_serializer);
3931         return error;
3932 }
3933
3934 static void
3935 bnx_coal_change(struct bnx_softc *sc)
3936 {
3937         struct ifnet *ifp = &sc->arpcom.ac_if;
3938
3939         ASSERT_SERIALIZED(ifp->if_serializer);
3940
3941         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3942                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3943                             sc->bnx_rx_coal_ticks);
3944                 DELAY(10);
3945                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3946
3947                 if (bootverbose) {
3948                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3949                                   sc->bnx_rx_coal_ticks);
3950                 }
3951         }
3952
3953         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3954                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3955                             sc->bnx_tx_coal_ticks);
3956                 DELAY(10);
3957                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3958
3959                 if (bootverbose) {
3960                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3961                                   sc->bnx_tx_coal_ticks);
3962                 }
3963         }
3964
3965         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3966                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3967                             sc->bnx_rx_coal_bds);
3968                 DELAY(10);
3969                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3970
3971                 if (bootverbose) {
3972                         if_printf(ifp, "rx_coal_bds -> %u\n",
3973                                   sc->bnx_rx_coal_bds);
3974                 }
3975         }
3976
3977         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3978                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3979                             sc->bnx_tx_coal_bds);
3980                 DELAY(10);
3981                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3982
3983                 if (bootverbose) {
3984                         if_printf(ifp, "tx_coal_bds -> %u\n",
3985                                   sc->bnx_tx_coal_bds);
3986                 }
3987         }
3988
3989         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3990                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3991                     sc->bnx_rx_coal_bds_int);
3992                 DELAY(10);
3993                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
3994
3995                 if (bootverbose) {
3996                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
3997                             sc->bnx_rx_coal_bds_int);
3998                 }
3999         }
4000
4001         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
4002                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4003                     sc->bnx_tx_coal_bds_int);
4004                 DELAY(10);
4005                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
4006
4007                 if (bootverbose) {
4008                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
4009                             sc->bnx_tx_coal_bds_int);
4010                 }
4011         }
4012
4013         sc->bnx_coal_chg = 0;
4014 }
4015
4016 static void
4017 bnx_intr_check(void *xsc)
4018 {
4019         struct bnx_softc *sc = xsc;
4020         struct ifnet *ifp = &sc->arpcom.ac_if;
4021         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
4022
4023         lwkt_serialize_enter(ifp->if_serializer);
4024
4025         KKASSERT(mycpuid == sc->bnx_intr_cpuid);
4026
4027         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4028                 lwkt_serialize_exit(ifp->if_serializer);
4029                 return;
4030         }
4031
4032         if (sblk->bge_idx[0].bge_rx_prod_idx != sc->bnx_rx_saved_considx ||
4033             sblk->bge_idx[0].bge_tx_cons_idx != sc->bnx_tx_saved_considx) {
4034                 if (sc->bnx_rx_check_considx == sc->bnx_rx_saved_considx &&
4035                     sc->bnx_tx_check_considx == sc->bnx_tx_saved_considx) {
4036                         if (!sc->bnx_intr_maylose) {
4037                                 sc->bnx_intr_maylose = TRUE;
4038                                 goto done;
4039                         }
4040                         if (bootverbose)
4041                                 if_printf(ifp, "lost interrupt\n");
4042                         bnx_msi(sc);
4043                 }
4044         }
4045         sc->bnx_intr_maylose = FALSE;
4046         sc->bnx_rx_check_considx = sc->bnx_rx_saved_considx;
4047         sc->bnx_tx_check_considx = sc->bnx_tx_saved_considx;
4048
4049 done:
4050         callout_reset(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
4051             bnx_intr_check, sc);
4052         lwkt_serialize_exit(ifp->if_serializer);
4053 }
4054
4055 static void
4056 bnx_enable_intr(struct bnx_softc *sc)
4057 {
4058         struct ifnet *ifp = &sc->arpcom.ac_if;
4059
4060         lwkt_serialize_handler_enable(ifp->if_serializer);
4061
4062         /*
4063          * Enable interrupt.
4064          */
4065         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
4066         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4067                 /* XXX Linux driver */
4068                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
4069         }
4070
4071         /*
4072          * Unmask the interrupt when we stop polling.
4073          */
4074         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4075             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4076
4077         /*
4078          * Trigger another interrupt, since above writing
4079          * to interrupt mailbox0 may acknowledge pending
4080          * interrupt.
4081          */
4082         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4083
4084         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
4085                 sc->bnx_intr_maylose = FALSE;
4086                 sc->bnx_rx_check_considx = 0;
4087                 sc->bnx_tx_check_considx = 0;
4088
4089                 if (bootverbose)
4090                         if_printf(ifp, "status tag bug workaround\n");
4091
4092                 /* 10ms check interval */
4093                 callout_reset_bycpu(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
4094                     bnx_intr_check, sc, sc->bnx_intr_cpuid);
4095         }
4096 }
4097
4098 static void
4099 bnx_disable_intr(struct bnx_softc *sc)
4100 {
4101         struct ifnet *ifp = &sc->arpcom.ac_if;
4102
4103         /*
4104          * Mask the interrupt when we start polling.
4105          */
4106         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4107             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4108
4109         /*
4110          * Acknowledge possible asserted interrupt.
4111          */
4112         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4113
4114         callout_stop(&sc->bnx_intr_timer);
4115         sc->bnx_intr_maylose = FALSE;
4116         sc->bnx_rx_check_considx = 0;
4117         sc->bnx_tx_check_considx = 0;
4118
4119         sc->bnx_npoll.ifpc_stcount = 0;
4120
4121         lwkt_serialize_handler_disable(ifp->if_serializer);
4122 }
4123
4124 static int
4125 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
4126 {
4127         uint32_t mac_addr;
4128         int ret = 1;
4129
4130         mac_addr = bnx_readmem_ind(sc, 0x0c14);
4131         if ((mac_addr >> 16) == 0x484b) {
4132                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4133                 ether_addr[1] = (uint8_t)mac_addr;
4134                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4135                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4136                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4137                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4138                 ether_addr[5] = (uint8_t)mac_addr;
4139                 ret = 0;
4140         }
4141         return ret;
4142 }
4143
4144 static int
4145 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4146 {
4147         int mac_offset = BGE_EE_MAC_OFFSET;
4148
4149         if (BNX_IS_5717_PLUS(sc)) {
4150                 int f;
4151
4152                 f = pci_get_function(sc->bnx_dev);
4153                 if (f & 1)
4154                         mac_offset = BGE_EE_MAC_OFFSET_5717;
4155                 if (f > 1)
4156                         mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4157         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
4158                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4159         }
4160
4161         return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4162 }
4163
4164 static int
4165 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4166 {
4167         if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4168                 return 1;
4169
4170         return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4171                                ETHER_ADDR_LEN);
4172 }
4173
4174 static int
4175 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4176 {
4177         static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4178                 /* NOTE: Order is critical */
4179                 bnx_get_eaddr_mem,
4180                 bnx_get_eaddr_nvram,
4181                 bnx_get_eaddr_eeprom,
4182                 NULL
4183         };
4184         const bnx_eaddr_fcn_t *func;
4185
4186         for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4187                 if ((*func)(sc, eaddr) == 0)
4188                         break;
4189         }
4190         return (*func == NULL ? ENXIO : 0);
4191 }
4192
4193 /*
4194  * NOTE: 'm' is not freed upon failure
4195  */
4196 struct mbuf *
4197 bnx_defrag_shortdma(struct mbuf *m)
4198 {
4199         struct mbuf *n;
4200         int found;
4201
4202         /*
4203          * If device receive two back-to-back send BDs with less than
4204          * or equal to 8 total bytes then the device may hang.  The two
4205          * back-to-back send BDs must in the same frame for this failure
4206          * to occur.  Scan mbuf chains and see whether two back-to-back
4207          * send BDs are there.  If this is the case, allocate new mbuf
4208          * and copy the frame to workaround the silicon bug.
4209          */
4210         for (n = m, found = 0; n != NULL; n = n->m_next) {
4211                 if (n->m_len < 8) {
4212                         found++;
4213                         if (found > 1)
4214                                 break;
4215                         continue;
4216                 }
4217                 found = 0;
4218         }
4219
4220         if (found > 1)
4221                 n = m_defrag(m, MB_DONTWAIT);
4222         else
4223                 n = m;
4224         return n;
4225 }
4226
4227 static void
4228 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4229 {
4230         int i;
4231
4232         BNX_CLRBIT(sc, reg, bit);
4233         for (i = 0; i < BNX_TIMEOUT; i++) {
4234                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4235                         return;
4236                 DELAY(100);
4237         }
4238 }
4239
4240 static void
4241 bnx_link_poll(struct bnx_softc *sc)
4242 {
4243         uint32_t status;
4244
4245         status = CSR_READ_4(sc, BGE_MAC_STS);
4246         if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4247                 sc->bnx_link_evt = 0;
4248                 sc->bnx_link_upd(sc, status);
4249         }
4250 }
4251
4252 static void
4253 bnx_enable_msi(struct bnx_softc *sc)
4254 {
4255         uint32_t msi_mode;
4256
4257         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4258         msi_mode |= BGE_MSIMODE_ENABLE;
4259         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4260                 /*
4261                  * NOTE:
4262                  * 5718-PG105-R says that "one shot" mode
4263                  * does not work if MSI is used, however,
4264                  * it obviously works.
4265                  */
4266                 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4267         }
4268         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4269 }
4270
4271 static uint32_t
4272 bnx_dma_swap_options(struct bnx_softc *sc)
4273 {
4274         uint32_t dma_options;
4275
4276         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4277             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4278 #if BYTE_ORDER == BIG_ENDIAN
4279         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4280 #endif
4281         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
4282                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4283                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4284                     BGE_MODECTL_HTX2B_ENABLE;
4285         }
4286         return dma_options;
4287 }
4288
4289 static int
4290 bnx_setup_tso(struct bnx_softc *sc, struct mbuf **mp,
4291     uint16_t *mss0, uint16_t *flags0)
4292 {
4293         struct mbuf *m;
4294         struct ip *ip;
4295         struct tcphdr *th;
4296         int thoff, iphlen, hoff, hlen;
4297         uint16_t flags, mss;
4298
4299         m = *mp;
4300         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4301
4302         hoff = m->m_pkthdr.csum_lhlen;
4303         iphlen = m->m_pkthdr.csum_iphlen;
4304         thoff = m->m_pkthdr.csum_thlen;
4305
4306         KASSERT(hoff > 0, ("invalid ether header len"));
4307         KASSERT(iphlen > 0, ("invalid ip header len"));
4308         KASSERT(thoff > 0, ("invalid tcp header len"));
4309
4310         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4311                 m = m_pullup(m, hoff + iphlen + thoff);
4312                 if (m == NULL) {
4313                         *mp = NULL;
4314                         return ENOBUFS;
4315                 }
4316                 *mp = m;
4317         }
4318         ip = mtodoff(m, struct ip *, hoff);
4319         th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4320
4321         mss = m->m_pkthdr.tso_segsz;
4322         flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4323
4324         ip->ip_len = htons(mss + iphlen + thoff);
4325         th->th_sum = 0;
4326
4327         hlen = (iphlen + thoff) >> 2;
4328         mss |= ((hlen & 0x3) << 14);
4329         flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2);
4330
4331         *mss0 = mss;
4332         *flags0 = flags;
4333
4334         return 0;
4335 }