2 * Copyright © 2011-2012 Intel Corporation
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11 * The above copyright notice and this permission notice (including the next
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded it's state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include <linux/err.h>
93 /* This is a HW constraint. The value below is the largest known requirement
94 * I've seen in a spec to date, and that was a workaround for a non-shipping
95 * part. It should be safe to decrease this, but it's more future proof as is.
97 #define CONTEXT_ALIGN (64<<10)
99 static struct i915_hw_context *
100 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
101 static int do_switch(struct i915_hw_context *to);
103 static int get_context_size(struct drm_device *dev)
105 struct drm_i915_private *dev_priv = dev->dev_private;
109 switch (INTEL_INFO(dev)->gen) {
111 reg = I915_READ(CXT_SIZE);
112 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
115 reg = I915_READ(GEN7_CXT_SIZE);
117 ret = HSW_CXT_TOTAL_SIZE;
119 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
128 void i915_gem_context_free(struct kref *ctx_ref)
130 struct i915_hw_context *ctx = container_of(ctx_ref,
133 drm_gem_object_unreference(&ctx->obj->base);
137 static struct i915_hw_context *
138 create_hw_context(struct drm_device *dev,
139 struct drm_i915_file_private *file_priv)
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 struct i915_hw_context *ctx;
145 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
147 return ERR_PTR(-ENOMEM);
149 kref_init(&ctx->ref);
150 ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size);
151 if (ctx->obj == NULL) {
153 DRM_DEBUG_DRIVER("Context object allocated failed\n");
154 return ERR_PTR(-ENOMEM);
157 if (INTEL_INFO(dev)->gen >= 7) {
158 ret = i915_gem_object_set_cache_level(ctx->obj,
160 /* Failure shouldn't ever happen this early */
165 /* The ring associated with the context object is handled by the normal
166 * object tracking code. We give an initial ring value simple to pass an
167 * assertion in the context switch code.
169 ctx->ring = &dev_priv->ring[RCS];
171 /* Default context will never have a file_priv */
172 if (file_priv == NULL)
175 ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID + 1, 0,
180 ctx->file_priv = file_priv;
186 i915_gem_context_unreference(ctx);
190 static inline bool is_default_context(struct i915_hw_context *ctx)
192 return (ctx == ctx->ring->default_context);
196 * The default context needs to exist per ring that uses contexts. It stores the
197 * context state of the GPU for applications that don't utilize HW contexts, as
198 * well as an idle case.
200 static int create_default_context(struct drm_i915_private *dev_priv)
202 struct i915_hw_context *ctx;
205 DRM_LOCK_ASSERT(dev_priv->dev);
207 ctx = create_hw_context(dev_priv->dev, NULL);
211 /* We may need to do things with the shrinker which require us to
212 * immediately switch back to the default context. This can cause a
213 * problem as pinning the default context also requires GTT space which
214 * may not be available. To avoid this we always pin the
217 dev_priv->ring[RCS].default_context = ctx;
218 ret = i915_gem_object_pin(ctx->obj, CONTEXT_ALIGN, false, false);
220 DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
224 ret = do_switch(ctx);
226 DRM_DEBUG_DRIVER("Switch failed %d\n", ret);
230 DRM_DEBUG_DRIVER("Default HW context loaded\n");
234 i915_gem_object_unpin(ctx->obj);
236 i915_gem_context_unreference(ctx);
240 void i915_gem_context_init(struct drm_device *dev)
242 struct drm_i915_private *dev_priv = dev->dev_private;
244 if (!HAS_HW_CONTEXTS(dev)) {
245 dev_priv->hw_contexts_disabled = true;
246 DRM_DEBUG_DRIVER("Disabling HW Contexts; old hardware\n");
250 /* If called from reset, or thaw... we've been here already */
251 if (dev_priv->hw_contexts_disabled ||
252 dev_priv->ring[RCS].default_context)
255 dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
257 if (dev_priv->hw_context_size > (1<<20)) {
258 dev_priv->hw_contexts_disabled = true;
259 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n");
263 if (create_default_context(dev_priv)) {
264 dev_priv->hw_contexts_disabled = true;
265 DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed\n");
269 DRM_DEBUG_DRIVER("HW context support initialized\n");
272 void i915_gem_context_fini(struct drm_device *dev)
274 struct drm_i915_private *dev_priv = dev->dev_private;
275 struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context;
277 if (dev_priv->hw_contexts_disabled)
280 /* The only known way to stop the gpu from accessing the hw context is
281 * to reset it. Do this as the very last operation to avoid confusing
282 * other code, leading to spurious errors. */
283 intel_gpu_reset(dev);
285 i915_gem_object_unpin(dctx->obj);
287 /* When default context is created and switched to, base object refcount
288 * will be 2 (+1 from object creation and +1 from do_switch()).
289 * i915_gem_context_fini() will be called after gpu_idle() has switched
290 * to default context. So we need to unreference the base object once
291 * to offset the do_switch part, so that i915_gem_context_unreference()
292 * can then free the base object correctly. */
293 drm_gem_object_unreference(&dctx->obj->base);
294 i915_gem_context_unreference(dctx);
297 static int context_idr_cleanup(int id, void *p, void *data)
299 struct i915_hw_context *ctx = p;
301 BUG_ON(id == DEFAULT_CONTEXT_ID);
303 i915_gem_context_unreference(ctx);
307 struct i915_ctx_hang_stats *
308 i915_gem_context_get_hang_stats(struct intel_ring_buffer *ring,
309 struct drm_file *file,
312 struct drm_i915_private *dev_priv = ring->dev->dev_private;
313 struct drm_i915_file_private *file_priv = file->driver_priv;
314 struct i915_hw_context *to;
316 if (dev_priv->hw_contexts_disabled)
317 return ERR_PTR(-ENOENT);
320 return ERR_PTR(-EINVAL);
323 return ERR_PTR(-EINVAL);
325 if (id == DEFAULT_CONTEXT_ID)
326 return &file_priv->hang_stats;
328 to = i915_gem_context_get(file->driver_priv, id);
330 return ERR_PTR(-ENOENT);
332 return &to->hang_stats;
335 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
337 struct drm_i915_file_private *file_priv = file->driver_priv;
339 mutex_lock(&dev->struct_mutex);
340 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
341 idr_destroy(&file_priv->context_idr);
342 mutex_unlock(&dev->struct_mutex);
345 static struct i915_hw_context *
346 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
348 return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id);
352 mi_set_context(struct intel_ring_buffer *ring,
353 struct i915_hw_context *new_context,
358 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
359 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
360 * explicitly, so we rely on the value at ring init, stored in
361 * itlb_before_ctx_switch.
363 if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
364 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
369 ret = intel_ring_begin(ring, 6);
373 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
374 if (IS_GEN7(ring->dev))
375 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
377 intel_ring_emit(ring, MI_NOOP);
379 intel_ring_emit(ring, MI_NOOP);
380 intel_ring_emit(ring, MI_SET_CONTEXT);
381 intel_ring_emit(ring, new_context->obj->gtt_offset |
383 MI_SAVE_EXT_STATE_EN |
384 MI_RESTORE_EXT_STATE_EN |
386 /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
387 intel_ring_emit(ring, MI_NOOP);
389 if (IS_GEN7(ring->dev))
390 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
392 intel_ring_emit(ring, MI_NOOP);
394 intel_ring_advance(ring);
399 static int do_switch(struct i915_hw_context *to)
401 struct intel_ring_buffer *ring = to->ring;
402 struct i915_hw_context *from = ring->last_context;
406 BUG_ON(from != NULL && from->obj != NULL && from->obj->pin_count == 0);
411 ret = i915_gem_object_pin(to->obj, CONTEXT_ALIGN, false, false);
415 /* Clear this page out of any CPU caches for coherent swap-in/out. Note
416 * that thanks to write = false in this call and us not setting any gpu
417 * write domains when putting a context object onto the active list
418 * (when switching away from it), this won't block.
419 * XXX: We need a real interface to do this instead of trickery. */
420 ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
422 i915_gem_object_unpin(to->obj);
426 if (!to->obj->has_global_gtt_mapping)
427 i915_gem_gtt_bind_object(to->obj, to->obj->cache_level);
429 if (!to->is_initialized || is_default_context(to))
430 hw_flags |= MI_RESTORE_INHIBIT;
431 else if (WARN_ON_ONCE(from == to)) /* not yet expected */
432 hw_flags |= MI_FORCE_RESTORE;
434 ret = mi_set_context(ring, to, hw_flags);
436 i915_gem_object_unpin(to->obj);
440 /* The backing object for the context is done after switching to the
441 * *next* context. Therefore we cannot retire the previous context until
442 * the next context has already started running. In fact, the below code
443 * is a bit suboptimal because the retiring can occur simply after the
444 * MI_SET_CONTEXT instead of when the next seqno has completed.
447 from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
448 i915_gem_object_move_to_active(from->obj, ring);
449 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
450 * whole damn pipeline, we don't need to explicitly mark the
451 * object dirty. The only exception is that the context must be
452 * correct in case the object gets swapped out. Ideally we'd be
453 * able to defer doing this until we know the object would be
454 * swapped, but there is no way to do that yet.
456 from->obj->dirty = 1;
457 BUG_ON(from->obj->ring != ring);
459 ret = i915_add_request(ring, NULL);
461 /* Too late, we've already scheduled a context switch.
462 * Try to undo the change so that the hw state is
463 * consistent with out tracking. In case of emergency,
466 WARN_ON(mi_set_context(ring, from, MI_RESTORE_INHIBIT));
470 i915_gem_object_unpin(from->obj);
471 i915_gem_context_unreference(from);
474 i915_gem_context_reference(to);
475 ring->last_context = to;
476 to->is_initialized = true;
482 * i915_switch_context() - perform a GPU context switch.
483 * @ring: ring for which we'll execute the context switch
484 * @file_priv: file_priv associated with the context, may be NULL
485 * @id: context id number
486 * @seqno: sequence number by which the new context will be switched to
489 * The context life cycle is simple. The context refcount is incremented and
490 * decremented by 1 and create and destroy. If the context is in use by the GPU,
491 * it will have a refoucnt > 1. This allows us to destroy the context abstract
492 * object while letting the normal object tracking destroy the backing BO.
494 int i915_switch_context(struct intel_ring_buffer *ring,
495 struct drm_file *file,
498 struct drm_i915_private *dev_priv = ring->dev->dev_private;
499 struct i915_hw_context *to;
501 if (dev_priv->hw_contexts_disabled)
504 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
506 if (ring != &dev_priv->ring[RCS])
509 if (to_id == DEFAULT_CONTEXT_ID) {
510 to = ring->default_context;
515 to = i915_gem_context_get(file->driver_priv, to_id);
520 return do_switch(to);
523 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
524 struct drm_file *file)
526 struct drm_i915_private *dev_priv = dev->dev_private;
527 struct drm_i915_gem_context_create *args = data;
528 struct drm_i915_file_private *file_priv = file->driver_priv;
529 struct i915_hw_context *ctx;
532 if (!(dev->driver->driver_features & DRIVER_GEM))
535 if (dev_priv->hw_contexts_disabled)
538 ret = i915_mutex_lock_interruptible(dev);
542 ctx = create_hw_context(dev, file_priv);
543 mutex_unlock(&dev->struct_mutex);
547 args->ctx_id = ctx->id;
548 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
553 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
554 struct drm_file *file)
556 struct drm_i915_gem_context_destroy *args = data;
557 struct drm_i915_file_private *file_priv = file->driver_priv;
558 struct i915_hw_context *ctx;
561 if (!(dev->driver->driver_features & DRIVER_GEM))
564 ret = i915_mutex_lock_interruptible(dev);
568 ctx = i915_gem_context_get(file_priv, args->ctx_id);
570 mutex_unlock(&dev->struct_mutex);
574 idr_remove(&ctx->file_priv->context_idr, ctx->id);
575 i915_gem_context_unreference(ctx);
576 mutex_unlock(&dev->struct_mutex);
578 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);