sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.83 2007/06/22 11:53:40 sephe Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include "opt_polling.h"
  76 #include <sys/param.h>
  77 #include <sys/bus.h>
  78 #include <sys/endian.h>
  79 #include <sys/kernel.h>
  80 #include <sys/ktr.h>
  81 #include <sys/mbuf.h>
  82 #include <sys/malloc.h>
  83 #include <sys/queue.h>
  84 #include <sys/rman.h>
  85 #include <sys/serialize.h>
  86 #include <sys/socket.h>
  87 #include <sys/sockio.h>
  88 #include <sys/sysctl.h>
  89
  90 #include <net/bpf.h>
  91 #include <net/ethernet.h>
  92 #include <net/if.h>
  93 #include <net/if_arp.h>
  94 #include <net/if_dl.h>
  95 #include <net/if_media.h>
  96 #include <net/if_types.h>
  97 #include <net/ifq_var.h>
  98 #include <net/vlan/if_vlan_var.h>
  99
 100 #include <dev/netif/mii_layer/mii.h>
 101 #include <dev/netif/mii_layer/miivar.h>
 102 #include <dev/netif/mii_layer/brgphyreg.h>
 103
 104 #include <bus/pci/pcidevs.h>
 105 #include <bus/pci/pcireg.h>
 106 #include <bus/pci/pcivar.h>
 107
 108 #include <dev/netif/bge/if_bgereg.h>
 109
 110 /* "device miibus" required.  See GENERIC if you get errors here. */
 111 #include "miibus_if.h"
 112
 113 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 114 #define BGE_MIN_FRAME           60
 115
 116 /*
 117  * Various supported device vendors/types and their names. Note: the
 118  * spec seems to indicate that the hardware still has Alteon's vendor
 119  * ID burned into it, though it will always be overriden by the vendor
 120  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 121  */
 122 #define BGE_DEVDESC_MAX         64      /* Maximum device description length */
 123
 124 static struct bge_type bge_devs[] = {
 125         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
 126                 "3COM 3C996 Gigabit Ethernet" },
 127
 128         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 129                 "Alteon BCM5700 Gigabit Ethernet" },
 130         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 131                 "Alteon BCM5701 Gigabit Ethernet" },
 132
 133         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 134                 "Altima AC1000 Gigabit Ethernet" },
 135         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 136                 "Altima AC1002 Gigabit Ethernet" },
 137         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 138                 "Altima AC9100 Gigabit Ethernet" },
 139
 140         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
 141                 "Apple BCM5701 Gigabit Ethernet" },
 142
 143         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 144                 "Broadcom BCM5700 Gigabit Ethernet" },
 145         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 146                 "Broadcom BCM5701 Gigabit Ethernet" },
 147         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
 148                 "Broadcom BCM5702 Gigabit Ethernet" },
 149         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 150                 "Broadcom BCM5702X Gigabit Ethernet" },
 151         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 152                 "Broadcom BCM5702 Gigabit Ethernet" },
 153         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
 154                 "Broadcom BCM5703 Gigabit Ethernet" },
 155         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 156                 "Broadcom BCM5703X Gigabit Ethernet" },
 157         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 158                 "Broadcom BCM5703 Gigabit Ethernet" },
 159         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 160                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 161         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 162                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 163         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
 164                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 165         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 166                 "Broadcom BCM5705 Gigabit Ethernet" },
 167         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
 168                 "Broadcom BCM5705F Gigabit Ethernet" },
 169         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 170                 "Broadcom BCM5705K Gigabit Ethernet" },
 171         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 172                 "Broadcom BCM5705M Gigabit Ethernet" },
 173         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 174                 "Broadcom BCM5705M Gigabit Ethernet" },
 175         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 176                 "Broadcom BCM5714C Gigabit Ethernet" },
 177         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
 178                 "Broadcom BCM5714S Gigabit Ethernet" },
 179         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
 180                 "Broadcom BCM5715 Gigabit Ethernet" },
 181         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
 182                 "Broadcom BCM5715S Gigabit Ethernet" },
 183         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
 184                 "Broadcom BCM5720 Gigabit Ethernet" },
 185         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 186                 "Broadcom BCM5721 Gigabit Ethernet" },
 187         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
 188                 "Broadcom BCM5722 Gigabit Ethernet" },
 189         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 190                 "Broadcom BCM5750 Gigabit Ethernet" },
 191         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 192                 "Broadcom BCM5750M Gigabit Ethernet" },
 193         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 194                 "Broadcom BCM5751 Gigabit Ethernet" },
 195         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
 196                 "Broadcom BCM5751F Gigabit Ethernet" },
 197         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 198                 "Broadcom BCM5751M Gigabit Ethernet" },
 199         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
 200                 "Broadcom BCM5752 Gigabit Ethernet" },
 201         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
 202                 "Broadcom BCM5752M Gigabit Ethernet" },
 203         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
 204                 "Broadcom BCM5753 Gigabit Ethernet" },
 205         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
 206                 "Broadcom BCM5753F Gigabit Ethernet" },
 207         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
 208                 "Broadcom BCM5753M Gigabit Ethernet" },
 209         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
 210                 "Broadcom BCM5754 Gigabit Ethernet" },
 211         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
 212                 "Broadcom BCM5754M Gigabit Ethernet" },
 213         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
 214                 "Broadcom BCM5755 Gigabit Ethernet" },
 215         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
 216                 "Broadcom BCM5755M Gigabit Ethernet" },
 217         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
 218                 "Broadcom BCM5756 Gigabit Ethernet" },
 219         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
 220                 "Broadcom BCM5780 Gigabit Ethernet" },
 221         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
 222                 "Broadcom BCM5780S Gigabit Ethernet" },
 223         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
 224                 "Broadcom BCM5781 Gigabit Ethernet" },
 225         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 226                 "Broadcom BCM5782 Gigabit Ethernet" },
 227         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
 228                 "Broadcom BCM5786 Gigabit Ethernet" },
 229         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
 230                 "Broadcom BCM5787 Gigabit Ethernet" },
 231         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
 232                 "Broadcom BCM5787F Gigabit Ethernet" },
 233         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
 234                 "Broadcom BCM5787M Gigabit Ethernet" },
 235         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 236                 "Broadcom BCM5788 Gigabit Ethernet" },
 237         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 238                 "Broadcom BCM5789 Gigabit Ethernet" },
 239         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 240                 "Broadcom BCM5901 Fast Ethernet" },
 241         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 242                 "Broadcom BCM5901A2 Fast Ethernet" },
 243         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
 244                 "Broadcom BCM5903M Fast Ethernet" },
 245
 246         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 247                 "SysKonnect Gigabit Ethernet" },
 248
 249         { 0, 0, NULL }
 250 };
 251
 252 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
 253 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
 254 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
 255 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
 256 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
 257
 258 static int      bge_probe(device_t);
 259 static int      bge_attach(device_t);
 260 static int      bge_detach(device_t);
 261 static void     bge_txeof(struct bge_softc *);
 262 static void     bge_rxeof(struct bge_softc *);
 263
 264 static void     bge_tick(void *);
 265 static void     bge_stats_update(struct bge_softc *);
 266 static void     bge_stats_update_regs(struct bge_softc *);
 267 static int      bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
 268
 269 #ifdef DEVICE_POLLING
 270 static void     bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 271 #endif
 272 static void     bge_intr(void *);
 273 static void     bge_start(struct ifnet *);
 274 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 275 static void     bge_init(void *);
 276 static void     bge_stop(struct bge_softc *);
 277 static void     bge_watchdog(struct ifnet *);
 278 static void     bge_shutdown(device_t);
 279 static int      bge_suspend(device_t);
 280 static int      bge_resume(device_t);
 281 static int      bge_ifmedia_upd(struct ifnet *);
 282 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 283
 284 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 285 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 286
 287 static void     bge_setmulti(struct bge_softc *);
 288 static void     bge_setpromisc(struct bge_softc *);
 289
 290 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 291 static void     bge_free_jumbo_mem(struct bge_softc *);
 292 static struct bge_jslot
 293                 *bge_jalloc(struct bge_softc *);
 294 static void     bge_jfree(void *);
 295 static void     bge_jref(void *);
 296 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 297 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 298 static int      bge_init_rx_ring_std(struct bge_softc *);
 299 static void     bge_free_rx_ring_std(struct bge_softc *);
 300 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 301 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 302 static void     bge_free_tx_ring(struct bge_softc *);
 303 static int      bge_init_tx_ring(struct bge_softc *);
 304
 305 static int      bge_chipinit(struct bge_softc *);
 306 static int      bge_blockinit(struct bge_softc *);
 307
 308 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 309 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 310 #ifdef notdef
 311 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 312 #endif
 313 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 314 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
 315
 316 static int      bge_miibus_readreg(device_t, int, int);
 317 static int      bge_miibus_writereg(device_t, int, int, int);
 318 static void     bge_miibus_statchg(device_t);
 319 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
 320 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
 321 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
 322
 323 static void     bge_reset(struct bge_softc *);
 324
 325 static void     bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 326 static void     bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
 327                                  bus_size_t, int);
 328 static int      bge_dma_alloc(struct bge_softc *);
 329 static void     bge_dma_free(struct bge_softc *);
 330 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
 331                                     bus_dma_tag_t *, bus_dmamap_t *,
 332                                     void **, bus_addr_t *);
 333 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 334
 335 static void     bge_coal_change(struct bge_softc *);
 336 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 337 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 338 static int      bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 339 static int      bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
 340 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
 341
 342 /*
 343  * Set following tunable to 1 for some IBM blade servers with the DNLK
 344  * switch module. Auto negotiation is broken for those configurations.
 345  */
 346 static int      bge_fake_autoneg = 0;
 347 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 348
 349 /* Interrupt moderation control variables. */
 350 static int      bge_rx_coal_ticks = 150;        /* usec */
 351 static int      bge_tx_coal_ticks = 1000000;    /* usec */
 352 static int      bge_rx_max_coal_bds = 16;
 353 static int      bge_tx_max_coal_bds = 32;
 354
 355 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
 356 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
 357 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
 358 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
 359
 360 #if !defined(KTR_IF_BGE)
 361 #define KTR_IF_BGE      KTR_ALL
 362 #endif
 363 KTR_INFO_MASTER(if_bge);
 364 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr", 0);
 365 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt", 0);
 366 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt", 0);
 367 #define logif(name)     KTR_LOG(if_bge_ ## name)
 368
 369 static device_method_t bge_methods[] = {
 370         /* Device interface */
 371         DEVMETHOD(device_probe,         bge_probe),
 372         DEVMETHOD(device_attach,        bge_attach),
 373         DEVMETHOD(device_detach,        bge_detach),
 374         DEVMETHOD(device_shutdown,      bge_shutdown),
 375         DEVMETHOD(device_suspend,       bge_suspend),
 376         DEVMETHOD(device_resume,        bge_resume),
 377
 378         /* bus interface */
 379         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 380         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 381
 382         /* MII interface */
 383         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 384         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 385         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 386
 387         { 0, 0 }
 388 };
 389
 390 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 391 static devclass_t bge_devclass;
 392
 393 DECLARE_DUMMY_MODULE(if_bge);
 394 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 395 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 396
 397 static uint32_t
 398 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 399 {
 400         device_t dev = sc->bge_dev;
 401         uint32_t val;
 402
 403         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 404         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 405         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 406         return (val);
 407 }
 408
 409 static void
 410 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 411 {
 412         device_t dev = sc->bge_dev;
 413
 414         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 415         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 416         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 417 }
 418
 419 #ifdef notdef
 420 static uint32_t
 421 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 422 {
 423         device_t dev = sc->bge_dev;
 424
 425         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 426         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 427 }
 428 #endif
 429
 430 static void
 431 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 432 {
 433         device_t dev = sc->bge_dev;
 434
 435         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 436         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 437 }
 438
 439 static void
 440 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
 441 {
 442         CSR_WRITE_4(sc, off, val);
 443 }
 444
 445 /*
 446  * Read a byte of data stored in the EEPROM at address 'addr.' The
 447  * BCM570x supports both the traditional bitbang interface and an
 448  * auto access interface for reading the EEPROM. We use the auto
 449  * access method.
 450  */
 451 static uint8_t
 452 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 453 {
 454         int i;
 455         uint32_t byte = 0;
 456
 457         /*
 458          * Enable use of auto EEPROM access so we can avoid
 459          * having to use the bitbang method.
 460          */
 461         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 462
 463         /* Reset the EEPROM, load the clock period. */
 464         CSR_WRITE_4(sc, BGE_EE_ADDR,
 465             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 466         DELAY(20);
 467
 468         /* Issue the read EEPROM command. */
 469         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 470
 471         /* Wait for completion */
 472         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 473                 DELAY(10);
 474                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 475                         break;
 476         }
 477
 478         if (i == BGE_TIMEOUT) {
 479                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 480                 return(1);
 481         }
 482
 483         /* Get result. */
 484         byte = CSR_READ_4(sc, BGE_EE_DATA);
 485
 486         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 487
 488         return(0);
 489 }
 490
 491 /*
 492  * Read a sequence of bytes from the EEPROM.
 493  */
 494 static int
 495 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 496 {
 497         size_t i;
 498         int err;
 499         uint8_t byte;
 500
 501         for (byte = 0, err = 0, i = 0; i < len; i++) {
 502                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 503                 if (err)
 504                         break;
 505                 *(dest + i) = byte;
 506         }
 507
 508         return(err ? 1 : 0);
 509 }
 510
 511 static int
 512 bge_miibus_readreg(device_t dev, int phy, int reg)
 513 {
 514         struct bge_softc *sc;
 515         struct ifnet *ifp;
 516         uint32_t val, autopoll;
 517         int i;
 518
 519         sc = device_get_softc(dev);
 520         ifp = &sc->arpcom.ac_if;
 521
 522         /*
 523          * Broadcom's own driver always assumes the internal
 524          * PHY is at GMII address 1. On some chips, the PHY responds
 525          * to accesses at all addresses, which could cause us to
 526          * bogusly attach the PHY 32 times at probe type. Always
 527          * restricting the lookup to address 1 is simpler than
 528          * trying to figure out which chips revisions should be
 529          * special-cased.
 530          */
 531         if (phy != 1)
 532                 return(0);
 533
 534         /* Reading with autopolling on may trigger PCI errors */
 535         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 536         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 537                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 538                 DELAY(40);
 539         }
 540
 541         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 542             BGE_MIPHY(phy)|BGE_MIREG(reg));
 543
 544         for (i = 0; i < BGE_TIMEOUT; i++) {
 545                 val = CSR_READ_4(sc, BGE_MI_COMM);
 546                 if (!(val & BGE_MICOMM_BUSY))
 547                         break;
 548         }
 549
 550         if (i == BGE_TIMEOUT) {
 551                 if_printf(ifp, "PHY read timed out\n");
 552                 val = 0;
 553                 goto done;
 554         }
 555
 556         val = CSR_READ_4(sc, BGE_MI_COMM);
 557
 558 done:
 559         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 560                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 561                 DELAY(40);
 562         }
 563
 564         if (val & BGE_MICOMM_READFAIL)
 565                 return(0);
 566
 567         return(val & 0xFFFF);
 568 }
 569
 570 static int
 571 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 572 {
 573         struct bge_softc *sc;
 574         uint32_t autopoll;
 575         int i;
 576
 577         sc = device_get_softc(dev);
 578
 579         /* Reading with autopolling on may trigger PCI errors */
 580         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 581         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 582                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 583                 DELAY(40);
 584         }
 585
 586         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 587             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 588
 589         for (i = 0; i < BGE_TIMEOUT; i++) {
 590                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
 591                         break;
 592         }
 593
 594         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 595                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 596                 DELAY(40);
 597         }
 598
 599         if (i == BGE_TIMEOUT) {
 600                 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
 601                 return(0);
 602         }
 603
 604         return(0);
 605 }
 606
 607 static void
 608 bge_miibus_statchg(device_t dev)
 609 {
 610         struct bge_softc *sc;
 611         struct mii_data *mii;
 612
 613         sc = device_get_softc(dev);
 614         mii = device_get_softc(sc->bge_miibus);
 615
 616         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 617         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 618                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 619         } else {
 620                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 621         }
 622
 623         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 624                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 625         } else {
 626                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 627         }
 628 }
 629
 630 /*
 631  * Memory management for jumbo frames.
 632  */
 633 static int
 634 bge_alloc_jumbo_mem(struct bge_softc *sc)
 635 {
 636         struct ifnet *ifp = &sc->arpcom.ac_if;
 637         struct bge_jslot *entry;
 638         uint8_t *ptr;
 639         bus_addr_t paddr;
 640         int i, error;
 641
 642         /*
 643          * Create tag for jumbo mbufs.
 644          * This is really a bit of a kludge. We allocate a special
 645          * jumbo buffer pool which (thanks to the way our DMA
 646          * memory allocation works) will consist of contiguous
 647          * pages. This means that even though a jumbo buffer might
 648          * be larger than a page size, we don't really need to
 649          * map it into more than one DMA segment. However, the
 650          * default mbuf tag will result in multi-segment mappings,
 651          * so we have to create a special jumbo mbuf tag that
 652          * lets us get away with mapping the jumbo buffers as
 653          * a single segment. I think eventually the driver should
 654          * be changed so that it uses ordinary mbufs and cluster
 655          * buffers, i.e. jumbo frames can span multiple DMA
 656          * descriptors. But that's a project for another day.
 657          */
 658
 659         /*
 660          * Create DMA stuffs for jumbo RX ring.
 661          */
 662         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 663                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
 664                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
 665                                     (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
 666                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 667         if (error) {
 668                 if_printf(ifp, "could not create jumbo RX ring\n");
 669                 return error;
 670         }
 671
 672         /*
 673          * Create DMA stuffs for jumbo buffer block.
 674          */
 675         error = bge_dma_block_alloc(sc, BGE_JMEM,
 676                                     &sc->bge_cdata.bge_jumbo_tag,
 677                                     &sc->bge_cdata.bge_jumbo_map,
 678                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
 679                                     &paddr);
 680         if (error) {
 681                 if_printf(ifp, "could not create jumbo buffer\n");
 682                 return error;
 683         }
 684
 685         SLIST_INIT(&sc->bge_jfree_listhead);
 686
 687         /*
 688          * Now divide it up into 9K pieces and save the addresses
 689          * in an array. Note that we play an evil trick here by using
 690          * the first few bytes in the buffer to hold the the address
 691          * of the softc structure for this interface. This is because
 692          * bge_jfree() needs it, but it is called by the mbuf management
 693          * code which will not pass it to us explicitly.
 694          */
 695         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
 696                 entry = &sc->bge_cdata.bge_jslots[i];
 697                 entry->bge_sc = sc;
 698                 entry->bge_buf = ptr;
 699                 entry->bge_paddr = paddr;
 700                 entry->bge_inuse = 0;
 701                 entry->bge_slot = i;
 702                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 703
 704                 ptr += BGE_JLEN;
 705                 paddr += BGE_JLEN;
 706         }
 707         return 0;
 708 }
 709
 710 static void
 711 bge_free_jumbo_mem(struct bge_softc *sc)
 712 {
 713         /* Destroy jumbo RX ring. */
 714         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 715                            sc->bge_cdata.bge_rx_jumbo_ring_map,
 716                            sc->bge_ldata.bge_rx_jumbo_ring);
 717
 718         /* Destroy jumbo buffer block. */
 719         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
 720                            sc->bge_cdata.bge_jumbo_map,
 721                            sc->bge_ldata.bge_jumbo_buf);
 722 }
 723
 724 /*
 725  * Allocate a jumbo buffer.
 726  */
 727 static struct bge_jslot *
 728 bge_jalloc(struct bge_softc *sc)
 729 {
 730         struct bge_jslot *entry;
 731
 732         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 733         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 734         if (entry) {
 735                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 736                 entry->bge_inuse = 1;
 737         } else {
 738                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 739         }
 740         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 741         return(entry);
 742 }
 743
 744 /*
 745  * Adjust usage count on a jumbo buffer.
 746  */
 747 static void
 748 bge_jref(void *arg)
 749 {
 750         struct bge_jslot *entry = (struct bge_jslot *)arg;
 751         struct bge_softc *sc = entry->bge_sc;
 752
 753         if (sc == NULL)
 754                 panic("bge_jref: can't find softc pointer!");
 755
 756         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 757                 panic("bge_jref: asked to reference buffer "
 758                     "that we don't manage!");
 759         } else if (entry->bge_inuse == 0) {
 760                 panic("bge_jref: buffer already free!");
 761         } else {
 762                 atomic_add_int(&entry->bge_inuse, 1);
 763         }
 764 }
 765
 766 /*
 767  * Release a jumbo buffer.
 768  */
 769 static void
 770 bge_jfree(void *arg)
 771 {
 772         struct bge_jslot *entry = (struct bge_jslot *)arg;
 773         struct bge_softc *sc = entry->bge_sc;
 774
 775         if (sc == NULL)
 776                 panic("bge_jfree: can't find softc pointer!");
 777
 778         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 779                 panic("bge_jfree: asked to free buffer that we don't manage!");
 780         } else if (entry->bge_inuse == 0) {
 781                 panic("bge_jfree: buffer already free!");
 782         } else {
 783                 /*
 784                  * Possible MP race to 0, use the serializer.  The atomic insn
 785                  * is still needed for races against bge_jref().
 786                  */
 787                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 788                 atomic_subtract_int(&entry->bge_inuse, 1);
 789                 if (entry->bge_inuse == 0) {
 790                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 791                                           entry, jslot_link);
 792                 }
 793                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 794         }
 795 }
 796
 797
 798 /*
 799  * Intialize a standard receive ring descriptor.
 800  */
 801 static int
 802 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 803 {
 804         struct mbuf *m_new = NULL;
 805         struct bge_dmamap_arg ctx;
 806         bus_dma_segment_t seg;
 807         struct bge_rx_bd *r;
 808         int error;
 809
 810         if (m == NULL) {
 811                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 812                 if (m_new == NULL)
 813                         return ENOBUFS;
 814         } else {
 815                 m_new = m;
 816                 m_new->m_data = m_new->m_ext.ext_buf;
 817         }
 818         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 819
 820         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 821                 m_adj(m_new, ETHER_ALIGN);
 822
 823         ctx.bge_maxsegs = 1;
 824         ctx.bge_segs = &seg;
 825         error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
 826                                      sc->bge_cdata.bge_rx_std_dmamap[i],
 827                                      m_new, bge_dma_map_mbuf, &ctx,
 828                                      BUS_DMA_NOWAIT);
 829         if (error || ctx.bge_maxsegs == 0) {
 830                 if (m == NULL)
 831                         m_freem(m_new);
 832                 return ENOMEM;
 833         }
 834
 835         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 836
 837         r = &sc->bge_ldata.bge_rx_std_ring[i];
 838         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
 839         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
 840         r->bge_flags = BGE_RXBDFLAG_END;
 841         r->bge_len = m_new->m_len;
 842         r->bge_idx = i;
 843
 844         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
 845                         sc->bge_cdata.bge_rx_std_dmamap[i],
 846                         BUS_DMASYNC_PREREAD);
 847         return 0;
 848 }
 849
 850 /*
 851  * Initialize a jumbo receive ring descriptor. This allocates
 852  * a jumbo buffer from the pool managed internally by the driver.
 853  */
 854 static int
 855 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 856 {
 857         struct mbuf *m_new = NULL;
 858         struct bge_jslot *buf;
 859         struct bge_rx_bd *r;
 860         bus_addr_t paddr;
 861
 862         if (m == NULL) {
 863                 /* Allocate the mbuf. */
 864                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 865                 if (m_new == NULL)
 866                         return(ENOBUFS);
 867
 868                 /* Allocate the jumbo buffer */
 869                 buf = bge_jalloc(sc);
 870                 if (buf == NULL) {
 871                         m_freem(m_new);
 872                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 873                             "-- packet dropped!\n");
 874                         return ENOBUFS;
 875                 }
 876
 877                 /* Attach the buffer to the mbuf. */
 878                 m_new->m_ext.ext_arg = buf;
 879                 m_new->m_ext.ext_buf = buf->bge_buf;
 880                 m_new->m_ext.ext_free = bge_jfree;
 881                 m_new->m_ext.ext_ref = bge_jref;
 882                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 883
 884                 m_new->m_flags |= M_EXT;
 885         } else {
 886                 KKASSERT(m->m_flags & M_EXT);
 887                 m_new = m;
 888                 buf = m_new->m_ext.ext_arg;
 889         }
 890         m_new->m_data = m_new->m_ext.ext_buf;
 891         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 892
 893         paddr = buf->bge_paddr;
 894         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
 895                 m_adj(m_new, ETHER_ALIGN);
 896                 paddr += ETHER_ALIGN;
 897         }
 898
 899         /* Set up the descriptor. */
 900         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 901
 902         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
 903         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
 904         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
 905         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 906         r->bge_len = m_new->m_len;
 907         r->bge_idx = i;
 908
 909         return 0;
 910 }
 911
 912 /*
 913  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 914  * that's 1MB or memory, which is a lot. For now, we fill only the first
 915  * 256 ring entries and hope that our CPU is fast enough to keep up with
 916  * the NIC.
 917  */
 918 static int
 919 bge_init_rx_ring_std(struct bge_softc *sc)
 920 {
 921         int i;
 922
 923         for (i = 0; i < BGE_SSLOTS; i++) {
 924                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 925                         return(ENOBUFS);
 926         };
 927
 928         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
 929                         sc->bge_cdata.bge_rx_std_ring_map,
 930                         BUS_DMASYNC_PREWRITE);
 931
 932         sc->bge_std = i - 1;
 933         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 934
 935         return(0);
 936 }
 937
 938 static void
 939 bge_free_rx_ring_std(struct bge_softc *sc)
 940 {
 941         int i;
 942
 943         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 944                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 945                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
 946                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
 947                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 948                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 949                 }
 950                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
 951                     sizeof(struct bge_rx_bd));
 952         }
 953 }
 954
 955 static int
 956 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 957 {
 958         int i;
 959         struct bge_rcb *rcb;
 960
 961         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 962                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 963                         return(ENOBUFS);
 964         };
 965
 966         bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
 967                         sc->bge_cdata.bge_rx_jumbo_ring_map,
 968                         BUS_DMASYNC_PREWRITE);
 969
 970         sc->bge_jumbo = i - 1;
 971
 972         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
 973         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 974         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 975
 976         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 977
 978         return(0);
 979 }
 980
 981 static void
 982 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 983 {
 984         int i;
 985
 986         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 987                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 988                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
 989                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
 990                 }
 991                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
 992                     sizeof(struct bge_rx_bd));
 993         }
 994 }
 995
 996 static void
 997 bge_free_tx_ring(struct bge_softc *sc)
 998 {
 999         int i;
1000
1001         for (i = 0; i < BGE_TX_RING_CNT; i++) {
1002                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1003                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1004                                           sc->bge_cdata.bge_tx_dmamap[i]);
1005                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
1006                         sc->bge_cdata.bge_tx_chain[i] = NULL;
1007                 }
1008                 bzero(&sc->bge_ldata.bge_tx_ring[i],
1009                     sizeof(struct bge_tx_bd));
1010         }
1011 }
1012
1013 static int
1014 bge_init_tx_ring(struct bge_softc *sc)
1015 {
1016         sc->bge_txcnt = 0;
1017         sc->bge_tx_saved_considx = 0;
1018         sc->bge_tx_prodidx = 0;
1019
1020         /* Initialize transmit producer index for host-memory send ring. */
1021         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1022
1023         /* 5700 b2 errata */
1024         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1025                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1026
1027         CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1028         /* 5700 b2 errata */
1029         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1030                 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1031
1032         return(0);
1033 }
1034
1035 static void
1036 bge_setmulti(struct bge_softc *sc)
1037 {
1038         struct ifnet *ifp;
1039         struct ifmultiaddr *ifma;
1040         uint32_t hashes[4] = { 0, 0, 0, 0 };
1041         int h, i;
1042
1043         ifp = &sc->arpcom.ac_if;
1044
1045         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1046                 for (i = 0; i < 4; i++)
1047                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1048                 return;
1049         }
1050
1051         /* First, zot all the existing filters. */
1052         for (i = 0; i < 4; i++)
1053                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1054
1055         /* Now program new ones. */
1056         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1057                 if (ifma->ifma_addr->sa_family != AF_LINK)
1058                         continue;
1059                 h = ether_crc32_le(
1060                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1061                     ETHER_ADDR_LEN) & 0x7f;
1062                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1063         }
1064
1065         for (i = 0; i < 4; i++)
1066                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1067 }
1068
1069 /*
1070  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1071  * self-test results.
1072  */
1073 static int
1074 bge_chipinit(struct bge_softc *sc)
1075 {
1076         int i;
1077         uint32_t dma_rw_ctl;
1078
1079         /* Set endian type before we access any non-PCI registers. */
1080         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1081
1082         /*
1083          * Check the 'ROM failed' bit on the RX CPU to see if
1084          * self-tests passed.
1085          */
1086         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1087                 if_printf(&sc->arpcom.ac_if,
1088                           "RX CPU self-diagnostics failed!\n");
1089                 return(ENODEV);
1090         }
1091
1092         /* Clear the MAC control register */
1093         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1094
1095         /*
1096          * Clear the MAC statistics block in the NIC's
1097          * internal memory.
1098          */
1099         for (i = BGE_STATS_BLOCK;
1100             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1101                 BGE_MEMWIN_WRITE(sc, i, 0);
1102
1103         for (i = BGE_STATUS_BLOCK;
1104             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1105                 BGE_MEMWIN_WRITE(sc, i, 0);
1106
1107         /* Set up the PCI DMA control register. */
1108         if (sc->bge_flags & BGE_FLAG_PCIE) {
1109                 /* PCI Express */
1110                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1111                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1112                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1113         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1114                 /* PCI-X bus */
1115                 if (BGE_IS_5714_FAMILY(sc)) {
1116                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1117                         dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1118                         /* XXX magic values, Broadcom-supplied Linux driver */
1119                         if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1120                                 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1121                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1122                         } else {
1123                                 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1124                         }
1125                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1126                         /*
1127                          * The 5704 uses a different encoding of read/write
1128                          * watermarks.
1129                          */
1130                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1131                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1132                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1133                 } else {
1134                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1135                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1136                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1137                             (0x0F);
1138                 }
1139
1140                 /*
1141                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1142                  * for hardware bugs.
1143                  */
1144                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1145                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1146                         uint32_t tmp;
1147
1148                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1149                         if (tmp == 0x6 || tmp == 0x7)
1150                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1151                 }
1152         } else {
1153                 /* Conventional PCI bus */
1154                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1155                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1156                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1157                     (0x0F);
1158         }
1159
1160         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1161             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1162             sc->bge_asicrev == BGE_ASICREV_BCM5705)
1163                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1164         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1165
1166         /*
1167          * Set up general mode register.
1168          */
1169         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1170             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1171             BGE_MODECTL_TX_NO_PHDR_CSUM);
1172
1173         /*
1174          * Disable memory write invalidate.  Apparently it is not supported
1175          * properly by these devices.
1176          */
1177         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1178
1179         /* Set the timer prescaler (always 66Mhz) */
1180         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1181
1182         return(0);
1183 }
1184
1185 static int
1186 bge_blockinit(struct bge_softc *sc)
1187 {
1188         struct bge_rcb *rcb;
1189         bus_size_t vrcb;
1190         bge_hostaddr taddr;
1191         uint32_t val;
1192         int i;
1193
1194         /*
1195          * Initialize the memory window pointer register so that
1196          * we can access the first 32K of internal NIC RAM. This will
1197          * allow us to set up the TX send ring RCBs and the RX return
1198          * ring RCBs, plus other things which live in NIC memory.
1199          */
1200         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1201
1202         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1203
1204         if (!BGE_IS_5705_PLUS(sc)) {
1205                 /* Configure mbuf memory pool */
1206                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1207                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1208                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1209                 else
1210                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1211
1212                 /* Configure DMA resource pool */
1213                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1214                     BGE_DMA_DESCRIPTORS);
1215                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1216         }
1217
1218         /* Configure mbuf pool watermarks */
1219         if (BGE_IS_5705_PLUS(sc)) {
1220                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1221                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1222         } else {
1223                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1224                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1225         }
1226         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1227
1228         /* Configure DMA resource watermarks */
1229         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1230         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1231
1232         /* Enable buffer manager */
1233         if (!BGE_IS_5705_PLUS(sc)) {
1234                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1235                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1236
1237                 /* Poll for buffer manager start indication */
1238                 for (i = 0; i < BGE_TIMEOUT; i++) {
1239                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1240                                 break;
1241                         DELAY(10);
1242                 }
1243
1244                 if (i == BGE_TIMEOUT) {
1245                         if_printf(&sc->arpcom.ac_if,
1246                                   "buffer manager failed to start\n");
1247                         return(ENXIO);
1248                 }
1249         }
1250
1251         /* Enable flow-through queues */
1252         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1253         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1254
1255         /* Wait until queue initialization is complete */
1256         for (i = 0; i < BGE_TIMEOUT; i++) {
1257                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1258                         break;
1259                 DELAY(10);
1260         }
1261
1262         if (i == BGE_TIMEOUT) {
1263                 if_printf(&sc->arpcom.ac_if,
1264                           "flow-through queue init failed\n");
1265                 return(ENXIO);
1266         }
1267
1268         /* Initialize the standard RX ring control block */
1269         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1270         rcb->bge_hostaddr.bge_addr_lo =
1271             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1272         rcb->bge_hostaddr.bge_addr_hi =
1273             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1274         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1275             sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1276         if (BGE_IS_5705_PLUS(sc))
1277                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1278         else
1279                 rcb->bge_maxlen_flags =
1280                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1281         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1282         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1283         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1284         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1285         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1286
1287         /*
1288          * Initialize the jumbo RX ring control block
1289          * We set the 'ring disabled' bit in the flags
1290          * field until we're actually ready to start
1291          * using this ring (i.e. once we set the MTU
1292          * high enough to require it).
1293          */
1294         if (BGE_IS_JUMBO_CAPABLE(sc)) {
1295                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1296
1297                 rcb->bge_hostaddr.bge_addr_lo =
1298                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1299                 rcb->bge_hostaddr.bge_addr_hi =
1300                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1301                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1302                     sc->bge_cdata.bge_rx_jumbo_ring_map,
1303                     BUS_DMASYNC_PREREAD);
1304                 rcb->bge_maxlen_flags =
1305                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1306                     BGE_RCB_FLAG_RING_DISABLED);
1307                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1308                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1309                     rcb->bge_hostaddr.bge_addr_hi);
1310                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1311                     rcb->bge_hostaddr.bge_addr_lo);
1312                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1313                     rcb->bge_maxlen_flags);
1314                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1315
1316                 /* Set up dummy disabled mini ring RCB */
1317                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1318                 rcb->bge_maxlen_flags =
1319                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1320                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1321                     rcb->bge_maxlen_flags);
1322         }
1323
1324         /*
1325          * Set the BD ring replentish thresholds. The recommended
1326          * values are 1/8th the number of descriptors allocated to
1327          * each ring.
1328          */
1329         if (BGE_IS_5705_PLUS(sc))
1330                 val = 8;
1331         else
1332                 val = BGE_STD_RX_RING_CNT / 8;
1333         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1334         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1335
1336         /*
1337          * Disable all unused send rings by setting the 'ring disabled'
1338          * bit in the flags field of all the TX send ring control blocks.
1339          * These are located in NIC memory.
1340          */
1341         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1342         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1343                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1344                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1345                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1346                 vrcb += sizeof(struct bge_rcb);
1347         }
1348
1349         /* Configure TX RCB 0 (we use only the first ring) */
1350         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1351         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1352         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1353         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1354         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1355             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1356         if (!BGE_IS_5705_PLUS(sc)) {
1357                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1358                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1359         }
1360
1361         /* Disable all unused RX return rings */
1362         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1363         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1364                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1365                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1366                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1367                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1368                     BGE_RCB_FLAG_RING_DISABLED));
1369                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1370                 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1371                     (i * (sizeof(uint64_t))), 0);
1372                 vrcb += sizeof(struct bge_rcb);
1373         }
1374
1375         /* Initialize RX ring indexes */
1376         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1377         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1378         CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1379
1380         /*
1381          * Set up RX return ring 0
1382          * Note that the NIC address for RX return rings is 0x00000000.
1383          * The return rings live entirely within the host, so the
1384          * nicaddr field in the RCB isn't used.
1385          */
1386         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1387         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1388         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1389         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1390         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1391         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1392             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1393
1394         /* Set random backoff seed for TX */
1395         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1396             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1397             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1398             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1399             BGE_TX_BACKOFF_SEED_MASK);
1400
1401         /* Set inter-packet gap */
1402         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1403
1404         /*
1405          * Specify which ring to use for packets that don't match
1406          * any RX rules.
1407          */
1408         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1409
1410         /*
1411          * Configure number of RX lists. One interrupt distribution
1412          * list, sixteen active lists, one bad frames class.
1413          */
1414         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1415
1416         /* Inialize RX list placement stats mask. */
1417         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1418         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1419
1420         /* Disable host coalescing until we get it set up */
1421         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1422
1423         /* Poll to make sure it's shut down. */
1424         for (i = 0; i < BGE_TIMEOUT; i++) {
1425                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1426                         break;
1427                 DELAY(10);
1428         }
1429
1430         if (i == BGE_TIMEOUT) {
1431                 if_printf(&sc->arpcom.ac_if,
1432                           "host coalescing engine failed to idle\n");
1433                 return(ENXIO);
1434         }
1435
1436         /* Set up host coalescing defaults */
1437         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1438         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1439         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1440         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1441         if (!BGE_IS_5705_PLUS(sc)) {
1442                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1443                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1444         }
1445         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1446         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1447
1448         /* Set up address of statistics block */
1449         if (!BGE_IS_5705_PLUS(sc)) {
1450                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1451                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1452                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1453                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1454
1455                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1456                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1457                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1458         }
1459
1460         /* Set up address of status block */
1461         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1462             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1463         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1464             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1465         sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1466         sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1467
1468         /* Turn on host coalescing state machine */
1469         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1470
1471         /* Turn on RX BD completion state machine and enable attentions */
1472         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1473             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1474
1475         /* Turn on RX list placement state machine */
1476         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1477
1478         /* Turn on RX list selector state machine. */
1479         if (!BGE_IS_5705_PLUS(sc))
1480                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1481
1482         /* Turn on DMA, clear stats */
1483         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1484             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1485             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1486             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1487             ((sc->bge_flags & BGE_FLAG_TBI) ?
1488              BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1489
1490         /* Set misc. local control, enable interrupts on attentions */
1491         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1492
1493 #ifdef notdef
1494         /* Assert GPIO pins for PHY reset */
1495         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1496             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1497         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1498             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1499 #endif
1500
1501         /* Turn on DMA completion state machine */
1502         if (!BGE_IS_5705_PLUS(sc))
1503                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1504
1505         /* Turn on write DMA state machine */
1506         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1507         if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1508             sc->bge_asicrev == BGE_ASICREV_BCM5787)
1509                 val |= (1 << 29);       /* Enable host coalescing bug fix. */
1510         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1511
1512         /* Turn on read DMA state machine */
1513         CSR_WRITE_4(sc, BGE_RDMA_MODE,
1514             BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1515
1516         /* Turn on RX data completion state machine */
1517         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1518
1519         /* Turn on RX BD initiator state machine */
1520         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1521
1522         /* Turn on RX data and RX BD initiator state machine */
1523         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1524
1525         /* Turn on Mbuf cluster free state machine */
1526         if (!BGE_IS_5705_PLUS(sc))
1527                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1528
1529         /* Turn on send BD completion state machine */
1530         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1531
1532         /* Turn on send data completion state machine */
1533         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1534
1535         /* Turn on send data initiator state machine */
1536         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1537
1538         /* Turn on send BD initiator state machine */
1539         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1540
1541         /* Turn on send BD selector state machine */
1542         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1543
1544         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1545         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1546             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1547
1548         /* ack/clear link change events */
1549         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1550             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1551             BGE_MACSTAT_LINK_CHANGED);
1552         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1553
1554         /* Enable PHY auto polling (for MII/GMII only) */
1555         if (sc->bge_flags & BGE_FLAG_TBI) {
1556                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1557         } else {
1558                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1559                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1560                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1561                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1562                             BGE_EVTENB_MI_INTERRUPT);
1563                 }
1564         }
1565
1566         /*
1567          * Clear any pending link state attention.
1568          * Otherwise some link state change events may be lost until attention
1569          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1570          * It's not necessary on newer BCM chips - perhaps enabling link
1571          * state change attentions implies clearing pending attention.
1572          */
1573         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1574             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1575             BGE_MACSTAT_LINK_CHANGED);
1576
1577         /* Enable link state change attentions. */
1578         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1579
1580         return(0);
1581 }
1582
1583 /*
1584  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1585  * against our list and return its name if we find a match. Note
1586  * that since the Broadcom controller contains VPD support, we
1587  * can get the device name string from the controller itself instead
1588  * of the compiled-in string. This is a little slow, but it guarantees
1589  * we'll always announce the right product name.
1590  */
1591 static int
1592 bge_probe(device_t dev)
1593 {
1594         struct bge_softc *sc;
1595         struct bge_type *t;
1596         char *descbuf;
1597         uint16_t product, vendor;
1598
1599         product = pci_get_device(dev);
1600         vendor = pci_get_vendor(dev);
1601
1602         for (t = bge_devs; t->bge_name != NULL; t++) {
1603                 if (vendor == t->bge_vid && product == t->bge_did)
1604                         break;
1605         }
1606
1607         if (t->bge_name == NULL)
1608                 return(ENXIO);
1609
1610         sc = device_get_softc(dev);
1611         descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1612         ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1613             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1614         device_set_desc_copy(dev, descbuf);
1615         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1616                 sc->bge_flags |= BGE_FLAG_NO_3LED;
1617         kfree(descbuf, M_TEMP);
1618         return(0);
1619 }
1620
1621 static int
1622 bge_attach(device_t dev)
1623 {
1624         struct ifnet *ifp;
1625         struct bge_softc *sc;
1626         uint32_t hwcfg = 0;
1627         uint32_t mac_addr = 0;
1628         int error = 0, rid;
1629         uint8_t ether_addr[ETHER_ADDR_LEN];
1630
1631         sc = device_get_softc(dev);
1632         sc->bge_dev = dev;
1633         callout_init(&sc->bge_stat_timer);
1634         lwkt_serialize_init(&sc->bge_jslot_serializer);
1635
1636         /*
1637          * Map control/status registers.
1638          */
1639         pci_enable_busmaster(dev);
1640
1641         rid = BGE_PCI_BAR0;
1642         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1643             RF_ACTIVE);
1644
1645         if (sc->bge_res == NULL) {
1646                 device_printf(dev, "couldn't map memory\n");
1647                 return ENXIO;
1648         }
1649
1650         sc->bge_btag = rman_get_bustag(sc->bge_res);
1651         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1652
1653         /* Save ASIC rev. */
1654         sc->bge_chipid =
1655             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1656             BGE_PCIMISCCTL_ASICREV;
1657         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1658         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1659
1660         /* Save chipset family. */
1661         switch (sc->bge_asicrev) {
1662         case BGE_ASICREV_BCM5700:
1663         case BGE_ASICREV_BCM5701:
1664         case BGE_ASICREV_BCM5703:
1665         case BGE_ASICREV_BCM5704:
1666                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1667                 break;
1668
1669         case BGE_ASICREV_BCM5714_A0:
1670         case BGE_ASICREV_BCM5780:
1671         case BGE_ASICREV_BCM5714:
1672                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1673                 /* Fall through */
1674
1675         case BGE_ASICREV_BCM5750:
1676         case BGE_ASICREV_BCM5752:
1677         case BGE_ASICREV_BCM5755:
1678         case BGE_ASICREV_BCM5787:
1679                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1680                 /* Fall through */
1681
1682         case BGE_ASICREV_BCM5705:
1683                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1684                 break;
1685         }
1686
1687         /*
1688          * Set various quirk flags.
1689          */
1690
1691         sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1692         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1693             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1694              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1695               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1696             sc->bge_asicrev == BGE_ASICREV_BCM5906)
1697                 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1698
1699         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1700             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1701                 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1702
1703         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1704             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1705                 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1706
1707         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1708                 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1709
1710         if (BGE_IS_5705_PLUS(sc)) {
1711                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1712                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1713                         uint32_t product = pci_get_device(dev);
1714
1715                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1716                             product != PCI_PRODUCT_BROADCOM_BCM5756)
1717                                 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1718                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1719                                 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1720                 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1721                         sc->bge_flags |= BGE_FLAG_BER_BUG;
1722                 }
1723         }
1724
1725         /* Allocate interrupt */
1726         rid = 0;
1727
1728         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1729             RF_SHAREABLE | RF_ACTIVE);
1730
1731         if (sc->bge_irq == NULL) {
1732                 device_printf(dev, "couldn't map interrupt\n");
1733                 error = ENXIO;
1734                 goto fail;
1735         }
1736
1737         /*
1738          * Check if this is a PCI-X or PCI Express device.
1739          */
1740         if (BGE_IS_5705_PLUS(sc)) {
1741                 uint32_t reg;
1742
1743                 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
1744                 if ((reg & 0xff) == BGE_PCIE_CAPID)
1745                         sc->bge_flags |= BGE_FLAG_PCIE;
1746         } else {
1747                 /*
1748                  * Check if the device is in PCI-X Mode.
1749                  * (This bit is not valid on PCI Express controllers.)
1750                  */
1751                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1752                     BGE_PCISTATE_PCI_BUSMODE) == 0)
1753                         sc->bge_flags |= BGE_FLAG_PCIX;
1754         }
1755
1756         ifp = &sc->arpcom.ac_if;
1757         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1758
1759         /* Try to reset the chip. */
1760         bge_reset(sc);
1761
1762         if (bge_chipinit(sc)) {
1763                 device_printf(dev, "chip initialization failed\n");
1764                 error = ENXIO;
1765                 goto fail;
1766         }
1767
1768         /*
1769          * Get station address from the EEPROM.
1770          */
1771         mac_addr = bge_readmem_ind(sc, 0x0c14);
1772         if ((mac_addr >> 16) == 0x484b) {
1773                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1774                 ether_addr[1] = (uint8_t)mac_addr;
1775                 mac_addr = bge_readmem_ind(sc, 0x0c18);
1776                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1777                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1778                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1779                 ether_addr[5] = (uint8_t)mac_addr;
1780         } else if (bge_read_eeprom(sc, ether_addr,
1781             BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1782                 device_printf(dev, "failed to read station address\n");
1783                 error = ENXIO;
1784                 goto fail;
1785         }
1786
1787         /* 5705/5750 limits RX return ring to 512 entries. */
1788         if (BGE_IS_5705_PLUS(sc))
1789                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1790         else
1791                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1792
1793         error = bge_dma_alloc(sc);
1794         if (error)
1795                 goto fail;
1796
1797         /* Set default tuneable values. */
1798         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1799         sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1800         sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1801         sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1802         sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1803
1804         /* Set up ifnet structure */
1805         ifp->if_softc = sc;
1806         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1807         ifp->if_ioctl = bge_ioctl;
1808         ifp->if_start = bge_start;
1809 #ifdef DEVICE_POLLING
1810         ifp->if_poll = bge_poll;
1811 #endif
1812         ifp->if_watchdog = bge_watchdog;
1813         ifp->if_init = bge_init;
1814         ifp->if_mtu = ETHERMTU;
1815         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1816         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1817         ifq_set_ready(&ifp->if_snd);
1818
1819         /*
1820          * 5700 B0 chips do not support checksumming correctly due
1821          * to hardware bugs.
1822          */
1823         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1824                 ifp->if_capabilities |= IFCAP_HWCSUM;
1825                 ifp->if_hwassist = BGE_CSUM_FEATURES;
1826         }
1827         ifp->if_capenable = ifp->if_capabilities;
1828
1829         /*
1830          * Figure out what sort of media we have by checking the
1831          * hardware config word in the first 32k of NIC internal memory,
1832          * or fall back to examining the EEPROM if necessary.
1833          * Note: on some BCM5700 cards, this value appears to be unset.
1834          * If that's the case, we have to rely on identifying the NIC
1835          * by its PCI subsystem ID, as we do below for the SysKonnect
1836          * SK-9D41.
1837          */
1838         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1839                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1840         else {
1841                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1842                                     sizeof(hwcfg))) {
1843                         device_printf(dev, "failed to read EEPROM\n");
1844                         error = ENXIO;
1845                         goto fail;
1846                 }
1847                 hwcfg = ntohl(hwcfg);
1848         }
1849
1850         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1851                 sc->bge_flags |= BGE_FLAG_TBI;
1852
1853         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1854         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1855                 sc->bge_flags |= BGE_FLAG_TBI;
1856
1857         if (sc->bge_flags & BGE_FLAG_TBI) {
1858                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1859                     bge_ifmedia_upd, bge_ifmedia_sts);
1860                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1861                 ifmedia_add(&sc->bge_ifmedia,
1862                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1863                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1864                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1865                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1866         } else {
1867                 /*
1868                  * Do transceiver setup.
1869                  */
1870                 if (mii_phy_probe(dev, &sc->bge_miibus,
1871                     bge_ifmedia_upd, bge_ifmedia_sts)) {
1872                         device_printf(dev, "MII without any PHY!\n");
1873                         error = ENXIO;
1874                         goto fail;
1875                 }
1876         }
1877
1878         /*
1879          * When using the BCM5701 in PCI-X mode, data corruption has
1880          * been observed in the first few bytes of some received packets.
1881          * Aligning the packet buffer in memory eliminates the corruption.
1882          * Unfortunately, this misaligns the packet payloads.  On platforms
1883          * which do not support unaligned accesses, we will realign the
1884          * payloads by copying the received packets.
1885          */
1886         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1887             (sc->bge_flags & BGE_FLAG_PCIX))
1888                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
1889
1890         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1891             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1892                 sc->bge_link_upd = bge_bcm5700_link_upd;
1893                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
1894         } else if (sc->bge_flags & BGE_FLAG_TBI) {
1895                 sc->bge_link_upd = bge_tbi_link_upd;
1896                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1897         } else {
1898                 sc->bge_link_upd = bge_copper_link_upd;
1899                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1900         }
1901
1902         /*
1903          * Create sysctl nodes.
1904          */
1905         sysctl_ctx_init(&sc->bge_sysctl_ctx);
1906         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
1907                                               SYSCTL_STATIC_CHILDREN(_hw),
1908                                               OID_AUTO,
1909                                               device_get_nameunit(dev),
1910                                               CTLFLAG_RD, 0, "");
1911         if (sc->bge_sysctl_tree == NULL) {
1912                 device_printf(dev, "can't add sysctl node\n");
1913                 error = ENXIO;
1914                 goto fail;
1915         }
1916
1917         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1918                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1919                         OID_AUTO, "rx_coal_ticks",
1920                         CTLTYPE_INT | CTLFLAG_RW,
1921                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
1922                         "Receive coalescing ticks (usec).");
1923         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1924                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1925                         OID_AUTO, "tx_coal_ticks",
1926                         CTLTYPE_INT | CTLFLAG_RW,
1927                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
1928                         "Transmit coalescing ticks (usec).");
1929         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1930                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1931                         OID_AUTO, "rx_max_coal_bds",
1932                         CTLTYPE_INT | CTLFLAG_RW,
1933                         sc, 0, bge_sysctl_rx_max_coal_bds, "I",
1934                         "Receive max coalesced BD count.");
1935         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1936                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1937                         OID_AUTO, "tx_max_coal_bds",
1938                         CTLTYPE_INT | CTLFLAG_RW,
1939                         sc, 0, bge_sysctl_tx_max_coal_bds, "I",
1940                         "Transmit max coalesced BD count.");
1941
1942         /*
1943          * Call MI attach routine.
1944          */
1945         ether_ifattach(ifp, ether_addr, NULL);
1946
1947         error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1948                                bge_intr, sc, &sc->bge_intrhand,
1949                                ifp->if_serializer);
1950         if (error) {
1951                 ether_ifdetach(ifp);
1952                 device_printf(dev, "couldn't set up irq\n");
1953                 goto fail;
1954         }
1955         return(0);
1956 fail:
1957         bge_detach(dev);
1958         return(error);
1959 }
1960
1961 static int
1962 bge_detach(device_t dev)
1963 {
1964         struct bge_softc *sc = device_get_softc(dev);
1965
1966         if (device_is_attached(dev)) {
1967                 struct ifnet *ifp = &sc->arpcom.ac_if;
1968
1969                 lwkt_serialize_enter(ifp->if_serializer);
1970                 bge_stop(sc);
1971                 bge_reset(sc);
1972                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1973                 lwkt_serialize_exit(ifp->if_serializer);
1974
1975                 ether_ifdetach(ifp);
1976         }
1977
1978         if (sc->bge_flags & BGE_FLAG_TBI)
1979                 ifmedia_removeall(&sc->bge_ifmedia);
1980         if (sc->bge_miibus)
1981                 device_delete_child(dev, sc->bge_miibus);
1982         bus_generic_detach(dev);
1983
1984         if (sc->bge_irq != NULL)
1985                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1986
1987         if (sc->bge_res != NULL)
1988                 bus_release_resource(dev, SYS_RES_MEMORY,
1989                     BGE_PCI_BAR0, sc->bge_res);
1990
1991         if (sc->bge_sysctl_tree != NULL)
1992                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
1993
1994         bge_dma_free(sc);
1995
1996         return 0;
1997 }
1998
1999 static void
2000 bge_reset(struct bge_softc *sc)
2001 {
2002         device_t dev;
2003         uint32_t cachesize, command, pcistate, reset;
2004         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2005         int i, val = 0;
2006
2007         dev = sc->bge_dev;
2008
2009         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
2010                 if (sc->bge_flags & BGE_FLAG_PCIE)
2011                         write_op = bge_writemem_direct;
2012                 else
2013                         write_op = bge_writemem_ind;
2014         } else {
2015                 write_op = bge_writereg_ind;
2016         }
2017
2018         /* Save some important PCI state. */
2019         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2020         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2021         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2022
2023         pci_write_config(dev, BGE_PCI_MISC_CTL,
2024             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2025             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2026
2027         /* Disable fastboot on controllers that support it. */
2028         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2029             sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2030             sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2031                 if (bootverbose)
2032                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2033                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2034         }
2035
2036         /*
2037          * Write the magic number to SRAM at offset 0xB50.
2038          * When firmware finishes its initialization it will
2039          * write ~BGE_MAGIC_NUMBER to the same location.
2040          */
2041         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2042
2043         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2044
2045         /* XXX: Broadcom Linux driver. */
2046         if (sc->bge_flags & BGE_FLAG_PCIE) {
2047                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
2048                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
2049                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2050                         /* Prevent PCIE link training during global reset */
2051                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2052                         reset |= (1<<29);
2053                 }
2054         }
2055
2056         /*
2057          * Set GPHY Power Down Override to leave GPHY
2058          * powered up in D0 uninitialized.
2059          */
2060         if (BGE_IS_5705_PLUS(sc))
2061                 reset |= 0x04000000;
2062
2063         /* Issue global reset */
2064         write_op(sc, BGE_MISC_CFG, reset);
2065
2066         DELAY(1000);
2067
2068         /* XXX: Broadcom Linux driver. */
2069         if (sc->bge_flags & BGE_FLAG_PCIE) {
2070                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2071                         uint32_t v;
2072
2073                         DELAY(500000); /* wait for link training to complete */
2074                         v = pci_read_config(dev, 0xc4, 4);
2075                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
2076                 }
2077                 /*
2078                  * Set PCIE max payload size to 128 bytes and
2079                  * clear error status.
2080                  */
2081                 pci_write_config(dev, 0xd8, 0xf5000, 4);
2082         }
2083
2084         /* Reset some of the PCI state that got zapped by reset */
2085         pci_write_config(dev, BGE_PCI_MISC_CTL,
2086             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2087             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2088         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2089         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2090         write_op(sc, BGE_MISC_CFG, (65 << 1));
2091
2092         /* Enable memory arbiter. */
2093         if (BGE_IS_5714_FAMILY(sc)) {
2094                 uint32_t val;
2095
2096                 val = CSR_READ_4(sc, BGE_MARB_MODE);
2097                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2098         } else {
2099                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2100         }
2101
2102         /*
2103          * Poll until we see the 1's complement of the magic number.
2104          * This indicates that the firmware initialization
2105          * is complete.
2106          */
2107         for (i = 0; i < BGE_TIMEOUT; i++) {
2108                 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2109                 if (val == ~BGE_MAGIC_NUMBER)
2110                         break;
2111                 DELAY(10);
2112         }
2113
2114         if (i == BGE_TIMEOUT) {
2115                 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out,"
2116                           "found 0x%08x\n", val);
2117                 return;
2118         }
2119
2120         /*
2121          * XXX Wait for the value of the PCISTATE register to
2122          * return to its original pre-reset state. This is a
2123          * fairly good indicator of reset completion. If we don't
2124          * wait for the reset to fully complete, trying to read
2125          * from the device's non-PCI registers may yield garbage
2126          * results.
2127          */
2128         for (i = 0; i < BGE_TIMEOUT; i++) {
2129                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2130                         break;
2131                 DELAY(10);
2132         }
2133
2134         if (sc->bge_flags & BGE_FLAG_PCIE) {
2135                 reset = bge_readmem_ind(sc, 0x7c00);
2136                 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2137         }
2138
2139         /* Fix up byte swapping */
2140         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2141             BGE_MODECTL_BYTESWAP_DATA);
2142
2143         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2144
2145         /*
2146          * The 5704 in TBI mode apparently needs some special
2147          * adjustment to insure the SERDES drive level is set
2148          * to 1.2V.
2149          */
2150         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2151             (sc->bge_flags & BGE_FLAG_TBI)) {
2152                 uint32_t serdescfg;
2153
2154                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2155                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2156                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2157         }
2158
2159         /* XXX: Broadcom Linux driver. */
2160         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2161             sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2162                 uint32_t v;
2163
2164                 v = CSR_READ_4(sc, 0x7c00);
2165                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2166         }
2167
2168         DELAY(10000);
2169 }
2170
2171 /*
2172  * Frame reception handling. This is called if there's a frame
2173  * on the receive return list.
2174  *
2175  * Note: we have to be able to handle two possibilities here:
2176  * 1) the frame is from the jumbo recieve ring
2177  * 2) the frame is from the standard receive ring
2178  */
2179
2180 static void
2181 bge_rxeof(struct bge_softc *sc)
2182 {
2183         struct ifnet *ifp;
2184         int stdcnt = 0, jumbocnt = 0;
2185
2186         if (sc->bge_rx_saved_considx ==
2187             sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2188                 return;
2189
2190         ifp = &sc->arpcom.ac_if;
2191
2192         bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2193                         sc->bge_cdata.bge_rx_return_ring_map,
2194                         BUS_DMASYNC_POSTREAD);
2195         bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2196                         sc->bge_cdata.bge_rx_std_ring_map,
2197                         BUS_DMASYNC_POSTREAD);
2198         if (BGE_IS_JUMBO_CAPABLE(sc)) {
2199                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2200                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2201                                 BUS_DMASYNC_POSTREAD);
2202         }
2203
2204         while (sc->bge_rx_saved_considx !=
2205                sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2206                 struct bge_rx_bd        *cur_rx;
2207                 uint32_t                rxidx;
2208                 struct mbuf             *m = NULL;
2209                 uint16_t                vlan_tag = 0;
2210                 int                     have_tag = 0;
2211
2212                 cur_rx =
2213             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2214
2215                 rxidx = cur_rx->bge_idx;
2216                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2217                 logif(rx_pkt);
2218
2219                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2220                         have_tag = 1;
2221                         vlan_tag = cur_rx->bge_vlan_tag;
2222                 }
2223
2224                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2225                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2226                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2227                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2228                         jumbocnt++;
2229                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2230                                 ifp->if_ierrors++;
2231                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2232                                 continue;
2233                         }
2234                         if (bge_newbuf_jumbo(sc,
2235                             sc->bge_jumbo, NULL) == ENOBUFS) {
2236                                 ifp->if_ierrors++;
2237                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2238                                 continue;
2239                         }
2240                 } else {
2241                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2242                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2243                                         sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2244                                         BUS_DMASYNC_POSTREAD);
2245                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2246                                 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2247                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2248                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2249                         stdcnt++;
2250                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2251                                 ifp->if_ierrors++;
2252                                 bge_newbuf_std(sc, sc->bge_std, m);
2253                                 continue;
2254                         }
2255                         if (bge_newbuf_std(sc, sc->bge_std,
2256                             NULL) == ENOBUFS) {
2257                                 ifp->if_ierrors++;
2258                                 bge_newbuf_std(sc, sc->bge_std, m);
2259                                 continue;
2260                         }
2261                 }
2262
2263                 ifp->if_ipackets++;
2264 #ifndef __i386__
2265                 /*
2266                  * The i386 allows unaligned accesses, but for other
2267                  * platforms we must make sure the payload is aligned.
2268                  */
2269                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2270                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2271                             cur_rx->bge_len);
2272                         m->m_data += ETHER_ALIGN;
2273                 }
2274 #endif
2275                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2276                 m->m_pkthdr.rcvif = ifp;
2277
2278                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2279                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2280                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2281                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2282                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2283                         }
2284                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
2285                             m->m_pkthdr.len >= BGE_MIN_FRAME) {
2286                                 m->m_pkthdr.csum_data =
2287                                     cur_rx->bge_tcp_udp_csum;
2288                                 m->m_pkthdr.csum_flags |=
2289                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2290                         }
2291                 }
2292
2293                 /*
2294                  * If we received a packet with a vlan tag, pass it
2295                  * to vlan_input() instead of ether_input().
2296                  */
2297                 if (have_tag) {
2298                         VLAN_INPUT_TAG(m, vlan_tag);
2299                         have_tag = vlan_tag = 0;
2300                 } else {
2301                         ifp->if_input(ifp, m);
2302                 }
2303         }
2304
2305         if (stdcnt > 0) {
2306                 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2307                                 sc->bge_cdata.bge_rx_std_ring_map,
2308                                 BUS_DMASYNC_PREWRITE);
2309         }
2310
2311         if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2312                 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2313                                 sc->bge_cdata.bge_rx_jumbo_ring_map,
2314                                 BUS_DMASYNC_PREWRITE);
2315         }
2316
2317         CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2318         if (stdcnt)
2319                 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2320         if (jumbocnt)
2321                 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2322 }
2323
2324 static void
2325 bge_txeof(struct bge_softc *sc)
2326 {
2327         struct bge_tx_bd *cur_tx = NULL;
2328         struct ifnet *ifp;
2329
2330         if (sc->bge_tx_saved_considx ==
2331             sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2332                 return;
2333
2334         ifp = &sc->arpcom.ac_if;
2335
2336         bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2337                         sc->bge_cdata.bge_tx_ring_map,
2338                         BUS_DMASYNC_POSTREAD);
2339
2340         /*
2341          * Go through our tx ring and free mbufs for those
2342          * frames that have been sent.
2343          */
2344         while (sc->bge_tx_saved_considx !=
2345                sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2346                 uint32_t idx = 0;
2347
2348                 idx = sc->bge_tx_saved_considx;
2349                 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2350                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2351                         ifp->if_opackets++;
2352                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2353                         bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2354                                         sc->bge_cdata.bge_tx_dmamap[idx],
2355                                         BUS_DMASYNC_POSTWRITE);
2356                         bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2357                             sc->bge_cdata.bge_tx_dmamap[idx]);
2358                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2359                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2360                 }
2361                 sc->bge_txcnt--;
2362                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2363                 logif(tx_pkt);
2364         }
2365
2366         if (cur_tx != NULL &&
2367             (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2368             (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2369                 ifp->if_flags &= ~IFF_OACTIVE;
2370
2371         if (sc->bge_txcnt == 0)
2372                 ifp->if_timer = 0;
2373
2374         if (!ifq_is_empty(&ifp->if_snd))
2375                 ifp->if_start(ifp);
2376 }
2377
2378 #ifdef DEVICE_POLLING
2379
2380 static void
2381 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2382 {
2383         struct bge_softc *sc = ifp->if_softc;
2384         uint32_t status;
2385
2386         switch(cmd) {
2387         case POLL_REGISTER:
2388                 /*
2389                  * Mask the interrupt when we start polling
2390                  */
2391                 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2392                 break;
2393         case POLL_DEREGISTER:
2394                 /*
2395                  * Unmask the interrupt when we stop polling.
2396                  */
2397                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2398                 break;
2399         case POLL_AND_CHECK_STATUS:
2400                 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2401                                 sc->bge_cdata.bge_status_map,
2402                                 BUS_DMASYNC_POSTREAD);
2403
2404                 /*
2405                  * Process link state changes.
2406                  */
2407                 status = CSR_READ_4(sc, BGE_MAC_STS);
2408                 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2409                         sc->bge_link_evt = 0;
2410                         sc->bge_link_upd(sc, status);
2411                 }
2412                 /* fall through */
2413         case POLL_ONLY:
2414                 if (ifp->if_flags & IFF_RUNNING) {
2415                         bge_rxeof(sc);
2416                         bge_txeof(sc);
2417                 }
2418                 break;
2419         }
2420 }
2421
2422 #endif
2423
2424 static void
2425 bge_intr(void *xsc)
2426 {
2427         struct bge_softc *sc = xsc;
2428         struct ifnet *ifp = &sc->arpcom.ac_if;
2429         uint32_t status;
2430
2431         logif(intr);
2432
2433         /*
2434          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
2435          * disable interrupts by writing nonzero like we used to, since with
2436          * our current organization this just gives complications and
2437          * pessimizations for re-enabling interrupts.  We used to have races
2438          * instead of the necessary complications.  Disabling interrupts
2439          * would just reduce the chance of a status update while we are
2440          * running (by switching to the interrupt-mode coalescence
2441          * parameters), but this chance is already very low so it is more
2442          * efficient to get another interrupt than prevent it.
2443          *
2444          * We do the ack first to ensure another interrupt if there is a
2445          * status update after the ack.  We don't check for the status
2446          * changing later because it is more efficient to get another
2447          * interrupt than prevent it, not quite as above (not checking is
2448          * a smaller optimization than not toggling the interrupt enable,
2449          * since checking doesn't involve PCI accesses and toggling require
2450          * the status check).  So toggling would probably be a pessimization
2451          * even with MSI.  It would only be needed for using a task queue.
2452          */
2453         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2454
2455         bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2456                         sc->bge_cdata.bge_status_map,
2457                         BUS_DMASYNC_POSTREAD);
2458
2459         /*
2460          * Process link state changes.
2461          */
2462         status = CSR_READ_4(sc, BGE_MAC_STS);
2463         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2464                 sc->bge_link_evt = 0;
2465                 sc->bge_link_upd(sc, status);
2466         }
2467
2468         if (ifp->if_flags & IFF_RUNNING) {
2469                 /* Check RX return ring producer/consumer */
2470                 bge_rxeof(sc);
2471
2472                 /* Check TX ring producer/consumer */
2473                 bge_txeof(sc);
2474         }
2475
2476         if (sc->bge_coal_chg)
2477                 bge_coal_change(sc);
2478 }
2479
2480 static void
2481 bge_tick(void *xsc)
2482 {
2483         struct bge_softc *sc = xsc;
2484         struct ifnet *ifp = &sc->arpcom.ac_if;
2485
2486         lwkt_serialize_enter(ifp->if_serializer);
2487
2488         if (BGE_IS_5705_PLUS(sc))
2489                 bge_stats_update_regs(sc);
2490         else
2491                 bge_stats_update(sc);
2492
2493         if (sc->bge_flags & BGE_FLAG_TBI) {
2494                 /*
2495                  * Since in TBI mode auto-polling can't be used we should poll
2496                  * link status manually. Here we register pending link event
2497                  * and trigger interrupt.
2498                  */
2499                 sc->bge_link_evt++;
2500                 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2501         } else if (!sc->bge_link) {
2502                 mii_tick(device_get_softc(sc->bge_miibus));
2503         }
2504
2505         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2506
2507         lwkt_serialize_exit(ifp->if_serializer);
2508 }
2509
2510 static void
2511 bge_stats_update_regs(struct bge_softc *sc)
2512 {
2513         struct ifnet *ifp = &sc->arpcom.ac_if;
2514         struct bge_mac_stats_regs stats;
2515         uint32_t *s;
2516         int i;
2517
2518         s = (uint32_t *)&stats;
2519         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2520                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2521                 s++;
2522         }
2523
2524         ifp->if_collisions +=
2525            (stats.dot3StatsSingleCollisionFrames +
2526            stats.dot3StatsMultipleCollisionFrames +
2527            stats.dot3StatsExcessiveCollisions +
2528            stats.dot3StatsLateCollisions) -
2529            ifp->if_collisions;
2530 }
2531
2532 static void
2533 bge_stats_update(struct bge_softc *sc)
2534 {
2535         struct ifnet *ifp = &sc->arpcom.ac_if;
2536         bus_size_t stats;
2537
2538         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2539
2540 #define READ_STAT(sc, stats, stat)      \
2541         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2542
2543         ifp->if_collisions +=
2544            (READ_STAT(sc, stats,
2545                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2546             READ_STAT(sc, stats,
2547                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2548             READ_STAT(sc, stats,
2549                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2550             READ_STAT(sc, stats,
2551                 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2552            ifp->if_collisions;
2553
2554 #undef READ_STAT
2555
2556 #ifdef notdef
2557         ifp->if_collisions +=
2558            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2559            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2560            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2561            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2562            ifp->if_collisions;
2563 #endif
2564 }
2565
2566 /*
2567  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2568  * pointers to descriptors.
2569  */
2570 static int
2571 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2572 {
2573         struct bge_tx_bd *d = NULL;
2574         uint16_t csum_flags = 0;
2575         struct ifvlan *ifv = NULL;
2576         struct bge_dmamap_arg ctx;
2577         bus_dma_segment_t segs[BGE_NSEG_NEW];
2578         bus_dmamap_t map;
2579         int error, maxsegs, idx, i;
2580
2581         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2582             m_head->m_pkthdr.rcvif != NULL &&
2583             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2584                 ifv = m_head->m_pkthdr.rcvif->if_softc;
2585
2586         if (m_head->m_pkthdr.csum_flags) {
2587                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2588                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2589                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2590                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2591                 if (m_head->m_flags & M_LASTFRAG)
2592                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2593                 else if (m_head->m_flags & M_FRAG)
2594                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2595         }
2596
2597         idx = *txidx;
2598         map = sc->bge_cdata.bge_tx_dmamap[idx];
2599
2600         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2601         KASSERT(maxsegs >= BGE_NSEG_SPARE,
2602                 ("not enough segments %d\n", maxsegs));
2603
2604         if (maxsegs > BGE_NSEG_NEW)
2605                 maxsegs = BGE_NSEG_NEW;
2606
2607         /*
2608          * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2609          * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2610          * but when such padded frames employ the bge IP/TCP checksum
2611          * offload, the hardware checksum assist gives incorrect results
2612          * (possibly from incorporating its own padding into the UDP/TCP
2613          * checksum; who knows).  If we pad such runts with zeros, the
2614          * onboard checksum comes out correct.  We do this by pretending
2615          * the mbuf chain has too many fragments so the coalescing code
2616          * below can assemble the packet into a single buffer that's
2617          * padded out to the mininum frame size.
2618          */
2619         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2620             m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2621                 error = EFBIG;
2622         } else {
2623                 ctx.bge_segs = segs;
2624                 ctx.bge_maxsegs = maxsegs;
2625                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2626                                              m_head, bge_dma_map_mbuf, &ctx,
2627                                              BUS_DMA_NOWAIT);
2628         }
2629         if (error == EFBIG || ctx.bge_maxsegs == 0) {
2630                 struct mbuf *m_new;
2631
2632                 m_new = m_defrag(m_head, MB_DONTWAIT);
2633                 if (m_new == NULL) {
2634                         if_printf(&sc->arpcom.ac_if,
2635                                   "could not defrag TX mbuf\n");
2636                         error = ENOBUFS;
2637                         goto back;
2638                 } else {
2639                         m_head = m_new;
2640                 }
2641
2642                 /*
2643                  * Manually pad short frames, and zero the pad space
2644                  * to avoid leaking data.
2645                  */
2646                 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2647                     m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2648                         int pad_len = BGE_MIN_FRAME - m_head->m_pkthdr.len;
2649
2650                         bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
2651                               pad_len);
2652                         m_head->m_pkthdr.len += pad_len;
2653                         m_head->m_len = m_head->m_pkthdr.len;
2654                 }
2655
2656                 ctx.bge_segs = segs;
2657                 ctx.bge_maxsegs = maxsegs;
2658                 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2659                                              m_head, bge_dma_map_mbuf, &ctx,
2660                                              BUS_DMA_NOWAIT);
2661                 if (error || ctx.bge_maxsegs == 0) {
2662                         if_printf(&sc->arpcom.ac_if,
2663                                   "could not defrag TX mbuf\n");
2664                         if (error == 0)
2665                                 error = EFBIG;
2666                         goto back;
2667                 }
2668         } else if (error) {
2669                 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2670                 goto back;
2671         }
2672
2673         bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2674
2675         for (i = 0; ; i++) {
2676                 d = &sc->bge_ldata.bge_tx_ring[idx];
2677
2678                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2679                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2680                 d->bge_len = segs[i].ds_len;
2681                 d->bge_flags = csum_flags;
2682
2683                 if (i == ctx.bge_maxsegs - 1)
2684                         break;
2685                 BGE_INC(idx, BGE_TX_RING_CNT);
2686         }
2687         /* Mark the last segment as end of packet... */
2688         d->bge_flags |= BGE_TXBDFLAG_END;
2689
2690         /* Set vlan tag to the first segment of the packet. */
2691         d = &sc->bge_ldata.bge_tx_ring[*txidx];
2692         if (ifv != NULL) {
2693                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2694                 d->bge_vlan_tag = ifv->ifv_tag;
2695         } else {
2696                 d->bge_vlan_tag = 0;
2697         }
2698
2699         /*
2700          * Insure that the map for this transmission is placed at
2701          * the array index of the last descriptor in this chain.
2702          */
2703         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2704         sc->bge_cdata.bge_tx_dmamap[idx] = map;
2705         sc->bge_cdata.bge_tx_chain[idx] = m_head;
2706         sc->bge_txcnt += ctx.bge_maxsegs;
2707
2708         BGE_INC(idx, BGE_TX_RING_CNT);
2709         *txidx = idx;
2710 back:
2711         if (error)
2712                 m_freem(m_head);
2713         return error;
2714 }
2715
2716 /*
2717  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2718  * to the mbuf data regions directly in the transmit descriptors.
2719  */
2720 static void
2721 bge_start(struct ifnet *ifp)
2722 {
2723         struct bge_softc *sc = ifp->if_softc;
2724         struct mbuf *m_head = NULL;
2725         uint32_t prodidx;
2726         int need_trans;
2727
2728         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2729                 return;
2730
2731         prodidx = sc->bge_tx_prodidx;
2732
2733         need_trans = 0;
2734         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2735                 m_head = ifq_poll(&ifp->if_snd);
2736                 if (m_head == NULL)
2737                         break;
2738
2739                 /*
2740                  * XXX
2741                  * The code inside the if() block is never reached since we
2742                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2743                  * requests to checksum TCP/UDP in a fragmented packet.
2744                  *
2745                  * XXX
2746                  * safety overkill.  If this is a fragmented packet chain
2747                  * with delayed TCP/UDP checksums, then only encapsulate
2748                  * it if we have enough descriptors to handle the entire
2749                  * chain at once.
2750                  * (paranoia -- may not actually be needed)
2751                  */
2752                 if (m_head->m_flags & M_FIRSTFRAG &&
2753                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2754                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2755                             m_head->m_pkthdr.csum_data + 16) {
2756                                 ifp->if_flags |= IFF_OACTIVE;
2757                                 break;
2758                         }
2759                 }
2760
2761                 /*
2762                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2763                  * descriptors of the end of the ring.  Also make
2764                  * sure there are BGE_NSEG_SPARE descriptors for
2765                  * jumbo buffers' defragmentation.
2766                  */
2767                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2768                     (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2769                         ifp->if_flags |= IFF_OACTIVE;
2770                         break;
2771                 }
2772
2773                 /*
2774                  * Dequeue the packet before encapsulation, since
2775                  * bge_encap() may free the packet if error happens.
2776                  */
2777                 ifq_dequeue(&ifp->if_snd, m_head);
2778
2779                 /*
2780                  * Pack the data into the transmit ring. If we
2781                  * don't have room, set the OACTIVE flag and wait
2782                  * for the NIC to drain the ring.
2783                  */
2784                 if (bge_encap(sc, m_head, &prodidx)) {
2785                         ifp->if_flags |= IFF_OACTIVE;
2786                         break;
2787                 }
2788                 need_trans = 1;
2789
2790                 BPF_MTAP(ifp, m_head);
2791         }
2792
2793         if (!need_trans)
2794                 return;
2795
2796         /* Transmit */
2797         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2798         /* 5700 b2 errata */
2799         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2800                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2801
2802         sc->bge_tx_prodidx = prodidx;
2803
2804         /*
2805          * Set a timeout in case the chip goes out to lunch.
2806          */
2807         ifp->if_timer = 5;
2808 }
2809
2810 static void
2811 bge_init(void *xsc)
2812 {
2813         struct bge_softc *sc = xsc;
2814         struct ifnet *ifp = &sc->arpcom.ac_if;
2815         uint16_t *m;
2816
2817         ASSERT_SERIALIZED(ifp->if_serializer);
2818
2819         if (ifp->if_flags & IFF_RUNNING)
2820                 return;
2821
2822         /* Cancel pending I/O and flush buffers. */
2823         bge_stop(sc);
2824         bge_reset(sc);
2825         bge_chipinit(sc);
2826
2827         /*
2828          * Init the various state machines, ring
2829          * control blocks and firmware.
2830          */
2831         if (bge_blockinit(sc)) {
2832                 if_printf(ifp, "initialization failure\n");
2833                 return;
2834         }
2835
2836         /* Specify MTU. */
2837         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2838             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2839
2840         /* Load our MAC address. */
2841         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2842         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2843         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2844
2845         /* Enable or disable promiscuous mode as needed. */
2846         bge_setpromisc(sc);
2847
2848         /* Program multicast filter. */
2849         bge_setmulti(sc);
2850
2851         /* Init RX ring. */
2852         bge_init_rx_ring_std(sc);
2853
2854         /*
2855          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2856          * memory to insure that the chip has in fact read the first
2857          * entry of the ring.
2858          */
2859         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2860                 uint32_t                v, i;
2861                 for (i = 0; i < 10; i++) {
2862                         DELAY(20);
2863                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2864                         if (v == (MCLBYTES - ETHER_ALIGN))
2865                                 break;
2866                 }
2867                 if (i == 10)
2868                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2869         }
2870
2871         /* Init jumbo RX ring. */
2872         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2873                 bge_init_rx_ring_jumbo(sc);
2874
2875         /* Init our RX return ring index */
2876         sc->bge_rx_saved_considx = 0;
2877
2878         /* Init TX ring. */
2879         bge_init_tx_ring(sc);
2880
2881         /* Turn on transmitter */
2882         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2883
2884         /* Turn on receiver */
2885         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2886
2887         /* Tell firmware we're alive. */
2888         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2889
2890         /* Enable host interrupts. */
2891         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2892 #ifdef DEVICE_POLLING
2893         if ((ifp->if_flags & IFF_POLLING) == 0)
2894 #endif
2895                 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2896         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2897
2898         bge_ifmedia_upd(ifp);
2899
2900         ifp->if_flags |= IFF_RUNNING;
2901         ifp->if_flags &= ~IFF_OACTIVE;
2902
2903         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2904 }
2905
2906 /*
2907  * Set media options.
2908  */
2909 static int
2910 bge_ifmedia_upd(struct ifnet *ifp)
2911 {
2912         struct bge_softc *sc = ifp->if_softc;
2913
2914         /* If this is a 1000baseX NIC, enable the TBI port. */
2915         if (sc->bge_flags & BGE_FLAG_TBI) {
2916                 struct ifmedia *ifm = &sc->bge_ifmedia;
2917
2918                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2919                         return(EINVAL);
2920
2921                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2922                 case IFM_AUTO:
2923                         /*
2924                          * The BCM5704 ASIC appears to have a special
2925                          * mechanism for programming the autoneg
2926                          * advertisement registers in TBI mode.
2927                          */
2928                         if (!bge_fake_autoneg &&
2929                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2930                                 uint32_t sgdig;
2931
2932                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2933                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2934                                 sgdig |= BGE_SGDIGCFG_AUTO |
2935                                          BGE_SGDIGCFG_PAUSE_CAP |
2936                                          BGE_SGDIGCFG_ASYM_PAUSE;
2937                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2938                                             sgdig | BGE_SGDIGCFG_SEND);
2939                                 DELAY(5);
2940                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2941                         }
2942                         break;
2943                 case IFM_1000_SX:
2944                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2945                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2946                                     BGE_MACMODE_HALF_DUPLEX);
2947                         } else {
2948                                 BGE_SETBIT(sc, BGE_MAC_MODE,
2949                                     BGE_MACMODE_HALF_DUPLEX);
2950                         }
2951                         break;
2952                 default:
2953                         return(EINVAL);
2954                 }
2955         } else {
2956                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2957
2958                 sc->bge_link_evt++;
2959                 sc->bge_link = 0;
2960                 if (mii->mii_instance) {
2961                         struct mii_softc *miisc;
2962
2963                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2964                                 mii_phy_reset(miisc);
2965                 }
2966                 mii_mediachg(mii);
2967         }
2968         return(0);
2969 }
2970
2971 /*
2972  * Report current media status.
2973  */
2974 static void
2975 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2976 {
2977         struct bge_softc *sc = ifp->if_softc;
2978
2979         if (sc->bge_flags & BGE_FLAG_TBI) {
2980                 ifmr->ifm_status = IFM_AVALID;
2981                 ifmr->ifm_active = IFM_ETHER;
2982                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2983                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
2984                         ifmr->ifm_status |= IFM_ACTIVE;
2985                 } else {
2986                         ifmr->ifm_active |= IFM_NONE;
2987                         return;
2988                 }
2989
2990                 ifmr->ifm_active |= IFM_1000_SX;
2991                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2992                         ifmr->ifm_active |= IFM_HDX;
2993                 else
2994                         ifmr->ifm_active |= IFM_FDX;
2995         } else {
2996                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2997
2998                 mii_pollstat(mii);
2999                 ifmr->ifm_active = mii->mii_media_active;
3000                 ifmr->ifm_status = mii->mii_media_status;
3001         }
3002 }
3003
3004 static int
3005 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3006 {
3007         struct bge_softc *sc = ifp->if_softc;
3008         struct ifreq *ifr = (struct ifreq *)data;
3009         int mask, error = 0;
3010
3011         ASSERT_SERIALIZED(ifp->if_serializer);
3012
3013         switch (command) {
3014         case SIOCSIFMTU:
3015                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3016                     (BGE_IS_JUMBO_CAPABLE(sc) &&
3017                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3018                         error = EINVAL;
3019                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3020                         ifp->if_mtu = ifr->ifr_mtu;
3021                         ifp->if_flags &= ~IFF_RUNNING;
3022                         bge_init(sc);
3023                 }
3024                 break;
3025         case SIOCSIFFLAGS:
3026                 if (ifp->if_flags & IFF_UP) {
3027                         if (ifp->if_flags & IFF_RUNNING) {
3028                                 mask = ifp->if_flags ^ sc->bge_if_flags;
3029
3030                                 /*
3031                                  * If only the state of the PROMISC flag
3032                                  * changed, then just use the 'set promisc
3033                                  * mode' command instead of reinitializing
3034                                  * the entire NIC. Doing a full re-init
3035                                  * means reloading the firmware and waiting
3036                                  * for it to start up, which may take a
3037                                  * second or two.  Similarly for ALLMULTI.
3038                                  */
3039                                 if (mask & IFF_PROMISC)
3040                                         bge_setpromisc(sc);
3041                                 if (mask & IFF_ALLMULTI)
3042                                         bge_setmulti(sc);
3043                         } else {
3044                                 bge_init(sc);
3045                         }
3046                 } else {
3047                         if (ifp->if_flags & IFF_RUNNING)
3048                                 bge_stop(sc);
3049                 }
3050                 sc->bge_if_flags = ifp->if_flags;
3051                 break;
3052         case SIOCADDMULTI:
3053         case SIOCDELMULTI:
3054                 if (ifp->if_flags & IFF_RUNNING)
3055                         bge_setmulti(sc);
3056                 break;
3057         case SIOCSIFMEDIA:
3058         case SIOCGIFMEDIA:
3059                 if (sc->bge_flags & BGE_FLAG_TBI) {
3060                         error = ifmedia_ioctl(ifp, ifr,
3061                             &sc->bge_ifmedia, command);
3062                 } else {
3063                         struct mii_data *mii;
3064
3065                         mii = device_get_softc(sc->bge_miibus);
3066                         error = ifmedia_ioctl(ifp, ifr,
3067                                               &mii->mii_media, command);
3068                 }
3069                 break;
3070         case SIOCSIFCAP:
3071                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3072                 if (mask & IFCAP_HWCSUM) {
3073                         ifp->if_capenable ^= IFCAP_HWCSUM;
3074                         if (IFCAP_HWCSUM & ifp->if_capenable)
3075                                 ifp->if_hwassist = BGE_CSUM_FEATURES;
3076                         else
3077                                 ifp->if_hwassist = 0;
3078                 }
3079                 break;
3080         default:
3081                 error = ether_ioctl(ifp, command, data);
3082                 break;
3083         }
3084         return error;
3085 }
3086
3087 static void
3088 bge_watchdog(struct ifnet *ifp)
3089 {
3090         struct bge_softc *sc = ifp->if_softc;
3091
3092         if_printf(ifp, "watchdog timeout -- resetting\n");
3093
3094         ifp->if_flags &= ~IFF_RUNNING;
3095         bge_init(sc);
3096
3097         ifp->if_oerrors++;
3098
3099         if (!ifq_is_empty(&ifp->if_snd))
3100                 ifp->if_start(ifp);
3101 }
3102
3103 /*
3104  * Stop the adapter and free any mbufs allocated to the
3105  * RX and TX lists.
3106  */
3107 static void
3108 bge_stop(struct bge_softc *sc)
3109 {
3110         struct ifnet *ifp = &sc->arpcom.ac_if;
3111         struct ifmedia_entry *ifm;
3112         struct mii_data *mii = NULL;
3113         int mtmp, itmp;
3114
3115         ASSERT_SERIALIZED(ifp->if_serializer);
3116
3117         if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3118                 mii = device_get_softc(sc->bge_miibus);
3119
3120         callout_stop(&sc->bge_stat_timer);
3121
3122         /*
3123          * Disable all of the receiver blocks
3124          */
3125         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3126         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3127         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3128         if (!BGE_IS_5705_PLUS(sc))
3129                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3130         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3131         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3132         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3133
3134         /*
3135          * Disable all of the transmit blocks
3136          */
3137         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3138         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3139         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3140         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3141         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3142         if (!BGE_IS_5705_PLUS(sc))
3143                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3144         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3145
3146         /*
3147          * Shut down all of the memory managers and related
3148          * state machines.
3149          */
3150         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3151         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3152         if (!BGE_IS_5705_PLUS(sc))
3153                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3154         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3155         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3156         if (!BGE_IS_5705_PLUS(sc)) {
3157                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3158                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3159         }
3160
3161         /* Disable host interrupts. */
3162         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3163         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3164
3165         /*
3166          * Tell firmware we're shutting down.
3167          */
3168         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3169
3170         /* Free the RX lists. */
3171         bge_free_rx_ring_std(sc);
3172
3173         /* Free jumbo RX list. */
3174         if (BGE_IS_JUMBO_CAPABLE(sc))
3175                 bge_free_rx_ring_jumbo(sc);
3176
3177         /* Free TX buffers. */
3178         bge_free_tx_ring(sc);
3179
3180         /*
3181          * Isolate/power down the PHY, but leave the media selection
3182          * unchanged so that things will be put back to normal when
3183          * we bring the interface back up.
3184          */
3185         if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3186                 itmp = ifp->if_flags;
3187                 ifp->if_flags |= IFF_UP;
3188                 ifm = mii->mii_media.ifm_cur;
3189                 mtmp = ifm->ifm_media;
3190                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3191                 mii_mediachg(mii);
3192                 ifm->ifm_media = mtmp;
3193                 ifp->if_flags = itmp;
3194         }
3195
3196         sc->bge_link = 0;
3197         sc->bge_coal_chg = 0;
3198
3199         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3200
3201         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3202         ifp->if_timer = 0;
3203 }
3204
3205 /*
3206  * Stop all chip I/O so that the kernel's probe routines don't
3207  * get confused by errant DMAs when rebooting.
3208  */
3209 static void
3210 bge_shutdown(device_t dev)
3211 {
3212         struct bge_softc *sc = device_get_softc(dev);
3213         struct ifnet *ifp = &sc->arpcom.ac_if;
3214
3215         lwkt_serialize_enter(ifp->if_serializer);
3216         bge_stop(sc);
3217         bge_reset(sc);
3218         lwkt_serialize_exit(ifp->if_serializer);
3219 }
3220
3221 static int
3222 bge_suspend(device_t dev)
3223 {
3224         struct bge_softc *sc = device_get_softc(dev);
3225         struct ifnet *ifp = &sc->arpcom.ac_if;
3226
3227         lwkt_serialize_enter(ifp->if_serializer);
3228         bge_stop(sc);
3229         lwkt_serialize_exit(ifp->if_serializer);
3230
3231         return 0;
3232 }
3233
3234 static int
3235 bge_resume(device_t dev)
3236 {
3237         struct bge_softc *sc = device_get_softc(dev);
3238         struct ifnet *ifp = &sc->arpcom.ac_if;
3239
3240         lwkt_serialize_enter(ifp->if_serializer);
3241
3242         if (ifp->if_flags & IFF_UP) {
3243                 bge_init(sc);
3244
3245                 if (!ifq_is_empty(&ifp->if_snd))
3246                         ifp->if_start(ifp);
3247         }
3248
3249         lwkt_serialize_exit(ifp->if_serializer);
3250
3251         return 0;
3252 }
3253
3254 static void
3255 bge_setpromisc(struct bge_softc *sc)
3256 {
3257         struct ifnet *ifp = &sc->arpcom.ac_if;
3258
3259         if (ifp->if_flags & IFF_PROMISC)
3260                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3261         else
3262                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3263 }
3264
3265 static void
3266 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3267 {
3268         struct bge_dmamap_arg *ctx = arg;
3269
3270         if (error)
3271                 return;
3272
3273         KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3274                 ("only one segment is allowed\n"));
3275
3276         ctx->bge_segs[0] = *segs;
3277 }
3278
3279 static void
3280 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3281                  bus_size_t mapsz __unused, int error)
3282 {
3283         struct bge_dmamap_arg *ctx = arg;
3284         int i;
3285
3286         if (error)
3287                 return;
3288
3289         if (nsegs > ctx->bge_maxsegs) {
3290                 ctx->bge_maxsegs = 0;
3291                 return;
3292         }
3293
3294         ctx->bge_maxsegs = nsegs;
3295         for (i = 0; i < nsegs; ++i)
3296                 ctx->bge_segs[i] = segs[i];
3297 }
3298
3299 static void
3300 bge_dma_free(struct bge_softc *sc)
3301 {
3302         int i;
3303
3304         /* Destroy RX/TX mbuf DMA stuffs. */
3305         if (sc->bge_cdata.bge_mtag != NULL) {
3306                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3307                         if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3308                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3309                                     sc->bge_cdata.bge_rx_std_dmamap[i]);
3310                         }
3311                 }
3312
3313                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3314                         if (sc->bge_cdata.bge_tx_dmamap[i]) {
3315                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3316                                     sc->bge_cdata.bge_tx_dmamap[i]);
3317                         }
3318                 }
3319                 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3320         }
3321
3322         /* Destroy standard RX ring */
3323         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3324                            sc->bge_cdata.bge_rx_std_ring_map,
3325                            sc->bge_ldata.bge_rx_std_ring);
3326
3327         if (BGE_IS_JUMBO_CAPABLE(sc))
3328                 bge_free_jumbo_mem(sc);
3329
3330         /* Destroy RX return ring */
3331         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3332                            sc->bge_cdata.bge_rx_return_ring_map,
3333                            sc->bge_ldata.bge_rx_return_ring);
3334
3335         /* Destroy TX ring */
3336         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3337                            sc->bge_cdata.bge_tx_ring_map,
3338                            sc->bge_ldata.bge_tx_ring);
3339
3340         /* Destroy status block */
3341         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3342                            sc->bge_cdata.bge_status_map,
3343                            sc->bge_ldata.bge_status_block);
3344
3345         /* Destroy statistics block */
3346         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3347                            sc->bge_cdata.bge_stats_map,
3348                            sc->bge_ldata.bge_stats);
3349
3350         /* Destroy the parent tag */
3351         if (sc->bge_cdata.bge_parent_tag != NULL)
3352                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3353 }
3354
3355 static int
3356 bge_dma_alloc(struct bge_softc *sc)
3357 {
3358         struct ifnet *ifp = &sc->arpcom.ac_if;
3359         int nseg, i, error;
3360
3361         /*
3362          * Allocate the parent bus DMA tag appropriate for PCI.
3363          */
3364         error = bus_dma_tag_create(NULL, 1, 0,
3365                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3366                                    NULL, NULL,
3367                                    MAXBSIZE, BGE_NSEG_NEW,
3368                                    BUS_SPACE_MAXSIZE_32BIT,
3369                                    0, &sc->bge_cdata.bge_parent_tag);
3370         if (error) {
3371                 if_printf(ifp, "could not allocate parent dma tag\n");
3372                 return error;
3373         }
3374
3375         /*
3376          * Create DMA tag for mbufs.
3377          */
3378         nseg = BGE_NSEG_NEW;
3379         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3380                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3381                                    NULL, NULL,
3382                                    MCLBYTES * nseg, nseg, MCLBYTES,
3383                                    BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3384         if (error) {
3385                 if_printf(ifp, "could not allocate mbuf dma tag\n");
3386                 return error;
3387         }
3388
3389         /*
3390          * Create DMA maps for TX/RX mbufs.
3391          */
3392         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3393                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3394                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
3395                 if (error) {
3396                         int j;
3397
3398                         for (j = 0; j < i; ++j) {
3399                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3400                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3401                         }
3402                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3403                         sc->bge_cdata.bge_mtag = NULL;
3404
3405                         if_printf(ifp, "could not create DMA map for RX\n");
3406                         return error;
3407                 }
3408         }
3409
3410         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3411                 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3412                                           &sc->bge_cdata.bge_tx_dmamap[i]);
3413                 if (error) {
3414                         int j;
3415
3416                         for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3417                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3418                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
3419                         }
3420                         for (j = 0; j < i; ++j) {
3421                                 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3422                                         sc->bge_cdata.bge_tx_dmamap[j]);
3423                         }
3424                         bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3425                         sc->bge_cdata.bge_mtag = NULL;
3426
3427                         if_printf(ifp, "could not create DMA map for TX\n");
3428                         return error;
3429                 }
3430         }
3431
3432         /*
3433          * Create DMA stuffs for standard RX ring.
3434          */
3435         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3436                                     &sc->bge_cdata.bge_rx_std_ring_tag,
3437                                     &sc->bge_cdata.bge_rx_std_ring_map,
3438                                     (void **)&sc->bge_ldata.bge_rx_std_ring,
3439                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
3440         if (error) {
3441                 if_printf(ifp, "could not create std RX ring\n");
3442                 return error;
3443         }
3444
3445         /*
3446          * Create jumbo buffer pool.
3447          */
3448         if (BGE_IS_JUMBO_CAPABLE(sc)) {
3449                 error = bge_alloc_jumbo_mem(sc);
3450                 if (error) {
3451                         if_printf(ifp, "could not create jumbo buffer pool\n");
3452                         return error;
3453                 }
3454         }
3455
3456         /*
3457          * Create DMA stuffs for RX return ring.
3458          */
3459         error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3460                                     &sc->bge_cdata.bge_rx_return_ring_tag,
3461                                     &sc->bge_cdata.bge_rx_return_ring_map,
3462                                     (void **)&sc->bge_ldata.bge_rx_return_ring,
3463                                     &sc->bge_ldata.bge_rx_return_ring_paddr);
3464         if (error) {
3465                 if_printf(ifp, "could not create RX ret ring\n");
3466                 return error;
3467         }
3468
3469         /*
3470          * Create DMA stuffs for TX ring.
3471          */
3472         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3473                                     &sc->bge_cdata.bge_tx_ring_tag,
3474                                     &sc->bge_cdata.bge_tx_ring_map,
3475                                     (void **)&sc->bge_ldata.bge_tx_ring,
3476                                     &sc->bge_ldata.bge_tx_ring_paddr);
3477         if (error) {
3478                 if_printf(ifp, "could not create TX ring\n");
3479                 return error;
3480         }
3481
3482         /*
3483          * Create DMA stuffs for status block.
3484          */
3485         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3486                                     &sc->bge_cdata.bge_status_tag,
3487                                     &sc->bge_cdata.bge_status_map,
3488                                     (void **)&sc->bge_ldata.bge_status_block,
3489                                     &sc->bge_ldata.bge_status_block_paddr);
3490         if (error) {
3491                 if_printf(ifp, "could not create status block\n");
3492                 return error;
3493         }
3494
3495         /*
3496          * Create DMA stuffs for statistics block.
3497          */
3498         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3499                                     &sc->bge_cdata.bge_stats_tag,
3500                                     &sc->bge_cdata.bge_stats_map,
3501                                     (void **)&sc->bge_ldata.bge_stats,
3502                                     &sc->bge_ldata.bge_stats_paddr);
3503         if (error) {
3504                 if_printf(ifp, "could not create stats block\n");
3505                 return error;
3506         }
3507         return 0;
3508 }
3509
3510 static int
3511 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3512                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3513 {
3514         struct ifnet *ifp = &sc->arpcom.ac_if;
3515         struct bge_dmamap_arg ctx;
3516         bus_dma_segment_t seg;
3517         int error;
3518
3519         /*
3520          * Create DMA tag
3521          */
3522         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3523                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3524                                    NULL, NULL, size, 1, size, 0, tag);
3525         if (error) {
3526                 if_printf(ifp, "could not allocate dma tag\n");
3527                 return error;
3528         }
3529
3530         /*
3531          * Allocate DMA'able memory
3532          */
3533         error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3534                                  map);
3535         if (error) {
3536                 if_printf(ifp, "could not allocate dma memory\n");
3537                 bus_dma_tag_destroy(*tag);
3538                 *tag = NULL;
3539                 return error;
3540         }
3541
3542         /*
3543          * Load the DMA'able memory
3544          */
3545         ctx.bge_maxsegs = 1;
3546         ctx.bge_segs = &seg;
3547         error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3548                                 BUS_DMA_WAITOK);
3549         if (error) {
3550                 if_printf(ifp, "could not load dma memory\n");
3551                 bus_dmamem_free(*tag, *addr, *map);
3552                 bus_dma_tag_destroy(*tag);
3553                 *tag = NULL;
3554                 return error;
3555         }
3556         *paddr = ctx.bge_segs[0].ds_addr;
3557
3558         return 0;
3559 }
3560
3561 static void
3562 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3563 {
3564         if (tag != NULL) {
3565                 bus_dmamap_unload(tag, map);
3566                 bus_dmamem_free(tag, addr, map);
3567                 bus_dma_tag_destroy(tag);
3568         }
3569 }
3570
3571 /*
3572  * Grrr. The link status word in the status block does
3573  * not work correctly on the BCM5700 rev AX and BX chips,
3574  * according to all available information. Hence, we have
3575  * to enable MII interrupts in order to properly obtain
3576  * async link changes. Unfortunately, this also means that
3577  * we have to read the MAC status register to detect link
3578  * changes, thereby adding an additional register access to
3579  * the interrupt handler.
3580  *
3581  * XXX: perhaps link state detection procedure used for
3582  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3583  */
3584 static void
3585 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3586 {
3587         struct ifnet *ifp = &sc->arpcom.ac_if;
3588         struct mii_data *mii = device_get_softc(sc->bge_miibus);
3589
3590         mii_pollstat(mii);
3591
3592         if (!sc->bge_link &&
3593             (mii->mii_media_status & IFM_ACTIVE) &&
3594             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3595                 sc->bge_link++;
3596                 if (bootverbose)
3597                         if_printf(ifp, "link UP\n");
3598         } else if (sc->bge_link &&
3599             (!(mii->mii_media_status & IFM_ACTIVE) ||
3600             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3601                 sc->bge_link = 0;
3602                 if (bootverbose)
3603                         if_printf(ifp, "link DOWN\n");
3604         }
3605
3606         /* Clear the interrupt. */
3607         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3608         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3609         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3610 }
3611
3612 static void
3613 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3614 {
3615         struct ifnet *ifp = &sc->arpcom.ac_if;
3616
3617 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3618
3619         /*
3620          * Sometimes PCS encoding errors are detected in
3621          * TBI mode (on fiber NICs), and for some reason
3622          * the chip will signal them as link changes.
3623          * If we get a link change event, but the 'PCS
3624          * encoding error' bit in the MAC status register
3625          * is set, don't bother doing a link check.
3626          * This avoids spurious "gigabit link up" messages
3627          * that sometimes appear on fiber NICs during
3628          * periods of heavy traffic.
3629          */
3630         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3631                 if (!sc->bge_link) {
3632                         sc->bge_link++;
3633                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3634                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
3635                                     BGE_MACMODE_TBI_SEND_CFGS);
3636                         }
3637                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3638
3639                         if (bootverbose)
3640                                 if_printf(ifp, "link UP\n");
3641
3642                         ifp->if_link_state = LINK_STATE_UP;
3643                         if_link_state_change(ifp);
3644                 }
3645         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3646                 if (sc->bge_link) {
3647                         sc->bge_link = 0;
3648
3649                         if (bootverbose)
3650                                 if_printf(ifp, "link DOWN\n");
3651
3652                         ifp->if_link_state = LINK_STATE_DOWN;
3653                         if_link_state_change(ifp);
3654                 }
3655         }
3656
3657 #undef PCS_ENCODE_ERR
3658
3659         /* Clear the attention. */
3660         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3661             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3662             BGE_MACSTAT_LINK_CHANGED);
3663 }
3664
3665 static void
3666 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3667 {
3668         /*
3669          * Check that the AUTOPOLL bit is set before
3670          * processing the event as a real link change.
3671          * Turning AUTOPOLL on and off in the MII read/write
3672          * functions will often trigger a link status
3673          * interrupt for no reason.
3674          */
3675         if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3676                 struct ifnet *ifp = &sc->arpcom.ac_if;
3677                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3678
3679                 mii_pollstat(mii);
3680
3681                 if (!sc->bge_link &&
3682                     (mii->mii_media_status & IFM_ACTIVE) &&
3683                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3684                         sc->bge_link++;
3685                         if (bootverbose)
3686                                 if_printf(ifp, "link UP\n");
3687                 } else if (sc->bge_link &&
3688                     (!(mii->mii_media_status & IFM_ACTIVE) ||
3689                     IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3690                         sc->bge_link = 0;
3691                         if (bootverbose)
3692                                 if_printf(ifp, "link DOWN\n");
3693                 }
3694         }
3695
3696         /* Clear the attention. */
3697         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3698             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3699             BGE_MACSTAT_LINK_CHANGED);
3700 }
3701
3702 static int
3703 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3704 {
3705         struct bge_softc *sc = arg1;
3706
3707         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3708                                    &sc->bge_rx_coal_ticks,
3709                                    BGE_RX_COAL_TICKS_CHG);
3710 }
3711
3712 static int
3713 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3714 {
3715         struct bge_softc *sc = arg1;
3716
3717         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3718                                    &sc->bge_tx_coal_ticks,
3719                                    BGE_TX_COAL_TICKS_CHG);
3720 }
3721
3722 static int
3723 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3724 {
3725         struct bge_softc *sc = arg1;
3726
3727         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3728                                    &sc->bge_rx_max_coal_bds,
3729                                    BGE_RX_MAX_COAL_BDS_CHG);
3730 }
3731
3732 static int
3733 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3734 {
3735         struct bge_softc *sc = arg1;
3736
3737         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3738                                    &sc->bge_tx_max_coal_bds,
3739                                    BGE_TX_MAX_COAL_BDS_CHG);
3740 }
3741
3742 static int
3743 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3744                     uint32_t coal_chg_mask)
3745 {
3746         struct bge_softc *sc = arg1;
3747         struct ifnet *ifp = &sc->arpcom.ac_if;
3748         int error = 0, v;
3749
3750         lwkt_serialize_enter(ifp->if_serializer);
3751
3752         v = *coal;
3753         error = sysctl_handle_int(oidp, &v, 0, req);
3754         if (!error && req->newptr != NULL) {
3755                 if (v < 0) {
3756                         error = EINVAL;
3757                 } else {
3758                         *coal = v;
3759                         sc->bge_coal_chg |= coal_chg_mask;
3760                 }
3761         }
3762
3763         lwkt_serialize_exit(ifp->if_serializer);
3764         return error;
3765 }
3766
3767 static void
3768 bge_coal_change(struct bge_softc *sc)
3769 {
3770         struct ifnet *ifp = &sc->arpcom.ac_if;
3771         uint32_t val;
3772
3773         ASSERT_SERIALIZED(ifp->if_serializer);
3774
3775         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3776                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3777                             sc->bge_rx_coal_ticks);
3778                 DELAY(10);
3779                 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3780
3781                 if (bootverbose) {
3782                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3783                                   sc->bge_rx_coal_ticks);
3784                 }
3785         }
3786
3787         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3788                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3789                             sc->bge_tx_coal_ticks);
3790                 DELAY(10);
3791                 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3792
3793                 if (bootverbose) {
3794                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3795                                   sc->bge_tx_coal_ticks);
3796                 }
3797         }
3798
3799         if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3800                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3801                             sc->bge_rx_max_coal_bds);
3802                 DELAY(10);
3803                 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3804
3805                 if (bootverbose) {
3806                         if_printf(ifp, "rx_max_coal_bds -> %u\n",
3807                                   sc->bge_rx_max_coal_bds);
3808                 }
3809         }
3810
3811         if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3812                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3813                             sc->bge_tx_max_coal_bds);
3814                 DELAY(10);
3815                 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3816
3817                 if (bootverbose) {
3818                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
3819                                   sc->bge_tx_max_coal_bds);
3820                 }
3821         }
3822
3823         sc->bge_coal_chg = 0;
3824 }