2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
45 #include "opt_compat.h"
48 #include "opt_directio.h"
50 #include "opt_msgbuf.h"
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/sysproto.h>
56 #include <sys/signalvar.h>
57 #include <sys/kernel.h>
58 #include <sys/linker.h>
59 #include <sys/malloc.h>
63 #include <sys/reboot.h>
65 #include <sys/msgbuf.h>
66 #include <sys/sysent.h>
67 #include <sys/sysctl.h>
68 #include <sys/vmmeter.h>
70 #include <sys/usched.h>
73 #include <sys/ctype.h>
74 #include <sys/serialize.h>
75 #include <sys/systimer.h>
78 #include <vm/vm_param.h>
80 #include <vm/vm_kern.h>
81 #include <vm/vm_object.h>
82 #include <vm/vm_page.h>
83 #include <vm/vm_map.h>
84 #include <vm/vm_pager.h>
85 #include <vm/vm_extern.h>
87 #include <sys/thread2.h>
88 #include <sys/mplock2.h>
89 #include <sys/mutex2.h>
97 #include <machine/cpu.h>
98 #include <machine/clock.h>
99 #include <machine/specialreg.h>
101 #include <machine/bootinfo.h>
103 #include <machine/md_var.h>
104 #include <machine/metadata.h>
105 #include <machine/pc/bios.h>
106 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
107 #include <machine/globaldata.h> /* CPU_prvspace */
108 #include <machine/smp.h>
110 #include <machine/perfmon.h>
112 #include <machine/cputypes.h>
113 #include <machine/intr_machdep.h>
116 #include <bus/isa/isa_device.h>
118 #include <machine_base/isa/isa_intr.h>
119 #include <bus/isa/rtc.h>
120 #include <sys/random.h>
121 #include <sys/ptrace.h>
122 #include <machine/sigframe.h>
124 #include <sys/machintr.h>
125 #include <machine_base/icu/icu_abi.h>
126 #include <machine_base/icu/elcr_var.h>
127 #include <machine_base/apic/lapic.h>
128 #include <machine_base/apic/ioapic.h>
129 #include <machine_base/apic/ioapic_abi.h>
130 #include <machine/mptable.h>
132 #define PHYSMAP_ENTRIES 10
134 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
136 extern void printcpuinfo(void); /* XXX header file */
137 extern void identify_cpu(void);
139 extern void finishidentcpu(void);
141 extern void panicifcpuunsupported(void);
143 static void cpu_startup(void *);
144 static void pic_finish(void *);
145 static void cpu_finish(void *);
147 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
148 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
150 extern void ffs_rawread_setup(void);
151 #endif /* DIRECTIO */
152 static void init_locks(void);
154 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
155 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL);
156 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL);
159 extern vm_offset_t ksym_start, ksym_end;
162 struct privatespace CPU_prvspace_bsp __aligned(4096);
163 struct privatespace *CPU_prvspace[MAXCPU] = { &CPU_prvspace_bsp };
165 int _udatasel, _ucodesel, _ucode32sel;
167 int64_t tsc_offsets[MAXCPU];
169 static int cpu_mwait_halt_global; /* MWAIT hint (EAX) or CPU_MWAIT_HINT_ */
171 #if defined(SWTCH_OPTIM_STATS)
172 extern int swtch_optim_stats;
173 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
174 CTLFLAG_RD, &swtch_optim_stats, 0, "");
175 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
176 CTLFLAG_RD, &tlb_flush_count, 0, "");
178 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
179 CTLFLAG_RD, &cpu_mwait_halt_global, 0, "");
180 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_spin, CTLFLAG_RD, &cpu_mwait_spin, 0,
181 "monitor/mwait target state");
183 #define CPU_MWAIT_HAS_CX \
184 ((cpu_feature2 & CPUID2_MON) && \
185 (cpu_mwait_feature & CPUID_MWAIT_EXT))
187 #define CPU_MWAIT_CX_NAMELEN 16
189 #define CPU_MWAIT_C1 1
190 #define CPU_MWAIT_C2 2
191 #define CPU_MWAIT_C3 3
192 #define CPU_MWAIT_CX_MAX 8
194 #define CPU_MWAIT_HINT_AUTO -1 /* C1 and C2 */
195 #define CPU_MWAIT_HINT_AUTODEEP -2 /* C3+ */
197 SYSCTL_NODE(_machdep, OID_AUTO, mwait, CTLFLAG_RW, 0, "MWAIT features");
198 SYSCTL_NODE(_machdep_mwait, OID_AUTO, CX, CTLFLAG_RW, 0, "MWAIT Cx settings");
200 struct cpu_mwait_cx {
203 struct sysctl_ctx_list sysctl_ctx;
204 struct sysctl_oid *sysctl_tree;
206 static struct cpu_mwait_cx cpu_mwait_cx_info[CPU_MWAIT_CX_MAX];
207 static char cpu_mwait_cx_supported[256];
209 static int cpu_mwait_c1_hints_cnt;
210 static int cpu_mwait_hints_cnt;
211 static int *cpu_mwait_hints;
213 static int cpu_mwait_deep_hints_cnt;
214 static int *cpu_mwait_deep_hints;
216 #define CPU_IDLE_REPEAT_DEFAULT 750
218 static u_int cpu_idle_repeat = CPU_IDLE_REPEAT_DEFAULT;
219 static u_long cpu_idle_repeat_max = CPU_IDLE_REPEAT_DEFAULT;
220 static u_int cpu_mwait_repeat_shift = 1;
222 #define CPU_MWAIT_C3_PREAMBLE_BM_ARB 0x1
223 #define CPU_MWAIT_C3_PREAMBLE_BM_STS 0x2
225 static int cpu_mwait_c3_preamble =
226 CPU_MWAIT_C3_PREAMBLE_BM_ARB |
227 CPU_MWAIT_C3_PREAMBLE_BM_STS;
229 SYSCTL_STRING(_machdep_mwait_CX, OID_AUTO, supported, CTLFLAG_RD,
230 cpu_mwait_cx_supported, 0, "MWAIT supported C states");
232 static int cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS,
234 static int cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS);
235 static int cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS);
236 static int cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS);
238 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, idle, CTLTYPE_STRING|CTLFLAG_RW,
239 NULL, 0, cpu_mwait_cx_idle_sysctl, "A", "");
240 SYSCTL_PROC(_machdep_mwait_CX, OID_AUTO, spin, CTLTYPE_STRING|CTLFLAG_RW,
241 NULL, 0, cpu_mwait_cx_spin_sysctl, "A", "");
242 SYSCTL_UINT(_machdep_mwait_CX, OID_AUTO, repeat_shift, CTLFLAG_RW,
243 &cpu_mwait_repeat_shift, 0, "");
247 u_long ebda_addr = 0;
249 int imcr_present = 0;
251 int naps = 0; /* # of Applications processors */
254 struct mtx dt_lock; /* lock for GDT and LDT */
257 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
259 u_long pmem = ctob(physmem);
261 int error = sysctl_handle_long(oidp, &pmem, 0, req);
265 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
266 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
269 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
271 int error = sysctl_handle_int(oidp, 0,
272 ctob(physmem - vmstats.v_wire_count), req);
276 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
277 0, 0, sysctl_hw_usermem, "IU", "");
280 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
282 int error = sysctl_handle_int(oidp, 0,
283 x86_64_btop(avail_end - avail_start), req);
287 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
288 0, 0, sysctl_hw_availpages, "I", "");
294 * The number of PHYSMAP entries must be one less than the number of
295 * PHYSSEG entries because the PHYSMAP entry that spans the largest
296 * physical address that is accessible by ISA DMA is split into two
299 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
301 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
302 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
304 /* must be 2 less so 0 0 can signal end of chunks */
305 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
306 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
308 static vm_offset_t buffer_sva, buffer_eva;
309 vm_offset_t clean_sva, clean_eva;
310 static vm_offset_t pager_sva, pager_eva;
311 static struct trapframe proc0_tf;
314 cpu_startup(void *dummy)
318 vm_offset_t firstaddr;
321 * Good {morning,afternoon,evening,night}.
323 kprintf("%s", version);
326 panicifcpuunsupported();
330 kprintf("real memory = %ju (%ju MB)\n",
332 (intmax_t)Realmem / 1024 / 1024);
334 * Display any holes after the first chunk of extended memory.
339 kprintf("Physical memory chunk(s):\n");
340 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
341 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
343 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
344 (intmax_t)phys_avail[indx],
345 (intmax_t)phys_avail[indx + 1] - 1,
347 (intmax_t)(size1 / PAGE_SIZE));
352 * Allocate space for system data structures.
353 * The first available kernel virtual address is in "v".
354 * As pages of kernel virtual memory are allocated, "v" is incremented.
355 * As pages of memory are allocated and cleared,
356 * "firstaddr" is incremented.
357 * An index into the kernel page table corresponding to the
358 * virtual memory address maintained in "v" is kept in "mapaddr".
362 * Make two passes. The first pass calculates how much memory is
363 * needed and allocates it. The second pass assigns virtual
364 * addresses to the various data structures.
368 v = (caddr_t)firstaddr;
370 #define valloc(name, type, num) \
371 (name) = (type *)v; v = (caddr_t)((name)+(num))
372 #define valloclim(name, type, num, lim) \
373 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
376 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
377 * For the first 64MB of ram nominally allocate sufficient buffers to
378 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
379 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
380 * the buffer cache we limit the eventual kva reservation to
383 * factor represents the 1/4 x ram conversion.
386 long factor = 4 * BKVASIZE / 1024;
387 long kbytes = physmem * (PAGE_SIZE / 1024);
391 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
393 nbuf += (kbytes - 65536) * 2 / (factor * 5);
394 if (maxbcache && nbuf > maxbcache / BKVASIZE)
395 nbuf = maxbcache / BKVASIZE;
399 * Do not allow the buffer_map to be more then 1/2 the size of the
402 if (nbuf > (virtual_end - virtual_start +
403 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
404 nbuf = (virtual_end - virtual_start +
405 virtual2_end - virtual2_start) / (BKVASIZE * 2);
406 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
410 * Do not allow the buffer_map to use more than 50% of available
411 * physical-equivalent memory. Since the VM pages which back
412 * individual buffers are typically wired, having too many bufs
413 * can prevent the system from paging properly.
415 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
416 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
417 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
421 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
422 * the valloc space which is just the virtual_end - virtual_start
423 * section. We use valloc() to allocate the buf header array.
425 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
426 nbuf = (virtual_end - virtual_start) /
427 sizeof(struct buf) / 2;
428 kprintf("Warning: nbufs capped at %ld due to valloc "
429 "considerations", nbuf);
432 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
434 if (nswbuf < NSWBUF_MIN)
441 valloc(swbuf, struct buf, nswbuf);
442 valloc(buf, struct buf, nbuf);
445 * End of first pass, size has been calculated so allocate memory
447 if (firstaddr == 0) {
448 size = (vm_size_t)(v - firstaddr);
449 firstaddr = kmem_alloc(&kernel_map, round_page(size));
451 panic("startup: no room for tables");
456 * End of second pass, addresses have been assigned
458 * nbuf is an int, make sure we don't overflow the field.
460 * On 64-bit systems we always reserve maximal allocations for
461 * buffer cache buffers and there are no fragmentation issues,
462 * so the KVA segment does not have to be excessively oversized.
464 if ((vm_size_t)(v - firstaddr) != size)
465 panic("startup: table size inconsistency");
467 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
468 ((vm_offset_t)(nbuf + 16) * BKVASIZE) +
469 (nswbuf * MAXPHYS) + pager_map_size);
470 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
471 ((vm_offset_t)(nbuf + 16) * BKVASIZE));
472 buffer_map.system_map = 1;
473 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
474 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
475 pager_map.system_map = 1;
477 #if defined(USERCONFIG)
479 cninit(); /* the preferred console may have changed */
482 kprintf("avail memory = %ju (%ju MB)\n",
483 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
484 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
488 struct cpu_idle_stat {
496 u_long mwait_cx[CPU_MWAIT_CX_MAX];
499 #define CPU_IDLE_STAT_HALT -1
500 #define CPU_IDLE_STAT_SPIN -2
502 static struct cpu_idle_stat cpu_idle_stats[MAXCPU];
505 sysctl_cpu_idle_cnt(SYSCTL_HANDLER_ARGS)
507 int idx = arg2, cpu, error;
510 if (idx == CPU_IDLE_STAT_HALT) {
511 for (cpu = 0; cpu < ncpus; ++cpu)
512 val += cpu_idle_stats[cpu].halt;
513 } else if (idx == CPU_IDLE_STAT_SPIN) {
514 for (cpu = 0; cpu < ncpus; ++cpu)
515 val += cpu_idle_stats[cpu].spin;
517 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
518 ("invalid index %d", idx));
519 for (cpu = 0; cpu < ncpus; ++cpu)
520 val += cpu_idle_stats[cpu].mwait_cx[idx];
523 error = sysctl_handle_quad(oidp, &val, 0, req);
524 if (error || req->newptr == NULL)
527 if (idx == CPU_IDLE_STAT_HALT) {
528 for (cpu = 0; cpu < ncpus; ++cpu)
529 cpu_idle_stats[cpu].halt = 0;
530 cpu_idle_stats[0].halt = val;
531 } else if (idx == CPU_IDLE_STAT_SPIN) {
532 for (cpu = 0; cpu < ncpus; ++cpu)
533 cpu_idle_stats[cpu].spin = 0;
534 cpu_idle_stats[0].spin = val;
536 KASSERT(idx >= 0 && idx < CPU_MWAIT_CX_MAX,
537 ("invalid index %d", idx));
538 for (cpu = 0; cpu < ncpus; ++cpu)
539 cpu_idle_stats[cpu].mwait_cx[idx] = 0;
540 cpu_idle_stats[0].mwait_cx[idx] = val;
546 cpu_mwait_attach(void)
551 if (!CPU_MWAIT_HAS_CX)
554 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
555 (CPUID_TO_FAMILY(cpu_id) > 0xf ||
556 (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
557 CPUID_TO_MODEL(cpu_id) >= 0xf))) {
561 * Pentium dual-core, Core 2 and beyond do not need any
562 * additional activities to enter deep C-state, i.e. C3(+).
564 cpu_mwait_cx_no_bmarb();
566 TUNABLE_INT_FETCH("machdep.cpu.mwait.bm_sts", &bm_sts);
568 cpu_mwait_cx_no_bmsts();
571 sbuf_new(&sb, cpu_mwait_cx_supported,
572 sizeof(cpu_mwait_cx_supported), SBUF_FIXEDLEN);
574 for (i = 0; i < CPU_MWAIT_CX_MAX; ++i) {
575 struct cpu_mwait_cx *cx = &cpu_mwait_cx_info[i];
578 ksnprintf(cx->name, sizeof(cx->name), "C%d", i);
580 sysctl_ctx_init(&cx->sysctl_ctx);
581 cx->sysctl_tree = SYSCTL_ADD_NODE(&cx->sysctl_ctx,
582 SYSCTL_STATIC_CHILDREN(_machdep_mwait), OID_AUTO,
583 cx->name, CTLFLAG_RW, NULL, "Cx control/info");
584 if (cx->sysctl_tree == NULL)
587 cx->subcnt = CPUID_MWAIT_CX_SUBCNT(cpu_mwait_extemu, i);
588 SYSCTL_ADD_INT(&cx->sysctl_ctx,
589 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
590 "subcnt", CTLFLAG_RD, &cx->subcnt, 0,
592 SYSCTL_ADD_PROC(&cx->sysctl_ctx,
593 SYSCTL_CHILDREN(cx->sysctl_tree), OID_AUTO,
594 "entered", (CTLTYPE_QUAD | CTLFLAG_RW), 0,
595 i, sysctl_cpu_idle_cnt, "Q", "# of times entered");
597 for (sub = 0; sub < cx->subcnt; ++sub)
598 sbuf_printf(&sb, "C%d/%d ", i, sub);
606 cpu_mwait_c1_hints_cnt = cpu_mwait_cx_info[CPU_MWAIT_C1].subcnt;
607 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i)
608 cpu_mwait_hints_cnt += cpu_mwait_cx_info[i].subcnt;
609 cpu_mwait_hints = kmalloc(sizeof(int) * cpu_mwait_hints_cnt,
613 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_C3; ++i) {
616 subcnt = cpu_mwait_cx_info[i].subcnt;
617 for (j = 0; j < subcnt; ++j) {
618 KASSERT(hint_idx < cpu_mwait_hints_cnt,
619 ("invalid mwait hint index %d", hint_idx));
620 cpu_mwait_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
624 KASSERT(hint_idx == cpu_mwait_hints_cnt,
625 ("mwait hint count %d != index %d",
626 cpu_mwait_hints_cnt, hint_idx));
629 kprintf("MWAIT hints (%d C1 hints):\n", cpu_mwait_c1_hints_cnt);
630 for (i = 0; i < cpu_mwait_hints_cnt; ++i) {
631 int hint = cpu_mwait_hints[i];
633 kprintf(" C%d/%d hint 0x%04x\n",
634 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
642 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i)
643 cpu_mwait_deep_hints_cnt += cpu_mwait_cx_info[i].subcnt;
644 cpu_mwait_deep_hints = kmalloc(sizeof(int) * cpu_mwait_deep_hints_cnt,
648 for (i = CPU_MWAIT_C1; i < CPU_MWAIT_CX_MAX; ++i) {
651 subcnt = cpu_mwait_cx_info[i].subcnt;
652 for (j = 0; j < subcnt; ++j) {
653 KASSERT(hint_idx < cpu_mwait_deep_hints_cnt,
654 ("invalid mwait deep hint index %d", hint_idx));
655 cpu_mwait_deep_hints[hint_idx] = MWAIT_EAX_HINT(i, j);
659 KASSERT(hint_idx == cpu_mwait_deep_hints_cnt,
660 ("mwait deep hint count %d != index %d",
661 cpu_mwait_deep_hints_cnt, hint_idx));
664 kprintf("MWAIT deep hints:\n");
665 for (i = 0; i < cpu_mwait_deep_hints_cnt; ++i) {
666 int hint = cpu_mwait_deep_hints[i];
668 kprintf(" C%d/%d hint 0x%04x\n",
669 MWAIT_EAX_TO_CX(hint), MWAIT_EAX_TO_CX_SUB(hint),
673 cpu_idle_repeat_max = 256 * cpu_mwait_deep_hints_cnt;
675 for (i = 0; i < ncpus; ++i) {
678 ksnprintf(name, sizeof(name), "idle%d", i);
679 SYSCTL_ADD_PROC(NULL,
680 SYSCTL_STATIC_CHILDREN(_machdep_mwait_CX), OID_AUTO,
681 name, (CTLTYPE_STRING | CTLFLAG_RW), &cpu_idle_stats[i],
682 0, cpu_mwait_cx_pcpu_idle_sysctl, "A", "");
687 cpu_finish(void *dummy __unused)
694 pic_finish(void *dummy __unused)
696 /* Log ELCR information */
699 /* Log MPTABLE information */
700 mptable_pci_int_dump();
703 MachIntrABI.finalize();
707 * Send an interrupt to process.
709 * Stack is set up to allow sigcode stored
710 * at top to call routine, followed by kcall
711 * to sigreturn routine below. After sigreturn
712 * resets the signal mask, the stack, and the
713 * frame pointer, it returns to the user
717 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
719 struct lwp *lp = curthread->td_lwp;
720 struct proc *p = lp->lwp_proc;
721 struct trapframe *regs;
722 struct sigacts *psp = p->p_sigacts;
723 struct sigframe sf, *sfp;
727 regs = lp->lwp_md.md_regs;
728 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
730 /* Save user context */
731 bzero(&sf, sizeof(struct sigframe));
732 sf.sf_uc.uc_sigmask = *mask;
733 sf.sf_uc.uc_stack = lp->lwp_sigstk;
734 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
735 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
736 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
738 /* Make the size of the saved context visible to userland */
739 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
741 /* Allocate and validate space for the signal handler context. */
742 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
743 SIGISMEMBER(psp->ps_sigonstack, sig)) {
744 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
745 sizeof(struct sigframe));
746 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
748 /* We take red zone into account */
749 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
753 * XXX AVX needs 64-byte alignment but sigframe has other fields and
754 * the embedded ucontext is not at the front, so aligning this won't
755 * help us. Fortunately we bcopy in/out of the sigframe, so the
758 * The problem though is if userland winds up trying to use the
761 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
763 /* Translate the signal is appropriate */
764 if (p->p_sysent->sv_sigtbl) {
765 if (sig <= p->p_sysent->sv_sigsize)
766 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
770 * Build the argument list for the signal handler.
772 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
774 regs->tf_rdi = sig; /* argument 1 */
775 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
777 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
779 * Signal handler installed with SA_SIGINFO.
781 * action(signo, siginfo, ucontext)
783 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
784 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
785 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
787 /* fill siginfo structure */
788 sf.sf_si.si_signo = sig;
789 sf.sf_si.si_code = code;
790 sf.sf_si.si_addr = (void *)regs->tf_addr;
793 * Old FreeBSD-style arguments.
795 * handler (signo, code, [uc], addr)
797 regs->tf_rsi = (register_t)code; /* argument 2 */
798 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
799 sf.sf_ahu.sf_handler = catcher;
803 * If we're a vm86 process, we want to save the segment registers.
804 * We also change eflags to be our emulated eflags, not the actual
808 if (regs->tf_eflags & PSL_VM) {
809 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
810 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
812 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
813 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
814 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
815 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
817 if (vm86->vm86_has_vme == 0)
818 sf.sf_uc.uc_mcontext.mc_eflags =
819 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
820 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
823 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
824 * syscalls made by the signal handler. This just avoids
825 * wasting time for our lazy fixup of such faults. PSL_NT
826 * does nothing in vm86 mode, but vm86 programs can set it
827 * almost legitimately in probes for old cpu types.
829 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
834 * Save the FPU state and reinit the FP unit
836 npxpush(&sf.sf_uc.uc_mcontext);
839 * Copy the sigframe out to the user's stack.
841 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
843 * Something is wrong with the stack pointer.
844 * ...Kill the process.
849 regs->tf_rsp = (register_t)sfp;
850 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
853 * i386 abi specifies that the direction flag must be cleared
856 regs->tf_rflags &= ~(PSL_T|PSL_D);
859 * 64 bit mode has a code and stack selector but
860 * no data or extra selector. %fs and %gs are not
863 regs->tf_cs = _ucodesel;
864 regs->tf_ss = _udatasel;
869 * Sanitize the trapframe for a virtual kernel passing control to a custom
870 * VM context. Remove any items that would otherwise create a privilage
873 * XXX at the moment we allow userland to set the resume flag. Is this a
877 cpu_sanitize_frame(struct trapframe *frame)
879 frame->tf_cs = _ucodesel;
880 frame->tf_ss = _udatasel;
881 /* XXX VM (8086) mode not supported? */
882 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
883 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
889 * Sanitize the tls so loading the descriptor does not blow up
890 * on us. For x86_64 we don't have to do anything.
893 cpu_sanitize_tls(struct savetls *tls)
899 * sigreturn(ucontext_t *sigcntxp)
901 * System call to cleanup state after a signal
902 * has been taken. Reset signal mask and
903 * stack state from context left by sendsig (above).
904 * Return to previous pc and psl as specified by
905 * context left by sendsig. Check carefully to
906 * make sure that the user has not modified the
907 * state to gain improper privileges.
911 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
912 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
915 sys_sigreturn(struct sigreturn_args *uap)
917 struct lwp *lp = curthread->td_lwp;
918 struct trapframe *regs;
926 * We have to copy the information into kernel space so userland
927 * can't modify it while we are sniffing it.
929 regs = lp->lwp_md.md_regs;
930 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
934 rflags = ucp->uc_mcontext.mc_rflags;
936 /* VM (8086) mode not supported */
937 rflags &= ~PSL_VM_UNSUPP;
940 if (eflags & PSL_VM) {
941 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
942 struct vm86_kernel *vm86;
945 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
946 * set up the vm86 area, and we can't enter vm86 mode.
948 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
950 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
951 if (vm86->vm86_inited == 0)
954 /* go back to user mode if both flags are set */
955 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
956 trapsignal(lp, SIGBUS, 0);
958 if (vm86->vm86_has_vme) {
959 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
960 (eflags & VME_USERCHANGE) | PSL_VM;
962 vm86->vm86_eflags = eflags; /* save VIF, VIP */
963 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
964 (eflags & VM_USERCHANGE) | PSL_VM;
966 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
967 tf->tf_eflags = eflags;
968 tf->tf_vm86_ds = tf->tf_ds;
969 tf->tf_vm86_es = tf->tf_es;
970 tf->tf_vm86_fs = tf->tf_fs;
971 tf->tf_vm86_gs = tf->tf_gs;
972 tf->tf_ds = _udatasel;
973 tf->tf_es = _udatasel;
974 tf->tf_fs = _udatasel;
975 tf->tf_gs = _udatasel;
980 * Don't allow users to change privileged or reserved flags.
983 * XXX do allow users to change the privileged flag PSL_RF.
984 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
985 * should sometimes set it there too. tf_eflags is kept in
986 * the signal context during signal handling and there is no
987 * other place to remember it, so the PSL_RF bit may be
988 * corrupted by the signal handler without us knowing.
989 * Corruption of the PSL_RF bit at worst causes one more or
990 * one less debugger trap, so allowing it is fairly harmless.
992 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
993 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
998 * Don't allow users to load a valid privileged %cs. Let the
999 * hardware check for invalid selectors, excess privilege in
1000 * other selectors, invalid %eip's and invalid %esp's.
1002 cs = ucp->uc_mcontext.mc_cs;
1003 if (!CS_SECURE(cs)) {
1004 kprintf("sigreturn: cs = 0x%x\n", cs);
1005 trapsignal(lp, SIGBUS, T_PROTFLT);
1008 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
1012 * Restore the FPU state from the frame
1015 npxpop(&ucp->uc_mcontext);
1017 if (ucp->uc_mcontext.mc_onstack & 1)
1018 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
1020 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
1022 lp->lwp_sigmask = ucp->uc_sigmask;
1023 SIG_CANTMASK(lp->lwp_sigmask);
1026 return(EJUSTRETURN);
1030 * Machine dependent boot() routine
1032 * I haven't seen anything to put here yet
1033 * Possibly some stuff might be grafted back here from boot()
1041 * Shutdown the CPU as much as possible
1047 __asm__ __volatile("hlt");
1051 * cpu_idle() represents the idle LWKT. You cannot return from this function
1052 * (unless you want to blow things up!). Instead we look for runnable threads
1053 * and loop or halt as appropriate. Giant is not held on entry to the thread.
1055 * The main loop is entered with a critical section held, we must release
1056 * the critical section before doing anything else. lwkt_switch() will
1057 * check for pending interrupts due to entering and exiting its own
1060 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
1061 * However, there are cases where the idlethread will be entered with
1062 * the possibility that no IPI will occur and in such cases
1063 * lwkt_switch() sets TDF_IDLE_NOHLT.
1065 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
1066 * must occur before it starts using ACPI halt.
1068 * NOTE: Value overridden in hammer_time().
1070 static int cpu_idle_hlt = 2;
1071 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
1072 &cpu_idle_hlt, 0, "Idle loop HLT enable");
1073 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
1074 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
1076 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_hltcnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1077 0, CPU_IDLE_STAT_HALT, sysctl_cpu_idle_cnt, "Q", "Idle loop entry halts");
1078 SYSCTL_PROC(_machdep, OID_AUTO, cpu_idle_spincnt, (CTLTYPE_QUAD | CTLFLAG_RW),
1079 0, CPU_IDLE_STAT_SPIN, sysctl_cpu_idle_cnt, "Q", "Idle loop entry spins");
1082 cpu_idle_default_hook(void)
1085 * We must guarentee that hlt is exactly the instruction
1086 * following the sti.
1088 __asm __volatile("sti; hlt");
1091 /* Other subsystems (e.g., ACPI) can hook this later. */
1092 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
1095 cpu_mwait_cx_hint(struct cpu_idle_stat *stat)
1104 idx = (stat->repeat + stat->repeat_last + stat->repeat_delta) >>
1105 cpu_mwait_repeat_shift;
1106 if (idx >= cpu_mwait_c1_hints_cnt) {
1107 /* Step up faster, once we walked through all C1 states */
1108 stat->repeat_delta += 1 << (cpu_mwait_repeat_shift + 1);
1110 if (hint == CPU_MWAIT_HINT_AUTODEEP) {
1111 if (idx >= cpu_mwait_deep_hints_cnt)
1112 idx = cpu_mwait_deep_hints_cnt - 1;
1113 hint = cpu_mwait_deep_hints[idx];
1115 if (idx >= cpu_mwait_hints_cnt)
1116 idx = cpu_mwait_hints_cnt - 1;
1117 hint = cpu_mwait_hints[idx];
1120 cx_idx = MWAIT_EAX_TO_CX(hint);
1121 if (cx_idx >= 0 && cx_idx < CPU_MWAIT_CX_MAX)
1122 stat->mwait_cx[cx_idx]++;
1129 globaldata_t gd = mycpu;
1130 struct cpu_idle_stat *stat = &cpu_idle_stats[gd->gd_cpuid];
1131 struct thread *td __debugvar = gd->gd_curthread;
1135 stat->repeat = stat->repeat_last = cpu_idle_repeat_max;
1138 KKASSERT(td->td_critcount == 0);
1142 * See if there are any LWKTs ready to go.
1147 * When halting inside a cli we must check for reqflags
1148 * races, particularly [re]schedule requests. Running
1149 * splz() does the job.
1152 * 0 Never halt, just spin
1154 * 1 Always use HLT (or MONITOR/MWAIT if avail).
1156 * Better default for modern (Haswell+) Intel
1159 * 2 Use HLT/MONITOR/MWAIT up to a point and then
1160 * use the ACPI halt (default). This is a hybrid
1161 * approach. See machdep.cpu_idle_repeat.
1163 * Better default for modern AMD cpus and older
1166 * 3 Always use the ACPI halt. This typically
1167 * eats the least amount of power but the cpu
1168 * will be slow waking up. Slows down e.g.
1169 * compiles and other pipe/event oriented stuff.
1173 * NOTE: Interrupts are enabled and we are not in a critical
1176 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
1177 * don't bother capping gd_idle_repeat, it is ok if
1180 if (gd->gd_idle_repeat == 0) {
1181 stat->repeat = (stat->repeat + stat->repeat_last) >> 1;
1182 if (stat->repeat > cpu_idle_repeat_max)
1183 stat->repeat = cpu_idle_repeat_max;
1184 stat->repeat_last = 0;
1185 stat->repeat_delta = 0;
1187 ++stat->repeat_last;
1189 ++gd->gd_idle_repeat;
1190 reqflags = gd->gd_reqflags;
1191 quick = (cpu_idle_hlt == 1) ||
1192 (cpu_idle_hlt < 3 &&
1193 gd->gd_idle_repeat < cpu_idle_repeat);
1195 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
1196 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1198 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
1199 cpu_mwait_cx_hint(stat), 0);
1201 } else if (cpu_idle_hlt) {
1202 __asm __volatile("cli");
1204 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
1206 cpu_idle_default_hook();
1210 __asm __volatile("sti");
1214 __asm __volatile("sti");
1221 * This routine is called if a spinlock has been held through the
1222 * exponential backoff period and is seriously contested. On a real cpu
1226 cpu_spinlock_contested(void)
1232 * Clear registers on exec
1235 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
1237 struct thread *td = curthread;
1238 struct lwp *lp = td->td_lwp;
1239 struct pcb *pcb = td->td_pcb;
1240 struct trapframe *regs = lp->lwp_md.md_regs;
1242 /* was i386_user_cleanup() in NetBSD */
1246 bzero((char *)regs, sizeof(struct trapframe));
1247 regs->tf_rip = entry;
1248 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
1249 regs->tf_rdi = stack; /* argv */
1250 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
1251 regs->tf_ss = _udatasel;
1252 regs->tf_cs = _ucodesel;
1253 regs->tf_rbx = ps_strings;
1256 * Reset the hardware debug registers if they were in use.
1257 * They won't have any meaning for the newly exec'd process.
1259 if (pcb->pcb_flags & PCB_DBREGS) {
1265 pcb->pcb_dr7 = 0; /* JG set bit 10? */
1266 if (pcb == td->td_pcb) {
1268 * Clear the debug registers on the running
1269 * CPU, otherwise they will end up affecting
1270 * the next process we switch to.
1274 pcb->pcb_flags &= ~PCB_DBREGS;
1278 * Initialize the math emulator (if any) for the current process.
1279 * Actually, just clear the bit that says that the emulator has
1280 * been initialized. Initialization is delayed until the process
1281 * traps to the emulator (if it is done at all) mainly because
1282 * emulators don't provide an entry point for initialization.
1284 pcb->pcb_flags &= ~FP_SOFTFP;
1287 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
1288 * gd_npxthread. Otherwise a preemptive interrupt thread
1289 * may panic in npxdna().
1292 load_cr0(rcr0() | CR0_MP);
1295 * NOTE: The MSR values must be correct so we can return to
1296 * userland. gd_user_fs/gs must be correct so the switch
1297 * code knows what the current MSR values are.
1299 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
1300 pcb->pcb_gsbase = 0;
1301 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
1302 mdcpu->gd_user_gs = 0;
1303 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
1304 wrmsr(MSR_KGSBASE, 0);
1306 /* Initialize the npx (if any) for the current process. */
1310 pcb->pcb_ds = _udatasel;
1311 pcb->pcb_es = _udatasel;
1312 pcb->pcb_fs = _udatasel;
1313 pcb->pcb_gs = _udatasel;
1322 cr0 |= CR0_NE; /* Done by npxinit() */
1323 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1324 cr0 |= CR0_WP | CR0_AM;
1330 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1333 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1335 if (!error && req->newptr)
1340 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1341 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1343 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1344 CTLFLAG_RW, &disable_rtc_set, 0, "");
1347 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1348 CTLFLAG_RD, &bootinfo, bootinfo, "");
1351 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1352 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1354 extern u_long bootdev; /* not a cdev_t - encoding is different */
1355 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1356 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1359 * Initialize 386 and configure to run kernel
1363 * Initialize segments & interrupt table
1367 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1368 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1370 union descriptor ldt[NLDT]; /* local descriptor table */
1373 /* table descriptors - used to load tables by cpu */
1374 struct region_descriptor r_gdt;
1375 struct region_descriptor r_idt_arr[MAXCPU];
1377 /* JG proc0paddr is a virtual address */
1380 char proc0paddr_buff[LWKT_THREAD_STACK];
1383 /* software prototypes -- in more palatable form */
1384 struct soft_segment_descriptor gdt_segs[] = {
1385 /* GNULL_SEL 0 Null Descriptor */
1386 { 0x0, /* segment base address */
1388 0, /* segment type */
1389 0, /* segment descriptor priority level */
1390 0, /* segment descriptor present */
1392 0, /* default 32 vs 16 bit size */
1393 0 /* limit granularity (byte/page units)*/ },
1394 /* GCODE_SEL 1 Code Descriptor for kernel */
1395 { 0x0, /* segment base address */
1396 0xfffff, /* length - all address space */
1397 SDT_MEMERA, /* segment type */
1398 SEL_KPL, /* segment descriptor priority level */
1399 1, /* segment descriptor present */
1401 0, /* default 32 vs 16 bit size */
1402 1 /* limit granularity (byte/page units)*/ },
1403 /* GDATA_SEL 2 Data Descriptor for kernel */
1404 { 0x0, /* segment base address */
1405 0xfffff, /* length - all address space */
1406 SDT_MEMRWA, /* segment type */
1407 SEL_KPL, /* segment descriptor priority level */
1408 1, /* segment descriptor present */
1410 0, /* default 32 vs 16 bit size */
1411 1 /* limit granularity (byte/page units)*/ },
1412 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1413 { 0x0, /* segment base address */
1414 0xfffff, /* length - all address space */
1415 SDT_MEMERA, /* segment type */
1416 SEL_UPL, /* segment descriptor priority level */
1417 1, /* segment descriptor present */
1419 1, /* default 32 vs 16 bit size */
1420 1 /* limit granularity (byte/page units)*/ },
1421 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1422 { 0x0, /* segment base address */
1423 0xfffff, /* length - all address space */
1424 SDT_MEMRWA, /* segment type */
1425 SEL_UPL, /* segment descriptor priority level */
1426 1, /* segment descriptor present */
1428 1, /* default 32 vs 16 bit size */
1429 1 /* limit granularity (byte/page units)*/ },
1430 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1431 { 0x0, /* segment base address */
1432 0xfffff, /* length - all address space */
1433 SDT_MEMERA, /* segment type */
1434 SEL_UPL, /* segment descriptor priority level */
1435 1, /* segment descriptor present */
1437 0, /* default 32 vs 16 bit size */
1438 1 /* limit granularity (byte/page units)*/ },
1439 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1441 0x0, /* segment base address */
1442 sizeof(struct x86_64tss)-1,/* length - all address space */
1443 SDT_SYSTSS, /* segment type */
1444 SEL_KPL, /* segment descriptor priority level */
1445 1, /* segment descriptor present */
1447 0, /* unused - default 32 vs 16 bit size */
1448 0 /* limit granularity (byte/page units)*/ },
1449 /* Actually, the TSS is a system descriptor which is double size */
1450 { 0x0, /* segment base address */
1452 0, /* segment type */
1453 0, /* segment descriptor priority level */
1454 0, /* segment descriptor present */
1456 0, /* default 32 vs 16 bit size */
1457 0 /* limit granularity (byte/page units)*/ },
1458 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1459 { 0x0, /* segment base address */
1460 0xfffff, /* length - all address space */
1461 SDT_MEMRWA, /* segment type */
1462 SEL_UPL, /* segment descriptor priority level */
1463 1, /* segment descriptor present */
1465 1, /* default 32 vs 16 bit size */
1466 1 /* limit granularity (byte/page units)*/ },
1470 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1474 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1475 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1477 ip->gd_looffset = (uintptr_t)func;
1478 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1484 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1489 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1491 struct gate_descriptor *ip;
1493 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1495 ip = &idt_arr[cpu][idx];
1496 ip->gd_looffset = (uintptr_t)func;
1497 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1503 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1506 #define IDTVEC(name) __CONCAT(X,name)
1509 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1510 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1511 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1512 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1513 IDTVEC(xmm), IDTVEC(dblfault),
1514 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1516 #ifdef DEBUG_INTERRUPTS
1517 extern inthand_t *Xrsvdary[256];
1521 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1523 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1524 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1525 ssd->ssd_type = sd->sd_type;
1526 ssd->ssd_dpl = sd->sd_dpl;
1527 ssd->ssd_p = sd->sd_p;
1528 ssd->ssd_def32 = sd->sd_def32;
1529 ssd->ssd_gran = sd->sd_gran;
1533 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1536 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1537 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1538 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1539 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1540 sd->sd_type = ssd->ssd_type;
1541 sd->sd_dpl = ssd->ssd_dpl;
1542 sd->sd_p = ssd->ssd_p;
1543 sd->sd_long = ssd->ssd_long;
1544 sd->sd_def32 = ssd->ssd_def32;
1545 sd->sd_gran = ssd->ssd_gran;
1549 ssdtosyssd(struct soft_segment_descriptor *ssd,
1550 struct system_segment_descriptor *sd)
1553 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1554 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1555 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1556 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1557 sd->sd_type = ssd->ssd_type;
1558 sd->sd_dpl = ssd->ssd_dpl;
1559 sd->sd_p = ssd->ssd_p;
1560 sd->sd_gran = ssd->ssd_gran;
1564 * Populate the (physmap) array with base/bound pairs describing the
1565 * available physical memory in the system, then test this memory and
1566 * build the phys_avail array describing the actually-available memory.
1568 * If we cannot accurately determine the physical memory map, then use
1569 * value from the 0xE801 call, and failing that, the RTC.
1571 * Total memory size may be set by the kernel environment variable
1572 * hw.physmem or the compile-time define MAXMEM.
1574 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1575 * of PAGE_SIZE. This also greatly reduces the memory test time
1576 * which would otherwise be excessive on machines with > 8G of ram.
1578 * XXX first should be vm_paddr_t.
1581 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1582 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1583 vm_paddr_t physmap[PHYSMAP_SIZE];
1584 struct bios_smap *smapbase, *smap, *smapend;
1588 getmemsize(caddr_t kmdp, u_int64_t first)
1590 int off, physmap_idx, pa_indx, da_indx;
1593 vm_paddr_t msgbuf_size;
1594 u_long physmem_tunable;
1596 quad_t dcons_addr, dcons_size;
1598 bzero(physmap, sizeof(physmap));
1602 * get memory map from INT 15:E820, kindly supplied by the loader.
1604 * subr_module.c says:
1605 * "Consumer may safely assume that size value precedes data."
1606 * ie: an int32_t immediately precedes smap.
1608 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1609 MODINFO_METADATA | MODINFOMD_SMAP);
1610 if (smapbase == NULL)
1611 panic("No BIOS smap info from loader!");
1613 smapsize = *((u_int32_t *)smapbase - 1);
1614 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1616 for (smap = smapbase; smap < smapend; smap++) {
1617 if (boothowto & RB_VERBOSE)
1618 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1619 smap->type, smap->base, smap->length);
1621 if (smap->type != SMAP_TYPE_MEMORY)
1624 if (smap->length == 0)
1627 for (i = 0; i <= physmap_idx; i += 2) {
1628 if (smap->base < physmap[i + 1]) {
1629 if (boothowto & RB_VERBOSE) {
1630 kprintf("Overlapping or non-monotonic "
1631 "memory region, ignoring "
1637 if (i <= physmap_idx)
1640 Realmem += smap->length;
1642 if (smap->base == physmap[physmap_idx + 1]) {
1643 physmap[physmap_idx + 1] += smap->length;
1648 if (physmap_idx == PHYSMAP_SIZE) {
1649 kprintf("Too many segments in the physical "
1650 "address map, giving up\n");
1653 physmap[physmap_idx] = smap->base;
1654 physmap[physmap_idx + 1] = smap->base + smap->length;
1657 base_memory = physmap[1] / 1024;
1658 /* make hole for AP bootstrap code */
1659 physmap[1] = mp_bootaddress(base_memory);
1661 /* Save EBDA address, if any */
1662 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1666 * Maxmem isn't the "maximum memory", it's one larger than the
1667 * highest page of the physical address space. It should be
1668 * called something like "Maxphyspage". We may adjust this
1669 * based on ``hw.physmem'' and the results of the memory test.
1671 Maxmem = atop(physmap[physmap_idx + 1]);
1674 Maxmem = MAXMEM / 4;
1677 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1678 Maxmem = atop(physmem_tunable);
1681 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1684 if (Maxmem > atop(physmap[physmap_idx + 1]))
1685 Maxmem = atop(physmap[physmap_idx + 1]);
1688 * Blowing out the DMAP will blow up the system.
1690 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1691 kprintf("Limiting Maxmem due to DMAP size\n");
1692 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1695 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1696 (boothowto & RB_VERBOSE)) {
1697 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1701 * Call pmap initialization to make new kernel address space
1705 pmap_bootstrap(&first);
1706 physmap[0] = PAGE_SIZE;
1709 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1712 for (i = j = 0; i <= physmap_idx; i += 2) {
1713 if (physmap[i+1] > ptoa(Maxmem))
1714 physmap[i+1] = ptoa(Maxmem);
1715 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1716 ~PHYSMAP_ALIGN_MASK;
1717 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1719 physmap[j] = physmap[i];
1720 physmap[j+1] = physmap[i+1];
1722 if (physmap[i] < physmap[i+1])
1725 physmap_idx = j - 2;
1728 * Align anything else used in the validation loop.
1730 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1733 * Size up each available chunk of physical memory.
1737 phys_avail[pa_indx++] = physmap[0];
1738 phys_avail[pa_indx] = physmap[0];
1739 dump_avail[da_indx] = physmap[0];
1743 * Get dcons buffer address
1745 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1746 kgetenv_quad("dcons.size", &dcons_size) == 0)
1750 * Validate the physical memory. The physical memory segments
1751 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1754 for (i = 0; i <= physmap_idx; i += 2) {
1757 end = physmap[i + 1];
1759 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
1760 int tmp, page_bad, full;
1761 int *ptr = (int *)CADDR1;
1765 * block out kernel memory as not available.
1767 if (pa >= 0x200000 && pa < first)
1771 * block out dcons buffer
1774 && pa >= trunc_page(dcons_addr)
1775 && pa < dcons_addr + dcons_size) {
1782 * map page into kernel: valid, read/write,non-cacheable
1785 kernel_pmap.pmap_bits[PG_V_IDX] |
1786 kernel_pmap.pmap_bits[PG_RW_IDX] |
1787 kernel_pmap.pmap_bits[PG_N_IDX];
1792 * Test for alternating 1's and 0's
1794 *(volatile int *)ptr = 0xaaaaaaaa;
1796 if (*(volatile int *)ptr != 0xaaaaaaaa)
1799 * Test for alternating 0's and 1's
1801 *(volatile int *)ptr = 0x55555555;
1803 if (*(volatile int *)ptr != 0x55555555)
1808 *(volatile int *)ptr = 0xffffffff;
1810 if (*(volatile int *)ptr != 0xffffffff)
1815 *(volatile int *)ptr = 0x0;
1817 if (*(volatile int *)ptr != 0x0)
1820 * Restore original value.
1825 * Adjust array of valid/good pages.
1827 if (page_bad == TRUE)
1830 * If this good page is a continuation of the
1831 * previous set of good pages, then just increase
1832 * the end pointer. Otherwise start a new chunk.
1833 * Note that "end" points one higher than end,
1834 * making the range >= start and < end.
1835 * If we're also doing a speculative memory
1836 * test and we at or past the end, bump up Maxmem
1837 * so that we keep going. The first bad page
1838 * will terminate the loop.
1840 if (phys_avail[pa_indx] == pa) {
1841 phys_avail[pa_indx] += PHYSMAP_ALIGN;
1844 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1846 "Too many holes in the physical address space, giving up\n");
1851 phys_avail[pa_indx++] = pa;
1852 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
1854 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
1856 if (dump_avail[da_indx] == pa) {
1857 dump_avail[da_indx] += PHYSMAP_ALIGN;
1860 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1864 dump_avail[da_indx++] = pa;
1865 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
1876 * The last chunk must contain at least one page plus the message
1877 * buffer to avoid complicating other code (message buffer address
1878 * calculation, etc.).
1880 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1882 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1883 msgbuf_size >= phys_avail[pa_indx]) {
1884 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1885 phys_avail[pa_indx--] = 0;
1886 phys_avail[pa_indx--] = 0;
1889 Maxmem = atop(phys_avail[pa_indx]);
1891 /* Trim off space for the message buffer. */
1892 phys_avail[pa_indx] -= msgbuf_size;
1894 avail_end = phys_avail[pa_indx];
1896 /* Map the message buffer. */
1897 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1898 pmap_kenter((vm_offset_t)msgbufp + off,
1899 phys_avail[pa_indx] + off);
1903 struct machintr_abi MachIntrABI;
1914 * 7 Device Not Available (x87)
1916 * 9 Coprocessor Segment overrun (unsupported, reserved)
1918 * 11 Segment not present
1920 * 13 General Protection
1923 * 16 x87 FP Exception pending
1924 * 17 Alignment Check
1926 * 19 SIMD floating point
1928 * 32-255 INTn/external sources
1931 hammer_time(u_int64_t modulep, u_int64_t physfree)
1934 int gsel_tss, x, cpu;
1936 int metadata_missing, off;
1938 struct mdglobaldata *gd;
1942 * Prevent lowering of the ipl if we call tsleep() early.
1944 gd = &CPU_prvspace[0]->mdglobaldata;
1945 bzero(gd, sizeof(*gd));
1948 * Note: on both UP and SMP curthread must be set non-NULL
1949 * early in the boot sequence because the system assumes
1950 * that 'curthread' is never NULL.
1953 gd->mi.gd_curthread = &thread0;
1954 thread0.td_gd = &gd->mi;
1956 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1959 metadata_missing = 0;
1960 if (bootinfo.bi_modulep) {
1961 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1962 preload_bootstrap_relocate(KERNBASE);
1964 metadata_missing = 1;
1966 if (bootinfo.bi_envp)
1967 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1970 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1971 preload_bootstrap_relocate(PTOV_OFFSET);
1972 kmdp = preload_search_by_type("elf kernel");
1974 kmdp = preload_search_by_type("elf64 kernel");
1975 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1976 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1978 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1979 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1982 if (boothowto & RB_VERBOSE)
1986 * Default MachIntrABI to ICU
1988 MachIntrABI = MachIntrABI_ICU;
1991 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1992 * and ncpus_fit_mask remain 0.
1997 /* Init basic tunables, hz etc */
2001 * make gdt memory segments
2003 gdt_segs[GPROC0_SEL].ssd_base =
2004 (uintptr_t) &CPU_prvspace[0]->mdglobaldata.gd_common_tss;
2006 gd->mi.gd_prvspace = CPU_prvspace[0];
2008 for (x = 0; x < NGDT; x++) {
2009 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
2010 ssdtosd(&gdt_segs[x], &gdt[x]);
2012 ssdtosyssd(&gdt_segs[GPROC0_SEL],
2013 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
2015 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
2016 r_gdt.rd_base = (long) gdt;
2019 wrmsr(MSR_FSBASE, 0); /* User value */
2020 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
2021 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
2023 mi_gdinit(&gd->mi, 0);
2025 proc0paddr = proc0paddr_buff;
2026 mi_proc0init(&gd->mi, proc0paddr);
2027 safepri = TDPRI_MAX;
2029 /* spinlocks and the BGL */
2033 for (x = 0; x < NIDT; x++)
2034 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
2035 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
2036 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
2037 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
2038 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
2039 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
2040 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
2041 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
2042 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
2043 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
2044 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
2045 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
2046 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
2047 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
2048 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
2049 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
2050 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
2051 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
2052 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
2053 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
2055 for (cpu = 0; cpu < MAXCPU; ++cpu) {
2056 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
2057 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
2060 lidt(&r_idt_arr[0]);
2063 * Initialize the console before we print anything out.
2068 if (metadata_missing)
2069 kprintf("WARNING: loader(8) metadata is missing!\n");
2079 * Initialize IRQ mapping
2082 * SHOULD be after elcr_probe()
2084 MachIntrABI_ICU.initmap();
2085 MachIntrABI_IOAPIC.initmap();
2089 if (boothowto & RB_KDB)
2090 Debugger("Boot flags requested debugger");
2094 finishidentcpu(); /* Final stage of CPU initialization */
2095 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2096 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
2098 identify_cpu(); /* Final stage of CPU initialization */
2099 initializecpu(0); /* Initialize CPU registers */
2102 * On modern intel cpus, haswell or later, cpu_idle_hlt=1 is better
2103 * becaue the cpu does significant power management in HLT
2104 * (also suggested is to set sysctl machdep.mwait.CX.idle=AUTODEEP).
2106 * On modern amd cpus or on any older amd or intel cpu,
2107 * cpu_idle_hlt=2 is better because ACPI is needed to reduce power
2110 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
2111 CPUID_TO_MODEL(cpu_id) >= 0x3C) { /* Haswell or later */
2115 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
2116 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
2117 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
2118 TUNABLE_INT_FETCH("machdep.cpu_idle_hlt", &cpu_idle_hlt);
2121 * Some of the virtual machines do not work w/ I/O APIC
2122 * enabled. If the user does not explicitly enable or
2123 * disable the I/O APIC (ioapic_enable < 0), then we
2124 * disable I/O APIC on all virtual machines.
2127 * This must be done after identify_cpu(), which sets
2130 if (ioapic_enable < 0) {
2131 if (cpu_feature2 & CPUID2_VMM)
2137 /* make an initial tss so cpu can get interrupt stack on syscall! */
2138 gd->gd_common_tss.tss_rsp0 =
2139 (register_t)(thread0.td_kstack +
2140 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
2141 /* Ensure the stack is aligned to 16 bytes */
2142 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
2144 /* double fault stack */
2145 gd->gd_common_tss.tss_ist1 =
2146 (long)&gd->mi.gd_prvspace->idlestack[
2147 sizeof(gd->mi.gd_prvspace->idlestack)];
2149 /* Set the IO permission bitmap (empty due to tss seg limit) */
2150 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
2152 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
2153 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
2154 gd->gd_common_tssd = *gd->gd_tss_gdt;
2157 /* Set up the fast syscall stuff */
2158 msr = rdmsr(MSR_EFER) | EFER_SCE;
2159 wrmsr(MSR_EFER, msr);
2160 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
2161 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
2162 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
2163 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
2164 wrmsr(MSR_STAR, msr);
2165 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
2167 getmemsize(kmdp, physfree);
2168 init_param2(physmem);
2170 /* now running on new page tables, configured,and u/iom is accessible */
2172 /* Map the message buffer. */
2174 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
2175 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
2178 msgbufinit(msgbufp, MSGBUF_SIZE);
2181 /* transfer to user mode */
2183 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
2184 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
2185 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
2191 /* setup proc 0's pcb */
2192 thread0.td_pcb->pcb_flags = 0;
2193 thread0.td_pcb->pcb_cr3 = KPML4phys;
2194 thread0.td_pcb->pcb_ext = NULL;
2195 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
2197 /* Location of kernel stack for locore */
2198 return ((u_int64_t)thread0.td_pcb);
2202 * Initialize machine-dependant portions of the global data structure.
2203 * Note that the global data area and cpu0's idlestack in the private
2204 * data space were allocated in locore.
2206 * Note: the idlethread's cpl is 0
2208 * WARNING! Called from early boot, 'mycpu' may not work yet.
2211 cpu_gdinit(struct mdglobaldata *gd, int cpu)
2214 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
2216 lwkt_init_thread(&gd->mi.gd_idlethread,
2217 gd->mi.gd_prvspace->idlestack,
2218 sizeof(gd->mi.gd_prvspace->idlestack),
2220 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
2221 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
2222 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
2223 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
2227 * We only have to check for DMAP bounds, the globaldata space is
2228 * actually part of the kernel_map so we don't have to waste time
2229 * checking CPU_prvspace[*].
2232 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
2235 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
2236 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
2240 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
2246 globaldata_find(int cpu)
2248 KKASSERT(cpu >= 0 && cpu < ncpus);
2249 return(&CPU_prvspace[cpu]->mdglobaldata.mi);
2253 * This path should be safe from the SYSRET issue because only stopped threads
2254 * can have their %rip adjusted this way (and all heavy weight thread switches
2255 * clear QUICKREF and thus do not use SYSRET). However, the code path is
2256 * convoluted so add a safety by forcing %rip to be cannonical.
2259 ptrace_set_pc(struct lwp *lp, unsigned long addr)
2261 if (addr & 0x0000800000000000LLU)
2262 lp->lwp_md.md_regs->tf_rip = addr | 0xFFFF000000000000LLU;
2264 lp->lwp_md.md_regs->tf_rip = addr & 0x0000FFFFFFFFFFFFLLU;
2269 ptrace_single_step(struct lwp *lp)
2271 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
2276 fill_regs(struct lwp *lp, struct reg *regs)
2278 struct trapframe *tp;
2280 if ((tp = lp->lwp_md.md_regs) == NULL)
2282 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
2287 set_regs(struct lwp *lp, struct reg *regs)
2289 struct trapframe *tp;
2291 tp = lp->lwp_md.md_regs;
2292 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
2293 !CS_SECURE(regs->r_cs))
2295 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
2301 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
2303 struct env87 *penv_87 = &sv_87->sv_env;
2304 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2307 /* FPU control/status */
2308 penv_87->en_cw = penv_xmm->en_cw;
2309 penv_87->en_sw = penv_xmm->en_sw;
2310 penv_87->en_tw = penv_xmm->en_tw;
2311 penv_87->en_fip = penv_xmm->en_fip;
2312 penv_87->en_fcs = penv_xmm->en_fcs;
2313 penv_87->en_opcode = penv_xmm->en_opcode;
2314 penv_87->en_foo = penv_xmm->en_foo;
2315 penv_87->en_fos = penv_xmm->en_fos;
2318 for (i = 0; i < 8; ++i)
2319 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
2323 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
2325 struct env87 *penv_87 = &sv_87->sv_env;
2326 struct envxmm *penv_xmm = &sv_xmm->sv_env;
2329 /* FPU control/status */
2330 penv_xmm->en_cw = penv_87->en_cw;
2331 penv_xmm->en_sw = penv_87->en_sw;
2332 penv_xmm->en_tw = penv_87->en_tw;
2333 penv_xmm->en_fip = penv_87->en_fip;
2334 penv_xmm->en_fcs = penv_87->en_fcs;
2335 penv_xmm->en_opcode = penv_87->en_opcode;
2336 penv_xmm->en_foo = penv_87->en_foo;
2337 penv_xmm->en_fos = penv_87->en_fos;
2340 for (i = 0; i < 8; ++i)
2341 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2345 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2347 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2350 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2351 (struct save87 *)fpregs);
2354 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2359 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2362 set_fpregs_xmm((struct save87 *)fpregs,
2363 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2366 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2371 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2376 dbregs->dr[0] = rdr0();
2377 dbregs->dr[1] = rdr1();
2378 dbregs->dr[2] = rdr2();
2379 dbregs->dr[3] = rdr3();
2380 dbregs->dr[4] = rdr4();
2381 dbregs->dr[5] = rdr5();
2382 dbregs->dr[6] = rdr6();
2383 dbregs->dr[7] = rdr7();
2386 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2388 dbregs->dr[0] = pcb->pcb_dr0;
2389 dbregs->dr[1] = pcb->pcb_dr1;
2390 dbregs->dr[2] = pcb->pcb_dr2;
2391 dbregs->dr[3] = pcb->pcb_dr3;
2394 dbregs->dr[6] = pcb->pcb_dr6;
2395 dbregs->dr[7] = pcb->pcb_dr7;
2400 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2403 load_dr0(dbregs->dr[0]);
2404 load_dr1(dbregs->dr[1]);
2405 load_dr2(dbregs->dr[2]);
2406 load_dr3(dbregs->dr[3]);
2407 load_dr4(dbregs->dr[4]);
2408 load_dr5(dbregs->dr[5]);
2409 load_dr6(dbregs->dr[6]);
2410 load_dr7(dbregs->dr[7]);
2413 struct ucred *ucred;
2415 uint64_t mask1, mask2;
2418 * Don't let an illegal value for dr7 get set. Specifically,
2419 * check for undefined settings. Setting these bit patterns
2420 * result in undefined behaviour and can lead to an unexpected
2423 /* JG this loop looks unreadable */
2424 /* Check 4 2-bit fields for invalid patterns.
2425 * These fields are R/Wi, for i = 0..3
2427 /* Is 10 in LENi allowed when running in compatibility mode? */
2428 /* Pattern 10 in R/Wi might be used to indicate
2429 * breakpoint on I/O. Further analysis should be
2430 * carried to decide if it is safe and useful to
2431 * provide access to that capability
2433 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2434 i++, mask1 <<= 4, mask2 <<= 4)
2435 if ((dbregs->dr[7] & mask1) == mask2)
2438 pcb = lp->lwp_thread->td_pcb;
2439 ucred = lp->lwp_proc->p_ucred;
2442 * Don't let a process set a breakpoint that is not within the
2443 * process's address space. If a process could do this, it
2444 * could halt the system by setting a breakpoint in the kernel
2445 * (if ddb was enabled). Thus, we need to check to make sure
2446 * that no breakpoints are being enabled for addresses outside
2447 * process's address space, unless, perhaps, we were called by
2450 * XXX - what about when the watched area of the user's
2451 * address space is written into from within the kernel
2452 * ... wouldn't that still cause a breakpoint to be generated
2453 * from within kernel mode?
2456 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2457 if (dbregs->dr[7] & 0x3) {
2458 /* dr0 is enabled */
2459 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2463 if (dbregs->dr[7] & (0x3<<2)) {
2464 /* dr1 is enabled */
2465 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2469 if (dbregs->dr[7] & (0x3<<4)) {
2470 /* dr2 is enabled */
2471 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2475 if (dbregs->dr[7] & (0x3<<6)) {
2476 /* dr3 is enabled */
2477 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2482 pcb->pcb_dr0 = dbregs->dr[0];
2483 pcb->pcb_dr1 = dbregs->dr[1];
2484 pcb->pcb_dr2 = dbregs->dr[2];
2485 pcb->pcb_dr3 = dbregs->dr[3];
2486 pcb->pcb_dr6 = dbregs->dr[6];
2487 pcb->pcb_dr7 = dbregs->dr[7];
2489 pcb->pcb_flags |= PCB_DBREGS;
2496 * Return > 0 if a hardware breakpoint has been hit, and the
2497 * breakpoint was in user space. Return 0, otherwise.
2500 user_dbreg_trap(void)
2502 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2503 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2504 int nbp; /* number of breakpoints that triggered */
2505 caddr_t addr[4]; /* breakpoint addresses */
2509 if ((dr7 & 0xff) == 0) {
2511 * all GE and LE bits in the dr7 register are zero,
2512 * thus the trap couldn't have been caused by the
2513 * hardware debug registers
2524 * None of the breakpoint bits are set meaning this
2525 * trap was not caused by any of the debug registers
2531 * at least one of the breakpoints were hit, check to see
2532 * which ones and if any of them are user space addresses
2536 addr[nbp++] = (caddr_t)rdr0();
2539 addr[nbp++] = (caddr_t)rdr1();
2542 addr[nbp++] = (caddr_t)rdr2();
2545 addr[nbp++] = (caddr_t)rdr3();
2548 for (i=0; i<nbp; i++) {
2550 (caddr_t)VM_MAX_USER_ADDRESS) {
2552 * addr[i] is in user space
2559 * None of the breakpoints are in user space.
2567 Debugger(const char *msg)
2569 kprintf("Debugger(\"%s\") called.\n", msg);
2576 * Provide inb() and outb() as functions. They are normally only
2577 * available as macros calling inlined functions, thus cannot be
2578 * called inside DDB.
2580 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2586 /* silence compiler warnings */
2588 void outb(u_int, u_char);
2595 * We use %%dx and not %1 here because i/o is done at %dx and not at
2596 * %edx, while gcc generates inferior code (movw instead of movl)
2597 * if we tell it to load (u_short) port.
2599 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2604 outb(u_int port, u_char data)
2608 * Use an unnecessary assignment to help gcc's register allocator.
2609 * This make a large difference for gcc-1.40 and a tiny difference
2610 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2611 * best results. gcc-2.6.0 can't handle this.
2614 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2622 * initialize all the SMP locks
2625 /* critical region when masking or unmasking interupts */
2626 struct spinlock_deprecated imen_spinlock;
2628 /* critical region for old style disable_intr/enable_intr */
2629 struct spinlock_deprecated mpintr_spinlock;
2631 /* critical region around INTR() routines */
2632 struct spinlock_deprecated intr_spinlock;
2634 /* lock region used by kernel profiling */
2635 struct spinlock_deprecated mcount_spinlock;
2637 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2638 struct spinlock_deprecated com_spinlock;
2640 /* lock regions around the clock hardware */
2641 struct spinlock_deprecated clock_spinlock;
2647 * Get the initial mplock with a count of 1 for the BSP.
2648 * This uses a LOGICAL cpu ID, ie BSP == 0.
2650 cpu_get_initial_mplock();
2652 spin_lock_init(&mcount_spinlock);
2653 spin_lock_init(&intr_spinlock);
2654 spin_lock_init(&mpintr_spinlock);
2655 spin_lock_init(&imen_spinlock);
2656 spin_lock_init(&com_spinlock);
2657 spin_lock_init(&clock_spinlock);
2659 /* our token pool needs to work early */
2660 lwkt_token_pool_init();
2664 cpu_mwait_hint_valid(uint32_t hint)
2668 cx_idx = MWAIT_EAX_TO_CX(hint);
2669 if (cx_idx >= CPU_MWAIT_CX_MAX)
2672 sub = MWAIT_EAX_TO_CX_SUB(hint);
2673 if (sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2680 cpu_mwait_cx_no_bmsts(void)
2682 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_STS);
2686 cpu_mwait_cx_no_bmarb(void)
2688 atomic_clear_int(&cpu_mwait_c3_preamble, CPU_MWAIT_C3_PREAMBLE_BM_ARB);
2692 cpu_mwait_cx_hint2name(int hint, char *name, int namelen, boolean_t allow_auto)
2694 int old_cx_idx, sub = 0;
2697 old_cx_idx = MWAIT_EAX_TO_CX(hint);
2698 sub = MWAIT_EAX_TO_CX_SUB(hint);
2699 } else if (hint == CPU_MWAIT_HINT_AUTO) {
2700 old_cx_idx = allow_auto ? CPU_MWAIT_C2 : CPU_MWAIT_CX_MAX;
2701 } else if (hint == CPU_MWAIT_HINT_AUTODEEP) {
2702 old_cx_idx = allow_auto ? CPU_MWAIT_C3 : CPU_MWAIT_CX_MAX;
2704 old_cx_idx = CPU_MWAIT_CX_MAX;
2707 if (!CPU_MWAIT_HAS_CX)
2708 strlcpy(name, "NONE", namelen);
2709 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTO)
2710 strlcpy(name, "AUTO", namelen);
2711 else if (allow_auto && hint == CPU_MWAIT_HINT_AUTODEEP)
2712 strlcpy(name, "AUTODEEP", namelen);
2713 else if (old_cx_idx >= CPU_MWAIT_CX_MAX ||
2714 sub >= cpu_mwait_cx_info[old_cx_idx].subcnt)
2715 strlcpy(name, "INVALID", namelen);
2717 ksnprintf(name, namelen, "C%d/%d", old_cx_idx, sub);
2723 cpu_mwait_cx_name2hint(char *name, int *hint0, boolean_t allow_auto)
2725 int cx_idx, sub, hint;
2728 if (allow_auto && strcmp(name, "AUTO") == 0) {
2729 hint = CPU_MWAIT_HINT_AUTO;
2730 cx_idx = CPU_MWAIT_C2;
2733 if (allow_auto && strcmp(name, "AUTODEEP") == 0) {
2734 hint = CPU_MWAIT_HINT_AUTODEEP;
2735 cx_idx = CPU_MWAIT_C3;
2739 if (strlen(name) < 4 || toupper(name[0]) != 'C')
2744 cx_idx = strtol(start, &ptr, 10);
2745 if (ptr == start || *ptr != '/')
2747 if (cx_idx < 0 || cx_idx >= CPU_MWAIT_CX_MAX)
2753 sub = strtol(start, &ptr, 10);
2756 if (sub < 0 || sub >= cpu_mwait_cx_info[cx_idx].subcnt)
2759 hint = MWAIT_EAX_HINT(cx_idx, sub);
2766 cpu_mwait_cx_transit(int old_cx_idx, int cx_idx)
2768 if (cx_idx >= CPU_MWAIT_C3 && cpu_mwait_c3_preamble)
2770 if (old_cx_idx < CPU_MWAIT_C3 && cx_idx >= CPU_MWAIT_C3) {
2773 error = cputimer_intr_powersave_addreq();
2776 } else if (old_cx_idx >= CPU_MWAIT_C3 && cx_idx < CPU_MWAIT_C3) {
2777 cputimer_intr_powersave_remreq();
2783 cpu_mwait_cx_select_sysctl(SYSCTL_HANDLER_ARGS, int *hint0,
2784 boolean_t allow_auto)
2786 int error, cx_idx, old_cx_idx, hint;
2787 char name[CPU_MWAIT_CX_NAMELEN];
2790 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name),
2793 error = sysctl_handle_string(oidp, name, sizeof(name), req);
2794 if (error != 0 || req->newptr == NULL)
2797 if (!CPU_MWAIT_HAS_CX)
2800 cx_idx = cpu_mwait_cx_name2hint(name, &hint, allow_auto);
2804 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
2813 cpu_mwait_cx_setname(struct cpu_idle_stat *stat, const char *cx_name)
2815 int error, cx_idx, old_cx_idx, hint;
2816 char name[CPU_MWAIT_CX_NAMELEN];
2818 KASSERT(CPU_MWAIT_HAS_CX, ("cpu does not support mwait CX extension"));
2821 old_cx_idx = cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
2823 strlcpy(name, cx_name, sizeof(name));
2824 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
2828 error = cpu_mwait_cx_transit(old_cx_idx, cx_idx);
2837 cpu_mwait_cx_idle_sysctl(SYSCTL_HANDLER_ARGS)
2839 int hint = cpu_mwait_halt_global;
2840 int error, cx_idx, cpu;
2841 char name[CPU_MWAIT_CX_NAMELEN], cx_name[CPU_MWAIT_CX_NAMELEN];
2843 cpu_mwait_cx_hint2name(hint, name, sizeof(name), TRUE);
2845 error = sysctl_handle_string(oidp, name, sizeof(name), req);
2846 if (error != 0 || req->newptr == NULL)
2849 if (!CPU_MWAIT_HAS_CX)
2852 /* Save name for later per-cpu CX configuration */
2853 strlcpy(cx_name, name, sizeof(cx_name));
2855 cx_idx = cpu_mwait_cx_name2hint(name, &hint, TRUE);
2859 /* Change per-cpu CX configuration */
2860 for (cpu = 0; cpu < ncpus; ++cpu) {
2861 error = cpu_mwait_cx_setname(&cpu_idle_stats[cpu], cx_name);
2866 cpu_mwait_halt_global = hint;
2871 cpu_mwait_cx_pcpu_idle_sysctl(SYSCTL_HANDLER_ARGS)
2873 struct cpu_idle_stat *stat = arg1;
2876 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2882 cpu_mwait_cx_spin_sysctl(SYSCTL_HANDLER_ARGS)
2886 error = cpu_mwait_cx_select_sysctl(oidp, arg1, arg2, req,
2887 &cpu_mwait_spin, FALSE);