2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-dma.c,v 1.35.2.31 2003/05/07 16:46:11 jhb Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-dma.c,v 1.5 2003/11/26 14:24:46 asmodai Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/malloc.h>
39 #include <sys/devicestat.h>
42 #include <bus/pci/pcivar.h>
43 #include <machine/bus.h>
48 static void cyrix_timing(struct ata_channel *, int, int);
49 static void promise_timing(struct ata_channel *, int, int);
50 static void hpt_timing(struct ata_channel *, int, int);
51 static int hpt_cable80(struct ata_channel *);
56 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
58 #define ATAPI_DEVICE(ch, device) \
59 ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) || \
60 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
63 ata_dmaalloc(struct ata_channel *ch, int device)
67 if ((dmatab = malloc(PAGE_SIZE, M_DEVBUF, M_NOWAIT))) {
68 if (((uintptr_t)dmatab >> PAGE_SHIFT) ^
69 (((uintptr_t)dmatab + PAGE_SIZE - 1) >> PAGE_SHIFT)) {
70 ata_printf(ch, device, "dmatab crosses page boundary, no DMA\n");
71 free(dmatab, M_DEVBUF);
79 ata_dmainit(struct ata_channel *ch, int device,
80 int apiomode, int wdmamode, int udmamode)
82 struct ata_device *atadev = &ch->device[ATA_DEV(device)];
83 device_t parent = device_get_parent(ch->dev);
84 int devno = (ch->unit << 1) + ATA_DEV(device);
87 /* set our most pessimistic default mode */
88 atadev->mode = ATA_PIO;
93 /* if simplex controller, only allow DMA on primary channel */
95 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
96 ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
97 (ATA_BMSTAT_DMA_MASTER | ATA_BMSTAT_DMA_SLAVE));
98 if (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_DMA_SIMPLEX) {
99 ata_prtdev(atadev, "simplex device, DMA on primary only\n");
104 /* DMA engine address alignment is usually 1 word (2 bytes) */
108 if (udmamode > 2 && !ch->device[ATA_DEV(device)].param->hwres_cblid) {
109 ata_prtdev(atadev,"DMA limited to UDMA33, non-ATA66 cable or device\n");
113 switch (ch->chiptype) {
115 case 0x24db8086: /* Intel ICH5 */
116 case 0x24ca8086: /* Intel ICH4 mobile */
117 case 0x24cb8086: /* Intel ICH4 */
118 case 0x248a8086: /* Intel ICH3 mobile */
119 case 0x248b8086: /* Intel ICH3 */
120 case 0x244a8086: /* Intel ICH2 mobile */
121 case 0x244b8086: /* Intel ICH2 */
123 int32_t mask48, new48;
126 word54 = pci_read_config(parent, 0x54, 2);
127 if (word54 & (0x10 << devno)) {
128 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
129 ATA_UDMA5, ATA_C_F_SETXFER,ATA_WAIT_READY);
131 ata_prtdev(atadev, "%s setting UDMA5 on Intel chip\n",
132 (error) ? "failed" : "success");
134 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
135 new48 = (1 << devno) + (1 << (16 + (devno << 2)));
136 pci_write_config(parent, 0x48,
137 (pci_read_config(parent, 0x48, 4) &
138 ~mask48) | new48, 4);
139 pci_write_config(parent, 0x54, word54 | (0x1000<<devno), 2);
140 atadev->mode = ATA_UDMA5;
145 /* make sure eventual ATA100 mode from the BIOS is disabled */
146 pci_write_config(parent, 0x54,
147 pci_read_config(parent, 0x54, 2) & ~(0x1000<<devno),2);
150 case 0x24118086: /* Intel ICH */
151 case 0x76018086: /* Intel ICH */
153 int32_t mask48, new48;
156 word54 = pci_read_config(parent, 0x54, 2);
157 if (word54 & (0x10 << devno)) {
158 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
159 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
161 ata_prtdev(atadev, "%s setting UDMA4 on Intel chip\n",
162 (error) ? "failed" : "success");
164 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
165 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
166 pci_write_config(parent, 0x48,
167 (pci_read_config(parent, 0x48, 4) &
168 ~mask48) | new48, 4);
169 pci_write_config(parent, 0x54, word54 | (1 << devno), 2);
170 atadev->mode = ATA_UDMA4;
175 /* make sure eventual ATA66 mode from the BIOS is disabled */
176 pci_write_config(parent, 0x54,
177 pci_read_config(parent, 0x54, 2) & ~(1 << devno), 2);
180 case 0x71118086: /* Intel PIIX4 */
181 case 0x84CA8086: /* Intel PIIX4 */
182 case 0x71998086: /* Intel PIIX4e */
183 case 0x24218086: /* Intel ICH0 */
185 int32_t mask48, new48;
187 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
188 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
190 ata_prtdev(atadev, "%s setting UDMA2 on Intel chip\n",
191 (error) ? "failed" : "success");
193 mask48 = (1 << devno) + (3 << (16 + (devno << 2)));
194 new48 = (1 << devno) + (2 << (16 + (devno << 2)));
195 pci_write_config(parent, 0x48,
196 (pci_read_config(parent, 0x48, 4) &
197 ~mask48) | new48, 4);
198 atadev->mode = ATA_UDMA2;
202 /* make sure eventual ATA33 mode from the BIOS is disabled */
203 pci_write_config(parent, 0x48,
204 pci_read_config(parent, 0x48, 4) & ~(1 << devno), 4);
207 case 0x70108086: /* Intel PIIX3 */
208 if (wdmamode >= 2 && apiomode >= 4) {
209 int32_t mask40, new40, mask44, new44;
211 /* if SITRE not set doit for both channels */
212 if (!((pci_read_config(parent,0x40,4)>>(ch->unit<<8))&0x4000)) {
213 new40 = pci_read_config(parent, 0x40, 4);
214 new44 = pci_read_config(parent, 0x44, 4);
215 if (!(new40 & 0x00004000)) {
216 new44 &= ~0x0000000f;
217 new44 |= ((new40&0x00003000)>>10)|((new40&0x00000300)>>8);
219 if (!(new40 & 0x40000000)) {
220 new44 &= ~0x000000f0;
221 new44 |= ((new40&0x30000000)>>22)|((new40&0x03000000)>>20);
224 pci_write_config(parent, 0x40, new40, 4);
225 pci_write_config(parent, 0x44, new44, 4);
227 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
228 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
230 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
231 (error) ? "failed" : "success");
233 if (device == ATA_MASTER) {
251 pci_write_config(parent, 0x40,
252 (pci_read_config(parent, 0x40, 4) & ~mask40)|
254 pci_write_config(parent, 0x44,
255 (pci_read_config(parent, 0x44, 4) & ~mask44)|
257 atadev->mode = ATA_WDMA2;
261 /* we could set PIO mode timings, but we assume the BIOS did that */
264 case 0x12308086: /* Intel PIIX */
265 if (wdmamode >= 2 && apiomode >= 4) {
268 word40 = pci_read_config(parent, 0x40, 4);
269 word40 >>= ch->unit * 16;
271 /* Check for timing config usable for DMA on controller */
272 if (!((word40 & 0x3300) == 0x2300 &&
273 ((word40 >> (device == ATA_MASTER ? 0 : 4)) & 1) == 1))
276 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
277 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
279 ata_prtdev(atadev, "%s setting WDMA2 on Intel chip\n",
280 (error) ? "failed" : "success");
282 atadev->mode = ATA_WDMA2;
288 case 0x522910b9: /* AcerLabs Aladdin IV/V */
289 /* the older Aladdin doesn't support ATAPI DMA on both master & slave */
290 if (pci_get_revid(parent) < 0xc2 &&
291 ch->devices & ATA_ATAPI_MASTER && ch->devices & ATA_ATAPI_SLAVE) {
292 ata_prtdev(atadev, "two atapi devices on this channel, no DMA\n");
295 if (udmamode >= 5 && pci_get_revid(parent) >= 0xc4) {
296 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
297 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
299 ata_prtdev(atadev, "%s setting UDMA5 on Acer chip\n",
300 (error) ? "failed" : "success");
302 int32_t word54 = pci_read_config(parent, 0x54, 4);
304 pci_write_config(parent, 0x4b,
305 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
306 word54 &= ~(0x000f000f << (devno << 2));
307 word54 |= (0x000f0005 << (devno << 2));
308 pci_write_config(parent, 0x54, word54, 4);
309 pci_write_config(parent, 0x53,
310 pci_read_config(parent, 0x53, 1) | 0x03, 1);
311 atadev->mode = ATA_UDMA5;
315 if (udmamode >= 4 && pci_get_revid(parent) >= 0xc2) {
316 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
317 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
319 ata_prtdev(atadev, "%s setting UDMA4 on Acer chip\n",
320 (error) ? "failed" : "success");
322 int32_t word54 = pci_read_config(parent, 0x54, 4);
324 pci_write_config(parent, 0x4b,
325 pci_read_config(parent, 0x4b, 1) | 0x01, 1);
326 word54 &= ~(0x000f000f << (devno << 2));
327 word54 |= (0x00080005 << (devno << 2));
328 pci_write_config(parent, 0x54, word54, 4);
329 pci_write_config(parent, 0x53,
330 pci_read_config(parent, 0x53, 1) | 0x03, 1);
331 atadev->mode = ATA_UDMA4;
335 if (udmamode >= 2 && pci_get_revid(parent) >= 0x20) {
336 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
337 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
339 ata_prtdev(atadev, "%s setting UDMA2 on Acer chip\n",
340 (error) ? "failed" : "success");
342 int32_t word54 = pci_read_config(parent, 0x54, 4);
344 word54 &= ~(0x000f000f << (devno << 2));
345 word54 |= (0x000a0005 << (devno << 2));
346 pci_write_config(parent, 0x54, word54, 4);
347 pci_write_config(parent, 0x53,
348 pci_read_config(parent, 0x53, 1) | 0x03, 1);
349 ch->flags |= ATA_ATAPI_DMA_RO;
350 atadev->mode = ATA_UDMA2;
355 /* make sure eventual UDMA mode from the BIOS is disabled */
356 pci_write_config(parent, 0x56, pci_read_config(parent, 0x56, 2) &
357 ~(0x0008 << (devno << 2)), 2);
359 if (wdmamode >= 2 && apiomode >= 4) {
360 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
361 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
363 ata_prtdev(atadev, "%s setting WDMA2 on Acer chip\n",
364 (error) ? "failed" : "success");
366 pci_write_config(parent, 0x53,
367 pci_read_config(parent, 0x53, 1) | 0x03, 1);
368 ch->flags |= ATA_ATAPI_DMA_RO;
369 atadev->mode = ATA_WDMA2;
373 pci_write_config(parent, 0x53,
374 (pci_read_config(parent, 0x53, 1) & ~0x01) | 0x02, 1);
375 /* we could set PIO mode timings, but we assume the BIOS did that */
378 case 0x01bc10de: /* NVIDIA nForce */
379 case 0x006510de: /* NVIDIA nForce2 */
380 case 0x74411022: /* AMD 768 */
381 case 0x74111022: /* AMD 766 */
382 case 0x74091022: /* AMD 756 */
383 case 0x05711106: /* VIA 82C571, 82C586, 82C596, 82C686, 8231,8233,8235 */
385 int via_modes[5][7] = {
386 { 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* ATA33 */
387 { 0x00, 0x00, 0xea, 0x00, 0xe8, 0x00, 0x00 }, /* ATA66 */
388 { 0x00, 0x00, 0xf4, 0x00, 0xf1, 0xf0, 0x00 }, /* ATA100 */
389 { 0x00, 0x00, 0xf6, 0x00, 0xf2, 0xf1, 0xf0 }, /* VIA ATA133 */
390 { 0x00, 0x00, 0xc0, 0x00, 0xc5, 0xc6, 0xc7 }}; /* AMD/NVIDIA */
394 if (ata_find_dev(parent, 0x31471106, 0) || /* 8233a */
395 ata_find_dev(parent, 0x31771106, 0)) { /* 8235 */
396 udmamode = imin(udmamode, 6);
397 reg_val = via_modes[3];
399 else if (ata_find_dev(parent, 0x06861106, 0x40) || /* 82C686b */
400 ata_find_dev(parent, 0x82311106, 0) || /* 8231 */
401 ata_find_dev(parent, 0x30741106, 0) || /* 8233 */
402 ata_find_dev(parent, 0x31091106, 0)) { /* 8233c */
403 udmamode = imin(udmamode, 5);
404 reg_val = via_modes[2];
406 else if (ata_find_dev(parent, 0x06861106, 0x10) || /* 82C686a */
407 ata_find_dev(parent, 0x05961106, 0x12)) { /* 82C596b */
408 udmamode = imin(udmamode, 4);
409 reg_val = via_modes[1];
411 else if (ata_find_dev(parent, 0x06861106, 0)) { /* 82C686 */
412 udmamode = imin(udmamode, 2);
413 reg_val = via_modes[1];
415 else if (ata_find_dev(parent, 0x05961106, 0) || /* 82C596a */
416 ata_find_dev(parent, 0x05861106, 0x03)) { /* 82C586b */
417 udmamode = imin(udmamode, 2);
418 reg_val = via_modes[0];
420 else if (ch->chiptype == 0x74411022 || /* AMD 768 */
421 ch->chiptype == 0x74111022) { /* AMD 766 */
422 udmamode = imin(udmamode, 5);
423 reg_val = via_modes[4];
426 else if (ch->chiptype == 0x74091022) { /* AMD 756 */
427 udmamode = imin(udmamode, 4);
428 reg_val = via_modes[4];
431 else if (ch->chiptype == 0x01bc10de) { /* nForce */
432 udmamode = imin(udmamode, 5);
433 reg_val = via_modes[4];
436 else if (ch->chiptype == 0x006510de) { /* nForce2 */
437 udmamode = imin(udmamode, 6);
438 reg_val = via_modes[4];
445 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
446 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
448 ata_prtdev(atadev, "%s setting UDMA6 on %s chip\n",
449 (error) ? "failed" : "success", chip);
451 pci_write_config(parent, 0x53 - devno, reg_val[6], 1);
452 atadev->mode = ATA_UDMA6;
457 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
458 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
460 ata_prtdev(atadev, "%s setting UDMA5 on %s chip\n",
461 (error) ? "failed" : "success", chip);
463 pci_write_config(parent, 0x53 - devno, reg_val[5], 1);
464 atadev->mode = ATA_UDMA5;
469 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
470 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
472 ata_prtdev(atadev, "%s setting UDMA4 on %s chip\n",
473 (error) ? "failed" : "success", chip);
475 pci_write_config(parent, 0x53 - devno, reg_val[4], 1);
476 atadev->mode = ATA_UDMA4;
481 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
482 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
484 ata_prtdev(atadev, "%s setting UDMA2 on %s chip\n",
485 (error) ? "failed" : "success", chip);
487 pci_write_config(parent, 0x53 - devno, reg_val[2], 1);
488 atadev->mode = ATA_UDMA2;
492 if (wdmamode >= 2 && apiomode >= 4) {
493 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
494 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
496 ata_prtdev(atadev, "%s setting WDMA2 on %s chip\n",
497 (error) ? "failed" : "success", chip);
499 pci_write_config(parent, 0x53 - devno, 0x0b, 1);
500 pci_write_config(parent, 0x4b - devno, 0x31, 1);
501 atadev->mode = ATA_WDMA2;
506 /* we could set PIO mode timings, but we assume the BIOS did that */
509 case 0x55131039: /* SiS 5591 */
510 if (ata_find_dev(parent, 0x06301039, 0x30) || /* SiS 630 */
511 ata_find_dev(parent, 0x06331039, 0) || /* SiS 633 */
512 ata_find_dev(parent, 0x06351039, 0) || /* SiS 635 */
513 ata_find_dev(parent, 0x06401039, 0) || /* SiS 640 */
514 ata_find_dev(parent, 0x06451039, 0) || /* SiS 645 */
515 ata_find_dev(parent, 0x06501039, 0) || /* SiS 650 */
516 ata_find_dev(parent, 0x07301039, 0) || /* SiS 730 */
517 ata_find_dev(parent, 0x07331039, 0) || /* SiS 733 */
518 ata_find_dev(parent, 0x07351039, 0) || /* SiS 735 */
519 ata_find_dev(parent, 0x07401039, 0) || /* SiS 740 */
520 ata_find_dev(parent, 0x07451039, 0) || /* SiS 745 */
521 ata_find_dev(parent, 0x07501039, 0)) { /* SiS 750 */
522 int8_t reg = 0x40 + (devno << 1);
523 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
526 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
527 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
529 ata_prtdev(atadev, "%s setting UDMA5 on SiS chip\n",
530 (error) ? "failed" : "success");
532 pci_write_config(parent, reg, val | 0x8000, 2);
533 atadev->mode = ATA_UDMA5;
538 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
539 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
541 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
542 (error) ? "failed" : "success");
544 pci_write_config(parent, reg, val | 0x9000, 2);
545 atadev->mode = ATA_UDMA4;
550 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
551 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
553 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
554 (error) ? "failed" : "success");
556 pci_write_config(parent, reg, val | 0xb000, 2);
557 atadev->mode = ATA_UDMA2;
561 } else if (ata_find_dev(parent, 0x05301039, 0) || /* SiS 530 */
562 ata_find_dev(parent, 0x05401039, 0) || /* SiS 540 */
563 ata_find_dev(parent, 0x06201039, 0) || /* SiS 620 */
564 ata_find_dev(parent, 0x06301039, 0)) { /* SiS 630 */
565 int8_t reg = 0x40 + (devno << 1);
566 int16_t val = pci_read_config(parent, reg, 2) & 0x0fff;
569 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
570 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
572 ata_prtdev(atadev, "%s setting UDMA4 on SiS chip\n",
573 (error) ? "failed" : "success");
575 pci_write_config(parent, reg, val | 0x9000, 2);
576 atadev->mode = ATA_UDMA4;
581 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
582 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
584 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
585 (error) ? "failed" : "success");
587 pci_write_config(parent, reg, val | 0xa000, 2);
588 atadev->mode = ATA_UDMA2;
592 } else if (udmamode >= 2 && pci_get_revid(parent) > 0xc1) {
593 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
594 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
596 ata_prtdev(atadev, "%s setting UDMA2 on SiS chip\n",
597 (error) ? "failed" : "success");
599 pci_write_config(parent, 0x40 + (devno << 1), 0xa301, 2);
600 atadev->mode = ATA_UDMA2;
604 if (wdmamode >=2 && apiomode >= 4) {
605 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
606 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
608 ata_prtdev(atadev, "%s setting WDMA2 on SiS chip\n",
609 (error) ? "failed" : "success");
611 pci_write_config(parent, 0x40 + (devno << 1), 0x0301, 2);
612 atadev->mode = ATA_WDMA2;
616 /* we could set PIO mode timings, but we assume the BIOS did that */
619 case 0x06801095: /* SiI 0680 ATA133 controller */
621 u_int8_t ureg = 0xac + (ATA_DEV(device) * 0x02) + (ch->unit * 0x10);
622 u_int8_t uval = pci_read_config(parent, ureg, 1);
623 u_int8_t mreg = ch->unit ? 0x84 : 0x80;
624 u_int8_t mask = ATA_DEV(device) ? 0x30 : 0x03;
625 u_int8_t mode = pci_read_config(parent, mreg, 1);
627 /* enable UDMA mode */
628 pci_write_config(parent, mreg,
629 (mode & ~mask) | (device ? 0x30 : 0x03), 1);
631 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
632 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
634 ata_prtdev(atadev, "%s setting UDMA6 on SiI chip\n",
635 (error) ? "failed" : "success");
637 pci_write_config(parent, ureg, (uval & 0x3f) | 0x01, 1);
638 atadev->mode = ATA_UDMA6;
643 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
644 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
646 ata_prtdev(atadev, "%s setting UDMA5 on SiI chip\n",
647 (error) ? "failed" : "success");
649 pci_write_config(parent, ureg, (uval & 0x3f) | 0x02, 1);
650 atadev->mode = ATA_UDMA5;
655 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
656 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
658 ata_prtdev(atadev, "%s setting UDMA4 on SiI chip\n",
659 (error) ? "failed" : "success");
661 pci_write_config(parent, ureg, (uval & 0x3f) | 0x03, 1);
662 atadev->mode = ATA_UDMA4;
667 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
668 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
670 ata_prtdev(atadev, "%s setting UDMA2 on SiI chip\n",
671 (error) ? "failed" : "success");
673 pci_write_config(parent, ureg, (uval & 0x3f) | 0x07, 1);
674 atadev->mode = ATA_UDMA2;
679 /* disable UDMA mode and enable WDMA mode */
680 pci_write_config(parent, mreg,
681 (mode & ~mask) | (device ? 0x20 : 0x02), 1);
682 if (wdmamode >= 2 && apiomode >= 4) {
683 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
684 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
686 ata_prtdev(atadev, "%s setting WDMA2 on SiI chip\n",
687 (error) ? "failed" : "success");
689 pci_write_config(parent, ureg - 0x4, 0x10c1, 2);
690 atadev->mode = ATA_WDMA2;
695 /* restore PIO mode */
696 pci_write_config(parent, mreg, mode, 1);
698 /* we could set PIO mode timings, but we assume the BIOS did that */
702 case 0x06491095: /* CMD 649 ATA100 controller */
706 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
707 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
709 ata_prtdev(atadev, "%s setting UDMA5 on CMD chip\n",
710 (error) ? "failed" : "success");
712 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
713 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
714 umode |= (device == ATA_MASTER ? 0x05 : 0x0a);
715 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
716 atadev->mode = ATA_UDMA5;
722 case 0x06481095: /* CMD 648 ATA66 controller */
726 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
727 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
729 ata_prtdev(atadev, "%s setting UDMA4 on CMD chip\n",
730 (error) ? "failed" : "success");
732 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
733 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
734 umode |= (device == ATA_MASTER ? 0x15 : 0x4a);
735 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
736 atadev->mode = ATA_UDMA4;
743 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
744 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
746 ata_prtdev(atadev, "%s setting UDMA2 on CMD chip\n",
747 (error) ? "failed" : "success");
749 umode = pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1);
750 umode &= ~(device == ATA_MASTER ? 0x35 : 0xca);
751 umode |= (device == ATA_MASTER ? 0x11 : 0x42);
752 pci_write_config(parent, ch->unit ? 0x7b : 0x73, umode, 1);
753 atadev->mode = ATA_UDMA2;
757 /* make sure eventual UDMA mode from the BIOS is disabled */
758 pci_write_config(parent, ch->unit ? 0x7b : 0x73,
759 pci_read_config(parent, ch->unit ? 0x7b : 0x73, 1)&
760 ~(device == ATA_MASTER ? 0x35 : 0xca), 1);
763 case 0x06461095: /* CMD 646 ATA controller */
764 if (wdmamode >= 2 && apiomode >= 4) {
765 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
766 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
768 ata_prtdev(atadev, "%s setting WDMA2 on CMD chip\n",
769 error ? "failed" : "success");
771 int32_t offset = (devno < 3) ? (devno << 1) : 7;
773 pci_write_config(parent, 0x54 + offset, 0x3f, 1);
774 atadev->mode = ATA_WDMA2;
778 /* we could set PIO mode timings, but we assume the BIOS did that */
781 case 0xc6931080: /* Cypress 82c693 ATA controller */
782 if (wdmamode >= 2 && apiomode >= 4) {
783 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
784 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
786 ata_prtdev(atadev, "%s setting WDMA2 on Cypress chip\n",
787 error ? "failed" : "success");
789 pci_write_config(ch->dev, ch->unit ? 0x4e:0x4c, 0x2020, 2);
790 atadev->mode = ATA_WDMA2;
794 /* we could set PIO mode timings, but we assume the BIOS did that */
797 case 0x01021078: /* Cyrix 5530 ATA33 controller */
798 ch->alignment = 0xf; /* DMA engine requires 16 byte alignment */
800 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
801 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
803 ata_prtdev(atadev, "%s setting UDMA2 on Cyrix chip\n",
804 (error) ? "failed" : "success");
806 cyrix_timing(ch, devno, ATA_UDMA2);
807 atadev->mode = ATA_UDMA2;
811 if (wdmamode >= 2 && apiomode >= 4) {
812 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
813 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
815 ata_prtdev(atadev, "%s setting WDMA2 on Cyrix chip\n",
816 (error) ? "failed" : "success");
818 cyrix_timing(ch, devno, ATA_WDMA2);
819 atadev->mode = ATA_WDMA2;
823 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
824 ATA_PIO0 + apiomode, ATA_C_F_SETXFER,
827 ata_prtdev(atadev, "%s setting %s on Cyrix chip\n",
828 (error) ? "failed" : "success",
829 ata_mode2str(ATA_PIO0 + apiomode));
830 cyrix_timing(ch, devno, ATA_PIO0 + apiomode);
831 atadev->mode = ATA_PIO0 + apiomode;
834 case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
835 if (udmamode >= 5 && pci_get_revid(parent) >= 0x92) {
836 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
837 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
839 ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
840 (error) ? "failed" : "success");
844 pci_write_config(parent, 0x54,
845 pci_read_config(parent, 0x54, 1) |
847 reg56 = pci_read_config(parent, 0x56, 2);
848 reg56 &= ~(0xf << (devno * 4));
849 reg56 |= (0x5 << (devno * 4));
850 pci_write_config(parent, 0x56, reg56, 2);
851 atadev->mode = ATA_UDMA5;
856 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
857 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
859 ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
860 (error) ? "failed" : "success");
864 pci_write_config(parent, 0x54,
865 pci_read_config(parent, 0x54, 1) |
867 reg56 = pci_read_config(parent, 0x56, 2);
868 reg56 &= ~(0xf << (devno * 4));
869 reg56 |= (0x4 << (devno * 4));
870 pci_write_config(parent, 0x56, reg56, 2);
871 atadev->mode = ATA_UDMA4;
877 case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
879 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
880 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
882 ata_prtdev(atadev, "%s setting UDMA2 on ServerWorks chip\n",
883 (error) ? "failed" : "success");
887 pci_write_config(parent, 0x54,
888 pci_read_config(parent, 0x54, 1) |
890 reg56 = pci_read_config(parent, 0x56, 2);
891 reg56 &= ~(0xf << (devno * 4));
892 reg56 |= (0x2 << (devno * 4));
893 pci_write_config(parent, 0x56, reg56, 2);
894 atadev->mode = ATA_UDMA2;
898 if (wdmamode >= 2 && apiomode >= 4) {
899 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
900 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
902 ata_prtdev(atadev, "%s setting WDMA2 on ServerWorks chip\n",
903 (error) ? "failed" : "success");
905 int offset = (ch->unit * 2) + (device == ATA_MASTER);
906 int word44 = pci_read_config(parent, 0x44, 4);
908 pci_write_config(parent, 0x54,
909 pci_read_config(parent, 0x54, 1) &
910 ~(0x01 << devno), 1);
911 word44 &= ~(0xff << (offset << 8));
912 word44 |= (0x20 << (offset << 8));
913 pci_write_config(parent, 0x44, 0x20, 4);
914 atadev->mode = ATA_WDMA2;
918 /* we could set PIO mode timings, but we assume the BIOS did that */
921 case 0x4d69105a: /* Promise TX2 ATA133 controllers */
922 case 0x5275105a: /* Promise TX2 ATA133 controllers */
923 case 0x6269105a: /* Promise TX2 ATA133 controllers */
924 case 0x7275105a: /* Promise TX2 ATA133 controllers */
925 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
926 if (udmamode >= 6 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
927 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
928 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
930 ata_prtdev(atadev, "%s setting UDMA6 on Promise chip\n",
931 (error) ? "failed" : "success");
933 atadev->mode = ATA_UDMA6;
939 case 0x4d68105a: /* Promise TX2 ATA100 controllers */
940 case 0x6268105a: /* Promise TX2 ATA100 controllers */
941 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
942 if (udmamode >= 5 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
943 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
944 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
946 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
947 (error) ? "failed" : "success");
949 atadev->mode = ATA_UDMA5;
953 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
954 if (udmamode >= 4 && !(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x04)) {
955 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
956 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
958 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
959 (error) ? "failed" : "success");
961 atadev->mode = ATA_UDMA4;
966 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
967 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
969 ata_prtdev(atadev, "%s setting UDMA on Promise chip\n",
970 (error) ? "failed" : "success");
972 atadev->mode = ATA_UDMA2;
976 if (wdmamode >= 2 && apiomode >= 4) {
977 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
978 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
980 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
981 (error) ? "failed" : "success");
983 atadev->mode = ATA_WDMA2;
989 case 0x0d30105a: /* Promise OEM ATA100 controllers */
990 case 0x4d30105a: /* Promise Ultra/FastTrak 100 controllers */
991 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 &&
992 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
993 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
994 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
996 ata_prtdev(atadev, "%s setting UDMA5 on Promise chip\n",
997 (error) ? "failed" : "success");
999 promise_timing(ch, devno, ATA_UDMA5);
1000 atadev->mode = ATA_UDMA5;
1006 case 0x0d38105a: /* Promise FastTrak 66 controllers */
1007 case 0x4d38105a: /* Promise Ultra/FastTrak 66 controllers */
1008 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 &&
1009 !(pci_read_config(parent, 0x50, 2)&(ch->unit ? 1<<11 : 1<<10))){
1010 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1011 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1013 ata_prtdev(atadev, "%s setting UDMA4 on Promise chip\n",
1014 (error) ? "failed" : "success");
1016 promise_timing(ch, devno, ATA_UDMA4);
1017 atadev->mode = ATA_UDMA4;
1023 case 0x4d33105a: /* Promise Ultra/FastTrak 33 controllers */
1024 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
1025 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1026 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1028 ata_prtdev(atadev, "%s setting UDMA2 on Promise chip\n",
1029 (error) ? "failed" : "success");
1031 promise_timing(ch, devno, ATA_UDMA2);
1032 atadev->mode = ATA_UDMA2;
1036 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
1037 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1038 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1040 ata_prtdev(atadev, "%s setting WDMA2 on Promise chip\n",
1041 (error) ? "failed" : "success");
1043 promise_timing(ch, devno, ATA_WDMA2);
1044 atadev->mode = ATA_WDMA2;
1048 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1049 ATA_PIO0 + apiomode,
1050 ATA_C_F_SETXFER, ATA_WAIT_READY);
1052 ata_prtdev(atadev, "%s setting PIO%d on Promise chip\n",
1053 (error) ? "failed" : "success",
1054 (apiomode >= 0) ? apiomode : 0);
1055 promise_timing(ch, devno, ATA_PIO0 + apiomode);
1056 atadev->mode = ATA_PIO0 + apiomode;
1059 case 0x00041103: /* HighPoint HPT366/368/370/372 controllers */
1060 case 0x00051103: /* HighPoint HPT372 controllers */
1061 case 0x00081103: /* HighPoint HPT374 controllers */
1062 if (!ATAPI_DEVICE(ch, device) && udmamode >= 6 && hpt_cable80(ch) &&
1063 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) ||
1064 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) ||
1065 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) {
1066 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1067 ATA_UDMA6, ATA_C_F_SETXFER, ATA_WAIT_READY);
1069 ata_prtdev(atadev, "%s setting UDMA6 on HighPoint chip\n",
1070 (error) ? "failed" : "success");
1072 hpt_timing(ch, devno, ATA_UDMA6);
1073 atadev->mode = ATA_UDMA6;
1077 if (!ATAPI_DEVICE(ch, device) && udmamode >= 5 && hpt_cable80(ch) &&
1078 ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) ||
1079 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01) ||
1080 (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07))) {
1081 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1082 ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
1084 ata_prtdev(atadev, "%s setting UDMA5 on HighPoint chip\n",
1085 (error) ? "failed" : "success");
1087 hpt_timing(ch, devno, ATA_UDMA5);
1088 atadev->mode = ATA_UDMA5;
1092 if (!ATAPI_DEVICE(ch, device) && udmamode >= 4 && hpt_cable80(ch)) {
1093 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1094 ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
1096 ata_prtdev(atadev, "%s setting UDMA4 on HighPoint chip\n",
1097 (error) ? "failed" : "success");
1099 hpt_timing(ch, devno, ATA_UDMA4);
1100 atadev->mode = ATA_UDMA4;
1104 if (!ATAPI_DEVICE(ch, device) && udmamode >= 2) {
1105 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1106 ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1108 ata_prtdev(atadev, "%s setting UDMA2 on HighPoint chip\n",
1109 (error) ? "failed" : "success");
1111 hpt_timing(ch, devno, ATA_UDMA2);
1112 atadev->mode = ATA_UDMA2;
1116 if (!ATAPI_DEVICE(ch, device) && wdmamode >= 2 && apiomode >= 4) {
1117 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1118 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1120 ata_prtdev(atadev, "%s setting WDMA2 on HighPoint chip\n",
1121 (error) ? "failed" : "success");
1123 hpt_timing(ch, devno, ATA_WDMA2);
1124 atadev->mode = ATA_WDMA2;
1128 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1129 ATA_PIO0 + apiomode,
1130 ATA_C_F_SETXFER, ATA_WAIT_READY);
1132 ata_prtdev(atadev, "%s setting PIO%d on HighPoint chip\n",
1133 (error) ? "failed" : "success",
1134 (apiomode >= 0) ? apiomode : 0);
1135 hpt_timing(ch, devno, ATA_PIO0 + apiomode);
1136 atadev->mode = ATA_PIO0 + apiomode;
1139 case 0x000116ca: /* Cenatek Rocket Drive controller */
1140 if (wdmamode >= 0 &&
1141 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
1142 ((device==ATA_MASTER)?ATA_BMSTAT_DMA_MASTER:ATA_BMSTAT_DMA_SLAVE)))
1143 atadev->mode = ATA_DMA;
1145 atadev->mode = ATA_PIO;
1148 default: /* unknown controller chip */
1149 /* better not try generic DMA on ATAPI devices it almost never works */
1150 if ((device == ATA_MASTER && ch->devices & ATA_ATAPI_MASTER) ||
1151 (device == ATA_SLAVE && ch->devices & ATA_ATAPI_SLAVE))
1154 /* if controller says its setup for DMA take the easy way out */
1155 /* the downside is we dont know what DMA mode we are in */
1156 if ((udmamode >= 0 || wdmamode >= 2) &&
1157 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) &
1158 ((device==ATA_MASTER) ?
1159 ATA_BMSTAT_DMA_MASTER : ATA_BMSTAT_DMA_SLAVE))) {
1160 atadev->mode = ATA_DMA;
1164 /* well, we have no support for this, but try anyways */
1165 if ((wdmamode >= 2 && apiomode >= 4) && ch->r_bmio) {
1166 error = ata_command(atadev, ATA_C_SETFEATURES, 0,
1167 ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
1169 ata_prtdev(atadev, "%s setting WDMA2 on generic chip\n",
1170 (error) ? "failed" : "success");
1172 atadev->mode = ATA_WDMA2;
1177 error = ata_command(atadev, ATA_C_SETFEATURES, 0, ATA_PIO0 + apiomode,
1178 ATA_C_F_SETXFER, ATA_WAIT_READY);
1180 ata_prtdev(atadev, "%s setting PIO%d on generic chip\n",
1181 (error) ? "failed" : "success", apiomode < 0 ? 0 : apiomode);
1183 atadev->mode = ATA_PIO0 + apiomode;
1186 ata_prtdev(atadev, "using PIO mode set by BIOS\n");
1187 atadev->mode = ATA_PIO;
1192 ata_dmasetup(struct ata_channel *ch, int device, struct ata_dmaentry *dmatab,
1193 caddr_t data, int32_t count)
1195 u_int32_t dma_count, dma_base;
1198 if (((uintptr_t)data & ch->alignment) || (count & ch->alignment)) {
1199 ata_printf(ch, device, "non aligned DMA transfer attempted\n");
1204 ata_printf(ch, device, "zero length DMA transfer attempted\n");
1208 dma_base = vtophys(data);
1209 dma_count = imin(count, (PAGE_SIZE - ((uintptr_t)data & PAGE_MASK)));
1214 dmatab[i].base = dma_base;
1215 dmatab[i].count = (dma_count & 0xffff);
1217 if (i >= ATA_DMA_ENTRIES) {
1218 ata_printf(ch, device, "too many segments in DMA table\n");
1221 dma_base = vtophys(data);
1222 dma_count = imin(count, PAGE_SIZE);
1223 data += imin(count, PAGE_SIZE);
1224 count -= imin(count, PAGE_SIZE);
1226 dmatab[i].base = dma_base;
1227 dmatab[i].count = (dma_count & 0xffff) | ATA_DMA_EOT;
1232 ata_dmastart(struct ata_channel *ch, int device,
1233 struct ata_dmaentry *dmatab, int dir)
1235 ch->flags |= ATA_DMA_ACTIVE;
1236 ATA_OUTL(ch->r_bmio, ATA_BMDTP_PORT, vtophys(dmatab));
1237 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT, dir ? ATA_BMCMD_WRITE_READ : 0);
1238 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1239 (ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) |
1240 (ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR)));
1241 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1242 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) | ATA_BMCMD_START_STOP);
1246 ata_dmadone(struct ata_channel *ch)
1250 ATA_OUTB(ch->r_bmio, ATA_BMCMD_PORT,
1251 ATA_INB(ch->r_bmio, ATA_BMCMD_PORT) & ~ATA_BMCMD_START_STOP);
1252 ch->flags &= ~ATA_DMA_ACTIVE;
1253 error = ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT);
1254 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT,
1255 error | ATA_BMSTAT_INTERRUPT | ATA_BMSTAT_ERROR);
1256 return error & ATA_BMSTAT_MASK;
1260 ata_dmastatus(struct ata_channel *ch)
1262 return ATA_INB(ch->r_bmio, ATA_BMSTAT_PORT) & ATA_BMSTAT_MASK;
1266 cyrix_timing(struct ata_channel *ch, int devno, int mode)
1268 u_int32_t reg20 = 0x0000e132;
1269 u_int32_t reg24 = 0x00017771;
1272 case ATA_PIO0: reg20 = 0x0000e132; break;
1273 case ATA_PIO1: reg20 = 0x00018121; break;
1274 case ATA_PIO2: reg20 = 0x00024020; break;
1275 case ATA_PIO3: reg20 = 0x00032010; break;
1276 case ATA_PIO4: reg20 = 0x00040010; break;
1277 case ATA_WDMA2: reg24 = 0x00002020; break;
1278 case ATA_UDMA2: reg24 = 0x00911030; break;
1280 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x20, reg20);
1281 ATA_OUTL(ch->r_bmio, (devno << 3) + 0x24, reg24);
1285 promise_timing(struct ata_channel *ch, int devno, int mode)
1287 u_int32_t timing = 0;
1288 struct promise_timing {
1290 u_int8_t prefetch:1;
1301 u_int8_t reserved:8;
1302 } *t = (struct promise_timing*)&timing;
1304 t->iordy = 1; t->iordyp = 1;
1305 if (mode >= ATA_DMA) {
1306 t->prefetch = 1; t->errdy = 1; t->syncin = 1;
1309 switch (ch->chiptype) {
1310 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
1313 case ATA_PIO0: t->pa = 9; t->pb = 19; t->mb = 7; t->mc = 15; break;
1314 case ATA_PIO1: t->pa = 5; t->pb = 12; t->mb = 7; t->mc = 15; break;
1315 case ATA_PIO2: t->pa = 3; t->pb = 8; t->mb = 7; t->mc = 15; break;
1316 case ATA_PIO3: t->pa = 2; t->pb = 6; t->mb = 7; t->mc = 15; break;
1317 case ATA_PIO4: t->pa = 1; t->pb = 4; t->mb = 7; t->mc = 15; break;
1318 case ATA_WDMA2: t->pa = 3; t->pb = 7; t->mb = 3; t->mc = 3; break;
1319 case ATA_UDMA2: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1323 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
1324 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
1325 case 0x0d30105a: /* Promise OEM ATA 100 */
1328 case ATA_PIO0: t->pa = 15; t->pb = 31; t->mb = 7; t->mc = 15; break;
1329 case ATA_PIO1: t->pa = 10; t->pb = 24; t->mb = 7; t->mc = 15; break;
1330 case ATA_PIO2: t->pa = 6; t->pb = 16; t->mb = 7; t->mc = 15; break;
1331 case ATA_PIO3: t->pa = 4; t->pb = 12; t->mb = 7; t->mc = 15; break;
1332 case ATA_PIO4: t->pa = 2; t->pb = 8; t->mb = 7; t->mc = 15; break;
1333 case ATA_WDMA2: t->pa = 6; t->pb = 14; t->mb = 6; t->mc = 6; break;
1334 case ATA_UDMA2: t->pa = 6; t->pb = 14; t->mb = 2; t->mc = 2; break;
1335 case ATA_UDMA4: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1336 case ATA_UDMA5: t->pa = 3; t->pb = 7; t->mb = 1; t->mc = 1; break;
1340 pci_write_config(device_get_parent(ch->dev), 0x60 + (devno<<2), timing, 4);
1344 hpt_timing(struct ata_channel *ch, int devno, int mode)
1346 device_t parent = device_get_parent(ch->dev);
1349 if (ch->chiptype == 0x00081103 && pci_get_revid(parent) >= 0x07) {
1350 switch (mode) { /* HPT374 */
1351 case ATA_PIO0: timing = 0x0ac1f48a; break;
1352 case ATA_PIO1: timing = 0x0ac1f465; break;
1353 case ATA_PIO2: timing = 0x0a81f454; break;
1354 case ATA_PIO3: timing = 0x0a81f443; break;
1355 case ATA_PIO4: timing = 0x0a81f442; break;
1356 case ATA_WDMA2: timing = 0x22808242; break;
1357 case ATA_UDMA2: timing = 0x120c8242; break;
1358 case ATA_UDMA4: timing = 0x12ac8242; break;
1359 case ATA_UDMA5: timing = 0x12848242; break;
1360 case ATA_UDMA6: timing = 0x12808242; break;
1361 default: timing = 0x0d029d5e;
1364 else if ((ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x05) ||
1365 (ch->chiptype == 0x00051103 && pci_get_revid(parent) >= 0x01)) {
1366 switch (mode) { /* HPT372 */
1367 case ATA_PIO0: timing = 0x0d029d5e; break;
1368 case ATA_PIO1: timing = 0x0d029d26; break;
1369 case ATA_PIO2: timing = 0x0c829ca6; break;
1370 case ATA_PIO3: timing = 0x0c829c84; break;
1371 case ATA_PIO4: timing = 0x0c829c62; break;
1372 case ATA_WDMA2: timing = 0x2c829262; break;
1373 case ATA_UDMA2: timing = 0x1c91dc62; break;
1374 case ATA_UDMA4: timing = 0x1c8ddc62; break;
1375 case ATA_UDMA5: timing = 0x1c6ddc62; break;
1376 case ATA_UDMA6: timing = 0x1c81dc62; break;
1377 default: timing = 0x0d029d5e;
1380 else if (ch->chiptype == 0x00041103 && pci_get_revid(parent) >= 0x03) {
1381 switch (mode) { /* HPT370 */
1382 case ATA_PIO0: timing = 0x06914e57; break;
1383 case ATA_PIO1: timing = 0x06914e43; break;
1384 case ATA_PIO2: timing = 0x06514e33; break;
1385 case ATA_PIO3: timing = 0x06514e22; break;
1386 case ATA_PIO4: timing = 0x06514e21; break;
1387 case ATA_WDMA2: timing = 0x26514e21; break;
1388 case ATA_UDMA2: timing = 0x16494e31; break;
1389 case ATA_UDMA4: timing = 0x16454e31; break;
1390 case ATA_UDMA5: timing = 0x16454e31; break;
1391 default: timing = 0x06514e57;
1393 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1395 else { /* HPT36[68] */
1396 switch (pci_read_config(parent, 0x41 + (devno << 2), 1)) {
1397 case 0x85: /* 25Mhz */
1399 case ATA_PIO0: timing = 0x40d08585; break;
1400 case ATA_PIO1: timing = 0x40d08572; break;
1401 case ATA_PIO2: timing = 0x40ca8542; break;
1402 case ATA_PIO3: timing = 0x40ca8532; break;
1403 case ATA_PIO4: timing = 0x40ca8521; break;
1404 case ATA_WDMA2: timing = 0x20ca8521; break;
1405 case ATA_UDMA2: timing = 0x10cf8521; break;
1406 case ATA_UDMA4: timing = 0x10c98521; break;
1407 default: timing = 0x01208585;
1411 case 0xa7: /* 33MHz */
1413 case ATA_PIO0: timing = 0x40d0a7aa; break;
1414 case ATA_PIO1: timing = 0x40d0a7a3; break;
1415 case ATA_PIO2: timing = 0x40d0a753; break;
1416 case ATA_PIO3: timing = 0x40c8a742; break;
1417 case ATA_PIO4: timing = 0x40c8a731; break;
1418 case ATA_WDMA2: timing = 0x20c8a731; break;
1419 case ATA_UDMA2: timing = 0x10caa731; break;
1420 case ATA_UDMA4: timing = 0x10c9a731; break;
1421 default: timing = 0x0120a7a7;
1424 case 0xd9: /* 40Mhz */
1426 case ATA_PIO0: timing = 0x4018d9d9; break;
1427 case ATA_PIO1: timing = 0x4010d9c7; break;
1428 case ATA_PIO2: timing = 0x4010d997; break;
1429 case ATA_PIO3: timing = 0x4010d974; break;
1430 case ATA_PIO4: timing = 0x4008d963; break;
1431 case ATA_WDMA2: timing = 0x2008d943; break;
1432 case ATA_UDMA2: timing = 0x100bd943; break;
1433 case ATA_UDMA4: timing = 0x100fd943; break;
1434 default: timing = 0x0120d9d9;
1438 pci_write_config(parent, 0x40 + (devno << 2) , timing, 4);
1442 hpt_cable80(struct ata_channel *ch)
1444 device_t parent = device_get_parent(ch->dev);
1445 u_int8_t reg, val, res;
1447 if (ch->chiptype == 0x00081103 && pci_get_function(parent) == 1) {
1448 reg = ch->unit ? 0x57 : 0x53;
1449 val = pci_read_config(parent, reg, 1);
1450 pci_write_config(parent, reg, val | 0x80, 1);
1454 val = pci_read_config(parent, reg, 1);
1455 pci_write_config(parent, reg, val & 0xfe, 1);
1457 res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x01 : 0x02);
1458 pci_write_config(parent, reg, val, 1);