2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5212_recv.c 195809 2009-07-21 19:23:34Z sam $
23 #include "ah_internal.h"
25 #include "ar5212/ar5212.h"
26 #include "ar5212/ar5212reg.h"
27 #include "ar5212/ar5212desc.h"
33 ar5212GetRxDP(struct ath_hal *ath)
35 return OS_REG_READ(ath, AR_RXDP);
42 ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp)
44 OS_REG_WRITE(ah, AR_RXDP, rxdp);
45 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
49 * Set Receive Enable bits.
52 ar5212EnableReceive(struct ath_hal *ah)
54 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
58 * Stop Receive at the DMA engine
61 ar5212StopDmaReceive(struct ath_hal *ah)
63 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
64 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
66 ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"
67 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
69 OS_REG_READ(ah, AR_CR),
70 OS_REG_READ(ah, AR_DIAG_SW));
79 * Start Transmit at the PCU engine (unpause receive)
82 ar5212StartPcuReceive(struct ath_hal *ah)
84 struct ath_hal_private *ahp = AH_PRIVATE(ah);
86 OS_REG_WRITE(ah, AR_DIAG_SW,
87 OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
88 ar5212EnableMibCounters(ah);
89 /* NB: restore current settings */
90 ar5212AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
94 * Stop Transmit at the PCU engine (pause receive)
97 ar5212StopPcuReceive(struct ath_hal *ah)
99 OS_REG_WRITE(ah, AR_DIAG_SW,
100 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
101 ar5212DisableMibCounters(ah);
105 * Set multicast filter 0 (lower 32-bits)
106 * filter 1 (upper 32-bits)
109 ar5212SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
111 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
112 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
116 * Clear multicast filter by index
119 ar5212ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
126 val = OS_REG_READ(ah, AR_MCAST_FIL1);
127 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
129 val = OS_REG_READ(ah, AR_MCAST_FIL0);
130 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
136 * Set multicast filter by index
139 ar5212SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
146 val = OS_REG_READ(ah, AR_MCAST_FIL1);
147 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
149 val = OS_REG_READ(ah, AR_MCAST_FIL0);
150 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
156 * Get the receive filter.
159 ar5212GetRxFilter(struct ath_hal *ah)
161 uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
162 uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
163 if (phybits & AR_PHY_ERR_RADAR)
164 bits |= HAL_RX_FILTER_PHYRADAR;
165 if (phybits & (AR_PHY_ERR_OFDM_TIMING|AR_PHY_ERR_CCK_TIMING))
166 bits |= HAL_RX_FILTER_PHYERR;
167 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport &&
168 (AH5212(ah)->ah_miscMode & AR_MISC_MODE_BSSID_MATCH_FORCE))
169 bits |= HAL_RX_FILTER_BSSID;
174 * Set the receive filter.
177 ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits)
179 struct ath_hal_5212 *ahp = AH5212(ah);
182 OS_REG_WRITE(ah, AR_RX_FILTER,
183 bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR|
184 HAL_RX_FILTER_BSSID));
186 if (bits & HAL_RX_FILTER_PHYRADAR)
187 phybits |= AR_PHY_ERR_RADAR;
188 if (bits & HAL_RX_FILTER_PHYERR)
189 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
190 OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
192 OS_REG_WRITE(ah, AR_RXCFG,
193 OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
195 OS_REG_WRITE(ah, AR_RXCFG,
196 OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
198 if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport) {
199 if (bits & HAL_RX_FILTER_BSSID)
200 ahp->ah_miscMode |= AR_MISC_MODE_BSSID_MATCH_FORCE;
202 ahp->ah_miscMode &= ~AR_MISC_MODE_BSSID_MATCH_FORCE;
203 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode);
208 * Initialize RX descriptor, by clearing the status and setting
209 * the size (and any other flags).
212 ar5212SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
213 uint32_t size, u_int flags)
215 struct ar5212_desc *ads = AR5212DESC(ds);
217 HALASSERT((size &~ AR_BufLen) == 0);
220 ads->ds_ctl1 = size & AR_BufLen;
222 if (flags & HAL_RXDESC_INTREQ)
223 ads->ds_ctl1 |= AR_RxInterReq;
224 ads->ds_rxstatus0 = ads->ds_rxstatus1 = 0;
230 * Process an RX descriptor, and return the status to the caller.
231 * Copy some hardware specific items into the software portion
234 * NB: the caller is responsible for validating the memory contents
235 * of the descriptor (e.g. flushing any cached copy).
238 ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
239 uint32_t pa, struct ath_desc *nds, uint64_t tsf,
240 struct ath_rx_status *rs)
242 struct ar5212_desc *ads = AR5212DESC(ds);
243 struct ar5212_desc *ands = AR5212DESC(nds);
245 if ((ads->ds_rxstatus1 & AR_Done) == 0)
246 return HAL_EINPROGRESS;
248 * Given the use of a self-linked tail be very sure that the hw is
249 * done with this descriptor; the hw may have done this descriptor
250 * once and picked it up again...make sure the hw has moved on.
252 if ((ands->ds_rxstatus1&AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
253 return HAL_EINPROGRESS;
255 rs->rs_datalen = ads->ds_rxstatus0 & AR_DataLen;
256 rs->rs_tstamp = MS(ads->ds_rxstatus1, AR_RcvTimestamp);
258 /* XXX what about KeyCacheMiss? */
259 rs->rs_rssi = MS(ads->ds_rxstatus0, AR_RcvSigStrength);
260 /* discard invalid h/w rssi data */
261 if (rs->rs_rssi == -128)
263 if (ads->ds_rxstatus1 & AR_KeyIdxValid)
264 rs->rs_keyix = MS(ads->ds_rxstatus1, AR_KeyIdx);
266 rs->rs_keyix = HAL_RXKEYIX_INVALID;
267 /* NB: caller expected to do rate table mapping */
268 rs->rs_rate = MS(ads->ds_rxstatus0, AR_RcvRate);
269 rs->rs_antenna = MS(ads->ds_rxstatus0, AR_RcvAntenna);
270 rs->rs_more = (ads->ds_rxstatus0 & AR_More) ? 1 : 0;
272 if ((ads->ds_rxstatus1 & AR_FrmRcvOK) == 0) {
274 * These four bits should not be set together. The
275 * 5212 spec states a Michael error can only occur if
276 * DecryptCRCErr not set (and TKIP is used). Experience
277 * indicates however that you can also get Michael errors
278 * when a CRC error is detected, but these are specious.
279 * Consequently we filter them out here so we don't
280 * confuse and/or complicate drivers.
282 if (ads->ds_rxstatus1 & AR_CRCErr)
283 rs->rs_status |= HAL_RXERR_CRC;
284 else if (ads->ds_rxstatus1 & AR_PHYErr) {
287 rs->rs_status |= HAL_RXERR_PHY;
288 phyerr = MS(ads->ds_rxstatus1, AR_PHYErrCode);
289 rs->rs_phyerr = phyerr;
290 if (!AH5212(ah)->ah_hasHwPhyCounters &&
291 phyerr != HAL_PHYERR_RADAR)
292 ar5212AniPhyErrReport(ah, rs);
293 } else if (ads->ds_rxstatus1 & AR_DecryptCRCErr)
294 rs->rs_status |= HAL_RXERR_DECRYPT;
295 else if (ads->ds_rxstatus1 & AR_MichaelErr)
296 rs->rs_status |= HAL_RXERR_MIC;