2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c 203159 2010-01-29 10:10:14Z rpaulo $
23 * XXX this is virtually the same code as for 5212; we reuse
24 * storage in the 5212 state block; need to refactor.
27 #include "ah_internal.h"
30 #include "ar5416/ar5416.h"
31 #include "ar5416/ar5416reg.h"
32 #include "ar5416/ar5416phy.h"
35 * Anti noise immunity support. We track phy errors and react
36 * to excessive errors by adjusting the noise immunity parameters.
39 #define HAL_EP_RND(x, mul) \
40 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
41 #define BEACON_RSSI(ahp) \
42 HAL_EP_RND(ahp->ah_stats.ast_nodestats.ns_avgbrssi, \
43 HAL_RSSI_EP_MULTIPLIER)
46 * ANI processing tunes radio parameters according to PHY errors
47 * and related information. This is done for for noise and spur
48 * immunity in all operating modes if the device indicates it's
49 * capable at attach time. In addition, when there is a reference
50 * rssi value (e.g. beacon frames from an ap in station mode)
51 * further tuning is done.
53 * ANI_ENA indicates whether any ANI processing should be done;
54 * this is specified at attach time.
56 * ANI_ENA_RSSI indicates whether rssi-based processing should
57 * done, this is enabled based on operating mode and is meaningful
58 * only if ANI_ENA is true.
60 * ANI parameters are typically controlled only by the hal. The
61 * AniControl interface however permits manual tuning through the
65 (AH5212(ah)->ah_procPhyErr & HAL_ANI_ENA)
66 #define ANI_ENA_RSSI(ah) \
67 (AH5212(ah)->ah_procPhyErr & HAL_RSSI_ANI_ENA)
69 #define ah_mibStats ah_stats.ast_mibstats
72 enableAniMIBCounters(struct ath_hal *ah, const struct ar5212AniParams *params)
74 struct ath_hal_5212 *ahp = AH5212(ah);
76 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: Enable mib counters: "
77 "OfdmPhyErrBase 0x%x cckPhyErrBase 0x%x\n",
78 __func__, params->ofdmPhyErrBase, params->cckPhyErrBase);
80 OS_REG_WRITE(ah, AR_FILTOFDM, 0);
81 OS_REG_WRITE(ah, AR_FILTCCK, 0);
83 OS_REG_WRITE(ah, AR_PHYCNT1, params->ofdmPhyErrBase);
84 OS_REG_WRITE(ah, AR_PHYCNT2, params->cckPhyErrBase);
85 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
86 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
88 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save+clear counters*/
89 ar5212EnableMibCounters(ah); /* enable everything */
93 disableAniMIBCounters(struct ath_hal *ah)
95 struct ath_hal_5212 *ahp = AH5212(ah);
97 HALDEBUG(ah, HAL_DEBUG_ANI, "Disable MIB counters\n");
99 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats); /* save stats */
100 ar5212DisableMibCounters(ah); /* disable everything */
102 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, 0);
103 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, 0);
107 setPhyErrBase(struct ath_hal *ah, struct ar5212AniParams *params)
109 if (params->ofdmTrigHigh >= AR_PHY_COUNTMAX) {
110 HALDEBUG(ah, HAL_DEBUG_ANY,
111 "OFDM Trigger %d is too high for hw counters, using max\n",
112 params->ofdmTrigHigh);
113 params->ofdmPhyErrBase = 0;
115 params->ofdmPhyErrBase = AR_PHY_COUNTMAX - params->ofdmTrigHigh;
116 if (params->cckTrigHigh >= AR_PHY_COUNTMAX) {
117 HALDEBUG(ah, HAL_DEBUG_ANY,
118 "CCK Trigger %d is too high for hw counters, using max\n",
119 params->cckTrigHigh);
120 params->cckPhyErrBase = 0;
122 params->cckPhyErrBase = AR_PHY_COUNTMAX - params->cckTrigHigh;
126 * Setup ANI handling. Sets all thresholds and reset the
127 * channel statistics. Note that ar5416AniReset should be
128 * called by ar5416Reset before anything else happens and
129 * that's where we force initial settings.
132 ar5416AniAttach(struct ath_hal *ah, const struct ar5212AniParams *params24,
133 const struct ar5212AniParams *params5, HAL_BOOL enable)
135 struct ath_hal_5212 *ahp = AH5212(ah);
137 if (params24 != AH_NULL) {
138 OS_MEMCPY(&ahp->ah_aniParams24, params24, sizeof(*params24));
139 setPhyErrBase(ah, &ahp->ah_aniParams24);
141 if (params5 != AH_NULL) {
142 OS_MEMCPY(&ahp->ah_aniParams5, params5, sizeof(*params5));
143 setPhyErrBase(ah, &ahp->ah_aniParams5);
146 OS_MEMZERO(ahp->ah_ani, sizeof(ahp->ah_ani));
147 /* Enable MIB Counters */
148 enableAniMIBCounters(ah, &ahp->ah_aniParams24 /*XXX*/);
150 if (enable) { /* Enable ani now */
151 HALASSERT(params24 != AH_NULL && params5 != AH_NULL);
152 ahp->ah_procPhyErr |= HAL_ANI_ENA;
154 ahp->ah_procPhyErr &= ~HAL_ANI_ENA;
159 * Cleanup any ANI state setup.
162 ar5416AniDetach(struct ath_hal *ah)
164 HALDEBUG(ah, HAL_DEBUG_ANI, "Detaching Ani\n");
165 disableAniMIBCounters(ah);
169 * Control Adaptive Noise Immunity Parameters
172 ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, int param)
175 struct ath_hal_5212 *ahp = AH5212(ah);
176 struct ar5212AniState *aniState = ahp->ah_curani;
177 const struct ar5212AniParams *params = aniState->params;
179 OS_MARK(ah, AH_MARK_ANI_CONTROL, cmd);
182 case HAL_ANI_NOISE_IMMUNITY_LEVEL: {
185 if (level >= params->maxNoiseImmunityLevel) {
186 HALDEBUG(ah, HAL_DEBUG_ANY,
187 "%s: immunity level out of range (%u > %u)\n",
188 __func__, level, params->maxNoiseImmunityLevel);
192 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
193 AR_PHY_DESIRED_SZ_TOT_DES, params->totalSizeDesired[level]);
194 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
195 AR_PHY_AGC_CTL1_COARSE_LOW, params->coarseLow[level]);
196 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
197 AR_PHY_AGC_CTL1_COARSE_HIGH, params->coarseHigh[level]);
198 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
199 AR_PHY_FIND_SIG_FIRPWR, params->firpwr[level]);
201 if (level > aniState->noiseImmunityLevel)
202 ahp->ah_stats.ast_ani_niup++;
203 else if (level < aniState->noiseImmunityLevel)
204 ahp->ah_stats.ast_ani_nidown++;
205 aniState->noiseImmunityLevel = level;
208 case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION: {
209 static const TABLE m1ThreshLow = { 127, 50 };
210 static const TABLE m2ThreshLow = { 127, 40 };
211 static const TABLE m1Thresh = { 127, 0x4d };
212 static const TABLE m2Thresh = { 127, 0x40 };
213 static const TABLE m2CountThr = { 31, 16 };
214 static const TABLE m2CountThrLow = { 63, 48 };
215 u_int on = param ? 1 : 0;
217 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
218 AR_PHY_SFCORR_LOW_M1_THRESH_LOW, m1ThreshLow[on]);
219 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
220 AR_PHY_SFCORR_LOW_M2_THRESH_LOW, m2ThreshLow[on]);
221 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
222 AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
223 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
224 AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
225 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
226 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
227 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
228 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, m2CountThrLow[on]);
230 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
231 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
232 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
233 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
234 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
235 AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
236 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
237 AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
240 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
241 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
243 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
244 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
247 ahp->ah_stats.ast_ani_ofdmon++;
249 ahp->ah_stats.ast_ani_ofdmoff++;
250 aniState->ofdmWeakSigDetectOff = !on;
253 case HAL_ANI_CCK_WEAK_SIGNAL_THR: {
254 static const TABLE weakSigThrCck = { 8, 6 };
255 u_int high = param ? 1 : 0;
257 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
258 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, weakSigThrCck[high]);
260 ahp->ah_stats.ast_ani_cckhigh++;
262 ahp->ah_stats.ast_ani_ccklow++;
263 aniState->cckWeakSigThreshold = high;
266 case HAL_ANI_FIRSTEP_LEVEL: {
269 if (level >= params->maxFirstepLevel) {
270 HALDEBUG(ah, HAL_DEBUG_ANY,
271 "%s: firstep level out of range (%u > %u)\n",
272 __func__, level, params->maxFirstepLevel);
275 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
276 AR_PHY_FIND_SIG_FIRSTEP, params->firstep[level]);
277 if (level > aniState->firstepLevel)
278 ahp->ah_stats.ast_ani_stepup++;
279 else if (level < aniState->firstepLevel)
280 ahp->ah_stats.ast_ani_stepdown++;
281 aniState->firstepLevel = level;
284 case HAL_ANI_SPUR_IMMUNITY_LEVEL: {
287 if (level >= params->maxSpurImmunityLevel) {
288 HALDEBUG(ah, HAL_DEBUG_ANY,
289 "%s: spur immunity level out of range (%u > %u)\n",
290 __func__, level, params->maxSpurImmunityLevel);
293 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
294 AR_PHY_TIMING5_CYCPWR_THR1, params->cycPwrThr1[level]);
295 if (level > aniState->spurImmunityLevel)
296 ahp->ah_stats.ast_ani_spurup++;
297 else if (level < aniState->spurImmunityLevel)
298 ahp->ah_stats.ast_ani_spurdown++;
299 aniState->spurImmunityLevel = level;
302 case HAL_ANI_PRESENT:
306 ahp->ah_procPhyErr &= ~HAL_ANI_ENA;
307 /* Turn off HW counters if we have them */
309 ar5212SetRxFilter(ah,
310 ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
311 } else { /* normal/auto mode */
312 /* don't mess with state if already enabled */
313 if (ahp->ah_procPhyErr & HAL_ANI_ENA)
315 ar5212SetRxFilter(ah,
316 ar5212GetRxFilter(ah) &~ HAL_RX_FILTER_PHYERR);
317 /* Enable MIB Counters */
318 enableAniMIBCounters(ah, ahp->ah_curani != AH_NULL ?
319 ahp->ah_curani->params: &ahp->ah_aniParams24 /*XXX*/);
320 ahp->ah_procPhyErr |= HAL_ANI_ENA;
323 #ifdef AH_PRIVATE_DIAG
324 case HAL_ANI_PHYERR_RESET:
325 ahp->ah_stats.ast_ani_ofdmerrs = 0;
326 ahp->ah_stats.ast_ani_cckerrs = 0;
328 #endif /* AH_PRIVATE_DIAG */
330 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid cmd %u\n",
338 ar5416AniOfdmErrTrigger(struct ath_hal *ah)
340 struct ath_hal_5212 *ahp = AH5212(ah);
341 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
342 struct ar5212AniState *aniState;
343 const struct ar5212AniParams *params;
345 HALASSERT(chan != AH_NULL);
350 aniState = ahp->ah_curani;
351 params = aniState->params;
352 /* First, raise noise immunity level, up to max */
353 if (aniState->noiseImmunityLevel+1 < params->maxNoiseImmunityLevel) {
354 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
355 aniState->noiseImmunityLevel + 1);
358 /* then, raise spur immunity level, up to max */
359 if (aniState->spurImmunityLevel+1 < params->maxSpurImmunityLevel) {
360 ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
361 aniState->spurImmunityLevel + 1);
365 if (ANI_ENA_RSSI(ah)) {
366 int32_t rssi = BEACON_RSSI(ahp);
367 if (rssi > params->rssiThrHigh) {
369 * Beacon rssi is high, can turn off ofdm
372 if (!aniState->ofdmWeakSigDetectOff) {
374 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
377 HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
381 * If weak sig detect is already off, as last resort,
382 * raise firstep level
384 if (aniState->firstepLevel+1 < params->maxFirstepLevel) {
385 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
386 aniState->firstepLevel + 1);
389 } else if (rssi > params->rssiThrLow) {
391 * Beacon rssi in mid range, need ofdm weak signal
392 * detect, but we can raise firststepLevel.
394 if (aniState->ofdmWeakSigDetectOff)
396 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
398 if (aniState->firstepLevel+1 < params->maxFirstepLevel)
399 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
400 aniState->firstepLevel + 1);
404 * Beacon rssi is low, if in 11b/g mode, turn off ofdm
405 * weak signal detection and zero firstepLevel to
406 * maximize CCK sensitivity
408 if (IEEE80211_IS_CHAN_CCK(chan)) {
409 if (!aniState->ofdmWeakSigDetectOff)
411 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
413 if (aniState->firstepLevel > 0)
415 HAL_ANI_FIRSTEP_LEVEL, 0);
423 ar5416AniCckErrTrigger(struct ath_hal *ah)
425 struct ath_hal_5212 *ahp = AH5212(ah);
426 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
427 struct ar5212AniState *aniState;
428 const struct ar5212AniParams *params;
430 HALASSERT(chan != AH_NULL);
435 /* first, raise noise immunity level, up to max */
436 aniState = ahp->ah_curani;
437 params = aniState->params;
438 if (aniState->noiseImmunityLevel+1 < params->maxNoiseImmunityLevel) {
439 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
440 aniState->noiseImmunityLevel + 1);
444 if (ANI_ENA_RSSI(ah)) {
445 int32_t rssi = BEACON_RSSI(ahp);
446 if (rssi > params->rssiThrLow) {
448 * Beacon signal in mid and high range,
449 * raise firstep level.
451 if (aniState->firstepLevel+1 < params->maxFirstepLevel)
452 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
453 aniState->firstepLevel + 1);
456 * Beacon rssi is low, zero firstep level to maximize
457 * CCK sensitivity in 11b/g mode.
459 if (IEEE80211_IS_CHAN_CCK(chan)) {
460 if (aniState->firstepLevel > 0)
462 HAL_ANI_FIRSTEP_LEVEL, 0);
469 ar5416AniRestart(struct ath_hal *ah, struct ar5212AniState *aniState)
471 struct ath_hal_5212 *ahp = AH5212(ah);
472 const struct ar5212AniParams *params = aniState->params;
474 aniState->listenTime = 0;
476 * NB: these are written on reset based on the
477 * ini so we must re-write them!
479 HALDEBUG(ah, HAL_DEBUG_ANI,
480 "%s: Writing ofdmbase=%u cckbase=%u\n", __func__,
481 params->ofdmPhyErrBase, params->cckPhyErrBase);
482 OS_REG_WRITE(ah, AR_PHY_ERR_1, params->ofdmPhyErrBase);
483 OS_REG_WRITE(ah, AR_PHY_ERR_2, params->cckPhyErrBase);
484 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
485 OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_CCK_TIMING);
487 /* Clear the mib counters and save them in the stats */
488 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
489 aniState->ofdmPhyErrCount = 0;
490 aniState->cckPhyErrCount = 0;
494 * Restore/reset the ANI parameters and reset the statistics.
495 * This routine must be called for every channel change.
497 * NOTE: This is where ah_curani is set; other ani code assumes
498 * it is setup to reflect the current channel.
501 ar5416AniReset(struct ath_hal *ah, const struct ieee80211_channel *chan,
502 HAL_OPMODE opmode, int restore)
504 struct ath_hal_5212 *ahp = AH5212(ah);
505 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
506 /* XXX bounds check ic_devdata */
507 struct ar5212AniState *aniState = &ahp->ah_ani[chan->ic_devdata];
510 if ((ichan->privFlags & CHANNEL_ANI_INIT) == 0) {
511 OS_MEMZERO(aniState, sizeof(*aniState));
512 if (IEEE80211_IS_CHAN_2GHZ(chan))
513 aniState->params = &ahp->ah_aniParams24;
515 aniState->params = &ahp->ah_aniParams5;
516 ichan->privFlags |= CHANNEL_ANI_INIT;
517 HALASSERT((ichan->privFlags & CHANNEL_ANI_SETUP) == 0);
519 ahp->ah_curani = aniState;
521 ath_hal_printf(ah,"%s: chan %u/0x%x restore %d opmode %u%s\n",
522 __func__, chan->ic_freq, chan->ic_flags, restore, opmode,
523 ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");
525 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: chan %u/0x%x restore %d opmode %u%s\n",
526 __func__, chan->ic_freq, chan->ic_flags, restore, opmode,
527 ichan->privFlags & CHANNEL_ANI_SETUP ? " setup" : "");
529 OS_MARK(ah, AH_MARK_ANI_RESET, opmode);
532 * Turn off PHY error frame delivery while we futz with settings.
534 rxfilter = ar5212GetRxFilter(ah);
535 ar5212SetRxFilter(ah, rxfilter &~ HAL_RX_FILTER_PHYERR);
537 * Automatic processing is done only in station mode right now.
539 if (opmode == HAL_M_STA)
540 ahp->ah_procPhyErr |= HAL_RSSI_ANI_ENA;
542 ahp->ah_procPhyErr &= ~HAL_RSSI_ANI_ENA;
544 * Set all ani parameters. We either set them to initial
545 * values or restore the previous ones for the channel.
546 * XXX if ANI follows hardware, we don't care what mode we're
547 * XXX in, we should keep the ani parameters
549 if (restore && (ichan->privFlags & CHANNEL_ANI_SETUP)) {
550 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
551 aniState->noiseImmunityLevel);
552 ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
553 aniState->spurImmunityLevel);
554 ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
555 !aniState->ofdmWeakSigDetectOff);
556 ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
557 aniState->cckWeakSigThreshold);
558 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
559 aniState->firstepLevel);
561 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
562 ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
563 ar5416AniControl(ah, HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
565 ar5416AniControl(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR, AH_FALSE);
566 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
567 ichan->privFlags |= CHANNEL_ANI_SETUP;
569 ar5416AniRestart(ah, aniState);
571 /* restore RX filter mask */
572 ar5212SetRxFilter(ah, rxfilter);
576 * Process a MIB interrupt. We may potentially be invoked because
577 * any of the MIB counters overflow/trigger so don't assume we're
578 * here because a PHY error counter triggered.
581 ar5416ProcessMibIntr(struct ath_hal *ah, const HAL_NODE_STATS *stats)
583 struct ath_hal_5212 *ahp = AH5212(ah);
584 uint32_t phyCnt1, phyCnt2;
586 HALDEBUG(ah, HAL_DEBUG_ANI, "%s: mibc 0x%x phyCnt1 0x%x phyCnt2 0x%x "
587 "filtofdm 0x%x filtcck 0x%x\n",
588 __func__, OS_REG_READ(ah, AR_MIBC),
589 OS_REG_READ(ah, AR_PHYCNT1), OS_REG_READ(ah, AR_PHYCNT2),
590 OS_REG_READ(ah, AR_FILTOFDM), OS_REG_READ(ah, AR_FILTCCK));
593 * First order of business is to clear whatever caused
594 * the interrupt so we don't keep getting interrupted.
595 * We have the usual mib counters that are reset-on-read
596 * and the additional counters that appeared starting in
597 * Hainan. We collect the mib counters and explicitly
598 * zero additional counters we are not using. Anything
599 * else is reset only if it caused the interrupt.
601 /* NB: these are not reset-on-read */
602 phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
603 phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);
604 /* not used, always reset them in case they are the cause */
605 OS_REG_WRITE(ah, AR_FILTOFDM, 0);
606 OS_REG_WRITE(ah, AR_FILTCCK, 0);
607 if ((OS_REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING) == 0)
608 OS_REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
610 /* Clear the mib counters and save them in the stats */
611 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
612 ahp->ah_stats.ast_nodestats = *stats;
615 * Check for an ani stat hitting the trigger threshold.
616 * When this happens we get a MIB interrupt and the top
617 * 2 bits of the counter register will be 0b11, hence
618 * the mask check of phyCnt?.
620 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
621 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
622 struct ar5212AniState *aniState = ahp->ah_curani;
623 const struct ar5212AniParams *params = aniState->params;
624 uint32_t ofdmPhyErrCnt, cckPhyErrCnt;
626 ofdmPhyErrCnt = phyCnt1 - params->ofdmPhyErrBase;
627 ahp->ah_stats.ast_ani_ofdmerrs +=
628 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
629 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
631 cckPhyErrCnt = phyCnt2 - params->cckPhyErrBase;
632 ahp->ah_stats.ast_ani_cckerrs +=
633 cckPhyErrCnt - aniState->cckPhyErrCount;
634 aniState->cckPhyErrCount = cckPhyErrCnt;
637 * NB: figure out which counter triggered. If both
638 * trigger we'll only deal with one as the processing
639 * clobbers the error counter so the trigger threshold
640 * check will never be true.
642 if (aniState->ofdmPhyErrCount > params->ofdmTrigHigh)
643 ar5416AniOfdmErrTrigger(ah);
644 if (aniState->cckPhyErrCount > params->cckTrigHigh)
645 ar5416AniCckErrTrigger(ah);
646 /* NB: always restart to insure the h/w counters are reset */
647 ar5416AniRestart(ah, aniState);
652 ar5416AniLowerImmunity(struct ath_hal *ah)
654 struct ath_hal_5212 *ahp = AH5212(ah);
655 struct ar5212AniState *aniState;
656 const struct ar5212AniParams *params;
658 HALASSERT(ANI_ENA(ah));
660 aniState = ahp->ah_curani;
661 params = aniState->params;
662 if (ANI_ENA_RSSI(ah)) {
663 int32_t rssi = BEACON_RSSI(ahp);
664 if (rssi > params->rssiThrHigh) {
666 * Beacon signal is high, leave ofdm weak signal
667 * detection off or it may oscillate. Let it fall
670 } else if (rssi > params->rssiThrLow) {
672 * Beacon rssi in mid range, turn on ofdm weak signal
673 * detection or lower firstep level.
675 if (aniState->ofdmWeakSigDetectOff) {
677 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
681 if (aniState->firstepLevel > 0) {
682 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
683 aniState->firstepLevel - 1);
688 * Beacon rssi is low, reduce firstep level.
690 if (aniState->firstepLevel > 0) {
691 ar5416AniControl(ah, HAL_ANI_FIRSTEP_LEVEL,
692 aniState->firstepLevel - 1);
697 /* then lower spur immunity level, down to zero */
698 if (aniState->spurImmunityLevel > 0) {
699 ar5416AniControl(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
700 aniState->spurImmunityLevel - 1);
704 * if all else fails, lower noise immunity level down to a min value
707 if (aniState->noiseImmunityLevel > 0) {
708 ar5416AniControl(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
709 aniState->noiseImmunityLevel - 1);
714 #define CLOCK_RATE 44000 /* XXX use mac_usec or similar */
715 /* convert HW counter values to ms using 11g clock rate, goo9d enough
719 * Return an approximation of the time spent ``listening'' by
720 * deducting the cycles spent tx'ing and rx'ing from the total
721 * cycle count since our last call. A return value <0 indicates
722 * an invalid/inconsistent time.
725 ar5416AniGetListenTime(struct ath_hal *ah)
727 struct ath_hal_5212 *ahp = AH5212(ah);
728 struct ar5212AniState *aniState;
729 uint32_t txFrameCount, rxFrameCount, cycleCount;
732 txFrameCount = OS_REG_READ(ah, AR_TFCNT);
733 rxFrameCount = OS_REG_READ(ah, AR_RFCNT);
734 cycleCount = OS_REG_READ(ah, AR_CCCNT);
736 aniState = ahp->ah_curani;
737 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
739 * Cycle counter wrap (or initial call); it's not possible
740 * to accurately calculate a value because the registers
741 * right shift rather than wrap--so punt and return 0.
744 ahp->ah_stats.ast_ani_lzero++;
746 int32_t ccdelta = cycleCount - aniState->cycleCount;
747 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
748 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
749 listenTime = (ccdelta - rfdelta - tfdelta) / CLOCK_RATE;
751 aniState->cycleCount = cycleCount;
752 aniState->txFrameCount = txFrameCount;
753 aniState->rxFrameCount = rxFrameCount;
758 * Update ani stats in preparation for listen time processing.
761 updateMIBStats(struct ath_hal *ah, struct ar5212AniState *aniState)
763 struct ath_hal_5212 *ahp = AH5212(ah);
764 const struct ar5212AniParams *params = aniState->params;
765 uint32_t phyCnt1, phyCnt2;
766 int32_t ofdmPhyErrCnt, cckPhyErrCnt;
768 /* Clear the mib counters and save them in the stats */
769 ar5212UpdateMibCounters(ah, &ahp->ah_mibStats);
771 /* NB: these are not reset-on-read */
772 phyCnt1 = OS_REG_READ(ah, AR_PHY_ERR_1);
773 phyCnt2 = OS_REG_READ(ah, AR_PHY_ERR_2);
775 /* NB: these are spec'd to never roll-over */
776 ofdmPhyErrCnt = phyCnt1 - params->ofdmPhyErrBase;
777 if (ofdmPhyErrCnt < 0) {
778 HALDEBUG(ah, HAL_DEBUG_ANI, "OFDM phyErrCnt %d phyCnt1 0x%x\n",
779 ofdmPhyErrCnt, phyCnt1);
780 ofdmPhyErrCnt = AR_PHY_COUNTMAX;
782 ahp->ah_stats.ast_ani_ofdmerrs +=
783 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
784 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
786 cckPhyErrCnt = phyCnt2 - params->cckPhyErrBase;
787 if (cckPhyErrCnt < 0) {
788 HALDEBUG(ah, HAL_DEBUG_ANI, "CCK phyErrCnt %d phyCnt2 0x%x\n",
789 cckPhyErrCnt, phyCnt2);
790 cckPhyErrCnt = AR_PHY_COUNTMAX;
792 ahp->ah_stats.ast_ani_cckerrs +=
793 cckPhyErrCnt - aniState->cckPhyErrCount;
794 aniState->cckPhyErrCount = cckPhyErrCnt;
798 * Do periodic processing. This routine is called from the
799 * driver's rx interrupt handler after processing frames.
802 ar5416AniPoll(struct ath_hal *ah, const HAL_NODE_STATS *stats,
803 const struct ieee80211_channel *chan)
805 struct ath_hal_5212 *ahp = AH5212(ah);
806 struct ar5212AniState *aniState = ahp->ah_curani;
807 const struct ar5212AniParams *params;
810 ahp->ah_stats.ast_nodestats.ns_avgbrssi = stats->ns_avgbrssi;
812 /* XXX can aniState be null? */
813 if (aniState == AH_NULL)
818 listenTime = ar5416AniGetListenTime(ah);
819 if (listenTime < 0) {
820 ahp->ah_stats.ast_ani_lneg++;
821 /* restart ANI period if listenTime is invalid */
822 ar5416AniRestart(ah, aniState);
824 /* XXX beware of overflow? */
825 aniState->listenTime += listenTime;
827 OS_MARK(ah, AH_MARK_ANI_POLL, aniState->listenTime);
829 params = aniState->params;
830 if (aniState->listenTime > 5*params->period) {
832 * Check to see if need to lower immunity if
833 * 5 aniPeriods have passed
835 updateMIBStats(ah, aniState);
836 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
837 params->ofdmTrigLow/1000 &&
838 aniState->cckPhyErrCount <= aniState->listenTime *
839 params->cckTrigLow/1000)
840 ar5416AniLowerImmunity(ah);
841 ar5416AniRestart(ah, aniState);
842 } else if (aniState->listenTime > params->period) {
843 updateMIBStats(ah, aniState);
844 /* check to see if need to raise immunity */
845 if (aniState->ofdmPhyErrCount > aniState->listenTime *
846 params->ofdmTrigHigh / 1000) {
847 ar5416AniOfdmErrTrigger(ah);
848 ar5416AniRestart(ah, aniState);
849 } else if (aniState->cckPhyErrCount > aniState->listenTime *
850 params->cckTrigHigh / 1000) {
851 ar5416AniCckErrTrigger(ah);
852 ar5416AniRestart(ah, aniState);