2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar9285_reset.c 203930 2010-02-15 17:49:49Z rpaulo $
22 * This is almost the same as ar5416_reset.c but uses the v4k EEPROM and
23 * supports only 2Ghz operation.
29 #include "ah_internal.h"
32 #include "ah_eeprom_v14.h"
33 #include "ah_eeprom_v4k.h"
35 #include "ar5416/ar9285.h"
36 #include "ar5416/ar5416.h"
37 #include "ar5416/ar5416reg.h"
38 #include "ar5416/ar5416phy.h"
40 /* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */
41 #define EEP_MINOR(_ah) \
42 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK)
43 #define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2)
44 #define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3)
46 /* Additional Time delay to wait after activiting the Base band */
47 #define BASE_ACTIVATE_DELAY 100 /* 100 usec */
48 #define PLL_SETTLE_DELAY 300 /* 300 usec */
49 #define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */
51 static HAL_BOOL ar9285SetPowerPerRateTable(struct ath_hal *ah,
52 struct ar5416eeprom_4k *pEepData,
53 const struct ieee80211_channel *chan, int16_t *ratesArray,
54 uint16_t cfgCtl, uint16_t AntennaReduction,
55 uint16_t twiceMaxRegulatoryPower,
57 static HAL_BOOL ar9285SetPowerCalTable(struct ath_hal *ah,
58 struct ar5416eeprom_4k *pEepData,
59 const struct ieee80211_channel *chan,
60 int16_t *pTxPowerIndexOffset);
61 static int16_t interpolate(uint16_t target, uint16_t srcLeft,
62 uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
63 static HAL_BOOL ar9285FillVpdTable(uint8_t, uint8_t, uint8_t *, uint8_t *,
65 static void ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,
66 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ_4K *pRawDataSet,
67 uint8_t * bChans, uint16_t availPiers,
68 uint16_t tPdGainOverlap, int16_t *pMinCalPower,
69 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues,
70 uint16_t numXpdGains);
71 static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList,
72 uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
73 static uint16_t ar9285GetMaxEdgePower(uint16_t, CAL_CTL_EDGES *);
75 /* XXX gag, this is sick */
76 typedef enum Ar5416_Rates {
77 rate6mb, rate9mb, rate12mb, rate18mb,
78 rate24mb, rate36mb, rate48mb, rate54mb,
79 rate1l, rate2l, rate2s, rate5_5l,
80 rate5_5s, rate11l, rate11s, rateXr,
81 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
82 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
83 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
84 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
85 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
90 ar9285SetTransmitPower(struct ath_hal *ah,
91 const struct ieee80211_channel *chan, uint16_t *rfXpdGain)
93 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
94 #define N(a) (sizeof (a) / sizeof (a[0]))
96 MODAL_EEP4K_HEADER *pModal;
97 struct ath_hal_5212 *ahp = AH5212(ah);
98 int16_t ratesArray[Ar5416RateSize];
99 int16_t txPowerIndexOffset = 0;
100 uint8_t ht40PowerIncForPdadc = 2;
105 uint16_t twiceAntennaReduction;
106 uint16_t twiceMaxRegulatoryPower;
108 HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
109 struct ar5416eeprom_4k *pEepData = &ee->ee_base;
111 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
113 /* Setup info for the actual eeprom */
114 OS_MEMZERO(ratesArray, sizeof(ratesArray));
115 cfgCtl = ath_hal_getctl(ah, chan);
116 powerLimit = chan->ic_maxregpower * 2;
117 twiceAntennaReduction = chan->ic_maxantgain;
118 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit);
119 pModal = &pEepData->modalHeader;
120 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n",
121 __func__,chan->ic_freq, cfgCtl );
123 if (IS_EEP_MINOR_V2(ah)) {
124 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
127 if (!ar9285SetPowerPerRateTable(ah, pEepData, chan,
128 &ratesArray[0],cfgCtl,
129 twiceAntennaReduction,
130 twiceMaxRegulatoryPower, powerLimit)) {
131 HALDEBUG(ah, HAL_DEBUG_ANY,
132 "%s: unable to set tx power per rate table\n", __func__);
136 if (!ar9285SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) {
137 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n",
142 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]);
143 maxPower = AH_MAX(maxPower, ratesArray[rate1l]);
145 if (IEEE80211_IS_CHAN_HT40(chan)) {
146 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]);
149 ahp->ah_tx6PowerInHalfDbm = maxPower;
150 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower;
151 ahp->ah_txPowerIndexOffset = txPowerIndexOffset;
154 * txPowerIndexOffset is set by the SetPowerTable() call -
155 * adjust the rate table (0 offset if rates EEPROM not loaded)
157 for (i = 0; i < N(ratesArray); i++) {
158 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
159 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
160 ratesArray[i] = AR5416_MAX_RATE_POWER;
161 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
164 #ifdef AH_EEPROM_DUMP
165 ar5416PrintPowerPerRate(ah, ratesArray);
168 /* Write the OFDM power per rate set */
169 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
170 POW_SM(ratesArray[rate18mb], 24)
171 | POW_SM(ratesArray[rate12mb], 16)
172 | POW_SM(ratesArray[rate9mb], 8)
173 | POW_SM(ratesArray[rate6mb], 0)
175 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
176 POW_SM(ratesArray[rate54mb], 24)
177 | POW_SM(ratesArray[rate48mb], 16)
178 | POW_SM(ratesArray[rate36mb], 8)
179 | POW_SM(ratesArray[rate24mb], 0)
182 /* Write the CCK power per rate set */
183 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
184 POW_SM(ratesArray[rate2s], 24)
185 | POW_SM(ratesArray[rate2l], 16)
186 | POW_SM(ratesArray[rateXr], 8) /* XR target power */
187 | POW_SM(ratesArray[rate1l], 0)
189 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
190 POW_SM(ratesArray[rate11s], 24)
191 | POW_SM(ratesArray[rate11l], 16)
192 | POW_SM(ratesArray[rate5_5s], 8)
193 | POW_SM(ratesArray[rate5_5l], 0)
195 HALDEBUG(ah, HAL_DEBUG_RESET,
196 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n",
197 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3),
198 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4));
200 /* Write the HT20 power per rate set */
201 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
202 POW_SM(ratesArray[rateHt20_3], 24)
203 | POW_SM(ratesArray[rateHt20_2], 16)
204 | POW_SM(ratesArray[rateHt20_1], 8)
205 | POW_SM(ratesArray[rateHt20_0], 0)
207 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
208 POW_SM(ratesArray[rateHt20_7], 24)
209 | POW_SM(ratesArray[rateHt20_6], 16)
210 | POW_SM(ratesArray[rateHt20_5], 8)
211 | POW_SM(ratesArray[rateHt20_4], 0)
214 if (IEEE80211_IS_CHAN_HT40(chan)) {
215 /* Write the HT40 power per rate set */
216 /* Correct PAR difference between HT40 and HT20/LEGACY */
217 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
218 POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24)
219 | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16)
220 | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8)
221 | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0)
223 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
224 POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24)
225 | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16)
226 | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8)
227 | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0)
229 /* Write the Dup/Ext 40 power per rate set */
230 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
231 POW_SM(ratesArray[rateExtOfdm], 24)
232 | POW_SM(ratesArray[rateExtCck], 16)
233 | POW_SM(ratesArray[rateDupOfdm], 8)
234 | POW_SM(ratesArray[rateDupCck], 0)
244 ar9285SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan)
246 const HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom;
247 const struct ar5416eeprom_4k *eep = &ee->ee_base;
248 const MODAL_EEP4K_HEADER *pModal;
249 int i, regChainOffset;
250 uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */
252 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1);
253 pModal = &eep->modalHeader;
255 /* NB: workaround for eeprom versions <= 14.2 */
258 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
259 for (i = 0; i < AR5416_4K_MAX_CHAINS; i++) {
260 if (AR_SREV_MERLIN(ah)) {
263 if (AR_SREV_OWL_20_OR_LATER(ah) &&
264 (AH5416(ah)->ah_rx_chainmask == 0x5 ||
265 AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) {
266 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
267 * only chains 0 and 2 populated
269 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
271 regChainOffset = i * 0x1000;
274 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]);
275 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset,
276 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) &
277 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
278 SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
279 SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
282 * Large signal upgrade.
286 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
287 OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset,
288 (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) |
289 SM(IS_EEP_MINOR_V3(ah) ? pModal->txRxAttenCh[i] : txRxAttenLocal,
290 AR_PHY_RXGAIN_TXRX_ATTEN));
292 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
293 (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
294 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
298 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
299 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
300 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize);
301 OS_REG_WRITE(ah, AR_PHY_RF_CTL4,
302 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
303 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
304 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
305 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
307 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
309 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
311 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
314 /* Minor Version Specific application */
315 if (IS_EEP_MINOR_V2(ah)) {
316 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart);
317 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn);
320 if (IS_EEP_MINOR_V3(ah)) {
321 if (IEEE80211_IS_CHAN_HT40(chan)) {
322 /* Overwrite switch settling with HT40 value */
323 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
326 if ((AR_SREV_OWL_20_OR_LATER(ah)) &&
327 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){
328 /* Reg Offsets are swapped for logical mapping */
329 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
330 SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
331 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
332 SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
333 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
334 SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
335 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
336 SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
338 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
339 SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN));
340 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
341 SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
342 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) |
343 SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN));
344 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) |
345 SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN));
347 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]);
348 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]);
354 * Helper functions common for AP/CB/XB
358 ar9285SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,
359 const struct ieee80211_channel *chan,
360 int16_t *ratesArray, uint16_t cfgCtl,
361 uint16_t AntennaReduction,
362 uint16_t twiceMaxRegulatoryPower,
365 #define N(a) (sizeof(a)/sizeof(a[0]))
366 /* Local defines to distinguish between extension and control CTL's */
367 #define EXT_ADDITIVE (0x8000)
368 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
369 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
371 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
373 int16_t twiceLargestAntenna;
374 CAL_CTL_DATA_4K *rep;
375 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}};
376 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}};
377 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}};
378 int16_t scaledPower, minCtlPower;
380 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
381 static const uint16_t ctlModesFor11g[] = {
382 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
384 const uint16_t *pCtlMode;
385 uint16_t numCtlModes, ctlMode, freq;
386 CHAN_CENTERS centers;
388 ar5416GetChannelCenters(ah, chan, ¢ers);
390 /* Compute TxPower reduction due to Antenna Gain */
392 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
393 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0);
395 /* XXX setup for 5212 use (really used?) */
396 ath_hal_eepromSet(ah, AR_EEP_ANTGAINMAX_2, twiceLargestAntenna);
399 * scaledPower is the minimum of the user input power level and
400 * the regulatory allowed power level
402 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna);
404 /* Get target powers from EEPROM - our baseline for TX Power */
405 /* Setup for CTL modes */
406 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */
407 pCtlMode = ctlModesFor11g;
409 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
410 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE);
411 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
412 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE);
413 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20,
414 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE);
416 if (IEEE80211_IS_CHAN_HT40(chan)) {
417 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */
419 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40,
420 AR5416_4K_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE);
421 /* Get target powers for extension channels */
422 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck,
423 AR5416_4K_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE);
424 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G,
425 AR5416_4K_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE);
429 * For MIMO, need to apply regulatory caps individually across dynamically
430 * running modes: CCK, OFDM, HT20, HT40
432 * The outer loop walks through each possible applicable runtime mode.
433 * The inner loop walks through each ctlIndex entry in EEPROM.
434 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
437 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
438 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
439 (pCtlMode[ctlMode] == CTL_2GHT40);
441 freq = centers.ctl_center;
442 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) {
443 freq = centers.ext_center;
445 freq = centers.ctl_center;
448 /* walk through each CTL index stored in EEPROM */
449 for (i = 0; (i < AR5416_4K_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
450 uint16_t twiceMinEdgePower;
452 /* compare test group from regulatory channel list with test mode from pCtlMode list */
453 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) ||
454 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) ==
455 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
456 rep = &(pEepData->ctlData[i]);
457 twiceMinEdgePower = ar9285GetMaxEdgePower(freq,
459 owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1]);
460 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
461 /* Find the minimum of all CTL edge powers that apply to this channel */
462 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower);
465 twiceMaxEdgePower = twiceMinEdgePower;
470 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower);
471 /* Apply ctl mode to correct target power set */
472 switch(pCtlMode[ctlMode]) {
474 for (i = 0; i < N(targetPowerCck.tPow2x); i++) {
475 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower);
480 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) {
481 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower);
486 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
487 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower);
491 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower);
494 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower);
498 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
499 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower);
506 } /* end ctl mode checking */
508 /* Set rates Array from collected data */
509 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
510 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
511 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
512 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
513 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
515 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) {
516 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
519 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
520 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
521 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
522 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
523 if (IEEE80211_IS_CHAN_HT40(chan)) {
524 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) {
525 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
527 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
528 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
529 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
530 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
531 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
538 #undef SUB_NUM_CTL_MODES_AT_2G_40
542 /**************************************************************************
545 * Get channel value from binary representation held in eeprom
546 * RETURNS: the frequency in MHz
549 fbin2freq(uint8_t fbin)
552 * Reserved value 0xFF provides an empty definition both as
553 * an fbin and as a frequency - do not convert
555 if (fbin == AR5416_BCHAN_UNUSED) {
559 return (uint16_t)(2300 + fbin);
563 * XXX almost the same as ar5416GetMaxEdgePower.
566 ar9285GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower)
568 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
571 /* Get the edge power */
572 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) {
574 * If there's an exact channel match or an inband flag set
575 * on the lower channel use the given rdEdgePower
577 if (freq == fbin2freq(pRdEdgesPower[i].bChannel)) {
578 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER);
580 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel))) {
581 if (fbin2freq(pRdEdgesPower[i - 1].bChannel) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) {
582 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER);
584 /* Leave loop - no more affecting edges possible in this monotonic increasing list */
588 HALASSERT(twiceMaxEdgePower > 0);
589 return twiceMaxEdgePower;
595 ar9285SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom_4k *pEepData,
596 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset)
598 CAL_DATA_PER_FREQ_4K *pRawDataset;
599 uint8_t *pCalBChans = AH_NULL;
600 uint16_t pdGainOverlap_t2;
601 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
602 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
603 uint16_t numPiers, i, j;
604 int16_t tMinCalPower;
605 uint16_t numXpdGain, xpdMask;
606 uint16_t xpdGainValues[AR5416_4K_NUM_PD_GAINS];
607 uint32_t reg32, regOffset, regChainOffset;
609 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues));
611 xpdMask = pEepData->modalHeader.xpdGain;
613 if (IS_EEP_MINOR_V2(ah)) {
614 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
616 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
619 pCalBChans = pEepData->calFreqPier2G;
620 numPiers = AR5416_4K_NUM_2G_CAL_PIERS;
622 /* Calculate the value of xpdgains from the xpdGain Mask */
623 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
624 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
625 if (numXpdGain >= AR5416_4K_NUM_PD_GAINS) {
629 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i);
634 /* Write the detector gain biases and their number */
635 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) &
636 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) |
637 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) |
638 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3));
640 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
642 if (AR_SREV_OWL_20_OR_LATER(ah) &&
643 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) {
644 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with
645 * only chains 0 and 2 populated
647 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
649 regChainOffset = i * 0x1000;
652 if (pEepData->baseEepHeader.txMask & (1 << i)) {
653 pRawDataset = pEepData->calPierData2G[i];
655 ar9285GetGainBoundariesAndPdadcs(ah, chan, pRawDataset,
656 pCalBChans, numPiers,
658 &tMinCalPower, gainBoundaries,
659 pdadcValues, numXpdGain);
661 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) {
663 * Note the pdadc table may not start at 0 dBm power, could be
664 * negative or greater than 0. Need to offset the power
665 * values by the amount of minPower for griffin
668 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
669 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
670 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) |
671 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) |
672 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) |
673 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
676 /* Write the power values into the baseband power table */
677 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
679 for (j = 0; j < 32; j++) {
680 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) |
681 ((pdadcValues[4*j + 1] & 0xFF) << 8) |
682 ((pdadcValues[4*j + 2] & 0xFF) << 16) |
683 ((pdadcValues[4*j + 3] & 0xFF) << 24) ;
684 OS_REG_WRITE(ah, regOffset, reg32);
687 ath_hal_printf(ah, "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n",
689 4*j, pdadcValues[4*j],
690 4*j+1, pdadcValues[4*j + 1],
691 4*j+2, pdadcValues[4*j + 2],
692 4*j+3, pdadcValues[4*j + 3]);
698 *pTxPowerIndexOffset = 0;
704 ar9285GetGainBoundariesAndPdadcs(struct ath_hal *ah,
705 const struct ieee80211_channel *chan,
706 CAL_DATA_PER_FREQ_4K *pRawDataSet,
707 uint8_t * bChans, uint16_t availPiers,
708 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries,
709 uint8_t * pPDADCValues, uint16_t numXpdGains)
713 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */
714 uint16_t idxL, idxR, numPiers; /* Pier indexes */
716 /* filled out Vpd table for all pdGains (chanL) */
717 static uint8_t vpdTableL[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
719 /* filled out Vpd table for all pdGains (chanR) */
720 static uint8_t vpdTableR[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
722 /* filled out Vpd table for all pdGains (interpolated) */
723 static uint8_t vpdTableI[AR5416_4K_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB];
725 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR;
726 uint8_t minPwrT4[AR5416_4K_NUM_PD_GAINS];
727 uint8_t maxPwrT4[AR5416_4K_NUM_PD_GAINS];
730 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex;
732 int16_t minDelta = 0;
733 CHAN_CENTERS centers;
735 ar5416GetChannelCenters(ah, chan, ¢ers);
737 /* Trim numPiers for the number of populated channel Piers */
738 for (numPiers = 0; numPiers < availPiers; numPiers++) {
739 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) {
744 /* Find pier indexes around the current channel */
745 match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
746 bChans, numPiers, &idxL, &idxR);
749 /* Directly fill both vpd tables from the matching index */
750 for (i = 0; i < numXpdGains; i++) {
751 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
752 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
753 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i],
754 pRawDataSet[idxL].pwrPdg[i],
755 pRawDataSet[idxL].vpdPdg[i],
756 AR5416_PD_GAIN_ICEPTS, vpdTableI[i]);
759 for (i = 0; i < numXpdGains; i++) {
760 pVpdL = pRawDataSet[idxL].vpdPdg[i];
761 pPwrL = pRawDataSet[idxL].pwrPdg[i];
762 pVpdR = pRawDataSet[idxR].vpdPdg[i];
763 pPwrR = pRawDataSet[idxR].pwrPdg[i];
765 /* Start Vpd interpolation from the max of the minimum powers */
766 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]);
768 /* End Vpd interpolation from the min of the max powers */
769 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
770 HALASSERT(maxPwrT4[i] > minPwrT4[i]);
773 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL,
774 AR5416_PD_GAIN_ICEPTS, vpdTableL[i]);
775 ar9285FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR,
776 AR5416_PD_GAIN_ICEPTS, vpdTableR[i]);
778 /* Interpolate the final vpd */
779 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
780 vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)),
781 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j]));
785 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
787 k = 0; /* index for the final table */
788 for (i = 0; i < numXpdGains; i++) {
789 if (i == (numXpdGains - 1)) {
790 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2);
792 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4);
795 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
797 /* NB: only applies to owl 1.0 */
798 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) {
800 * fix the gain delta, but get a delta that can be applied to min to
801 * keep the upper power values accurate, don't think max needs to
802 * be adjusted because should not be at that area of the table?
804 minDelta = pPdGainBoundaries[0] - 23;
805 pPdGainBoundaries[0] = 23;
811 /* Find starting index for this pdGain */
813 ss = 0; /* for the first pdGain, start from index 0 */
815 /* need overlap entries extrapolated below. */
816 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta);
818 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
819 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
821 *-ve ss indicates need to extrapolate data below for this pdGain
823 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
824 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
825 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal);
829 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1);
830 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2));
831 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
833 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
834 pPDADCValues[k++] = vpdTableI[i][ss++];
837 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]);
838 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
840 * for last gain, pdGainBoundary == Pmax_t2, so will
841 * have to extrapolate
843 if (tgtIndex > maxIndex) { /* need to extrapolate above */
844 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
845 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
846 (ss - maxIndex +1) * vpdStep));
847 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal);
850 } /* extrapolated above */
851 } /* for all pdGainUsed */
853 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */
854 while (i < AR5416_PD_GAINS_IN_MASK) {
855 pPdGainBoundaries[i] = pPdGainBoundaries[i-1];
859 while (k < AR5416_NUM_PDADC_VALUES) {
860 pPDADCValues[k] = pPDADCValues[k-1];
866 * XXX same as ar5416FillVpdTable
869 ar9285FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList,
870 uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList)
873 uint8_t currPwr = pwrMin;
876 HALASSERT(pwrMax > pwrMin);
877 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
878 getLowerUpperIndex(currPwr, pPwrList, numIntercepts,
881 idxR = 1; /* extrapolate below */
882 if (idxL == numIntercepts - 1)
883 idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */
884 if (pPwrList[idxL] == pPwrList[idxR])
887 k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
888 (pPwrList[idxR] - pPwrList[idxL]) );
890 pRetVpdList[i] = (uint8_t)k;
891 currPwr += 2; /* half dB steps */
897 interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight,
898 int16_t targetLeft, int16_t targetRight)
902 if (srcRight == srcLeft) {
905 rv = (int16_t)( ((target - srcLeft) * targetRight +
906 (srcRight - target) * targetLeft) / (srcRight - srcLeft) );
912 getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize,
913 uint16_t *indexL, uint16_t *indexR)
918 * Check first and last elements for beyond ordered array cases.
920 if (target <= pList[0]) {
921 *indexL = *indexR = 0;
924 if (target >= pList[listSize-1]) {
925 *indexL = *indexR = (uint16_t)(listSize - 1);
929 /* look for value being near or between 2 values in list */
930 for (i = 0; i < listSize - 1; i++) {
932 * If value is close to the current value of the list
933 * then target is not between values, it is one of the values
935 if (pList[i] == target) {
936 *indexL = *indexR = i;
940 * Look for value being between current value and next value
941 * if so return these 2 values
943 if (target < pList[i + 1]) {
945 *indexR = (uint16_t)(i + 1);
950 *indexL = *indexR = 0;