3 * Copyright (c) 2012 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #define DWC_OTG_MAX_DEVICES (USB_MIN_DEVICES + 1)
31 #define DWC_OTG_FRAME_MASK 0x7FF
32 #define DWC_OTG_MAX_TXP 4
33 #define DWC_OTG_MAX_TXN (0x200 * DWC_OTG_MAX_TXP)
35 /* Global CSR registers */
37 #define DWC_OTG_REG_GOTGCTL 0x0000
38 #define DWC_OTG_MSK_GOTGCTL_CHIRP_ON (1U << 27)
39 #define DWC_OTG_MSK_GOTGCTL_BSESS_VALID (1U << 19)
40 #define DWC_OTG_MSK_GOTGCTL_ASESS_VALID (1U << 18)
41 #define DWC_OTG_MSK_GOTGCTL_CONN_ID_STATUS (1U << 16)
42 #define DWC_OTG_MSK_GOTGCTL_SESS_REQ (1U << 1)
43 #define DWC_OTG_MSK_GOTGCTL_SESS_VALID (1U << 0)
45 #define DWC_OTG_REG_GOTGINT 0x0004
46 #define DWC_OTG_REG_GAHBCFG 0x0008
47 #define DWC_OTG_MSK_GAHBCFG_GLOBAL_IRQ (1U << 0)
49 #define DWC_OTG_REG_GUSBCFG 0x000C
50 #define DWC_OTG_MSK_GUSBCFG_FORCE_DEVICE (1U << 30)
51 #define DWC_OTG_MSK_GUSBCFG_FORCE_HOST (1U << 29)
52 #define DWC_OTG_MSK_GUSBCFG_NO_PULLUP (1U << 27)
53 #define DWC_OTG_MSK_GUSBCFG_NO_PULLUP (1U << 27)
54 #define DWC_OTG_MSK_GUSBCFG_IC_USB_CAP (1U << 26)
55 #define DWC_OTG_MSK_GUSBCFG_ULPI_FS_LS (1U << 17)
56 #define DWC_OTG_MSK_GUSBCFG_TRD_TIM(x) (((x) & 15U) << 10)
57 #define DWC_OTG_MSK_GUSBCFG_HRP (1U << 9)
58 #define DWC_OTG_MSK_GUSBCFG_SRP (1U << 8)
59 #define DWC_OTG_MSK_GUSBCFG_HS_PHY (1U << 6)
60 #define DWC_OTG_MSK_GUSBCFG_FS_INTF (1U << 5)
61 #define DWC_OTG_MSK_GUSBCFG_ULPI_UMTI_SEL (1U << 4)
62 #define DWC_OTG_MSK_GUSBCFG_PHY_INTF (1U << 3)
64 #define DWC_OTG_REG_GRSTCTL 0x0010
65 #define DWC_OTG_MSK_GRSTCTL_TXFIFO(n) (((n) & 31U) << 6)
66 #define DWC_OTG_MSK_GRSTCTL_TXFFLUSH (1U << 5)
67 #define DWC_OTG_MSK_GRSTCTL_RXFFLUSH (1U << 4)
68 #define DWC_OTG_MSK_GRSTCTL_FRMCNTRRST (1U << 2)
69 #define DWC_OTG_MSK_GRSTCTL_CSFTRST (1U << 0)
71 #define DWC_OTG_REG_GINTSTS 0x0014
72 #define DWC_OTG_REG_GINTMSK 0x0018
73 #define DWC_OTG_MSK_GINT_WKUPINT (1U << 31)
74 #define DWC_OTG_MSK_GINT_SESSREQINT (1U << 30)
75 #define DWC_OTG_MSK_GINT_DISCONNINT (1U << 29)
76 #define DWC_OTG_MSK_GINT_CONNIDSTSCHNG (1U << 28)
77 #define DWC_OTG_MSK_GINT_LPM (1U << 27)
78 #define DWC_OTG_MSK_GINT_PTXFEMP (1U << 26)
79 #define DWC_OTG_MSK_GINT_HCHINT (1U << 25)
80 #define DWC_OTG_MSK_GINT_PRTINT (1U << 24)
81 #define DWC_OTG_MSK_GINT_RESETDET (1U << 23)
82 #define DWC_OTG_MSK_GINT_FETSUSP (1U << 22)
83 #define DWC_OTG_MSK_GINT_INCOMPL_P (1U << 21)
84 #define DWC_OTG_MSK_GINT_INCOMPL_ISO_IN (1U << 20)
85 #define DWC_OTG_MSK_GINT_OUTEP (1U << 19)
86 #define DWC_OTG_MSK_GINT_INEP (1U << 18)
87 #define DWC_OTG_MSK_GINT_EP_MISMATCH (1U << 17)
88 #define DWC_OTG_MSK_GINT_RESTORE_DONE (1U << 16)
89 #define DWC_OTG_MSK_GINT_EOP_FRAME (1U << 15)
90 #define DWC_OTG_MSK_GINT_ISO_OUT_DROP (1U << 14)
91 #define DWC_OTG_MSK_GINT_ENUM_DONE (1U << 13)
92 #define DWC_OTG_MSK_GINT_USB_RESET (1U << 12)
93 #define DWC_OTG_MSK_GINT_USB_SUSPEND (1U << 11)
94 #define DWC_OTG_MSK_GINT_EARLY_SUSPEND (1U << 10)
95 #define DWC_OTG_MSK_GINT_I2C_INT (1U << 9)
96 #define DWC_OTG_MSK_GINT_ULPI_CARKIT (1U << 8)
97 #define DWC_OTG_MSK_GINT_GLOBAL_OUT_NAK (1U << 7)
98 #define DWC_OTG_MSK_GINT_GLOBAL_IN_NAK (1U << 6)
99 #define DWC_OTG_MSK_GINT_NPTXFEMP (1U << 5)
100 #define DWC_OTG_MSK_GINT_RXFLVL (1U << 4)
101 #define DWC_OTG_MSK_GINT_SOF (1U << 3)
102 #define DWC_OTG_MSK_GINT_OTG (1U << 2)
103 #define DWC_OTG_MSK_GINT_MODE_MISMATCH (1U << 1)
104 #define DWC_OTG_MSK_GINT_CUR_MODE (1U << 0)
106 #define DWC_OTG_REG_GRXSTSR 0x001C
107 #define DWC_OTG_REG_GRXSTSP 0x0020
108 #define DWC_OTG_MSK_GRXSTS_PACKET_STS (15U << 17)
109 #define DWC_OTG_MSK_GRXSTS_HST_IN_DATA (2U << 17)
110 #define DWC_OTG_MSK_GRXSTS_HST_IN_COMPLETE (3U << 17)
111 #define DWC_OTG_MSK_GRXSTS_HST_DT_ERROR (5U << 17)
112 #define DWC_OTG_MSK_GRXSTS_HST_HALTED (7U << 17)
113 #define DWC_OTG_MSK_GRXSTS_DEV_GLOB_OUT_NAK (1U << 17)
114 #define DWC_OTG_MSK_GRXSTS_DEV_OUT_DATA (2U << 17)
115 #define DWC_OTG_MSK_GRXSTS_DEV_OUT_COMPLETE (3U << 17)
116 #define DWC_OTG_MSK_GRXSTS_DEV_STP_COMPLETE (4U << 17)
117 #define DWC_OTG_MSK_GRXSTS_DEV_STP_DATA (6U << 17)
118 #define DWC_OTG_MSK_GRXSTS_PID (3U << 15)
119 #define DWC_OTG_MSK_GRXSTS_PID_DATA0 (0U << 15)
120 #define DWC_OTG_MSK_GRXSTS_PID_DATA1 (2U << 15)
121 #define DWC_OTG_MSK_GRXSTS_PID_DATA2 (1U << 15)
122 #define DWC_OTG_MSK_GRXSTS_PID_MDATA (3U << 15)
123 #define DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT(x) (((x) >> 4) & 0x7FFU)
124 #define DWC_OTG_MSK_GRXSTS_GET_CHANNEL(x) ((x) & 15U)
125 #define DWC_OTG_MSK_GRXSTS_GET_FRNUM (x) (((x) >> 21) & 15U)
127 #define DWC_OTG_REG_GRXFSIZ 0x0024
128 #define DWC_OTG_REG_GNPTXFSIZ 0x0028
129 #define DWC_OTG_REG_GNPTXSTS 0x002C
130 #define DWC_OTG_REG_GI2CCTL 0x0030
131 #define DWC_OTG_REG_GPVNDCTL 0x0034
132 #define DWC_OTG_REG_GGPIO 0x0038
133 #define DWC_OTG_REG_GUID 0x003C
134 #define DWC_OTG_REG_GSNPSID 0x0040
135 #define DWC_OTG_REG_GHWCFG1 0x0044
136 #define DWC_OTG_MSK_GHWCFG1_GET_DIR(x, n) (((x) >> (2 * (n))) & 3U)
137 #define DWC_OTG_MSK_GHWCFG1_BIDIR (0U)
138 #define DWC_OTG_MSK_GHWCFG1_IN (1U)
139 #define DWC_OTG_MSK_GHWCFG1_OUT (2U)
140 #define DWC_OTG_REG_GHWCFG2 0x0048
141 #define DWC_OTG_MSK_GHWCFG2_NUM_DEV_EP(x) ((((x) >> 10) & 15) + 1)
142 #define DWC_OTG_MSK_GHWCFG2_NUM_HOST_EP(x) ((((x) >> 14) & 15) + 1)
143 #define DWC_OTG_REG_GHWCFG3 0x004C
144 #define DWC_OTG_MSK_GHWCFG3_GET_DFIFO(x) ((x) >> 16)
145 #define DWC_OTG_MSK_GHWCFG3_PKT_SIZE (0x10U << (((x) >> 4) & 7))
146 #define DWC_OTG_MSK_GHWCFG3_XFR_SIZE (0x400U << (((x) >> 0) & 15))
148 #define DWC_OTG_REG_GHWCFG4 0x0050
149 #define DWC_OTG_MSK_GHWCFG4_NUM_IN_EPS(x) ((((x) >> 26) & 15U) + 1U)
150 #define DWC_OTG_MSK_GHWCFG4_NUM_CTRL_EPS(x) (((x) >> 16) & 15U)
151 #define DWC_OTG_MSK_GHWCFG4_NUM_IN_PERIODIC_EPS(x) (((x) >> 0) & 15U)
153 #define DWC_OTG_REG_GLPMCFG 0x0054
154 #define DWC_OTG_MSK_GLPMCFG_HSIC_CONN (1U << 30)
155 #define DWC_OTG_REG_GPWRDN 0x0058
156 #define DWC_OTG_MSK_GPWRDN_BVALID (1U << 22)
157 #define DWC_OTG_MSK_GPWRDN_IDDIG (1U << 21)
158 #define DWC_OTG_MSK_GPWRDN_CONNDET_INT (1U << 14)
159 #define DWC_OTG_MSK_GPWRDN_CONNDET (1U << 13)
160 #define DWC_OTG_MSK_GPWRDN_DISCONN_INT (1U << 12)
161 #define DWC_OTG_MSK_GPWRDN_DISCONN (1U << 11)
162 #define DWC_OTG_MSK_GPWRDN_RESETDET_INT (1U << 10)
163 #define DWC_OTG_MSK_GPWRDN_RESETDET (1U << 9)
164 #define DWC_OTG_MSK_GPWRDN_LINESTATE_INT (1U << 8)
165 #define DWC_OTG_MSK_GPWRDN_LINESTATE (1U << 7)
166 #define DWC_OTG_MSK_GPWRDN_DISABLE_VBUS (1U << 6)
167 #define DWC_OTG_MSK_GPWRDN_POWER_DOWN (1U << 5)
168 #define DWC_OTG_MSK_GPWRDN_POWER_DOWN_RST (1U << 4)
169 #define DWC_OTG_MSK_GPWRDN_POWER_DOWN_CLAMP (1U << 3)
170 #define DWC_OTG_MSK_GPWRDN_RESTORE (1U << 2)
171 #define DWC_OTG_MSK_GPWRDN_PMU_ACTIVE (1U << 1)
172 #define DWC_OTG_MSK_GPWRDN_PMU_IRQ_SEL (1U << 0)
174 #define DWC_OTG_REG_GDFIFOCFG 0x005C
175 #define DWC_OTG_REG_GADPCTL 0x0060
176 #define DWC_OTG_REG_HPTXFSIZ 0x0100
177 #define DWC_OTG_REG_DPTXFSIZ(n) (0x0100 + (4*(n)))
178 #define DWC_OTG_REG_DIEPTXF(n) (0x0100 + (4*(n)))
180 /* Host Mode CSR registers */
182 #define DWC_OTG_REG_HCFG 0x0400
183 #define DWC_OTG_REG_HFIR 0x0404
184 #define DWC_OTG_REG_HFNUM 0x0408
185 #define DWC_OTG_REG_HPTXSTS 0x0410
186 #define DWC_OTG_REG_HAINT 0x0414
187 #define DWC_OTG_REG_HAINTMSK 0x0418
188 #define DWC_OTG_REG_HPRT 0x0440
189 #define DWC_OTG_REG_HCCHAR(n) (0x0500 + (32*(n)))
190 #define DWC_OTG_REG_HCSPLT(n) (0x0504 + (32*(n)))
191 #define DWC_OTG_REG_HCINT(n) (0x0508 + (32*(n)))
192 #define DWC_OTG_REG_HCINTMSK(n) (0x050C + (32*(n)))
193 #define DWC_OTG_REG_HCTSIZ(n) (0x0510 + (32*(n)))
194 #define DWC_OTG_REG_HCDMA(n) (0x0514 + (32*(n)))
195 #define DWC_OTG_REG_HCDMAB(n) (0x051C + (32*(n)))
197 /* Device Mode CSR registers */
199 #define DWC_OTG_REG_DCFG 0x0800
200 #define DWC_OTG_MSK_DCFG_SET_DEV_ADDR(x) (((x) & 0x7FU) << 4)
201 #define DWC_OTG_MSK_DCFG_SET_DEV_SPEED(x) ((x) & 0x3U)
202 #define DWC_OTG_MSK_DCFG_DEV_SPEED_HI (0U)
203 #define DWC_OTG_MSK_DCFG_DEV_SPEED_FULL20 (1U)
204 #define DWC_OTG_MSK_DCFG_DEV_SPEED_FULL10 (3U)
206 #define DWC_OTG_REG_DCTL 0x0804
207 #define DWC_OTG_MSK_DCTL_PWRON_PROG_DONE (1U << 11)
208 #define DWC_OTG_MSK_DCTL_CGOUT_NAK (1U << 10)
209 #define DWC_OTG_MSK_DCTL_CGNPIN_NAK (1U << 8)
210 #define DWC_OTG_MSK_DCTL_SOFT_DISC (1U << 1)
211 #define DWC_OTG_MSK_DCTL_REMOTE_WAKEUP (1U << 0)
213 #define DWC_OTG_REG_DSTS 0x0808
214 #define DWC_OTG_MSK_DSTS_GET_FNUM(x) (((x) >> 8) & 0x3FFF)
215 #define DWC_OTG_MSK_DSTS_GET_ENUM_SPEED(x) (((x) >> 1) & 3U)
216 #define DWC_OTG_MSK_DSTS_ENUM_SPEED_HI (0U)
217 #define DWC_OTG_MSK_DSTS_ENUM_SPEED_FULL20 (1U)
218 #define DWC_OTG_MSK_DSTS_ENUM_SPEED_LOW10 (2U)
219 #define DWC_OTG_MSK_DSTS_ENUM_SPEED_FULL10 (3U)
220 #define DWC_OTG_MSK_DSTS_SUSPEND (1U << 0)
222 #define DWC_OTG_REG_DIEPMSK 0x0810
223 #define DWC_OTG_MSK_DIEP_FIFO_EMPTY (1U << 4)
224 #define DWC_OTG_MSK_DIEP_XFER_COMPLETE (1U << 0)
226 #define DWC_OTG_REG_DOEPMSK 0x0814
227 #define DWC_OTG_MSK_DOEP_FIFO_EMPTY (1U << 4)
228 #define DWC_OTG_MSK_DOEP_XFER_COMPLETE (1U << 0)
230 #define DWC_OTG_REG_DAINT 0x0818
231 #define DWC_OTG_REG_DAINTMSK 0x081C
233 #define DWC_OTG_MSK_ENDPOINT(x,in) \
234 ((in) ? (1U << ((x) & 15U)) : \
235 (0x10000U << ((x) & 15U)))
237 #define DWC_OTG_REG_DTKNQR1 0x0820
238 #define DWC_OTG_REG_DTKNQR2 0x0824
239 #define DWC_OTG_REG_DTKNQR3 0x0830
240 #define DWC_OTG_REG_DTKNQR4 0x0834
241 #define DWC_OTG_REG_DVBUSDIS 0x0828
242 #define DWC_OTG_REG_DVBUSPULSE 0x082C
243 #define DWC_OTG_REG_DTHRCTL 0x0830
244 #define DWC_OTG_REG_DIEPEMPMSK 0x0834
245 #define DWC_OTG_REG_DEACHINT 0x0838
246 #define DWC_OTG_REG_DEACHINTMSK 0x083C
247 #define DWC_OTG_REG_DIEPEACHMSK(n) (0x0840 + (4*(n)))
248 #define DWC_OTG_MSK_DIEPEACH_XFER_COMPLETE (1U << 0)
250 #define DWC_OTG_REG_DOEPEACHMSK(n) (0x0880 + (4*(n)))
251 #define DWC_OTG_MSK_DOEPEACH_SETUP (1U << 3)
252 #define DWC_OTG_MSK_DOEPEACH_XFER_COMPLETE (1U << 0)
254 #define DWC_OTG_REG_DIEPCTL(n) (0x0900 + (32*(n)))
255 #define DWC_OTG_MSK_DIEPCTL_ENABLE (1U << 31)
256 #define DWC_OTG_MSK_DIEPCTL_DISABLE (1U << 30)
257 #define DWC_OTG_MSK_DIEPCTL_SET_DATA1 (1U << 29) /* non-control */
258 #define DWC_OTG_MSK_DIEPCTL_SET_DATA0 (1U << 28) /* non-control */
259 #define DWC_OTG_MSK_DIEPCTL_SET_NAK (1U << 27)
260 #define DWC_OTG_MSK_DIEPCTL_CLR_NAK (1U << 26)
261 #define DWC_OTG_MSK_DIEPCTL_FNUM(n) (((n) & 15U) << 22)
262 #define DWC_OTG_MSK_DIEPCTL_STALL (1U << 21)
263 #define DWC_OTG_MSK_EP_SET_TYPE(n) (((n) & 3) << 18)
264 #define DWC_OTG_MSK_EP_TYPE_CONTROL (0U)
265 #define DWC_OTG_MSK_EP_TYPE_ISOC (1U)
266 #define DWC_OTG_MSK_EP_TYPE_BULK (2U)
267 #define DWC_OTG_MSK_EP_TYPE_INTERRUPT (3U)
268 #define DWC_OTG_MSK_DIEPCTL_USB_AEP (1U << 15)
269 #define DWC_OTG_MSK_DIEPCTL_MPS_64 (0U << 0) /* control-only */
270 #define DWC_OTG_MSK_DIEPCTL_MPS_32 (1U << 0) /* control-only */
271 #define DWC_OTG_MSK_DIEPCTL_MPS_16 (2U << 0) /* control-only */
272 #define DWC_OTG_MSK_DIEPCTL_MPS_8 (3U << 0) /* control-only */
273 #define DWC_OTG_MSK_DIEPCTL_MPS(n) ((n) & 0x7FF) /* non-control */
275 #define DWC_OTG_REG_DIEPINT(n) (0x0908 + (32*(n)))
276 #define DWC_OTG_MSK_DXEPINT_TXFEMP (1U << 7)
277 #define DWC_OTG_MSK_DXEPINT_SETUP (1U << 3)
278 #define DWC_OTG_MSK_DXEPINT_XFER_COMPL (1U << 0)
280 #define DWC_OTG_REG_DIEPTSIZ(n) (0x0910 + (32*(n)))
281 #define DWC_OTG_MSK_DXEPTSIZ_SET_MULTI(n) (((n) & 3) << 29)
282 #define DWC_OTG_MSK_DXEPTSIZ_SET_NPKT(n) (((n) & 0x3FF) << 19)
283 #define DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(n) (((n) >> 19) & 0x3FF)
284 #define DWC_OTG_MSK_DXEPTSIZ_SET_NBYTES(n) (((n) & 0x7FFFFF) << 0)
285 #define DWC_OTG_MSK_DXEPTSIZ_GET_NBYTES(n) (((n) >> 0) & 0x7FFFFF)
287 #define DWC_OTG_REG_DIEPDMA(n) (0x0914 + (32*(n)))
288 #define DWC_OTG_REG_DTXFSTS(n) (0x0918 + (32*(n)))
289 #define DWC_OTG_REG_DIEPDMAB0 (0x091C + (32*(n)))
291 #define DWC_OTG_REG_DOEPCTL(n) (0x0B00 + (32*(n)))
292 #define DWC_OTG_MSK_DOEPCTL_ENABLE (1U << 31)
293 #define DWC_OTG_MSK_DOEPCTL_DISABLE (1U << 30)
294 #define DWC_OTG_MSK_DOEPCTL_SET_DATA1 (1U << 29) /* non-control */
295 #define DWC_OTG_MSK_DOEPCTL_SET_DATA0 (1U << 28) /* non-control */
296 #define DWC_OTG_MSK_DOEPCTL_SET_NAK (1U << 27)
297 #define DWC_OTG_MSK_DOEPCTL_CLR_NAK (1U << 26)
298 #define DWC_OTG_MSK_DOEPCTL_FNUM(n) (((n) & 15U) << 22)
299 #define DWC_OTG_MSK_DOEPCTL_STALL (1U << 21)
300 #define DWC_OTG_MSK_DOEPCTL_EP_TYPE(n) (((n) & 3) << 18)
301 #define DWC_OTG_MSK_DOEPCTL_USB_AEP (1U << 15)
302 #define DWC_OTG_MSK_DOEPCTL_MPS_64 (0U << 0) /* control-only */
303 #define DWC_OTG_MSK_DOEPCTL_MPS_32 (1U << 0) /* control-only */
304 #define DWC_OTG_MSK_DOEPCTL_MPS_16 (2U << 0) /* control-only */
305 #define DWC_OTG_MSK_DOEPCTL_MPS_8 (3U << 0) /* control-only */
306 #define DWC_OTG_MSK_DOEPCTL_MPS(n) ((n) & 0x7FF) /* non-control */
308 #define DWC_OTG_REG_DOEPINT(n) (0x0B08 + (32*(n)))
309 #define DWC_OTG_REG_DOEPTSIZ(n) (0x0B10 + (32*(n)))
310 #define DWC_OTG_REG_DOEPDMA(n) (0x0B14 + (32*(n)))
311 #define DWC_OTG_REG_DOEPDMAB(n) (0x0B1C + (32*(n)))
313 /* FIFO access registers */
315 #define DWC_OTG_REG_DFIFO(n) (0x1000 + (0x1000 * (n)))
317 /* Power and clock gating CSR */
319 #define DWC_OTG_REG_PCGCCTL 0x0E00
321 #define DWC_OTG_READ_4(sc, reg) \
322 bus_space_read_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
324 #define DWC_OTG_WRITE_4(sc, reg, data) \
325 bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
328 struct dwc_otg_softc;
330 typedef uint8_t (dwc_otg_cmd_t)(struct dwc_otg_td *td);
333 struct dwc_otg_td *obj_next;
335 struct usb_page_cache *pc;
339 uint16_t max_packet_size; /* packet_size */
348 struct dwc_otg_std_temp {
350 struct usb_page_cache *pc;
351 struct dwc_otg_td *td;
352 struct dwc_otg_td *td_next;
355 uint16_t max_frame_size;
358 * short_pkt = 0: transfer should be short terminated
359 * short_pkt = 1: transfer should not be short terminated
361 uint8_t setup_alt_next;
363 uint8_t bulk_or_control;
366 struct dwc_otg_config_desc {
367 struct usb_config_descriptor confd;
368 struct usb_interface_descriptor ifcd;
369 struct usb_endpoint_descriptor endpd;
372 union dwc_otg_hub_temp {
374 struct usb_port_status ps;
377 struct dwc_otg_flags {
378 uint8_t change_connect:1;
379 uint8_t change_suspend:1;
380 uint8_t status_suspend:1; /* set if suspended */
381 uint8_t status_vbus:1; /* set if present */
382 uint8_t status_bus_reset:1; /* set if reset complete */
383 uint8_t status_high_speed:1; /* set if High Speed is selected */
384 uint8_t remote_wakeup:1;
385 uint8_t self_powered:1;
386 uint8_t clocks_off:1;
387 uint8_t port_powered:1;
388 uint8_t port_enabled:1;
389 uint8_t d_pulled_up:1;
392 struct dwc_otg_profile {
393 struct usb_hw_ep_profile usb;
397 struct dwc_otg_softc {
398 struct usb_bus sc_bus;
399 union dwc_otg_hub_temp sc_hub_temp;
400 struct dwc_otg_profile sc_hw_ep_profile[16];
402 struct usb_device *sc_devices[DWC_OTG_MAX_DEVICES];
403 struct resource *sc_io_res;
404 struct resource *sc_irq_res;
406 bus_size_t sc_io_size;
407 bus_space_tag_t sc_io_tag;
408 bus_space_handle_t sc_io_hdl;
410 uint32_t sc_rx_bounce_buffer[1024 / 4];
411 uint32_t sc_tx_bounce_buffer[(512 * DWC_OTG_MAX_TXP) / 4];
413 uint32_t sc_fifo_size;
414 uint32_t sc_irq_mask;
415 uint32_t sc_last_rx_status;
416 uint32_t sc_out_ctl[16];
417 uint32_t sc_in_ctl[16];
419 uint16_t sc_active_out_ep;
421 uint8_t sc_dev_ep_max;
422 uint8_t sc_dev_in_ep_max;
423 uint8_t sc_rt_addr; /* root HUB address */
424 uint8_t sc_conf; /* root HUB config */
426 uint8_t sc_hub_idata[1];
428 struct dwc_otg_flags sc_flags;
433 void dwc_otg_interrupt(struct dwc_otg_softc *);
434 int dwc_otg_init(struct dwc_otg_softc *);
435 void dwc_otg_uninit(struct dwc_otg_softc *);
437 #endif /* _DWC_OTG_H_ */