2 * Copyright (c) 1990 The Regents of the University of California.
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
37 * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38 * $DragonFly: src/sys/platform/pc32/isa/clock.c,v 1.9 2004/01/07 20:21:20 dillon Exp $
42 * Routines to handle clock hardware.
46 * inittodr, settodr and support routines written
47 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
49 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
54 #include "opt_clock.h"
56 #include <sys/param.h>
57 #include <sys/systm.h>
59 #include <sys/kernel.h>
63 #include <sys/sysctl.h>
66 #include <machine/clock.h>
67 #ifdef CLK_CALIBRATION_LOOP
69 #include <machine/cputypes.h>
70 #include <machine/frame.h>
71 #include <machine/ipl.h>
72 #include <machine/limits.h>
73 #include <machine/md_var.h>
74 #include <machine/psl.h>
76 #include <machine/segments.h>
78 #if defined(SMP) || defined(APIC_IO)
79 #include <machine/smp.h>
80 #endif /* SMP || APIC_IO */
81 #include <machine/specialreg.h>
83 #include <i386/isa/icu.h>
84 #include <bus/isa/i386/isa.h>
85 #include <bus/isa/rtc.h>
86 #include <i386/isa/timerreg.h>
88 #include <i386/isa/intr_machdep.h>
91 #include <bus/mca/i386/mca_machdep.h>
95 #include <i386/isa/intr_machdep.h>
96 /* The interrupt triggered by the 8254 (timer) chip */
98 static u_long read_intr_count (int vec);
99 static void setup_8254_mixed_mode (void);
103 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
104 * can use a simple formula for leap years.
106 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
107 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
109 #define TIMER_DIV(x) (timer_freq / (x))
110 #define FRAC_ADJUST(x) (timer_freq - ((timer_freq / (x)) * (x)))
113 * Time in timer cycles that it takes for microtime() to disable interrupts
114 * and latch the count. microtime() currently uses "cli; outb ..." so it
115 * normally takes less than 2 timer cycles. Add a few for cache misses.
116 * Add a few more to allow for latency in bogus calls to microtime() with
117 * interrupts already disabled.
119 #define TIMER0_LATCH_COUNT 20
122 * Maximum frequency that we are willing to allow for timer0. Must be
123 * low enough to guarantee that the timer interrupt handler returns
124 * before the next timer interrupt.
126 #define TIMER0_MAX_FREQ 20000
128 int adjkerntz; /* local offset from GMT in seconds */
130 int disable_rtc_set; /* disable resettodr() if != 0 */
131 volatile u_int idelayed;
132 int statclock_disable;
133 u_int stat_imask = SWI_CLOCK_MASK;
135 #define TIMER_FREQ 1193182
137 u_int timer_freq = TIMER_FREQ;
138 int timer0_max_count;
139 int timer0_frac_adjust;
140 int timer0_frac_accum; /* fractional adjustments to match frequency */
141 u_int timer0_frac_freq;
144 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
146 static int beeping = 0;
147 static u_int clk_imask = HWI_MASK | SWI_MASK;
148 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
149 static u_int hardclock_max_count;
150 static u_int32_t i8254_lastcount;
151 static u_int32_t i8254_offset;
152 static int i8254_ticked;
154 * XXX new_function and timer_func should not handle clockframes, but
155 * timer_func currently needs to hold hardclock to handle the
156 * timer0_state == 0 case. We should use inthand_add()/inthand_remove()
157 * to switch between clkintr() and a slightly different timerintr().
159 static void (*new_function) (struct clockframe *frame);
160 static u_int new_rate;
161 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
162 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
163 static u_int timer0_prescaler_count;
165 /* Values for timerX_state: */
167 #define RELEASE_PENDING 1
169 #define ACQUIRE_PENDING 3
171 static u_char timer0_state;
172 static u_char timer2_state;
173 static void (*timer_func) (struct clockframe *frame) = hardclock;
174 static u_int tsc_present;
176 static unsigned i8254_get_timecount (struct timecounter *tc);
177 static unsigned tsc_get_timecount (struct timecounter *tc);
178 static void set_timer_freq(u_int freq, int intr_freq);
180 static struct timecounter tsc_timecounter = {
181 tsc_get_timecount, /* get_timecount */
183 ~0u, /* counter_mask */
188 SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD,
189 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", "");
191 static struct timecounter i8254_timecounter = {
192 i8254_get_timecount, /* get_timecount */
194 ~0u, /* counter_mask */
199 SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD,
200 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", "");
203 clkintr(struct clockframe frame)
205 if (timecounter->tc_get_timecount == i8254_get_timecount) {
210 i8254_offset += timer0_max_count;
214 * Lets say we are running at 100Hz. Our counter load will
215 * be 1193182 / 100 = 11931.82, which is really only 11931.
216 * The fractional code accounts for the .82 count. When it
217 * exceeds 1.00 count we adjust the reload register by + 1
218 * to compensate for the error. We must also adjust
221 * If we did not do this a high frequency would cause the
222 * actual interrupt rate to seriously diverge from 'hz'.
224 timer0_frac_accum += timer0_frac_adjust;
225 if (timer0_frac_accum >= timer0_frac_freq) {
226 timer0_frac_accum -= timer0_frac_freq;
227 outb(TIMER_CNTR0, (timer0_max_count + 1) & 0xff);
228 outb(TIMER_CNTR0, (timer0_max_count + 1) >> 8);
231 outb(TIMER_CNTR0, timer0_max_count & 0xff);
232 outb(TIMER_CNTR0, timer0_max_count >> 8);
240 switch (timer0_state) {
245 timer0_prescaler_count += timer0_max_count;
246 if (timer0_prescaler_count >= hardclock_max_count) {
247 timer0_prescaler_count -= hardclock_max_count;
252 case ACQUIRE_PENDING:
254 i8254_offset = i8254_get_timecount(NULL);
256 timer0_max_count = TIMER_DIV(new_rate);
257 timer0_frac_adjust = FRAC_ADJUST(new_rate);
258 timer0_frac_freq = new_rate;
259 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
260 outb(TIMER_CNTR0, timer0_max_count & 0xff);
261 outb(TIMER_CNTR0, timer0_max_count >> 8);
263 timer_func = new_function;
264 timer0_state = ACQUIRED;
267 case RELEASE_PENDING:
268 timer0_prescaler_count += timer0_max_count;
269 if (timer0_prescaler_count >= hardclock_max_count) {
271 i8254_offset = i8254_get_timecount(NULL);
273 timer0_max_count = hardclock_max_count;
275 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
276 outb(TIMER_CNTR0, timer0_max_count & 0xff);
277 outb(TIMER_CNTR0, timer0_max_count >> 8);
279 timer0_prescaler_count = 0;
280 timer_func = hardclock;
281 timer0_state = RELEASED;
288 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
290 outb(0x61, inb(0x61) | 0x80);
295 * The acquire and release functions must be called at ipl >= splclock().
298 acquire_timer0(int rate, void (*function) (struct clockframe *frame))
302 if (rate <= 0 || rate > TIMER0_MAX_FREQ)
304 switch (timer0_state) {
307 timer0_state = ACQUIRE_PENDING;
310 case RELEASE_PENDING:
311 if (rate != old_rate)
314 * The timer has been released recently, but is being
315 * re-acquired before the release completed. In this
316 * case, we simply reclaim it as if it had not been
319 timer0_state = ACQUIRED;
323 return (-1); /* busy */
325 new_function = function;
326 old_rate = new_rate = rate;
331 acquire_timer2(int mode)
334 if (timer2_state != RELEASED)
336 timer2_state = ACQUIRED;
339 * This access to the timer registers is as atomic as possible
340 * because it is a single instruction. We could do better if we
341 * knew the rate. Use of splclock() limits glitches to 10-100us,
342 * and this is probably good enough for timer2, so we aren't as
343 * careful with it as with timer0.
345 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
353 switch (timer0_state) {
356 timer0_state = RELEASE_PENDING;
359 case ACQUIRE_PENDING:
360 /* Nothing happened yet, release quickly. */
361 timer0_state = RELEASED;
374 if (timer2_state != ACQUIRED)
376 timer2_state = RELEASED;
377 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
382 * This routine receives statistical clock interrupts from the RTC.
383 * As explained above, these occur at 128 interrupts per second.
384 * When profiling, we receive interrupts at a rate of 1024 Hz.
386 * This does not actually add as much overhead as it sounds, because
387 * when the statistical clock is active, the hardclock driver no longer
388 * needs to keep (inaccurate) statistics on its own. This decouples
389 * statistics gathering from scheduling interrupts.
391 * The RTC chip requires that we read status register C (RTC_INTR)
392 * to acknowledge an interrupt, before it will generate the next one.
393 * Under high interrupt load, rtcintr() can be indefinitely delayed and
394 * the clock can tick immediately after the read from RTC_INTR. In this
395 * case, the mc146818A interrupt signal will not drop for long enough
396 * to register with the 8259 PIC. If an interrupt is missed, the stat
397 * clock will halt, considerably degrading system performance. This is
398 * why we use 'while' rather than a more straightforward 'if' below.
399 * Stat clock ticks can still be lost, causing minor loss of accuracy
400 * in the statistics, but the stat clock will no longer stop.
403 rtcintr(struct clockframe frame)
405 while (rtcin(RTC_INTR) & RTCIR_PERIOD)
413 DB_SHOW_COMMAND(rtc, rtc)
415 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
416 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
417 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
418 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
429 /* Select timer0 and latch counter value. */
430 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
432 low = inb(TIMER_CNTR0);
433 high = inb(TIMER_CNTR0);
436 return ((high << 8) | low);
440 * Wait "n" microseconds.
441 * Relies on timer 1 counting down from (timer_freq / hz)
442 * Note: timer had better have been programmed before this is first used!
447 int delta, prev_tick, tick, ticks_left;
452 static int state = 0;
456 for (n1 = 1; n1 <= 10000000; n1 *= 10)
461 printf("DELAY(%d)...", n);
464 * Guard against the timer being uninitialized if we are called
465 * early for console i/o.
467 if (timer0_max_count == 0)
468 set_timer_freq(timer_freq, hz);
471 * Read the counter first, so that the rest of the setup overhead is
472 * counted. Guess the initial overhead is 20 usec (on most systems it
473 * takes about 1.5 usec for each of the i/o's in getit(). The loop
474 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
475 * multiplications and divisions to scale the count take a while).
478 n -= 0; /* XXX actually guess no initial overhead */
480 * Calculate (n * (timer_freq / 1e6)) without using floating point
481 * and without any avoidable overflows.
487 * Use fixed point to avoid a slow division by 1000000.
488 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
489 * 2^15 is the first power of 2 that gives exact results
490 * for n between 0 and 256.
492 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
495 * Don't bother using fixed point, although gcc-2.7.2
496 * generates particularly poor code for the long long
497 * division, since even the slow way will complete long
498 * before the delay is up (unless we're interrupted).
500 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
503 while (ticks_left > 0) {
508 delta = prev_tick - tick;
511 delta += timer0_max_count;
513 * Guard against timer0_max_count being wrong.
514 * This shouldn't happen in normal operation,
515 * but it may happen if set_timer_freq() is
525 printf(" %d calls to getit() at %d usec each\n",
526 getit_calls, (n + 5) / getit_calls);
531 sysbeepstop(void *chan)
533 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
539 sysbeep(int pitch, int period)
543 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
545 /* Something else owns it. */
547 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
550 outb(TIMER_CNTR2, pitch);
551 outb(TIMER_CNTR2, (pitch>>8));
554 /* enable counter2 output to speaker */
555 outb(IO_PPI, inb(IO_PPI) | 3);
557 timeout(sysbeepstop, (void *)NULL, period);
564 * RTC support routines
577 val = inb(IO_RTC + 1);
584 writertc(u_char reg, u_char val)
592 outb(IO_RTC + 1, val);
593 inb(0x84); /* XXX work around wrong order in rtcin() */
600 return(bcd2bin(rtcin(port)));
604 calibrate_clocks(void)
607 u_int count, prev_count, tot_count;
608 int sec, start_sec, timeout;
611 printf("Calibrating clock(s) ... ");
612 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
616 /* Read the mc146818A seconds counter. */
618 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
619 sec = rtcin(RTC_SEC);
626 /* Wait for the mC146818A seconds counter to change. */
629 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
630 sec = rtcin(RTC_SEC);
631 if (sec != start_sec)
638 /* Start keeping track of the i8254 counter. */
639 prev_count = getit();
640 if (prev_count == 0 || prev_count > timer0_max_count)
647 old_tsc = 0; /* shut up gcc */
650 * Wait for the mc146818A seconds counter to change. Read the i8254
651 * counter for each iteration since this is convenient and only
652 * costs a few usec of inaccuracy. The timing of the final reads
653 * of the counters almost matches the timing of the initial reads,
654 * so the main cause of inaccuracy is the varying latency from
655 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
656 * rtcin(RTC_SEC) that returns a changed seconds count. The
657 * maximum inaccuracy from this cause is < 10 usec on 486's.
661 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
662 sec = rtcin(RTC_SEC);
664 if (count == 0 || count > timer0_max_count)
666 if (count > prev_count)
667 tot_count += prev_count - (count - timer0_max_count);
669 tot_count += prev_count - count;
671 if (sec != start_sec)
678 * Read the cpu cycle counter. The timing considerations are
679 * similar to those for the i8254 clock.
682 tsc_freq = rdtsc() - old_tsc;
686 printf("TSC clock: %u Hz, ", tsc_freq);
687 printf("i8254 clock: %u Hz\n", tot_count);
693 printf("failed, using default i8254 clock of %u Hz\n",
699 set_timer_freq(u_int freq, int intr_freq)
701 int new_timer0_max_count;
705 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
706 timer0_frac_adjust = FRAC_ADJUST(intr_freq);
707 timer0_frac_freq = intr_freq;
708 if (new_timer0_max_count != timer0_max_count) {
709 timer0_max_count = new_timer0_max_count;
710 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
711 outb(TIMER_CNTR0, timer0_max_count & 0xff);
712 outb(TIMER_CNTR0, timer0_max_count >> 8);
721 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
722 outb(TIMER_CNTR0, timer0_max_count & 0xff);
723 outb(TIMER_CNTR0, timer0_max_count >> 8);
731 /* Restore all of the RTC's "status" (actually, control) registers. */
732 writertc(RTC_STATUSB, RTCSB_24HR);
733 writertc(RTC_STATUSA, rtc_statusa);
734 writertc(RTC_STATUSB, rtc_statusb);
738 * Restore all the timers non-atomically (XXX: should be atomically).
740 * This function is called from apm_default_resume() to restore all the timers.
741 * This should not be necessary, but there are broken laptops that do not
742 * restore all the timers on resume.
748 i8254_restore(); /* restore timer_freq and hz */
749 rtc_restore(); /* reenable RTC interrupts */
753 * Initialize 8254 timer 0 early so that it can be used in DELAY().
754 * XXX initialization of other timers is unintentionally left blank.
761 if (cpu_feature & CPUID_TSC)
766 writertc(RTC_STATUSA, rtc_statusa);
767 writertc(RTC_STATUSB, RTCSB_24HR);
769 set_timer_freq(timer_freq, hz);
770 freq = calibrate_clocks();
771 #ifdef CLK_CALIBRATION_LOOP
774 "Press a key on the console to abort clock calibration\n");
775 while (cncheckc() == -1)
781 * Use the calibrated i8254 frequency if it seems reasonable.
782 * Otherwise use the default, and don't use the calibrated i586
785 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
786 if (delta < timer_freq / 100) {
787 #ifndef CLK_USE_I8254_CALIBRATION
790 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
797 "%d Hz differs from default of %d Hz by more than 1%%\n",
802 set_timer_freq(timer_freq, hz);
803 i8254_timecounter.tc_frequency = timer_freq;
804 init_timecounter(&i8254_timecounter);
806 #ifndef CLK_USE_TSC_CALIBRATION
810 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
814 if (tsc_present && tsc_freq == 0) {
816 * Calibration of the i586 clock relative to the mc146818A
817 * clock failed. Do a less accurate calibration relative
818 * to the i8254 clock.
820 u_int64_t old_tsc = rdtsc();
823 tsc_freq = rdtsc() - old_tsc;
824 #ifdef CLK_USE_TSC_CALIBRATION
826 printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
832 * We can not use the TSC in SMP mode, until we figure out a
833 * cheap (impossible), reliable and precise (yeah right!) way
834 * to synchronize the TSCs of all the CPUs.
835 * Curse Intel for leaving the counter out of the I/O APIC.
840 * We can not use the TSC if we support APM. Precise timekeeping
841 * on an APM'ed machine is at best a fools pursuit, since
842 * any and all of the time spent in various SMM code can't
843 * be reliably accounted for. Reading the RTC is your only
844 * source of reliable time info. The i8254 looses too of course
845 * but we need to have some kind of time...
846 * We don't know at this point whether APM is going to be used
847 * or not, nor when it might be activated. Play it safe.
850 #endif /* NAPM > 0 */
852 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
853 tsc_timecounter.tc_frequency = tsc_freq;
854 init_timecounter(&tsc_timecounter);
857 #endif /* !defined(SMP) */
861 * Initialize the time of day register, based on the time base which is, e.g.
865 inittodr(time_t base)
867 unsigned long sec, days;
877 set_timecounter(&ts);
881 /* Look if we have a RTC present and the time is valid */
882 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
885 /* wait for time update to complete */
886 /* If RTCSA_TUP is zero, we have at least 244us before next update */
888 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
894 #ifdef USE_RTC_CENTURY
895 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
897 year = readrtc(RTC_YEAR) + 1900;
905 month = readrtc(RTC_MONTH);
906 for (m = 1; m < month; m++)
907 days += daysinmonth[m-1];
908 if ((month > 2) && LEAPYEAR(year))
910 days += readrtc(RTC_DAY) - 1;
912 for (y = 1970; y < year; y++)
913 days += DAYSPERYEAR + LEAPYEAR(y);
914 sec = ((( days * 24 +
915 readrtc(RTC_HRS)) * 60 +
916 readrtc(RTC_MIN)) * 60 +
918 /* sec now contains the number of seconds, since Jan 1 1970,
919 in the local time zone */
921 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
923 y = time_second - sec;
924 if (y <= -2 || y >= 2) {
925 /* badly off, adjust it */
928 set_timecounter(&ts);
934 printf("Invalid time in real time clock.\n");
935 printf("Check and reset the date immediately!\n");
939 * Write system time back to RTC
954 /* Disable RTC updates and interrupts. */
955 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
957 /* Calculate local time to put in RTC */
959 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
961 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
962 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
963 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
965 /* We have now the days since 01-01-1970 in tm */
966 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */
967 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
969 y++, m = DAYSPERYEAR + LEAPYEAR(y))
972 /* Now we have the years in y and the day-of-the-year in tm */
973 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
974 #ifdef USE_RTC_CENTURY
975 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
981 if (m == 1 && LEAPYEAR(y))
988 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
989 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
991 /* Reenable RTC updates and interrupts. */
992 writertc(RTC_STATUSB, rtc_statusb);
997 * Start both clocks running.
1004 int apic_8254_trial;
1005 struct intrec *clkdesc;
1006 #endif /* APIC_IO */
1008 if (statclock_disable) {
1010 * The stat interrupt mask is different without the
1011 * statistics clock. Also, don't set the interrupt
1012 * flag which would normally cause the RTC to generate
1015 stat_imask = HWI_MASK | SWI_MASK;
1016 rtc_statusb = RTCSB_24HR;
1018 /* Setting stathz to nonzero early helps avoid races. */
1019 stathz = RTC_NOPROFRATE;
1020 profhz = RTC_PROFRATE;
1023 /* Finish initializing 8253 timer 0. */
1026 apic_8254_intr = isa_apic_irq(0);
1027 apic_8254_trial = 0;
1028 if (apic_8254_intr >= 0 ) {
1029 if (apic_int_type(0, 0) == 3)
1030 apic_8254_trial = 1;
1032 /* look for ExtInt on pin 0 */
1033 if (apic_int_type(0, 0) == 3) {
1034 apic_8254_intr = apic_irq(0, 0);
1035 setup_8254_mixed_mode();
1037 panic("APIC_IO: Cannot route 8254 interrupt to CPU");
1040 clkdesc = inthand_add("clk", apic_8254_intr, (inthand2_t *)clkintr,
1041 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
1042 INTREN(1 << apic_8254_intr);
1046 inthand_add("clk", 0, (inthand2_t *)clkintr, NULL, &clk_imask,
1047 INTR_EXCL | INTR_FAST);
1050 #endif /* APIC_IO */
1052 /* Initialize RTC. */
1053 writertc(RTC_STATUSA, rtc_statusa);
1054 writertc(RTC_STATUSB, RTCSB_24HR);
1056 /* Don't bother enabling the statistics clock. */
1057 if (statclock_disable)
1059 diag = rtcin(RTC_DIAG);
1061 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
1064 if (isa_apic_irq(8) != 8)
1065 panic("APIC RTC != 8");
1066 #endif /* APIC_IO */
1068 inthand_add("rtc", 8, (inthand2_t *)rtcintr, NULL, &stat_imask,
1069 INTR_EXCL | INTR_FAST);
1075 #endif /* APIC_IO */
1077 writertc(RTC_STATUSB, rtc_statusb);
1080 if (apic_8254_trial) {
1082 printf("APIC_IO: Testing 8254 interrupt delivery\n");
1083 while (read_intr_count(8) < 6)
1085 if (read_intr_count(apic_8254_intr) < 3) {
1087 * The MP table is broken.
1088 * The 8254 was not connected to the specified pin
1090 * Workaround: Limited variant of mixed mode.
1092 INTRDIS(1 << apic_8254_intr);
1093 inthand_remove(clkdesc);
1094 printf("APIC_IO: Broken MP table detected: "
1095 "8254 is not connected to "
1096 "IOAPIC #%d intpin %d\n",
1097 int_to_apicintpin[apic_8254_intr].ioapic,
1098 int_to_apicintpin[apic_8254_intr].int_pin);
1100 * Revoke current ISA IRQ 0 assignment and
1101 * configure a fallback interrupt routing from
1102 * the 8254 Timer via the 8259 PIC to the
1103 * an ExtInt interrupt line on IOAPIC #0 intpin 0.
1104 * We reuse the low level interrupt handler number.
1106 if (apic_irq(0, 0) < 0) {
1107 revoke_apic_irq(apic_8254_intr);
1108 assign_apic_irq(0, 0, apic_8254_intr);
1110 apic_8254_intr = apic_irq(0, 0);
1111 setup_8254_mixed_mode();
1112 inthand_add("clk", apic_8254_intr,
1113 (inthand2_t *)clkintr,
1114 NULL, &clk_imask, INTR_EXCL | INTR_FAST);
1115 INTREN(1 << apic_8254_intr);
1119 if (apic_int_type(0, 0) != 3 ||
1120 int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
1121 int_to_apicintpin[apic_8254_intr].int_pin != 0)
1122 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
1123 int_to_apicintpin[apic_8254_intr].ioapic,
1124 int_to_apicintpin[apic_8254_intr].int_pin);
1127 "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
1134 read_intr_count(int vec)
1137 up = intr_countp[vec];
1144 setup_8254_mixed_mode()
1147 * Allow 8254 timer to INTerrupt 8259:
1148 * re-initialize master 8259:
1149 * reset; prog 4 bytes, single ICU, edge triggered
1151 outb(IO_ICU1, 0x13);
1152 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */
1153 outb(IO_ICU1 + 1, 0x00); /* ignore slave */
1154 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */
1155 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */
1157 /* program IO APIC for type 3 INT on INT0 */
1158 if (ext_int_setup(0, 0) < 0)
1159 panic("8254 redirect via APIC pin0 impossible!");
1164 setstatclockrate(int newhz)
1166 if (newhz == RTC_PROFRATE)
1167 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1169 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1170 writertc(RTC_STATUSA, rtc_statusa);
1174 sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
1180 * Use `i8254' instead of `timer' in external names because `timer'
1181 * is is too generic. Should use it everywhere.
1184 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1185 if (error == 0 && req->newptr != NULL) {
1186 if (timer0_state != RELEASED)
1187 return (EBUSY); /* too much trouble to handle */
1188 set_timer_freq(freq, hz);
1189 i8254_timecounter.tc_frequency = freq;
1190 update_timecounter(&i8254_timecounter);
1195 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
1196 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", "");
1199 sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
1204 if (tsc_timecounter.tc_frequency == 0)
1205 return (EOPNOTSUPP);
1207 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
1208 if (error == 0 && req->newptr != NULL) {
1210 tsc_timecounter.tc_frequency = tsc_freq;
1211 update_timecounter(&tsc_timecounter);
1216 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW,
1217 0, sizeof(u_int), sysctl_machdep_tsc_freq, "IU", "");
1220 i8254_get_timecount(struct timecounter *tc)
1230 * Select timer0 and latch counter value. Because we may reload
1231 * the counter with timer0_max_count + 1 to correct the frequency
1232 * our delta count calculation must use timer0_max_count + 1.
1234 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
1236 low = inb(TIMER_CNTR0);
1237 high = inb(TIMER_CNTR0);
1238 count = timer0_max_count + 1 - ((high << 8) | low);
1239 if (count < i8254_lastcount ||
1240 (!i8254_ticked && (clkintr_pending ||
1241 ((count < 20 || (!(ef & PSL_I) && count < timer0_max_count / 2u)) &&
1243 #define lapic_irr1 ((volatile u_int *)&lapic)[0x210 / 4] /* XXX XXX */
1244 /* XXX this assumes that apic_8254_intr is < 24. */
1245 (lapic_irr1 & (1 << apic_8254_intr))))
1247 (inb(IO_ICU1) & 1)))
1251 i8254_offset += timer0_max_count;
1253 i8254_lastcount = count;
1254 count += i8254_offset;
1260 tsc_get_timecount(struct timecounter *tc)
1265 #ifdef KERN_TIMESTAMP
1266 #define KERN_TIMESTAMP_SIZE 16384
1267 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1268 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1269 sizeof(tsc), "LU", "Kernel timestamps");
1275 tsc[i] = (u_int32_t)rdtsc();
1278 if (i >= KERN_TIMESTAMP_SIZE)
1280 tsc[i] = 0; /* mark last entry */
1282 #endif /* KERN_TIMESTAMP */