2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1993 The Regents of the University of California.
4 * Copyright (c) 2008 The DragonFly Project.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the University of
18 * California, Berkeley and its contributors.
19 * 4. Neither the name of the University nor the names of its contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * $FreeBSD: src/sys/amd64/include/cpufunc.h,v 1.139 2004/01/28 23:53:04 peter Exp $
39 * Functions to provide access to special i386 instructions.
40 * This in included in sys/systm.h, and that file should be
41 * used in preference to this.
44 #ifndef _CPU_CPUFUNC_H_
45 #define _CPU_CPUFUNC_H_
47 #include <sys/cdefs.h>
48 #include <sys/thread.h>
49 #include <machine/psl.h>
50 #include <machine/smp.h>
53 struct region_descriptor;
56 #define readb(va) (*(volatile u_int8_t *) (va))
57 #define readw(va) (*(volatile u_int16_t *) (va))
58 #define readl(va) (*(volatile u_int32_t *) (va))
59 #define readq(va) (*(volatile u_int64_t *) (va))
61 #define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
62 #define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
63 #define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
64 #define writeq(va, d) (*(volatile u_int64_t *) (va) = (d))
68 #include <machine/lock.h> /* XXX */
73 __asm __volatile("int $3");
79 __asm __volatile("pause":::"memory");
87 __asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
91 static __inline u_long
96 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
100 static __inline u_long
105 __asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
109 static __inline u_int
114 __asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
118 static __inline u_long
123 __asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
130 __asm __volatile("clflush %0" : : "m" (*(char *) addr));
134 do_cpuid(u_int ax, u_int *p)
136 __asm __volatile("cpuid"
137 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
142 cpuid_count(u_int ax, u_int cx, u_int *p)
144 __asm __volatile("cpuid"
145 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
146 : "0" (ax), "c" (cx));
149 #ifndef _CPU_DISABLE_INTR_DEFINED
152 cpu_disable_intr(void)
154 __asm __volatile("cli" : : : "memory");
159 #ifndef _CPU_ENABLE_INTR_DEFINED
162 cpu_enable_intr(void)
164 __asm __volatile("sti");
170 * Cpu and compiler memory ordering fence. mfence ensures strong read and
173 * A serializing or fence instruction is required here. A locked bus
174 * cycle on data for which we already own cache mastership is the most
180 __asm __volatile("mfence" : : : "memory");
184 * cpu_lfence() ensures strong read ordering for reads issued prior
185 * to the instruction verses reads issued afterwords.
187 * A serializing or fence instruction is required here. A locked bus
188 * cycle on data for which we already own cache mastership is the most
194 __asm __volatile("lfence" : : : "memory");
198 * cpu_sfence() ensures strong write ordering for writes issued prior
199 * to the instruction verses writes issued afterwords. Writes are
200 * ordered on intel cpus so we do not actually have to do anything.
207 * Don't use 'sfence' here, as it will create a lot of
208 * unnecessary stalls.
210 __asm __volatile("" : : : "memory");
214 * cpu_ccfence() prevents the compiler from reordering instructions, in
215 * particular stores, relative to the current cpu. Use cpu_sfence() if
216 * you need to guarentee ordering by both the compiler and by the cpu.
218 * This also prevents the compiler from caching memory loads into local
219 * variables across the routine.
224 __asm __volatile("" : : : "memory");
228 * This is a horrible, horrible hack that might have to be put at the
229 * end of certain procedures (on a case by case basis), just before it
230 * returns to avoid what we believe to be an unreported AMD cpu bug.
231 * Found to occur on both a Phenom II X4 820 (two of them), as well
232 * as a 48-core built around an Opteron 6168 (Id = 0x100f91 Stepping = 1).
233 * The problem does not appear to occur w/Intel cpus.
235 * The bug is likely related to either a write combining issue or the
236 * Return Address Stack (RAS) hardware cache.
238 * In particular, we had to do this for GCC's fill_sons_in_loop() routine
239 * which due to its deep recursion and stack flow appears to be able to
240 * tickle the amd cpu bug (w/ gcc-4.4.7). Adding a single 'nop' to the
241 * end of the routine just before it returns works around the bug.
243 * The bug appears to be extremely sensitive to %rip and %rsp values, to
244 * the point where even just inserting an instruction in an unrelated
245 * procedure (shifting the entire code base being run) effects the outcome.
246 * DragonFly is probably able to more readily reproduce the bug due to
247 * the stackgap randomization code. We would expect OpenBSD (where we got
248 * the stackgap randomization code from) to also be able to reproduce the
249 * issue. To date we have only reproduced the issue in DragonFly.
251 #define __AMDCPUBUG_DFLY01_AVAILABLE__
254 cpu_amdcpubug_dfly01(void)
256 __asm __volatile("nop" : : : "memory");
261 #define HAVE_INLINE_FFS
268 * Note that gcc-2's builtin ffs would be used if we didn't declare
269 * this inline or turn off the builtin. The builtin is faster but
270 * broken in gcc-2.4.5 and slower but working in gcc-2.5 and later
273 return (mask == 0 ? mask : (int)bsfl((u_int)mask) + 1);
275 /* Actually, the above is way out of date. The builtins use cmov etc */
276 return (__builtin_ffs(mask));
280 #define HAVE_INLINE_FFSL
285 return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
288 #define HAVE_INLINE_FLS
293 return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
296 #define HAVE_INLINE_FLSL
301 return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
309 __asm __volatile("hlt");
313 * The following complications are to get around gcc not having a
314 * constraint letter for the range 0..255. We still put "d" in the
315 * constraint because "i" isn't a valid constraint when the port
316 * isn't constant. This only matters for -O0 because otherwise
317 * the non-working version gets optimized away.
319 * Use an expression-statement instead of a conditional expression
320 * because gcc-2.6.0 would promote the operands of the conditional
321 * and produce poor code for "if ((inb(var) & const1) == const2)".
323 * The unnecessary test `(port) < 0x10000' is to generate a warning if
324 * the `port' has type u_short or smaller. Such types are pessimal.
325 * This actually only works for signed types. The range check is
326 * careful to avoid generating warnings.
328 #define inb(port) __extension__ ({ \
330 if (__builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
331 && (port) < 0x10000) \
332 _data = inbc(port); \
334 _data = inbv(port); \
337 #define outb(port, data) ( \
338 __builtin_constant_p(port) && ((port) & 0xffff) < 0x100 \
339 && (port) < 0x10000 \
340 ? outbc(port, data) : outbv(port, data))
342 static __inline u_char
347 __asm __volatile("inb %1,%0" : "=a" (data) : "id" ((u_short)(port)));
352 outbc(u_int port, u_char data)
354 __asm __volatile("outb %0,%1" : : "a" (data), "id" ((u_short)(port)));
357 static __inline u_char
362 * We use %%dx and not %1 here because i/o is done at %dx and not at
363 * %edx, while gcc generates inferior code (movw instead of movl)
364 * if we tell it to load (u_short) port.
366 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
370 static __inline u_int
375 __asm __volatile("inl %%dx,%0" : "=a" (data) : "d" (port));
380 insb(u_int port, void *addr, size_t cnt)
382 __asm __volatile("cld; rep; insb"
383 : "+D" (addr), "+c" (cnt)
389 insw(u_int port, void *addr, size_t cnt)
391 __asm __volatile("cld; rep; insw"
392 : "+D" (addr), "+c" (cnt)
398 insl(u_int port, void *addr, size_t cnt)
400 __asm __volatile("cld; rep; insl"
401 : "+D" (addr), "+c" (cnt)
409 __asm __volatile("invd");
415 * If we are not a true-SMP box then smp_invltlb() is a NOP. Note that this
416 * will cause the invl*() functions to be equivalent to the cpu_invl*()
419 void smp_invltlb(void);
420 void smp_invltlb_intr(void);
422 #ifndef _CPU_INVLPG_DEFINED
425 * Invalidate a patricular VA on this cpu only
428 cpu_invlpg(void *addr)
430 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
438 __asm __volatile("rep; nop");
443 static __inline u_short
448 __asm __volatile("inw %%dx,%0" : "=a" (data) : "d" (port));
452 static __inline u_int
453 loadandclear(volatile u_int *addr)
457 __asm __volatile("xorl %0,%0; xchgl %1,%0"
458 : "=&r" (result) : "m" (*addr));
463 outbv(u_int port, u_char data)
467 * Use an unnecessary assignment to help gcc's register allocator.
468 * This make a large difference for gcc-1.40 and a tiny difference
469 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
470 * best results. gcc-2.6.0 can't handle this.
473 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
477 outl(u_int port, u_int data)
480 * outl() and outw() aren't used much so we haven't looked at
481 * possible micro-optimizations such as the unnecessary
482 * assignment for them.
484 __asm __volatile("outl %0,%%dx" : : "a" (data), "d" (port));
488 outsb(u_int port, const void *addr, size_t cnt)
490 __asm __volatile("cld; rep; outsb"
491 : "+S" (addr), "+c" (cnt)
496 outsw(u_int port, const void *addr, size_t cnt)
498 __asm __volatile("cld; rep; outsw"
499 : "+S" (addr), "+c" (cnt)
504 outsl(u_int port, const void *addr, size_t cnt)
506 __asm __volatile("cld; rep; outsl"
507 : "+S" (addr), "+c" (cnt)
512 outw(u_int port, u_short data)
514 __asm __volatile("outw %0,%%dx" : : "a" (data), "d" (port));
520 __asm __volatile("pause");
523 static __inline u_long
528 __asm __volatile("pushfq; popq %0" : "=r" (rf));
532 static __inline u_int64_t
537 __asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
538 return (low | ((u_int64_t)high << 32));
541 static __inline u_int64_t
546 __asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
547 return (low | ((u_int64_t)high << 32));
550 #define _RDTSC_SUPPORTED_
552 static __inline u_int64_t
557 __asm __volatile("rdtsc" : "=a" (low), "=d" (high));
558 return (low | ((u_int64_t)high << 32));
564 __asm __volatile("wbinvd");
568 void cpu_wbinvd_on_all_cpus_callback(void *arg);
571 cpu_wbinvd_on_all_cpus(void)
573 lwkt_cpusync_simple(smp_active_mask, cpu_wbinvd_on_all_cpus_callback, NULL);
578 write_rflags(u_long rf)
580 __asm __volatile("pushq %0; popfq" : : "r" (rf));
584 wrmsr(u_int msr, u_int64_t newval)
590 __asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
594 xsetbv(u_int ecx, u_int eax, u_int edx)
596 __asm __volatile(".byte 0x0f,0x01,0xd1"
598 : "a" (eax), "c" (ecx), "d" (edx));
602 load_cr0(u_long data)
605 __asm __volatile("movq %0,%%cr0" : : "r" (data));
608 static __inline u_long
613 __asm __volatile("movq %%cr0,%0" : "=r" (data));
617 static __inline u_long
622 __asm __volatile("movq %%cr2,%0" : "=r" (data));
627 load_cr3(u_long data)
630 __asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
633 static __inline u_long
638 __asm __volatile("movq %%cr3,%0" : "=r" (data));
643 load_cr4(u_long data)
645 __asm __volatile("movq %0,%%cr4" : : "r" (data));
648 static __inline u_long
653 __asm __volatile("movq %%cr4,%0" : "=r" (data));
657 #ifndef _CPU_INVLTLB_DEFINED
660 * Invalidate the TLB on this cpu only
666 #if defined(SWTCH_OPTIM_STATS)
674 * TLB flush for an individual page (even if it has PG_G).
675 * Only works on 486+ CPUs (i386 does not have PG_G).
681 __asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
684 static __inline u_short
688 __asm __volatile("movw %%fs,%0" : "=rm" (sel));
692 static __inline u_short
696 __asm __volatile("movw %%gs,%0" : "=rm" (sel));
703 __asm __volatile("movw %0,%%ds" : : "rm" (sel));
709 __asm __volatile("movw %0,%%es" : : "rm" (sel));
713 /* This is defined in <machine/specialreg.h> but is too painful to get to */
715 #define MSR_FSBASE 0xc0000100
720 /* Preserve the fsbase value across the selector load */
721 __asm __volatile("rdmsr; movw %0,%%fs; wrmsr"
722 : : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
726 #define MSR_GSBASE 0xc0000101
732 * Preserve the gsbase value across the selector load.
733 * Note that we have to disable interrupts because the gsbase
734 * being trashed happens to be the kernel gsbase at the time.
736 __asm __volatile("pushfq; cli; rdmsr; movw %0,%%gs; wrmsr; popfq"
737 : : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
740 /* Usable by userland */
744 __asm __volatile("movw %0,%%fs" : : "rm" (sel));
750 __asm __volatile("movw %0,%%gs" : : "rm" (sel));
754 /* void lidt(struct region_descriptor *addr); */
756 lidt(struct region_descriptor *addr)
758 __asm __volatile("lidt (%0)" : : "r" (addr));
761 /* void lldt(u_short sel); */
765 __asm __volatile("lldt %0" : : "r" (sel));
768 /* void ltr(u_short sel); */
772 __asm __volatile("ltr %0" : : "r" (sel));
775 static __inline u_int64_t
779 __asm __volatile("movq %%dr0,%0" : "=r" (data));
784 load_dr0(u_int64_t dr0)
786 __asm __volatile("movq %0,%%dr0" : : "r" (dr0));
789 static __inline u_int64_t
793 __asm __volatile("movq %%dr1,%0" : "=r" (data));
798 load_dr1(u_int64_t dr1)
800 __asm __volatile("movq %0,%%dr1" : : "r" (dr1));
803 static __inline u_int64_t
807 __asm __volatile("movq %%dr2,%0" : "=r" (data));
812 load_dr2(u_int64_t dr2)
814 __asm __volatile("movq %0,%%dr2" : : "r" (dr2));
817 static __inline u_int64_t
821 __asm __volatile("movq %%dr3,%0" : "=r" (data));
826 load_dr3(u_int64_t dr3)
828 __asm __volatile("movq %0,%%dr3" : : "r" (dr3));
831 static __inline u_int64_t
835 __asm __volatile("movq %%dr4,%0" : "=r" (data));
840 load_dr4(u_int64_t dr4)
842 __asm __volatile("movq %0,%%dr4" : : "r" (dr4));
845 static __inline u_int64_t
849 __asm __volatile("movq %%dr5,%0" : "=r" (data));
854 load_dr5(u_int64_t dr5)
856 __asm __volatile("movq %0,%%dr5" : : "r" (dr5));
859 static __inline u_int64_t
863 __asm __volatile("movq %%dr6,%0" : "=r" (data));
868 load_dr6(u_int64_t dr6)
870 __asm __volatile("movq %0,%%dr6" : : "r" (dr6));
873 static __inline u_int64_t
877 __asm __volatile("movq %%dr7,%0" : "=r" (data));
882 load_dr7(u_int64_t dr7)
884 __asm __volatile("movq %0,%%dr7" : : "r" (dr7));
887 static __inline register_t
892 rflags = read_rflags();
898 intr_restore(register_t rflags)
900 write_rflags(rflags);
903 #else /* !__GNUC__ */
905 int breakpoint(void);
906 void cpu_pause(void);
907 u_int bsfl(u_int mask);
908 u_int bsrl(u_int mask);
909 void cpu_disable_intr(void);
910 void cpu_enable_intr(void);
911 void cpu_invlpg(u_long addr);
912 void cpu_invlpg_range(u_long start, u_long end);
913 void do_cpuid(u_int ax, u_int *p);
915 u_char inb(u_int port);
916 u_int inl(u_int port);
917 void insb(u_int port, void *addr, size_t cnt);
918 void insl(u_int port, void *addr, size_t cnt);
919 void insw(u_int port, void *addr, size_t cnt);
921 void invlpg(u_int addr);
922 void invlpg_range(u_int start, u_int end);
923 void cpu_invltlb(void);
924 u_short inw(u_int port);
925 void load_cr0(u_int cr0);
926 void load_cr3(u_int cr3);
927 void load_cr4(u_int cr4);
928 void load_fs(u_int sel);
929 void load_gs(u_int sel);
930 struct region_descriptor;
931 void lidt(struct region_descriptor *addr);
932 void lldt(u_short sel);
933 void ltr(u_short sel);
934 void outb(u_int port, u_char data);
935 void outl(u_int port, u_int data);
936 void outsb(u_int port, void *addr, size_t cnt);
937 void outsl(u_int port, void *addr, size_t cnt);
938 void outsw(u_int port, void *addr, size_t cnt);
939 void outw(u_int port, u_short data);
940 void ia32_pause(void);
947 u_int64_t rdmsr(u_int msr);
948 u_int64_t rdpmc(u_int pmc);
949 u_int64_t rdtsc(void);
950 u_int read_rflags(void);
952 void write_rflags(u_int rf);
953 void wrmsr(u_int msr, u_int64_t newval);
954 u_int64_t rdr0(void);
955 void load_dr0(u_int64_t dr0);
956 u_int64_t rdr1(void);
957 void load_dr1(u_int64_t dr1);
958 u_int64_t rdr2(void);
959 void load_dr2(u_int64_t dr2);
960 u_int64_t rdr3(void);
961 void load_dr3(u_int64_t dr3);
962 u_int64_t rdr4(void);
963 void load_dr4(u_int64_t dr4);
964 u_int64_t rdr5(void);
965 void load_dr5(u_int64_t dr5);
966 u_int64_t rdr6(void);
967 void load_dr6(u_int64_t dr6);
968 u_int64_t rdr7(void);
969 void load_dr7(u_int64_t dr7);
970 register_t intr_disable(void);
971 void intr_restore(register_t rf);
973 #endif /* __GNUC__ */
975 int rdmsr_safe(u_int msr, uint64_t *val);
976 void reset_dbregs(void);
980 #endif /* !_CPU_CPUFUNC_H_ */