2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/if_ringmap.h>
95 #include <net/toeplitz.h>
96 #include <net/toeplitz2.h>
97 #include <net/vlan/if_vlan_var.h>
98 #include <net/vlan/if_vlan_ether.h>
99 #include <net/if_poll.h>
101 #include <netinet/in_systm.h>
102 #include <netinet/in.h>
103 #include <netinet/ip.h>
104 #include <netinet/tcp.h>
105 #include <netinet/udp.h>
107 #include <bus/pci/pcivar.h>
108 #include <bus/pci/pcireg.h>
110 #include <dev/netif/ig_hal/e1000_api.h>
111 #include <dev/netif/ig_hal/e1000_82571.h>
112 #include <dev/netif/ig_hal/e1000_dragonfly.h>
113 #include <dev/netif/emx/if_emx.h>
118 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
120 if (sc->rss_debug >= lvl) \
121 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
123 #else /* !EMX_RSS_DEBUG */
124 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
125 #endif /* EMX_RSS_DEBUG */
127 #define EMX_NAME "Intel(R) PRO/1000 "
129 #define EMX_DEVICE(id) \
130 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
131 #define EMX_DEVICE_NULL { 0, 0, NULL }
133 static const struct emx_device {
138 EMX_DEVICE(82571EB_COPPER),
139 EMX_DEVICE(82571EB_FIBER),
140 EMX_DEVICE(82571EB_SERDES),
141 EMX_DEVICE(82571EB_SERDES_DUAL),
142 EMX_DEVICE(82571EB_SERDES_QUAD),
143 EMX_DEVICE(82571EB_QUAD_COPPER),
144 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
145 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
146 EMX_DEVICE(82571EB_QUAD_FIBER),
147 EMX_DEVICE(82571PT_QUAD_COPPER),
149 EMX_DEVICE(82572EI_COPPER),
150 EMX_DEVICE(82572EI_FIBER),
151 EMX_DEVICE(82572EI_SERDES),
155 EMX_DEVICE(82573E_IAMT),
158 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
159 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
160 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
161 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
166 EMX_DEVICE(PCH_LPT_I217_LM),
167 EMX_DEVICE(PCH_LPT_I217_V),
168 EMX_DEVICE(PCH_LPTLP_I218_LM),
169 EMX_DEVICE(PCH_LPTLP_I218_V),
170 EMX_DEVICE(PCH_I218_LM2),
171 EMX_DEVICE(PCH_I218_V2),
172 EMX_DEVICE(PCH_I218_LM3),
173 EMX_DEVICE(PCH_I218_V3),
174 EMX_DEVICE(PCH_SPT_I219_LM),
175 EMX_DEVICE(PCH_SPT_I219_V),
176 EMX_DEVICE(PCH_SPT_I219_LM2),
177 EMX_DEVICE(PCH_SPT_I219_V2),
178 EMX_DEVICE(PCH_LBG_I219_LM3),
179 EMX_DEVICE(PCH_SPT_I219_LM4),
180 EMX_DEVICE(PCH_SPT_I219_V4),
181 EMX_DEVICE(PCH_SPT_I219_LM5),
182 EMX_DEVICE(PCH_SPT_I219_V5),
184 /* required last entry */
188 static int emx_probe(device_t);
189 static int emx_attach(device_t);
190 static int emx_detach(device_t);
191 static int emx_shutdown(device_t);
192 static int emx_suspend(device_t);
193 static int emx_resume(device_t);
195 static void emx_init(void *);
196 static void emx_stop(struct emx_softc *);
197 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
198 static void emx_start(struct ifnet *, struct ifaltq_subque *);
200 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
201 static void emx_npoll_status(struct ifnet *);
202 static void emx_npoll_tx(struct ifnet *, void *, int);
203 static void emx_npoll_rx(struct ifnet *, void *, int);
205 static void emx_watchdog(struct ifaltq_subque *);
206 static void emx_media_status(struct ifnet *, struct ifmediareq *);
207 static int emx_media_change(struct ifnet *);
208 static void emx_timer(void *);
209 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
210 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
211 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
213 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
217 static void emx_intr(void *);
218 static void emx_intr_mask(void *);
219 static void emx_intr_body(struct emx_softc *, boolean_t);
220 static void emx_rxeof(struct emx_rxdata *, int);
221 static void emx_txeof(struct emx_txdata *);
222 static void emx_tx_collect(struct emx_txdata *, boolean_t);
223 static void emx_txgc_timer(void *);
224 static void emx_tx_purge(struct emx_softc *);
225 static void emx_enable_intr(struct emx_softc *);
226 static void emx_disable_intr(struct emx_softc *);
228 static int emx_dma_alloc(struct emx_softc *);
229 static void emx_dma_free(struct emx_softc *);
230 static void emx_init_tx_ring(struct emx_txdata *);
231 static int emx_init_rx_ring(struct emx_rxdata *);
232 static void emx_free_tx_ring(struct emx_txdata *);
233 static void emx_free_rx_ring(struct emx_rxdata *);
234 static int emx_create_tx_ring(struct emx_txdata *);
235 static int emx_create_rx_ring(struct emx_rxdata *);
236 static void emx_destroy_tx_ring(struct emx_txdata *, int);
237 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
238 static int emx_newbuf(struct emx_rxdata *, int, int);
239 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *);
240 static int emx_txcsum(struct emx_txdata *, struct mbuf *,
241 uint32_t *, uint32_t *);
242 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **);
243 static int emx_tso_setup(struct emx_txdata *, struct mbuf *,
244 uint32_t *, uint32_t *);
245 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t);
247 static int emx_is_valid_eaddr(const uint8_t *);
248 static int emx_reset(struct emx_softc *);
249 static void emx_setup_ifp(struct emx_softc *);
250 static void emx_init_tx_unit(struct emx_softc *);
251 static void emx_init_rx_unit(struct emx_softc *);
252 static void emx_update_stats(struct emx_softc *);
253 static void emx_set_promisc(struct emx_softc *);
254 static void emx_disable_promisc(struct emx_softc *);
255 static void emx_set_multi(struct emx_softc *);
256 static void emx_update_link_status(struct emx_softc *);
257 static void emx_smartspeed(struct emx_softc *);
258 static void emx_set_itr(struct emx_softc *, uint32_t);
259 static void emx_disable_aspm(struct emx_softc *);
260 static void emx_flush_tx_ring(struct emx_softc *);
261 static void emx_flush_rx_ring(struct emx_softc *);
262 static void emx_flush_txrx_ring(struct emx_softc *);
264 static void emx_print_debug_info(struct emx_softc *);
265 static void emx_print_nvm_info(struct emx_softc *);
266 static void emx_print_hw_stats(struct emx_softc *);
268 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
269 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
270 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
271 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
272 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
273 static void emx_add_sysctl(struct emx_softc *);
275 static void emx_serialize_skipmain(struct emx_softc *);
276 static void emx_deserialize_skipmain(struct emx_softc *);
278 /* Management and WOL Support */
279 static void emx_get_mgmt(struct emx_softc *);
280 static void emx_rel_mgmt(struct emx_softc *);
281 static void emx_get_hw_control(struct emx_softc *);
282 static void emx_rel_hw_control(struct emx_softc *);
283 static void emx_enable_wol(device_t);
285 static device_method_t emx_methods[] = {
286 /* Device interface */
287 DEVMETHOD(device_probe, emx_probe),
288 DEVMETHOD(device_attach, emx_attach),
289 DEVMETHOD(device_detach, emx_detach),
290 DEVMETHOD(device_shutdown, emx_shutdown),
291 DEVMETHOD(device_suspend, emx_suspend),
292 DEVMETHOD(device_resume, emx_resume),
296 static driver_t emx_driver = {
299 sizeof(struct emx_softc),
302 static devclass_t emx_devclass;
304 DECLARE_DUMMY_MODULE(if_emx);
305 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
306 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
311 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
312 static int emx_rxd = EMX_DEFAULT_RXD;
313 static int emx_txd = EMX_DEFAULT_TXD;
314 static int emx_smart_pwr_down = 0;
315 static int emx_rxr = 0;
316 static int emx_txr = 1;
318 /* Controls whether promiscuous also shows bad packets */
319 static int emx_debug_sbp = 0;
321 static int emx_82573_workaround = 1;
322 static int emx_msi_enable = 1;
324 static char emx_flowctrl[IFM_ETH_FC_STRLEN] = IFM_ETH_FC_NONE;
326 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
327 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
328 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
329 TUNABLE_INT("hw.emx.txd", &emx_txd);
330 TUNABLE_INT("hw.emx.txr", &emx_txr);
331 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
332 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
333 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
334 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
335 TUNABLE_STR("hw.emx.flow_ctrl", emx_flowctrl, sizeof(emx_flowctrl));
337 /* Global used in WOL setup with multiport cards */
338 static int emx_global_quad_port_a = 0;
340 /* Set this to one to display debug statistics */
341 static int emx_display_debug_stats = 0;
343 #if !defined(KTR_IF_EMX)
344 #define KTR_IF_EMX KTR_ALL
346 KTR_INFO_MASTER(if_emx);
347 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
348 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
349 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
350 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
351 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
352 #define logif(name) KTR_LOG(if_emx_ ## name)
355 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
357 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
358 /* DD bit must be cleared */
359 rxd->rxd_staterr = 0;
363 emx_free_txbuf(struct emx_txdata *tdata, struct emx_txbuf *tx_buffer)
366 KKASSERT(tx_buffer->m_head != NULL);
367 KKASSERT(tdata->tx_nmbuf > 0);
370 bus_dmamap_unload(tdata->txtag, tx_buffer->map);
371 m_freem(tx_buffer->m_head);
372 tx_buffer->m_head = NULL;
376 emx_tx_intr(struct emx_txdata *tdata)
380 if (!ifsq_is_empty(tdata->ifsq))
381 ifsq_devstart(tdata->ifsq);
385 emx_try_txgc(struct emx_txdata *tdata, int16_t dec)
388 if (tdata->tx_running > 0) {
389 tdata->tx_running -= dec;
390 if (tdata->tx_running <= 0 && tdata->tx_nmbuf &&
391 tdata->num_tx_desc_avail < tdata->num_tx_desc &&
392 tdata->num_tx_desc_avail + tdata->tx_intr_nsegs >
394 emx_tx_collect(tdata, TRUE);
399 emx_txgc_timer(void *xtdata)
401 struct emx_txdata *tdata = xtdata;
402 struct ifnet *ifp = &tdata->sc->arpcom.ac_if;
404 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP | IFF_NPOLLING)) !=
405 (IFF_RUNNING | IFF_UP))
408 if (!lwkt_serialize_try(&tdata->tx_serialize))
411 if ((ifp->if_flags & (IFF_RUNNING | IFF_UP | IFF_NPOLLING)) !=
412 (IFF_RUNNING | IFF_UP)) {
413 lwkt_serialize_exit(&tdata->tx_serialize);
416 emx_try_txgc(tdata, EMX_TX_RUNNING_DEC);
418 lwkt_serialize_exit(&tdata->tx_serialize);
420 callout_reset(&tdata->tx_gc_timer, 1, emx_txgc_timer, tdata);
424 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
426 /* Ignore Checksum bit is set */
427 if (staterr & E1000_RXD_STAT_IXSM)
430 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
432 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
434 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
435 E1000_RXD_STAT_TCPCS) {
436 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
438 CSUM_FRAG_NOT_CHECKED;
439 mp->m_pkthdr.csum_data = htons(0xffff);
443 static __inline struct pktinfo *
444 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
445 uint32_t mrq, uint32_t hash, uint32_t staterr)
447 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
448 case EMX_RXDMRQ_IPV4_TCP:
449 pi->pi_netisr = NETISR_IP;
451 pi->pi_l3proto = IPPROTO_TCP;
454 case EMX_RXDMRQ_IPV6_TCP:
455 pi->pi_netisr = NETISR_IPV6;
457 pi->pi_l3proto = IPPROTO_TCP;
460 case EMX_RXDMRQ_IPV4:
461 if (staterr & E1000_RXD_STAT_IXSM)
465 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
466 E1000_RXD_STAT_TCPCS) {
467 pi->pi_netisr = NETISR_IP;
469 pi->pi_l3proto = IPPROTO_UDP;
477 m_sethash(m, toeplitz_hash(hash));
482 emx_probe(device_t dev)
484 const struct emx_device *d;
487 vid = pci_get_vendor(dev);
488 did = pci_get_device(dev);
490 for (d = emx_devices; d->desc != NULL; ++d) {
491 if (vid == d->vid && did == d->did) {
492 device_set_desc(dev, d->desc);
493 device_set_async_attach(dev, TRUE);
501 emx_attach(device_t dev)
503 struct emx_softc *sc = device_get_softc(dev);
504 int error = 0, i, throttle, msi_enable;
505 int tx_ring_max, ring_cnt;
507 uint16_t eeprom_data, device_id, apme_mask;
508 driver_intr_t *intr_func;
509 char flowctrl[IFM_ETH_FC_STRLEN];
514 for (i = 0; i < EMX_NRX_RING; ++i) {
515 sc->rx_data[i].sc = sc;
516 sc->rx_data[i].idx = i;
522 for (i = 0; i < EMX_NTX_RING; ++i) {
523 sc->tx_data[i].sc = sc;
524 sc->tx_data[i].idx = i;
525 callout_init_mp(&sc->tx_data[i].tx_gc_timer);
529 * Initialize serializers
531 lwkt_serialize_init(&sc->main_serialize);
532 for (i = 0; i < EMX_NTX_RING; ++i)
533 lwkt_serialize_init(&sc->tx_data[i].tx_serialize);
534 for (i = 0; i < EMX_NRX_RING; ++i)
535 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
538 * Initialize serializer array
542 KKASSERT(i < EMX_NSERIALIZE);
543 sc->serializes[i++] = &sc->main_serialize;
545 KKASSERT(i < EMX_NSERIALIZE);
546 sc->serializes[i++] = &sc->tx_data[0].tx_serialize;
547 KKASSERT(i < EMX_NSERIALIZE);
548 sc->serializes[i++] = &sc->tx_data[1].tx_serialize;
550 KKASSERT(i < EMX_NSERIALIZE);
551 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
552 KKASSERT(i < EMX_NSERIALIZE);
553 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
555 KKASSERT(i == EMX_NSERIALIZE);
557 ifmedia_init(&sc->media, IFM_IMASK | IFM_ETH_FCMASK,
558 emx_media_change, emx_media_status);
559 callout_init_mp(&sc->timer);
561 sc->dev = sc->osdep.dev = dev;
564 * Determine hardware and mac type
566 sc->hw.vendor_id = pci_get_vendor(dev);
567 sc->hw.device_id = pci_get_device(dev);
568 sc->hw.revision_id = pci_get_revid(dev);
569 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
570 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
572 if (e1000_set_mac_type(&sc->hw))
575 /* Enable bus mastering */
576 pci_enable_busmaster(dev);
581 sc->memory_rid = EMX_BAR_MEM;
582 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
583 &sc->memory_rid, RF_ACTIVE);
584 if (sc->memory == NULL) {
585 device_printf(dev, "Unable to allocate bus resource: memory\n");
589 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
590 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
592 /* XXX This is quite goofy, it is not actually used */
593 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
596 * Don't enable MSI-X on 82574, see:
597 * 82574 specification update errata #15
599 * Don't enable MSI on 82571/82572, see:
600 * 82571/82572 specification update errata #63
602 msi_enable = emx_msi_enable;
604 (sc->hw.mac.type == e1000_82571 ||
605 sc->hw.mac.type == e1000_82572))
611 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
612 &sc->intr_rid, &intr_flags);
614 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
617 unshared = device_getenv_int(dev, "irq.unshared", 0);
619 sc->flags |= EMX_FLAG_SHARED_INTR;
621 device_printf(dev, "IRQ shared\n");
623 intr_flags &= ~RF_SHAREABLE;
625 device_printf(dev, "IRQ unshared\n");
629 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
631 if (sc->intr_res == NULL) {
632 device_printf(dev, "Unable to allocate bus resource: %s\n",
633 sc->intr_type == PCI_INTR_TYPE_MSI ? "MSI" : "legacy intr");
635 /* Retry with MSI. */
637 sc->flags &= ~EMX_FLAG_SHARED_INTR;
644 /* Save PCI command register for Shared Code */
645 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
646 sc->hw.back = &sc->osdep;
649 * For I217/I218, we need to map the flash memory and this
650 * must happen after the MAC is identified.
652 if (sc->hw.mac.type == e1000_pch_lpt) {
653 sc->flash_rid = EMX_BAR_FLASH;
655 sc->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
656 &sc->flash_rid, RF_ACTIVE);
657 if (sc->flash == NULL) {
658 device_printf(dev, "Mapping of Flash failed\n");
662 sc->osdep.flash_bus_space_tag = rman_get_bustag(sc->flash);
663 sc->osdep.flash_bus_space_handle =
664 rman_get_bushandle(sc->flash);
667 * This is used in the shared code
668 * XXX this goof is actually not used.
670 sc->hw.flash_address = (uint8_t *)sc->flash;
671 } else if (sc->hw.mac.type == e1000_pch_spt) {
673 * In the new SPT device flash is not a seperate BAR,
674 * rather it is also in BAR0, so use the same tag and
675 * an offset handle for the FLASH read/write macros
676 * in the shared code.
678 sc->osdep.flash_bus_space_tag = sc->osdep.mem_bus_space_tag;
679 sc->osdep.flash_bus_space_handle =
680 sc->osdep.mem_bus_space_handle + E1000_FLASH_BASE_ADDR;
683 /* Do Shared Code initialization */
684 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
685 device_printf(dev, "Setup of Shared code failed\n");
689 e1000_get_bus_info(&sc->hw);
691 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
692 sc->hw.phy.autoneg_wait_to_complete = FALSE;
693 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
696 * Interrupt throttle rate
698 throttle = device_getenv_int(dev, "int_throttle_ceil",
699 emx_int_throttle_ceil);
701 sc->int_throttle_ceil = 0;
704 throttle = EMX_DEFAULT_ITR;
706 /* Recalculate the tunable value to get the exact frequency. */
707 throttle = 1000000000 / 256 / throttle;
709 /* Upper 16bits of ITR is reserved and should be zero */
710 if (throttle & 0xffff0000)
711 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
713 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
716 e1000_init_script_state_82541(&sc->hw, TRUE);
717 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
720 if (sc->hw.phy.media_type == e1000_media_type_copper) {
721 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
722 sc->hw.phy.disable_polarity_correction = FALSE;
723 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
726 /* Set the frame limits assuming standard ethernet sized frames. */
727 sc->hw.mac.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
729 /* This controls when hardware reports transmit completion status. */
730 sc->hw.mac.report_tx_early = 1;
733 * Calculate # of RX/TX rings
735 ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
736 sc->rx_rmap = if_ringmap_alloc(dev, ring_cnt, EMX_NRX_RING);
739 if (sc->hw.mac.type == e1000_82571 ||
740 sc->hw.mac.type == e1000_82572 ||
741 sc->hw.mac.type == e1000_80003es2lan ||
742 sc->hw.mac.type == e1000_pch_lpt ||
743 sc->hw.mac.type == e1000_pch_spt ||
744 sc->hw.mac.type == e1000_82574)
745 tx_ring_max = EMX_NTX_RING;
746 ring_cnt = device_getenv_int(dev, "txr", emx_txr);
747 sc->tx_rmap = if_ringmap_alloc(dev, ring_cnt, tx_ring_max);
749 if_ringmap_match(dev, sc->rx_rmap, sc->tx_rmap);
750 sc->rx_ring_cnt = if_ringmap_count(sc->rx_rmap);
751 sc->tx_ring_cnt = if_ringmap_count(sc->tx_rmap);
753 /* Allocate RX/TX rings' busdma(9) stuffs */
754 error = emx_dma_alloc(sc);
758 /* Allocate multicast array memory. */
759 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
762 /* Indicate SOL/IDER usage */
763 if (e1000_check_reset_block(&sc->hw)) {
765 "PHY reset is blocked due to SOL/IDER session.\n");
768 /* Disable EEE on I217/I218 */
769 sc->hw.dev_spec.ich8lan.eee_disable = 1;
772 * Start from a known state, this is important in reading the
773 * nvm and mac from that.
775 e1000_reset_hw(&sc->hw);
777 /* Make sure we have a good EEPROM before we read from it */
778 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
780 * Some PCI-E parts fail the first check due to
781 * the link being in sleep state, call it again,
782 * if it fails a second time its a real issue.
784 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
786 "The EEPROM Checksum Is Not Valid\n");
792 /* Copy the permanent MAC address out of the EEPROM */
793 if (e1000_read_mac_addr(&sc->hw) < 0) {
794 device_printf(dev, "EEPROM read error while reading MAC"
799 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
800 device_printf(dev, "Invalid MAC address\n");
805 /* Disable ULP support */
806 e1000_disable_ulp_lpt_lp(&sc->hw, TRUE);
808 /* Determine if we have to control management hardware */
809 if (e1000_enable_mng_pass_thru(&sc->hw))
810 sc->flags |= EMX_FLAG_HAS_MGMT;
815 apme_mask = EMX_EEPROM_APME;
817 switch (sc->hw.mac.type) {
819 sc->flags |= EMX_FLAG_HAS_AMT;
824 case e1000_80003es2lan:
825 if (sc->hw.bus.func == 1) {
826 e1000_read_nvm(&sc->hw,
827 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
829 e1000_read_nvm(&sc->hw,
830 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
835 e1000_read_nvm(&sc->hw,
836 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
839 if (eeprom_data & apme_mask)
840 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
843 * We have the eeprom settings, now apply the special cases
844 * where the eeprom may be wrong or the board won't support
845 * wake on lan on a particular port
847 device_id = pci_get_device(dev);
849 case E1000_DEV_ID_82571EB_FIBER:
851 * Wake events only supported on port A for dual fiber
852 * regardless of eeprom setting
854 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
859 case E1000_DEV_ID_82571EB_QUAD_COPPER:
860 case E1000_DEV_ID_82571EB_QUAD_FIBER:
861 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
862 /* if quad port sc, disable WoL on all but port A */
863 if (emx_global_quad_port_a != 0)
865 /* Reset for multiple quad port adapters */
866 if (++emx_global_quad_port_a == 4)
867 emx_global_quad_port_a = 0;
871 /* XXX disable wol */
874 /* Initialized #of TX rings to use. */
875 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE);
877 /* Setup flow control. */
878 device_getenv_string(dev, "flow_ctrl", flowctrl, sizeof(flowctrl),
880 sc->ifm_flowctrl = ifmedia_str2ethfc(flowctrl);
882 /* Setup OS specific network interface */
885 /* Add sysctl tree, must after em_setup_ifp() */
888 /* Reset the hardware */
889 error = emx_reset(sc);
892 * Some 82573 parts fail the first reset, call it again,
893 * if it fails a second time its a real issue.
895 error = emx_reset(sc);
897 device_printf(dev, "Unable to reset the hardware\n");
898 ether_ifdetach(&sc->arpcom.ac_if);
903 /* Initialize statistics */
904 emx_update_stats(sc);
906 sc->hw.mac.get_link_status = 1;
907 emx_update_link_status(sc);
909 /* Non-AMT based hardware can now take control from firmware */
910 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
912 emx_get_hw_control(sc);
915 * Missing Interrupt Following ICR read:
917 * 82571/82572 specification update errata #76
918 * 82573 specification update errata #31
919 * 82574 specification update errata #12
921 intr_func = emx_intr;
922 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
923 (sc->hw.mac.type == e1000_82571 ||
924 sc->hw.mac.type == e1000_82572 ||
925 sc->hw.mac.type == e1000_82573 ||
926 sc->hw.mac.type == e1000_82574))
927 intr_func = emx_intr_mask;
929 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
930 &sc->intr_tag, &sc->main_serialize);
932 device_printf(dev, "Failed to register interrupt handler");
933 ether_ifdetach(&sc->arpcom.ac_if);
943 emx_detach(device_t dev)
945 struct emx_softc *sc = device_get_softc(dev);
947 if (device_is_attached(dev)) {
948 struct ifnet *ifp = &sc->arpcom.ac_if;
950 ifnet_serialize_all(ifp);
954 e1000_phy_hw_reset(&sc->hw);
957 emx_rel_hw_control(sc);
960 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
961 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
965 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
967 ifnet_deserialize_all(ifp);
970 } else if (sc->memory != NULL) {
971 emx_rel_hw_control(sc);
974 ifmedia_removeall(&sc->media);
975 bus_generic_detach(dev);
977 if (sc->intr_res != NULL) {
978 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
982 if (sc->intr_type == PCI_INTR_TYPE_MSI)
983 pci_release_msi(dev);
985 if (sc->memory != NULL) {
986 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
990 if (sc->flash != NULL) {
991 bus_release_resource(dev, SYS_RES_MEMORY, sc->flash_rid,
998 kfree(sc->mta, M_DEVBUF);
1000 if (sc->rx_rmap != NULL)
1001 if_ringmap_free(sc->rx_rmap);
1002 if (sc->tx_rmap != NULL)
1003 if_ringmap_free(sc->tx_rmap);
1009 emx_shutdown(device_t dev)
1011 return emx_suspend(dev);
1015 emx_suspend(device_t dev)
1017 struct emx_softc *sc = device_get_softc(dev);
1018 struct ifnet *ifp = &sc->arpcom.ac_if;
1020 ifnet_serialize_all(ifp);
1025 emx_rel_hw_control(sc);
1028 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
1029 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
1030 emx_enable_wol(dev);
1033 ifnet_deserialize_all(ifp);
1035 return bus_generic_suspend(dev);
1039 emx_resume(device_t dev)
1041 struct emx_softc *sc = device_get_softc(dev);
1042 struct ifnet *ifp = &sc->arpcom.ac_if;
1045 ifnet_serialize_all(ifp);
1049 for (i = 0; i < sc->tx_ring_inuse; ++i)
1050 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1052 ifnet_deserialize_all(ifp);
1054 return bus_generic_resume(dev);
1058 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1060 struct emx_softc *sc = ifp->if_softc;
1061 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1062 struct mbuf *m_head;
1063 int idx = -1, nsegs = 0;
1065 KKASSERT(tdata->ifsq == ifsq);
1066 ASSERT_SERIALIZED(&tdata->tx_serialize);
1068 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
1071 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) {
1076 while (!ifsq_is_empty(ifsq)) {
1077 /* Now do we at least have a minimal? */
1078 if (EMX_IS_OACTIVE(tdata)) {
1079 emx_tx_collect(tdata, FALSE);
1080 if (EMX_IS_OACTIVE(tdata)) {
1081 ifsq_set_oactive(ifsq);
1087 m_head = ifsq_dequeue(ifsq);
1091 if (emx_encap(tdata, &m_head, &nsegs, &idx)) {
1092 IFNET_STAT_INC(ifp, oerrors, 1);
1093 emx_tx_collect(tdata, FALSE);
1098 * TX interrupt are aggressively aggregated, so increasing
1099 * opackets at TX interrupt time will make the opackets
1100 * statistics vastly inaccurate; we do the opackets increment
1103 IFNET_STAT_INC(ifp, opackets, 1);
1105 if (nsegs >= tdata->tx_wreg_nsegs) {
1106 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1111 /* Send a copy of the frame to the BPF listener */
1112 ETHER_BPF_MTAP(ifp, m_head);
1114 /* Set timeout in case hardware has problems transmitting. */
1115 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1118 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1119 tdata->tx_running = EMX_TX_RUNNING;
1123 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1125 struct emx_softc *sc = ifp->if_softc;
1126 struct ifreq *ifr = (struct ifreq *)data;
1127 uint16_t eeprom_data = 0;
1128 int max_frame_size, mask, reinit;
1131 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1135 switch (sc->hw.mac.type) {
1138 * 82573 only supports jumbo frames
1139 * if ASPM is disabled.
1141 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
1143 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1144 max_frame_size = ETHER_MAX_LEN;
1149 /* Limit Jumbo Frame size */
1155 case e1000_80003es2lan:
1156 max_frame_size = 9234;
1160 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1163 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1169 ifp->if_mtu = ifr->ifr_mtu;
1170 sc->hw.mac.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1173 if (ifp->if_flags & IFF_RUNNING)
1178 if (ifp->if_flags & IFF_UP) {
1179 if ((ifp->if_flags & IFF_RUNNING)) {
1180 if ((ifp->if_flags ^ sc->if_flags) &
1181 (IFF_PROMISC | IFF_ALLMULTI)) {
1182 emx_disable_promisc(sc);
1183 emx_set_promisc(sc);
1188 } else if (ifp->if_flags & IFF_RUNNING) {
1191 sc->if_flags = ifp->if_flags;
1196 if (ifp->if_flags & IFF_RUNNING) {
1197 emx_disable_intr(sc);
1199 #ifdef IFPOLL_ENABLE
1200 if (!(ifp->if_flags & IFF_NPOLLING))
1202 emx_enable_intr(sc);
1207 /* Check SOL/IDER usage */
1208 if (e1000_check_reset_block(&sc->hw)) {
1209 device_printf(sc->dev, "Media change is"
1210 " blocked due to SOL/IDER session.\n");
1216 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1221 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1222 if (mask & IFCAP_RXCSUM) {
1223 ifp->if_capenable ^= IFCAP_RXCSUM;
1226 if (mask & IFCAP_VLAN_HWTAGGING) {
1227 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1230 if (mask & IFCAP_TXCSUM) {
1231 ifp->if_capenable ^= IFCAP_TXCSUM;
1232 if (ifp->if_capenable & IFCAP_TXCSUM)
1233 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1235 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1237 if (mask & IFCAP_TSO) {
1238 ifp->if_capenable ^= IFCAP_TSO;
1239 if (ifp->if_capenable & IFCAP_TSO)
1240 ifp->if_hwassist |= CSUM_TSO;
1242 ifp->if_hwassist &= ~CSUM_TSO;
1244 if (mask & IFCAP_RSS)
1245 ifp->if_capenable ^= IFCAP_RSS;
1246 if (reinit && (ifp->if_flags & IFF_RUNNING))
1251 error = ether_ioctl(ifp, command, data);
1258 emx_watchdog(struct ifaltq_subque *ifsq)
1260 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1261 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1262 struct emx_softc *sc = ifp->if_softc;
1265 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1268 * The timer is set to 5 every time start queues a packet.
1269 * Then txeof keeps resetting it as long as it cleans at
1270 * least one descriptor.
1271 * Finally, anytime all descriptors are clean the timer is
1275 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) ==
1276 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) {
1278 * If we reach here, all TX jobs are completed and
1279 * the TX engine should have been idled for some time.
1280 * We don't need to call ifsq_devstart_sched() here.
1282 ifsq_clr_oactive(ifsq);
1283 tdata->tx_watchdog.wd_timer = 0;
1288 * If we are in this routine because of pause frames, then
1289 * don't reset the hardware.
1291 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1292 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1296 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx);
1298 IFNET_STAT_INC(ifp, oerrors, 1);
1301 for (i = 0; i < sc->tx_ring_inuse; ++i)
1302 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1308 struct emx_softc *sc = xsc;
1309 struct ifnet *ifp = &sc->arpcom.ac_if;
1310 device_t dev = sc->dev;
1314 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1318 /* Get the latest mac address, User can use a LAA */
1319 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1321 /* Put the address into the Receive Address Array */
1322 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1325 * With the 82571 sc, RAR[0] may be overwritten
1326 * when the other port is reset, we make a duplicate
1327 * in RAR[14] for that eventuality, this assures
1328 * the interface continues to function.
1330 if (sc->hw.mac.type == e1000_82571) {
1331 e1000_set_laa_state_82571(&sc->hw, TRUE);
1332 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1333 E1000_RAR_ENTRIES - 1);
1336 /* Initialize the hardware */
1337 if (emx_reset(sc)) {
1338 device_printf(dev, "Unable to reset the hardware\n");
1339 /* XXX emx_stop()? */
1342 emx_update_link_status(sc);
1344 /* Setup VLAN support, basic and offload if available */
1345 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1347 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1350 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1351 ctrl |= E1000_CTRL_VME;
1352 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1355 /* Configure for OS presence */
1359 #ifdef IFPOLL_ENABLE
1360 if (ifp->if_flags & IFF_NPOLLING)
1363 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling);
1364 ifq_set_subq_divisor(&ifp->if_snd, sc->tx_ring_inuse);
1366 /* Prepare transmit descriptors and buffers */
1367 for (i = 0; i < sc->tx_ring_inuse; ++i)
1368 emx_init_tx_ring(&sc->tx_data[i]);
1369 emx_init_tx_unit(sc);
1371 /* Setup Multicast table */
1374 /* Prepare receive descriptors and buffers */
1375 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1376 if (emx_init_rx_ring(&sc->rx_data[i])) {
1378 "Could not setup receive structures\n");
1383 emx_init_rx_unit(sc);
1385 /* Don't lose promiscuous settings */
1386 emx_set_promisc(sc);
1388 /* Reset hardware counters */
1389 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1391 /* MSI/X configuration for 82574 */
1392 if (sc->hw.mac.type == e1000_82574) {
1395 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1396 tmp |= E1000_CTRL_EXT_PBA_CLR;
1397 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1400 * Set the IVAR - interrupt vector routing.
1401 * Each nibble represents a vector, high bit
1402 * is enable, other 3 bits are the MSIX table
1403 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1404 * Link (other) to 2, hence the magic number.
1406 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1410 * Only enable interrupts if we are not polling, make sure
1411 * they are off otherwise.
1414 emx_disable_intr(sc);
1416 emx_enable_intr(sc);
1418 /* AMT based hardware can now take control from firmware */
1419 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1420 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1421 emx_get_hw_control(sc);
1423 ifp->if_flags |= IFF_RUNNING;
1424 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1425 struct emx_txdata *tdata = &sc->tx_data[i];
1427 ifsq_clr_oactive(tdata->ifsq);
1428 ifsq_watchdog_start(&tdata->tx_watchdog);
1430 callout_reset_bycpu(&tdata->tx_gc_timer, 1,
1431 emx_txgc_timer, tdata, ifsq_get_cpuid(tdata->ifsq));
1434 callout_reset(&sc->timer, hz, emx_timer, sc);
1440 emx_intr_body(xsc, TRUE);
1444 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1446 struct ifnet *ifp = &sc->arpcom.ac_if;
1450 ASSERT_SERIALIZED(&sc->main_serialize);
1452 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1454 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1460 * XXX: some laptops trigger several spurious interrupts
1461 * on emx(4) when in the resume cycle. The ICR register
1462 * reports all-ones value in this case. Processing such
1463 * interrupts would lead to a freeze. I don't know why.
1465 if (reg_icr == 0xffffffff) {
1470 if (ifp->if_flags & IFF_RUNNING) {
1472 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1475 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1476 lwkt_serialize_enter(
1477 &sc->rx_data[i].rx_serialize);
1478 emx_rxeof(&sc->rx_data[i], -1);
1479 lwkt_serialize_exit(
1480 &sc->rx_data[i].rx_serialize);
1483 if (reg_icr & E1000_ICR_TXDW) {
1484 struct emx_txdata *tdata = &sc->tx_data[0];
1486 lwkt_serialize_enter(&tdata->tx_serialize);
1488 lwkt_serialize_exit(&tdata->tx_serialize);
1492 /* Link status change */
1493 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1494 emx_serialize_skipmain(sc);
1496 callout_stop(&sc->timer);
1497 sc->hw.mac.get_link_status = 1;
1498 emx_update_link_status(sc);
1500 /* Deal with TX cruft when link lost */
1503 callout_reset(&sc->timer, hz, emx_timer, sc);
1505 emx_deserialize_skipmain(sc);
1508 if (reg_icr & E1000_ICR_RXO)
1515 emx_intr_mask(void *xsc)
1517 struct emx_softc *sc = xsc;
1519 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1522 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1523 * so don't check it.
1525 emx_intr_body(sc, FALSE);
1526 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1530 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1532 struct emx_softc *sc = ifp->if_softc;
1534 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1536 emx_update_link_status(sc);
1538 ifmr->ifm_status = IFM_AVALID;
1539 ifmr->ifm_active = IFM_ETHER;
1541 if (!sc->link_active) {
1542 if (sc->hw.mac.autoneg)
1543 ifmr->ifm_active |= IFM_NONE;
1545 ifmr->ifm_active |= sc->media.ifm_media;
1549 ifmr->ifm_status |= IFM_ACTIVE;
1550 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
1551 ifmr->ifm_active |= sc->ifm_flowctrl;
1553 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1554 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1555 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1557 switch (sc->link_speed) {
1559 ifmr->ifm_active |= IFM_10_T;
1562 ifmr->ifm_active |= IFM_100_TX;
1566 ifmr->ifm_active |= IFM_1000_T;
1569 if (sc->link_duplex == FULL_DUPLEX)
1570 ifmr->ifm_active |= IFM_FDX;
1572 ifmr->ifm_active |= IFM_HDX;
1574 if (ifmr->ifm_active & IFM_FDX)
1575 ifmr->ifm_active |= e1000_fc2ifmedia(sc->hw.fc.current_mode);
1579 emx_media_change(struct ifnet *ifp)
1581 struct emx_softc *sc = ifp->if_softc;
1582 struct ifmedia *ifm = &sc->media;
1584 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1586 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1589 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1591 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1592 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1597 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1598 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1602 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1603 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1605 if (IFM_OPTIONS(ifm->ifm_media) &
1606 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1608 if_printf(ifp, "Flow control is not "
1609 "allowed for half-duplex\n");
1613 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1615 sc->hw.mac.autoneg = FALSE;
1616 sc->hw.phy.autoneg_advertised = 0;
1620 if (IFM_OPTIONS(ifm->ifm_media) & IFM_FDX) {
1621 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1623 if (IFM_OPTIONS(ifm->ifm_media) &
1624 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
1626 if_printf(ifp, "Flow control is not "
1627 "allowed for half-duplex\n");
1631 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1633 sc->hw.mac.autoneg = FALSE;
1634 sc->hw.phy.autoneg_advertised = 0;
1639 if_printf(ifp, "Unsupported media type %d\n",
1640 IFM_SUBTYPE(ifm->ifm_media));
1644 sc->ifm_flowctrl = ifm->ifm_media & IFM_ETH_FCMASK;
1646 if (ifp->if_flags & IFF_RUNNING)
1653 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp,
1654 int *segs_used, int *idx)
1656 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1658 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1659 struct e1000_tx_desc *ctxd = NULL;
1660 struct mbuf *m_head = *m_headp;
1661 uint32_t txd_upper, txd_lower, cmd = 0;
1662 int maxsegs, nsegs, i, j, first, last = 0, error;
1664 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1665 error = emx_tso_pullup(tdata, m_headp);
1671 txd_upper = txd_lower = 0;
1674 * Capture the first descriptor index, this descriptor
1675 * will have the index of the EOP which is the only one
1676 * that now gets a DONE bit writeback.
1678 first = tdata->next_avail_tx_desc;
1679 tx_buffer = &tdata->tx_buf[first];
1680 tx_buffer_mapped = tx_buffer;
1681 map = tx_buffer->map;
1683 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED;
1684 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc"));
1685 if (maxsegs > EMX_MAX_SCATTER)
1686 maxsegs = EMX_MAX_SCATTER;
1688 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp,
1689 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1695 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE);
1698 tdata->tx_nsegs += nsegs;
1699 *segs_used += nsegs;
1701 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1702 /* TSO will consume one TX desc */
1703 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower);
1704 tdata->tx_nsegs += i;
1706 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1707 /* TX csum offloading will consume one TX desc */
1708 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower);
1709 tdata->tx_nsegs += i;
1713 /* Handle VLAN tag */
1714 if (m_head->m_flags & M_VLANTAG) {
1715 /* Set the vlan id. */
1716 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16);
1717 /* Tell hardware to add tag */
1718 txd_lower |= htole32(E1000_TXD_CMD_VLE);
1721 i = tdata->next_avail_tx_desc;
1723 /* Set up our transmit descriptors */
1724 for (j = 0; j < nsegs; j++) {
1725 tx_buffer = &tdata->tx_buf[i];
1726 ctxd = &tdata->tx_desc_base[i];
1728 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1729 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1730 txd_lower | segs[j].ds_len);
1731 ctxd->upper.data = htole32(txd_upper);
1734 if (++i == tdata->num_tx_desc)
1738 tdata->next_avail_tx_desc = i;
1740 KKASSERT(tdata->num_tx_desc_avail > nsegs);
1741 tdata->num_tx_desc_avail -= nsegs;
1744 tx_buffer->m_head = m_head;
1745 tx_buffer_mapped->map = tx_buffer->map;
1746 tx_buffer->map = map;
1748 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) {
1749 tdata->tx_nsegs = 0;
1752 * Report Status (RS) is turned on
1753 * every tx_intr_nsegs descriptors.
1755 cmd = E1000_TXD_CMD_RS;
1758 * Keep track of the descriptor, which will
1759 * be written back by hardware.
1761 tdata->tx_dd[tdata->tx_dd_tail] = last;
1762 EMX_INC_TXDD_IDX(tdata->tx_dd_tail);
1763 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head);
1767 * Last Descriptor of Packet needs End Of Packet (EOP)
1769 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1772 * Defer TDT updating, until enough descriptors are setup
1776 #ifdef EMX_TSS_DEBUG
1784 emx_set_promisc(struct emx_softc *sc)
1786 struct ifnet *ifp = &sc->arpcom.ac_if;
1789 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1791 if (ifp->if_flags & IFF_PROMISC) {
1792 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1793 /* Turn this on if you want to see bad packets */
1795 reg_rctl |= E1000_RCTL_SBP;
1796 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1797 } else if (ifp->if_flags & IFF_ALLMULTI) {
1798 reg_rctl |= E1000_RCTL_MPE;
1799 reg_rctl &= ~E1000_RCTL_UPE;
1800 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1805 emx_disable_promisc(struct emx_softc *sc)
1807 struct ifnet *ifp = &sc->arpcom.ac_if;
1811 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1812 reg_rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
1814 if (ifp->if_flags & IFF_ALLMULTI) {
1815 mcnt = EMX_MCAST_ADDR_MAX;
1817 const struct ifmultiaddr *ifma;
1819 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1820 if (ifma->ifma_addr->sa_family != AF_LINK)
1822 if (mcnt == EMX_MCAST_ADDR_MAX)
1827 /* Don't disable if in MAX groups */
1828 if (mcnt < EMX_MCAST_ADDR_MAX)
1829 reg_rctl &= ~E1000_RCTL_MPE;
1831 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1835 emx_set_multi(struct emx_softc *sc)
1837 struct ifnet *ifp = &sc->arpcom.ac_if;
1838 struct ifmultiaddr *ifma;
1839 uint32_t reg_rctl = 0;
1844 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1846 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1847 if (ifma->ifma_addr->sa_family != AF_LINK)
1850 if (mcnt == EMX_MCAST_ADDR_MAX)
1853 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1854 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1858 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1859 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1860 reg_rctl |= E1000_RCTL_MPE;
1861 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1863 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1868 * This routine checks for link status and updates statistics.
1871 emx_timer(void *xsc)
1873 struct emx_softc *sc = xsc;
1874 struct ifnet *ifp = &sc->arpcom.ac_if;
1876 lwkt_serialize_enter(&sc->main_serialize);
1878 emx_update_link_status(sc);
1879 emx_update_stats(sc);
1881 /* Reset LAA into RAR[0] on 82571 */
1882 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1883 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1885 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1886 emx_print_hw_stats(sc);
1890 callout_reset(&sc->timer, hz, emx_timer, sc);
1892 lwkt_serialize_exit(&sc->main_serialize);
1896 emx_update_link_status(struct emx_softc *sc)
1898 struct e1000_hw *hw = &sc->hw;
1899 struct ifnet *ifp = &sc->arpcom.ac_if;
1900 device_t dev = sc->dev;
1901 uint32_t link_check = 0;
1903 /* Get the cached link value or read phy for real */
1904 switch (hw->phy.media_type) {
1905 case e1000_media_type_copper:
1906 if (hw->mac.get_link_status) {
1907 if (hw->mac.type == e1000_pch_spt)
1909 /* Do the work to read phy */
1910 e1000_check_for_link(hw);
1911 link_check = !hw->mac.get_link_status;
1912 if (link_check) /* ESB2 fix */
1913 e1000_cfg_on_link_up(hw);
1919 case e1000_media_type_fiber:
1920 e1000_check_for_link(hw);
1921 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1924 case e1000_media_type_internal_serdes:
1925 e1000_check_for_link(hw);
1926 link_check = sc->hw.mac.serdes_has_link;
1929 case e1000_media_type_unknown:
1934 /* Now check for a transition */
1935 if (link_check && sc->link_active == 0) {
1936 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1940 * Check if we should enable/disable SPEED_MODE bit on
1943 if (sc->link_speed != SPEED_1000 &&
1944 (hw->mac.type == e1000_82571 ||
1945 hw->mac.type == e1000_82572)) {
1948 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1949 tarc0 &= ~EMX_TARC_SPEED_MODE;
1950 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1953 char flowctrl[IFM_ETH_FC_STRLEN];
1955 e1000_fc2str(hw->fc.current_mode, flowctrl,
1957 device_printf(dev, "Link is up %d Mbps %s, "
1958 "Flow control: %s\n",
1960 (sc->link_duplex == FULL_DUPLEX) ?
1961 "Full Duplex" : "Half Duplex",
1964 if (sc->ifm_flowctrl & IFM_ETH_FORCEPAUSE)
1965 e1000_force_flowctrl(hw, sc->ifm_flowctrl);
1966 sc->link_active = 1;
1968 ifp->if_baudrate = sc->link_speed * 1000000;
1969 ifp->if_link_state = LINK_STATE_UP;
1970 if_link_state_change(ifp);
1971 } else if (!link_check && sc->link_active == 1) {
1972 ifp->if_baudrate = sc->link_speed = 0;
1973 sc->link_duplex = 0;
1975 device_printf(dev, "Link is Down\n");
1976 sc->link_active = 0;
1977 ifp->if_link_state = LINK_STATE_DOWN;
1978 if_link_state_change(ifp);
1983 emx_stop(struct emx_softc *sc)
1985 struct ifnet *ifp = &sc->arpcom.ac_if;
1988 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1990 emx_disable_intr(sc);
1992 callout_stop(&sc->timer);
1994 ifp->if_flags &= ~IFF_RUNNING;
1995 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1996 struct emx_txdata *tdata = &sc->tx_data[i];
1998 ifsq_clr_oactive(tdata->ifsq);
1999 ifsq_watchdog_stop(&tdata->tx_watchdog);
2000 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED;
2002 tdata->tx_running = 0;
2003 callout_stop(&tdata->tx_gc_timer);
2006 /* I219 needs some special flushing to avoid hangs */
2007 if (sc->hw.mac.type == e1000_pch_spt)
2008 emx_flush_txrx_ring(sc);
2011 * Disable multiple receive queues.
2014 * We should disable multiple receive queues before
2015 * resetting the hardware.
2017 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
2019 e1000_reset_hw(&sc->hw);
2020 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
2022 for (i = 0; i < sc->tx_ring_cnt; ++i)
2023 emx_free_tx_ring(&sc->tx_data[i]);
2024 for (i = 0; i < sc->rx_ring_cnt; ++i)
2025 emx_free_rx_ring(&sc->rx_data[i]);
2029 emx_reset(struct emx_softc *sc)
2031 device_t dev = sc->dev;
2032 uint16_t rx_buffer_size;
2035 /* Set up smart power down as default off on newer adapters. */
2036 if (!emx_smart_pwr_down &&
2037 (sc->hw.mac.type == e1000_82571 ||
2038 sc->hw.mac.type == e1000_82572)) {
2039 uint16_t phy_tmp = 0;
2041 /* Speed up time to link by disabling smart power down. */
2042 e1000_read_phy_reg(&sc->hw,
2043 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
2044 phy_tmp &= ~IGP02E1000_PM_SPD;
2045 e1000_write_phy_reg(&sc->hw,
2046 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
2050 * Packet Buffer Allocation (PBA)
2051 * Writing PBA sets the receive portion of the buffer
2052 * the remainder is used for the transmit buffer.
2054 switch (sc->hw.mac.type) {
2055 /* Total Packet Buffer on these is 48K */
2058 case e1000_80003es2lan:
2059 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
2062 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
2063 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
2067 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
2072 pba = E1000_PBA_26K;
2076 /* Devices before 82547 had a Packet Buffer of 64K. */
2077 if (sc->hw.mac.max_frame_size > 8192)
2078 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
2080 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
2082 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
2085 * These parameters control the automatic generation (Tx) and
2086 * response (Rx) to Ethernet PAUSE frames.
2087 * - High water mark should allow for at least two frames to be
2088 * received after sending an XOFF.
2089 * - Low water mark works best when it is very near the high water mark.
2090 * This allows the receiver to restart by sending XON when it has
2091 * drained a bit. Here we use an arbitary value of 1500 which will
2092 * restart after one full frame is pulled from the buffer. There
2093 * could be several smaller frames in the buffer and if so they will
2094 * not trigger the XON until their total number reduces the buffer
2096 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2098 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
2100 sc->hw.fc.high_water = rx_buffer_size -
2101 roundup2(sc->hw.mac.max_frame_size, 1024);
2102 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
2104 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
2105 sc->hw.fc.send_xon = TRUE;
2106 sc->hw.fc.requested_mode = e1000_ifmedia2fc(sc->ifm_flowctrl);
2109 * Device specific overrides/settings
2111 if (sc->hw.mac.type == e1000_pch_lpt ||
2112 sc->hw.mac.type == e1000_pch_spt) {
2113 sc->hw.fc.high_water = 0x5C20;
2114 sc->hw.fc.low_water = 0x5048;
2115 sc->hw.fc.pause_time = 0x0650;
2116 sc->hw.fc.refresh_time = 0x0400;
2117 /* Jumbos need adjusted PBA */
2118 if (sc->arpcom.ac_if.if_mtu > ETHERMTU)
2119 E1000_WRITE_REG(&sc->hw, E1000_PBA, 12);
2121 E1000_WRITE_REG(&sc->hw, E1000_PBA, 26);
2122 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2123 sc->hw.fc.pause_time = 0xFFFF;
2126 /* I219 needs some special flushing to avoid hangs */
2127 if (sc->hw.mac.type == e1000_pch_spt)
2128 emx_flush_txrx_ring(sc);
2130 /* Issue a global reset */
2131 e1000_reset_hw(&sc->hw);
2132 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
2133 emx_disable_aspm(sc);
2135 if (e1000_init_hw(&sc->hw) < 0) {
2136 device_printf(dev, "Hardware Initialization Failed\n");
2140 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
2141 e1000_get_phy_info(&sc->hw);
2142 e1000_check_for_link(&sc->hw);
2148 emx_setup_ifp(struct emx_softc *sc)
2150 struct ifnet *ifp = &sc->arpcom.ac_if;
2153 if_initname(ifp, device_get_name(sc->dev),
2154 device_get_unit(sc->dev));
2156 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2157 ifp->if_init = emx_init;
2158 ifp->if_ioctl = emx_ioctl;
2159 ifp->if_start = emx_start;
2160 #ifdef IFPOLL_ENABLE
2161 ifp->if_npoll = emx_npoll;
2163 ifp->if_serialize = emx_serialize;
2164 ifp->if_deserialize = emx_deserialize;
2165 ifp->if_tryserialize = emx_tryserialize;
2167 ifp->if_serialize_assert = emx_serialize_assert;
2170 ifp->if_nmbclusters = sc->rx_ring_cnt * sc->rx_data[0].num_rx_desc;
2172 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1);
2173 ifq_set_ready(&ifp->if_snd);
2174 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
2176 ifp->if_mapsubq = ifq_mapsubq_modulo;
2177 ifq_set_subq_divisor(&ifp->if_snd, 1);
2179 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
2181 ifp->if_capabilities = IFCAP_HWCSUM |
2182 IFCAP_VLAN_HWTAGGING |
2185 if (sc->rx_ring_cnt > 1)
2186 ifp->if_capabilities |= IFCAP_RSS;
2187 ifp->if_capenable = ifp->if_capabilities;
2188 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
2191 * Tell the upper layer(s) we support long frames.
2193 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2195 for (i = 0; i < sc->tx_ring_cnt; ++i) {
2196 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2197 struct emx_txdata *tdata = &sc->tx_data[i];
2199 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res));
2200 ifsq_set_priv(ifsq, tdata);
2201 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize);
2204 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog);
2208 * Specify the media types supported by this sc and register
2209 * callbacks to update media and link information
2211 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2212 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
2213 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2216 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2217 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2219 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2220 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2222 if (sc->hw.phy.type != e1000_phy_ife) {
2223 ifmedia_add(&sc->media,
2224 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2227 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2228 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO | sc->ifm_flowctrl);
2232 * Workaround for SmartSpeed on 82541 and 82547 controllers
2235 emx_smartspeed(struct emx_softc *sc)
2239 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
2240 sc->hw.mac.autoneg == 0 ||
2241 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2244 if (sc->smartspeed == 0) {
2246 * If Master/Slave config fault is asserted twice,
2247 * we assume back-to-back
2249 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2250 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2252 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2253 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2254 e1000_read_phy_reg(&sc->hw,
2255 PHY_1000T_CTRL, &phy_tmp);
2256 if (phy_tmp & CR_1000T_MS_ENABLE) {
2257 phy_tmp &= ~CR_1000T_MS_ENABLE;
2258 e1000_write_phy_reg(&sc->hw,
2259 PHY_1000T_CTRL, phy_tmp);
2261 if (sc->hw.mac.autoneg &&
2262 !e1000_phy_setup_autoneg(&sc->hw) &&
2263 !e1000_read_phy_reg(&sc->hw,
2264 PHY_CONTROL, &phy_tmp)) {
2265 phy_tmp |= MII_CR_AUTO_NEG_EN |
2266 MII_CR_RESTART_AUTO_NEG;
2267 e1000_write_phy_reg(&sc->hw,
2268 PHY_CONTROL, phy_tmp);
2273 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2274 /* If still no link, perhaps using 2/3 pair cable */
2275 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2276 phy_tmp |= CR_1000T_MS_ENABLE;
2277 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2278 if (sc->hw.mac.autoneg &&
2279 !e1000_phy_setup_autoneg(&sc->hw) &&
2280 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2281 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2282 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2286 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2287 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2292 emx_create_tx_ring(struct emx_txdata *tdata)
2294 device_t dev = tdata->sc->dev;
2295 struct emx_txbuf *tx_buffer;
2296 int error, i, tsize, ntxd;
2299 * Validate number of transmit descriptors. It must not exceed
2300 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2302 ntxd = device_getenv_int(dev, "txd", emx_txd);
2303 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2304 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2305 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2306 EMX_DEFAULT_TXD, ntxd);
2307 tdata->num_tx_desc = EMX_DEFAULT_TXD;
2309 tdata->num_tx_desc = ntxd;
2313 * Allocate Transmit Descriptor ring
2315 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc),
2317 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag,
2318 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2319 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap,
2320 &tdata->tx_desc_paddr);
2321 if (tdata->tx_desc_base == NULL) {
2322 device_printf(dev, "Unable to allocate tx_desc memory\n");
2326 tsize = __VM_CACHELINE_ALIGN(
2327 sizeof(struct emx_txbuf) * tdata->num_tx_desc);
2328 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
2331 * Create DMA tags for tx buffers
2333 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */
2334 1, 0, /* alignment, bounds */
2335 BUS_SPACE_MAXADDR, /* lowaddr */
2336 BUS_SPACE_MAXADDR, /* highaddr */
2337 NULL, NULL, /* filter, filterarg */
2338 EMX_TSO_SIZE, /* maxsize */
2339 EMX_MAX_SCATTER, /* nsegments */
2340 EMX_MAX_SEGSIZE, /* maxsegsize */
2341 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2342 BUS_DMA_ONEBPAGE, /* flags */
2345 device_printf(dev, "Unable to allocate TX DMA tag\n");
2346 kfree(tdata->tx_buf, M_DEVBUF);
2347 tdata->tx_buf = NULL;
2352 * Create DMA maps for tx buffers
2354 for (i = 0; i < tdata->num_tx_desc; i++) {
2355 tx_buffer = &tdata->tx_buf[i];
2357 error = bus_dmamap_create(tdata->txtag,
2358 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2361 device_printf(dev, "Unable to create TX DMA map\n");
2362 emx_destroy_tx_ring(tdata, i);
2368 * Setup TX parameters
2370 tdata->spare_tx_desc = EMX_TX_SPARE;
2371 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG;
2374 * Keep following relationship between spare_tx_desc, oact_tx_desc
2375 * and tx_intr_nsegs:
2376 * (spare_tx_desc + EMX_TX_RESERVED) <=
2377 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs
2379 tdata->oact_tx_desc = tdata->num_tx_desc / 8;
2380 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX)
2381 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX;
2382 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED)
2383 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED;
2385 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16;
2386 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc)
2387 tdata->tx_intr_nsegs = tdata->oact_tx_desc;
2390 * Pullup extra 4bytes into the first data segment for TSO, see:
2391 * 82571/82572 specification update errata #7
2393 * Same applies to I217 (and maybe I218 and I219).
2396 * 4bytes instead of 2bytes, which are mentioned in the errata,
2397 * are pulled; mainly to keep rest of the data properly aligned.
2399 if (tdata->sc->hw.mac.type == e1000_82571 ||
2400 tdata->sc->hw.mac.type == e1000_82572 ||
2401 tdata->sc->hw.mac.type == e1000_pch_lpt ||
2402 tdata->sc->hw.mac.type == e1000_pch_spt)
2403 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX;
2409 emx_init_tx_ring(struct emx_txdata *tdata)
2411 /* Clear the old ring contents */
2412 bzero(tdata->tx_desc_base,
2413 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc);
2416 tdata->next_avail_tx_desc = 0;
2417 tdata->next_tx_to_clean = 0;
2418 tdata->num_tx_desc_avail = tdata->num_tx_desc;
2419 tdata->tx_nmbuf = 0;
2420 tdata->tx_running = 0;
2422 tdata->tx_flags |= EMX_TXFLAG_ENABLED;
2423 if (tdata->sc->tx_ring_inuse > 1) {
2424 tdata->tx_flags |= EMX_TXFLAG_FORCECTX;
2426 if_printf(&tdata->sc->arpcom.ac_if,
2427 "TX %d force ctx setup\n", tdata->idx);
2433 emx_init_tx_unit(struct emx_softc *sc)
2435 uint32_t tctl, tarc, tipg = 0, txdctl;
2438 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2439 struct emx_txdata *tdata = &sc->tx_data[i];
2442 /* Setup the Base and Length of the Tx Descriptor Ring */
2443 bus_addr = tdata->tx_desc_paddr;
2444 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i),
2445 tdata->num_tx_desc * sizeof(struct e1000_tx_desc));
2446 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i),
2447 (uint32_t)(bus_addr >> 32));
2448 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i),
2449 (uint32_t)bus_addr);
2450 /* Setup the HW Tx Head and Tail descriptor pointers */
2451 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0);
2452 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0);
2454 txdctl = 0x1f; /* PTHRESH */
2455 txdctl |= 1 << 8; /* HTHRESH */
2456 txdctl |= 1 << 16; /* WTHRESH */
2457 txdctl |= 1 << 22; /* Reserved bit 22 must always be 1 */
2458 txdctl |= E1000_TXDCTL_GRAN;
2459 txdctl |= 1 << 25; /* LWTHRESH */
2461 E1000_WRITE_REG(&sc->hw, E1000_TXDCTL(i), txdctl);
2464 /* Set the default values for the Tx Inter Packet Gap timer */
2465 switch (sc->hw.mac.type) {
2466 case e1000_80003es2lan:
2467 tipg = DEFAULT_82543_TIPG_IPGR1;
2468 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2469 E1000_TIPG_IPGR2_SHIFT;
2473 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2474 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2475 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2477 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2478 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2479 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2483 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2485 /* NOTE: 0 is not allowed for TIDV */
2486 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2487 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2490 * Errata workaround (obtained from Linux). This is necessary
2491 * to make multiple TX queues work on 82574.
2492 * XXX can't find it in any published errata though.
2494 txdctl = E1000_READ_REG(&sc->hw, E1000_TXDCTL(0));
2495 E1000_WRITE_REG(&sc->hw, E1000_TXDCTL(1), txdctl);
2497 if (sc->hw.mac.type == e1000_82571 ||
2498 sc->hw.mac.type == e1000_82572) {
2499 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2500 tarc |= EMX_TARC_SPEED_MODE;
2501 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2502 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2503 /* errata: program both queues to unweighted RR */
2504 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2506 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2507 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2509 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2510 } else if (sc->hw.mac.type == e1000_82574) {
2511 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2512 tarc |= EMX_TARC_ERRATA;
2513 if (sc->tx_ring_inuse > 1) {
2514 tarc |= (EMX_TARC_COMPENSATION_MODE | EMX_TARC_MQ_FIX);
2515 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2516 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2518 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2522 /* Program the Transmit Control Register */
2523 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2524 tctl &= ~E1000_TCTL_CT;
2525 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2526 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2527 tctl |= E1000_TCTL_MULR;
2529 /* This write will effectively turn on the transmit unit. */
2530 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2532 if (sc->hw.mac.type == e1000_82571 ||
2533 sc->hw.mac.type == e1000_82572 ||
2534 sc->hw.mac.type == e1000_80003es2lan) {
2535 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2536 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2538 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2539 } else if (sc->hw.mac.type == e1000_pch_spt) {
2542 reg = E1000_READ_REG(&sc->hw, E1000_IOSFPC);
2543 reg |= E1000_RCTL_RDMTS_HEX;
2544 E1000_WRITE_REG(&sc->hw, E1000_IOSFPC, reg);
2545 reg = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2546 reg |= E1000_TARC0_CB_MULTIQ_3_REQ;
2547 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), reg);
2550 if (sc->tx_ring_inuse > 1) {
2551 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2552 tarc &= ~EMX_TARC_COUNT_MASK;
2554 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2556 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2557 tarc &= ~EMX_TARC_COUNT_MASK;
2559 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2564 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc)
2566 struct emx_txbuf *tx_buffer;
2569 /* Free Transmit Descriptor ring */
2570 if (tdata->tx_desc_base) {
2571 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap);
2572 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base,
2573 tdata->tx_desc_dmap);
2574 bus_dma_tag_destroy(tdata->tx_desc_dtag);
2576 tdata->tx_desc_base = NULL;
2579 if (tdata->tx_buf == NULL)
2582 for (i = 0; i < ndesc; i++) {
2583 tx_buffer = &tdata->tx_buf[i];
2585 KKASSERT(tx_buffer->m_head == NULL);
2586 bus_dmamap_destroy(tdata->txtag, tx_buffer->map);
2588 bus_dma_tag_destroy(tdata->txtag);
2590 kfree(tdata->tx_buf, M_DEVBUF);
2591 tdata->tx_buf = NULL;
2595 * The offload context needs to be set when we transfer the first
2596 * packet of a particular protocol (TCP/UDP). This routine has been
2597 * enhanced to deal with inserted VLAN headers.
2599 * If the new packet's ether header length, ip header length and
2600 * csum offloading type are same as the previous packet, we should
2601 * avoid allocating a new csum context descriptor; mainly to take
2602 * advantage of the pipeline effect of the TX data read request.
2604 * This function returns number of TX descrptors allocated for
2608 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp,
2609 uint32_t *txd_upper, uint32_t *txd_lower)
2611 struct e1000_context_desc *TXD;
2612 int curr_txd, ehdrlen, csum_flags;
2613 uint32_t cmd, hdr_len, ip_hlen;
2615 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2616 ip_hlen = mp->m_pkthdr.csum_iphlen;
2617 ehdrlen = mp->m_pkthdr.csum_lhlen;
2619 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
2620 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen &&
2621 tdata->csum_flags == csum_flags) {
2623 * Same csum offload context as the previous packets;
2626 *txd_upper = tdata->csum_txd_upper;
2627 *txd_lower = tdata->csum_txd_lower;
2632 * Setup a new csum offload context.
2635 curr_txd = tdata->next_avail_tx_desc;
2636 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
2640 /* Setup of IP header checksum. */
2641 if (csum_flags & CSUM_IP) {
2643 * Start offset for header checksum calculation.
2644 * End offset for header checksum calculation.
2645 * Offset of place to put the checksum.
2647 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2648 TXD->lower_setup.ip_fields.ipcse =
2649 htole16(ehdrlen + ip_hlen - 1);
2650 TXD->lower_setup.ip_fields.ipcso =
2651 ehdrlen + offsetof(struct ip, ip_sum);
2652 cmd |= E1000_TXD_CMD_IP;
2653 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2655 hdr_len = ehdrlen + ip_hlen;
2657 if (csum_flags & CSUM_TCP) {
2659 * Start offset for payload checksum calculation.
2660 * End offset for payload checksum calculation.
2661 * Offset of place to put the checksum.
2663 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2664 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2665 TXD->upper_setup.tcp_fields.tucso =
2666 hdr_len + offsetof(struct tcphdr, th_sum);
2667 cmd |= E1000_TXD_CMD_TCP;
2668 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2669 } else if (csum_flags & CSUM_UDP) {
2671 * Start offset for header checksum calculation.
2672 * End offset for header checksum calculation.
2673 * Offset of place to put the checksum.
2675 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2676 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2677 TXD->upper_setup.tcp_fields.tucso =
2678 hdr_len + offsetof(struct udphdr, uh_sum);
2679 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2682 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2683 E1000_TXD_DTYP_D; /* Data descr */
2685 /* Save the information for this csum offloading context */
2686 tdata->csum_lhlen = ehdrlen;
2687 tdata->csum_iphlen = ip_hlen;
2688 tdata->csum_flags = csum_flags;
2689 tdata->csum_txd_upper = *txd_upper;
2690 tdata->csum_txd_lower = *txd_lower;
2692 TXD->tcp_seg_setup.data = htole32(0);
2693 TXD->cmd_and_length =
2694 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2696 if (++curr_txd == tdata->num_tx_desc)
2699 KKASSERT(tdata->num_tx_desc_avail > 0);
2700 tdata->num_tx_desc_avail--;
2702 tdata->next_avail_tx_desc = curr_txd;
2707 emx_txeof(struct emx_txdata *tdata)
2709 struct emx_txbuf *tx_buffer;
2710 int first, num_avail;
2712 if (tdata->tx_dd_head == tdata->tx_dd_tail)
2715 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2718 num_avail = tdata->num_tx_desc_avail;
2719 first = tdata->next_tx_to_clean;
2721 while (tdata->tx_dd_head != tdata->tx_dd_tail) {
2722 int dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2723 struct e1000_tx_desc *tx_desc;
2725 tx_desc = &tdata->tx_desc_base[dd_idx];
2726 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2727 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2729 if (++dd_idx == tdata->num_tx_desc)
2732 while (first != dd_idx) {
2735 KKASSERT(num_avail < tdata->num_tx_desc);
2738 tx_buffer = &tdata->tx_buf[first];
2739 if (tx_buffer->m_head)
2740 emx_free_txbuf(tdata, tx_buffer);
2742 if (++first == tdata->num_tx_desc)
2749 tdata->next_tx_to_clean = first;
2750 tdata->num_tx_desc_avail = num_avail;
2752 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2753 tdata->tx_dd_head = 0;
2754 tdata->tx_dd_tail = 0;
2757 if (!EMX_IS_OACTIVE(tdata)) {
2758 ifsq_clr_oactive(tdata->ifsq);
2760 /* All clean, turn off the timer */
2761 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2762 tdata->tx_watchdog.wd_timer = 0;
2764 tdata->tx_running = EMX_TX_RUNNING;
2768 emx_tx_collect(struct emx_txdata *tdata, boolean_t gc)
2770 struct emx_txbuf *tx_buffer;
2771 int tdh, first, num_avail, dd_idx = -1;
2773 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2776 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx));
2777 if (tdh == tdata->next_tx_to_clean) {
2778 if (gc && tdata->tx_nmbuf > 0)
2779 tdata->tx_running = EMX_TX_RUNNING;
2785 if (tdata->tx_dd_head != tdata->tx_dd_tail)
2786 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2788 num_avail = tdata->num_tx_desc_avail;
2789 first = tdata->next_tx_to_clean;
2791 while (first != tdh) {
2794 KKASSERT(num_avail < tdata->num_tx_desc);
2797 tx_buffer = &tdata->tx_buf[first];
2798 if (tx_buffer->m_head)
2799 emx_free_txbuf(tdata, tx_buffer);
2801 if (first == dd_idx) {
2802 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2803 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2804 tdata->tx_dd_head = 0;
2805 tdata->tx_dd_tail = 0;
2808 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2812 if (++first == tdata->num_tx_desc)
2815 tdata->next_tx_to_clean = first;
2816 tdata->num_tx_desc_avail = num_avail;
2818 if (!EMX_IS_OACTIVE(tdata)) {
2819 ifsq_clr_oactive(tdata->ifsq);
2821 /* All clean, turn off the timer */
2822 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2823 tdata->tx_watchdog.wd_timer = 0;
2825 if (!gc || tdata->tx_nmbuf > 0)
2826 tdata->tx_running = EMX_TX_RUNNING;
2830 * When Link is lost sometimes there is work still in the TX ring
2831 * which will result in a watchdog, rather than allow that do an
2832 * attempted cleanup and then reinit here. Note that this has been
2833 * seens mostly with fiber adapters.
2836 emx_tx_purge(struct emx_softc *sc)
2840 if (sc->link_active)
2843 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2844 struct emx_txdata *tdata = &sc->tx_data[i];
2846 if (tdata->tx_watchdog.wd_timer) {
2847 emx_tx_collect(tdata, FALSE);
2848 if (tdata->tx_watchdog.wd_timer) {
2849 if_printf(&sc->arpcom.ac_if,
2850 "Link lost, TX pending, reinit\n");
2859 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2862 bus_dma_segment_t seg;
2864 struct emx_rxbuf *rx_buffer;
2867 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2870 if_printf(&rdata->sc->arpcom.ac_if,
2871 "Unable to allocate RX mbuf\n");
2875 m->m_len = m->m_pkthdr.len = MCLBYTES;
2877 if (rdata->sc->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN)
2878 m_adj(m, ETHER_ALIGN);
2880 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2881 rdata->rx_sparemap, m,
2882 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2886 if_printf(&rdata->sc->arpcom.ac_if,
2887 "Unable to load RX mbuf\n");
2892 rx_buffer = &rdata->rx_buf[i];
2893 if (rx_buffer->m_head != NULL)
2894 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2896 map = rx_buffer->map;
2897 rx_buffer->map = rdata->rx_sparemap;
2898 rdata->rx_sparemap = map;
2900 rx_buffer->m_head = m;
2901 rx_buffer->paddr = seg.ds_addr;
2903 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2908 emx_create_rx_ring(struct emx_rxdata *rdata)
2910 device_t dev = rdata->sc->dev;
2911 struct emx_rxbuf *rx_buffer;
2912 int i, error, rsize, nrxd;
2915 * Validate number of receive descriptors. It must not exceed
2916 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2918 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2919 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2920 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2921 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2922 EMX_DEFAULT_RXD, nrxd);
2923 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2925 rdata->num_rx_desc = nrxd;
2929 * Allocate Receive Descriptor ring
2931 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2933 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2934 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2935 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2936 &rdata->rx_desc_paddr);
2937 if (rdata->rx_desc == NULL) {
2938 device_printf(dev, "Unable to allocate rx_desc memory\n");
2942 rsize = __VM_CACHELINE_ALIGN(
2943 sizeof(struct emx_rxbuf) * rdata->num_rx_desc);
2944 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2947 * Create DMA tag for rx buffers
2949 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2950 1, 0, /* alignment, bounds */
2951 BUS_SPACE_MAXADDR, /* lowaddr */
2952 BUS_SPACE_MAXADDR, /* highaddr */
2953 NULL, NULL, /* filter, filterarg */
2954 MCLBYTES, /* maxsize */
2956 MCLBYTES, /* maxsegsize */
2957 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2960 device_printf(dev, "Unable to allocate RX DMA tag\n");
2961 kfree(rdata->rx_buf, M_DEVBUF);
2962 rdata->rx_buf = NULL;
2967 * Create spare DMA map for rx buffers
2969 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2970 &rdata->rx_sparemap);
2972 device_printf(dev, "Unable to create spare RX DMA map\n");
2973 bus_dma_tag_destroy(rdata->rxtag);
2974 kfree(rdata->rx_buf, M_DEVBUF);
2975 rdata->rx_buf = NULL;
2980 * Create DMA maps for rx buffers
2982 for (i = 0; i < rdata->num_rx_desc; i++) {
2983 rx_buffer = &rdata->rx_buf[i];
2985 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2988 device_printf(dev, "Unable to create RX DMA map\n");
2989 emx_destroy_rx_ring(rdata, i);
2997 emx_free_rx_ring(struct emx_rxdata *rdata)
3001 for (i = 0; i < rdata->num_rx_desc; i++) {
3002 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
3004 if (rx_buffer->m_head != NULL) {
3005 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
3006 m_freem(rx_buffer->m_head);
3007 rx_buffer->m_head = NULL;
3011 if (rdata->fmp != NULL)
3012 m_freem(rdata->fmp);
3018 emx_free_tx_ring(struct emx_txdata *tdata)
3022 for (i = 0; i < tdata->num_tx_desc; i++) {
3023 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i];
3025 if (tx_buffer->m_head != NULL)
3026 emx_free_txbuf(tdata, tx_buffer);
3029 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX;
3031 tdata->csum_flags = 0;
3032 tdata->csum_lhlen = 0;
3033 tdata->csum_iphlen = 0;
3034 tdata->csum_thlen = 0;
3035 tdata->csum_mss = 0;
3036 tdata->csum_pktlen = 0;
3038 tdata->tx_dd_head = 0;
3039 tdata->tx_dd_tail = 0;
3040 tdata->tx_nsegs = 0;
3044 emx_init_rx_ring(struct emx_rxdata *rdata)
3048 /* Reset descriptor ring */
3049 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
3051 /* Allocate new ones. */
3052 for (i = 0; i < rdata->num_rx_desc; i++) {
3053 error = emx_newbuf(rdata, i, 1);
3058 /* Setup our descriptor pointers */
3059 rdata->next_rx_desc_to_check = 0;
3065 emx_init_rx_unit(struct emx_softc *sc)
3067 struct ifnet *ifp = &sc->arpcom.ac_if;
3069 uint32_t rctl, itr, rfctl, rxcsum;
3073 * Make sure receives are disabled while setting
3074 * up the descriptor ring
3076 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
3077 /* Do not disable if ever enabled on this hardware */
3078 if (sc->hw.mac.type != e1000_82574)
3079 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
3082 * Set the interrupt throttling rate. Value is calculated
3083 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
3085 if (sc->int_throttle_ceil)
3086 itr = 1000000000 / 256 / sc->int_throttle_ceil;
3089 emx_set_itr(sc, itr);
3091 /* Use extended RX descriptor */
3092 rfctl = E1000_READ_REG(&sc->hw, E1000_RFCTL);
3093 rfctl |= E1000_RFCTL_EXTEN;
3094 /* Disable accelerated ackknowledge */
3095 if (sc->hw.mac.type == e1000_82574)
3096 rfctl |= E1000_RFCTL_ACK_DIS;
3097 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
3100 * Receive Checksum Offload for TCP and UDP
3102 * Checksum offloading is also enabled if multiple receive
3103 * queue is to be supported, since we need it to figure out
3106 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
3107 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
3108 sc->rx_ring_cnt > 1) {
3111 * PCSD must be enabled to enable multiple
3114 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
3117 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
3120 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
3123 * Configure multiple receive queue (RSS)
3125 if (sc->rx_ring_cnt > 1) {
3126 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
3129 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
3130 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
3134 * When we reach here, RSS has already been disabled
3135 * in emx_stop(), so we could safely configure RSS key
3136 * and redirect table.
3142 toeplitz_get_key(key, sizeof(key));
3143 for (i = 0; i < EMX_NRSSRK; ++i) {
3146 rssrk = EMX_RSSRK_VAL(key, i);
3147 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
3149 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
3153 * Configure RSS redirect table.
3155 if_ringmap_rdrtable(sc->rx_rmap, sc->rdr_table,
3159 for (j = 0; j < EMX_NRETA; ++j) {
3162 for (i = 0; i < EMX_RETA_SIZE; ++i) {
3165 q = sc->rdr_table[r] << EMX_RETA_RINGIDX_SHIFT;
3166 reta |= q << (8 * i);
3169 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
3170 E1000_WRITE_REG(&sc->hw, E1000_RETA(j), reta);
3174 * Enable multiple receive queues.
3175 * Enable IPv4 RSS standard hash functions.
3176 * Disable RSS interrupt.
3178 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
3179 E1000_MRQC_ENABLE_RSS_2Q |
3180 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3181 E1000_MRQC_RSS_FIELD_IPV4);
3185 * XXX TEMPORARY WORKAROUND: on some systems with 82573
3186 * long latencies are observed, like Lenovo X60. This
3187 * change eliminates the problem, but since having positive
3188 * values in RDTR is a known source of problems on other
3189 * platforms another solution is being sought.
3191 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
3192 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
3193 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
3196 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3197 struct emx_rxdata *rdata = &sc->rx_data[i];
3200 * Setup the Base and Length of the Rx Descriptor Ring
3202 bus_addr = rdata->rx_desc_paddr;
3203 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
3204 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
3205 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
3206 (uint32_t)(bus_addr >> 32));
3207 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
3208 (uint32_t)bus_addr);
3211 * Setup the HW Rx Head and Tail Descriptor Pointers
3213 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
3214 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
3215 sc->rx_data[i].num_rx_desc - 1);
3218 /* Set PTHRESH for improved jumbo performance */
3219 if (ifp->if_mtu > ETHERMTU && sc->hw.mac.type == e1000_82574) {
3222 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3223 rxdctl = E1000_READ_REG(&sc->hw, E1000_RXDCTL(i));
3224 rxdctl |= 0x20; /* PTHRESH */
3225 rxdctl |= 4 << 8; /* HTHRESH */
3226 rxdctl |= 4 << 16; /* WTHRESH */
3227 rxdctl |= 1 << 24; /* Switch to granularity */
3228 E1000_WRITE_REG(&sc->hw, E1000_RXDCTL(i), rxdctl);
3232 if (sc->hw.mac.type >= e1000_pch2lan) {
3233 if (ifp->if_mtu > ETHERMTU)
3234 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, TRUE);
3236 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, FALSE);
3239 /* Setup the Receive Control Register */
3240 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3241 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3242 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
3243 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3245 /* Make sure VLAN Filters are off */
3246 rctl &= ~E1000_RCTL_VFE;
3248 /* Don't store bad paket */
3249 rctl &= ~E1000_RCTL_SBP;
3252 rctl |= E1000_RCTL_SZ_2048;
3254 if (ifp->if_mtu > ETHERMTU)
3255 rctl |= E1000_RCTL_LPE;
3257 rctl &= ~E1000_RCTL_LPE;
3259 /* Enable Receives */
3260 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
3264 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
3266 struct emx_rxbuf *rx_buffer;
3269 /* Free Receive Descriptor ring */
3270 if (rdata->rx_desc) {
3271 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
3272 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
3273 rdata->rx_desc_dmap);
3274 bus_dma_tag_destroy(rdata->rx_desc_dtag);
3276 rdata->rx_desc = NULL;
3279 if (rdata->rx_buf == NULL)
3282 for (i = 0; i < ndesc; i++) {
3283 rx_buffer = &rdata->rx_buf[i];
3285 KKASSERT(rx_buffer->m_head == NULL);
3286 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
3288 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
3289 bus_dma_tag_destroy(rdata->rxtag);
3291 kfree(rdata->rx_buf, M_DEVBUF);
3292 rdata->rx_buf = NULL;
3296 emx_rxeof(struct emx_rxdata *rdata, int count)
3298 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
3300 emx_rxdesc_t *current_desc;
3302 int i, cpuid = mycpuid;
3304 i = rdata->next_rx_desc_to_check;
3305 current_desc = &rdata->rx_desc[i];
3306 staterr = le32toh(current_desc->rxd_staterr);
3308 if (!(staterr & E1000_RXD_STAT_DD))
3311 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
3312 struct pktinfo *pi = NULL, pi0;
3313 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
3314 struct mbuf *m = NULL;
3319 mp = rx_buf->m_head;
3322 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3323 * needs to access the last received byte in the mbuf.
3325 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
3326 BUS_DMASYNC_POSTREAD);
3328 len = le16toh(current_desc->rxd_length);
3329 if (staterr & E1000_RXD_STAT_EOP) {
3336 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3338 uint32_t mrq, rss_hash;
3341 * Save several necessary information,
3342 * before emx_newbuf() destroy it.
3344 if ((staterr & E1000_RXD_STAT_VP) && eop)
3345 vlan = le16toh(current_desc->rxd_vlan);
3347 mrq = le32toh(current_desc->rxd_mrq);
3348 rss_hash = le32toh(current_desc->rxd_rss);
3350 EMX_RSS_DPRINTF(rdata->sc, 10,
3351 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
3352 rdata->idx, mrq, rss_hash);
3354 if (emx_newbuf(rdata, i, 0) != 0) {
3355 IFNET_STAT_INC(ifp, iqdrops, 1);
3359 /* Assign correct length to the current fragment */
3362 if (rdata->fmp == NULL) {
3363 mp->m_pkthdr.len = len;
3364 rdata->fmp = mp; /* Store the first mbuf */
3368 * Chain mbuf's together
3370 rdata->lmp->m_next = mp;
3371 rdata->lmp = rdata->lmp->m_next;
3372 rdata->fmp->m_pkthdr.len += len;
3376 rdata->fmp->m_pkthdr.rcvif = ifp;
3377 IFNET_STAT_INC(ifp, ipackets, 1);
3379 if (ifp->if_capenable & IFCAP_RXCSUM)
3380 emx_rxcsum(staterr, rdata->fmp);
3382 if (staterr & E1000_RXD_STAT_VP) {
3383 rdata->fmp->m_pkthdr.ether_vlantag =
3385 rdata->fmp->m_flags |= M_VLANTAG;
3391 if (ifp->if_capenable & IFCAP_RSS) {
3392 pi = emx_rssinfo(m, &pi0, mrq,
3395 #ifdef EMX_RSS_DEBUG
3400 IFNET_STAT_INC(ifp, ierrors, 1);
3402 emx_setup_rxdesc(current_desc, rx_buf);
3403 if (rdata->fmp != NULL) {
3404 m_freem(rdata->fmp);
3412 ifp->if_input(ifp, m, pi, cpuid);
3414 /* Advance our pointers to the next descriptor. */
3415 if (++i == rdata->num_rx_desc)
3418 current_desc = &rdata->rx_desc[i];
3419 staterr = le32toh(current_desc->rxd_staterr);
3421 rdata->next_rx_desc_to_check = i;
3423 /* Advance the E1000's Receive Queue "Tail Pointer". */
3425 i = rdata->num_rx_desc - 1;
3426 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3430 emx_enable_intr(struct emx_softc *sc)
3432 uint32_t ims_mask = IMS_ENABLE_MASK;
3434 lwkt_serialize_handler_enable(&sc->main_serialize);
3437 if (sc->hw.mac.type == e1000_82574) {
3438 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3439 ims_mask |= EM_MSIX_MASK;
3442 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3446 emx_disable_intr(struct emx_softc *sc)
3448 if (sc->hw.mac.type == e1000_82574)
3449 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3450 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3452 lwkt_serialize_handler_disable(&sc->main_serialize);
3456 * Bit of a misnomer, what this really means is
3457 * to enable OS management of the system... aka
3458 * to disable special hardware management features
3461 emx_get_mgmt(struct emx_softc *sc)
3463 /* A shared code workaround */
3464 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3465 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3466 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3468 /* disable hardware interception of ARP */
3469 manc &= ~(E1000_MANC_ARP_EN);
3471 /* enable receiving management packets to the host */
3472 manc |= E1000_MANC_EN_MNG2HOST;
3473 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3474 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3475 manc2h |= E1000_MNG2HOST_PORT_623;
3476 manc2h |= E1000_MNG2HOST_PORT_664;
3477 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3479 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3484 * Give control back to hardware management
3485 * controller if there is one.
3488 emx_rel_mgmt(struct emx_softc *sc)
3490 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3491 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3493 /* re-enable hardware interception of ARP */
3494 manc |= E1000_MANC_ARP_EN;
3495 manc &= ~E1000_MANC_EN_MNG2HOST;
3497 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3502 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3503 * For ASF and Pass Through versions of f/w this means that
3504 * the driver is loaded. For AMT version (only with 82573)
3505 * of the f/w this means that the network i/f is open.
3508 emx_get_hw_control(struct emx_softc *sc)
3510 /* Let firmware know the driver has taken over */
3511 if (sc->hw.mac.type == e1000_82573) {
3514 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3515 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3516 swsm | E1000_SWSM_DRV_LOAD);
3520 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3521 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3522 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3524 sc->flags |= EMX_FLAG_HW_CTRL;
3528 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3529 * For ASF and Pass Through versions of f/w this means that the
3530 * driver is no longer loaded. For AMT version (only with 82573)
3531 * of the f/w this means that the network i/f is closed.
3534 emx_rel_hw_control(struct emx_softc *sc)
3536 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3538 sc->flags &= ~EMX_FLAG_HW_CTRL;
3540 /* Let firmware taken over control of h/w */
3541 if (sc->hw.mac.type == e1000_82573) {
3544 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3545 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3546 swsm & ~E1000_SWSM_DRV_LOAD);
3550 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3551 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3552 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3557 emx_is_valid_eaddr(const uint8_t *addr)
3559 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3561 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3568 * Enable PCI Wake On Lan capability
3571 emx_enable_wol(device_t dev)
3573 uint16_t cap, status;
3576 /* First find the capabilities pointer*/
3577 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3579 /* Read the PM Capabilities */
3580 id = pci_read_config(dev, cap, 1);
3581 if (id != PCIY_PMG) /* Something wrong */
3585 * OK, we have the power capabilities,
3586 * so now get the status register
3588 cap += PCIR_POWER_STATUS;
3589 status = pci_read_config(dev, cap, 2);
3590 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3591 pci_write_config(dev, cap, status, 2);
3595 emx_update_stats(struct emx_softc *sc)
3597 struct ifnet *ifp = &sc->arpcom.ac_if;
3599 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3600 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3601 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3602 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3604 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3605 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3606 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3607 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3609 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3610 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3611 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3612 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3613 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3614 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3615 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3616 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3617 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3618 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3619 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3620 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3621 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3622 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3623 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3624 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3625 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3626 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3627 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3628 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3630 /* For the 64-bit byte counters the low dword must be read first. */
3631 /* Both registers clear on the read of the high dword */
3633 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3634 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3636 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3637 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3638 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3639 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3640 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3642 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3643 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3645 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3646 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3647 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3648 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3649 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3650 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3651 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3652 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3653 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3654 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3656 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3657 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3658 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3659 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3660 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3661 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3663 IFNET_STAT_SET(ifp, collisions, sc->stats.colc);
3666 IFNET_STAT_SET(ifp, ierrors,
3667 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc +
3668 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
3671 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol);
3675 emx_print_debug_info(struct emx_softc *sc)
3677 device_t dev = sc->dev;
3678 uint8_t *hw_addr = sc->hw.hw_addr;
3681 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3682 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3683 E1000_READ_REG(&sc->hw, E1000_CTRL),
3684 E1000_READ_REG(&sc->hw, E1000_RCTL));
3685 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3686 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3687 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3688 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3689 sc->hw.fc.high_water, sc->hw.fc.low_water);
3690 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3691 E1000_READ_REG(&sc->hw, E1000_TIDV),
3692 E1000_READ_REG(&sc->hw, E1000_TADV));
3693 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3694 E1000_READ_REG(&sc->hw, E1000_RDTR),
3695 E1000_READ_REG(&sc->hw, E1000_RADV));
3697 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3698 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i,
3699 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
3700 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
3702 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3703 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i,
3704 E1000_READ_REG(&sc->hw, E1000_RDH(i)),
3705 E1000_READ_REG(&sc->hw, E1000_RDT(i)));
3708 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3709 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i,
3710 sc->tx_data[i].num_tx_desc_avail);
3711 device_printf(dev, "TX %d TSO segments = %lu\n", i,
3712 sc->tx_data[i].tso_segments);
3713 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i,
3714 sc->tx_data[i].tso_ctx_reused);
3719 emx_print_hw_stats(struct emx_softc *sc)
3721 device_t dev = sc->dev;
3723 device_printf(dev, "Excessive collisions = %lld\n",
3724 (long long)sc->stats.ecol);
3725 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3726 device_printf(dev, "Symbol errors = %lld\n",
3727 (long long)sc->stats.symerrs);
3729 device_printf(dev, "Sequence errors = %lld\n",
3730 (long long)sc->stats.sec);
3731 device_printf(dev, "Defer count = %lld\n",
3732 (long long)sc->stats.dc);
3733 device_printf(dev, "Missed Packets = %lld\n",
3734 (long long)sc->stats.mpc);
3735 device_printf(dev, "Receive No Buffers = %lld\n",
3736 (long long)sc->stats.rnbc);
3737 /* RLEC is inaccurate on some hardware, calculate our own. */
3738 device_printf(dev, "Receive Length Errors = %lld\n",
3739 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3740 device_printf(dev, "Receive errors = %lld\n",
3741 (long long)sc->stats.rxerrc);
3742 device_printf(dev, "Crc errors = %lld\n",
3743 (long long)sc->stats.crcerrs);
3744 device_printf(dev, "Alignment errors = %lld\n",
3745 (long long)sc->stats.algnerrc);
3746 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3747 (long long)sc->stats.cexterr);
3748 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3749 device_printf(dev, "XON Rcvd = %lld\n",
3750 (long long)sc->stats.xonrxc);
3751 device_printf(dev, "XON Xmtd = %lld\n",
3752 (long long)sc->stats.xontxc);
3753 device_printf(dev, "XOFF Rcvd = %lld\n",
3754 (long long)sc->stats.xoffrxc);
3755 device_printf(dev, "XOFF Xmtd = %lld\n",
3756 (long long)sc->stats.xofftxc);
3757 device_printf(dev, "Good Packets Rcvd = %lld\n",
3758 (long long)sc->stats.gprc);
3759 device_printf(dev, "Good Packets Xmtd = %lld\n",
3760 (long long)sc->stats.gptc);
3764 emx_print_nvm_info(struct emx_softc *sc)
3766 uint16_t eeprom_data;
3769 /* Its a bit crude, but it gets the job done */
3770 kprintf("\nInterface EEPROM Dump:\n");
3771 kprintf("Offset\n0x0000 ");
3772 for (i = 0, j = 0; i < 32; i++, j++) {
3773 if (j == 8) { /* Make the offset block */
3775 kprintf("\n0x00%x0 ",row);
3777 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3778 kprintf("%04x ", eeprom_data);
3784 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3786 struct emx_softc *sc;
3791 error = sysctl_handle_int(oidp, &result, 0, req);
3792 if (error || !req->newptr)
3795 sc = (struct emx_softc *)arg1;
3796 ifp = &sc->arpcom.ac_if;
3798 ifnet_serialize_all(ifp);
3801 emx_print_debug_info(sc);
3804 * This value will cause a hex dump of the
3805 * first 32 16-bit words of the EEPROM to
3809 emx_print_nvm_info(sc);
3811 ifnet_deserialize_all(ifp);
3817 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3822 error = sysctl_handle_int(oidp, &result, 0, req);
3823 if (error || !req->newptr)
3827 struct emx_softc *sc = (struct emx_softc *)arg1;
3828 struct ifnet *ifp = &sc->arpcom.ac_if;
3830 ifnet_serialize_all(ifp);
3831 emx_print_hw_stats(sc);
3832 ifnet_deserialize_all(ifp);
3838 emx_add_sysctl(struct emx_softc *sc)
3840 struct sysctl_ctx_list *ctx;
3841 struct sysctl_oid *tree;
3845 ctx = device_get_sysctl_ctx(sc->dev);
3846 tree = device_get_sysctl_tree(sc->dev);
3847 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3848 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3849 emx_sysctl_debug_info, "I", "Debug Information");
3851 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3852 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3853 emx_sysctl_stats, "I", "Statistics");
3855 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3856 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0,
3858 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3859 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0,
3862 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3863 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3864 emx_sysctl_int_throttle, "I", "interrupt throttling rate");
3865 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3866 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3867 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt");
3868 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3869 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3870 emx_sysctl_tx_wreg_nsegs, "I",
3871 "# segments sent before write to hardware register");
3873 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3874 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0,
3876 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3877 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0,
3879 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3880 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
3881 "# of TX rings used");
3883 #ifdef IFPOLL_ENABLE
3884 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3885 OID_AUTO, "tx_poll_cpumap", CTLTYPE_OPAQUE | CTLFLAG_RD,
3886 sc->tx_rmap, 0, if_ringmap_cpumap_sysctl, "I",
3887 "TX polling CPU map");
3888 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3889 OID_AUTO, "rx_poll_cpumap", CTLTYPE_OPAQUE | CTLFLAG_RD,
3890 sc->rx_rmap, 0, if_ringmap_cpumap_sysctl, "I",
3891 "RX polling CPU map");
3894 #ifdef EMX_RSS_DEBUG
3895 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3896 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3897 0, "RSS debug level");
3898 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3899 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i);
3900 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3901 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts,
3905 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3906 #ifdef EMX_TSS_DEBUG
3907 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i);
3908 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3909 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts,
3913 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_nmbuf", i);
3914 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3915 pkt_desc, CTLFLAG_RD, &sc->tx_data[i].tx_nmbuf, 0,
3916 "# of pending TX mbufs");
3917 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_gc", i);
3918 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3919 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_gc,
3925 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3927 struct emx_softc *sc = (void *)arg1;
3928 struct ifnet *ifp = &sc->arpcom.ac_if;
3929 int error, throttle;
3931 throttle = sc->int_throttle_ceil;
3932 error = sysctl_handle_int(oidp, &throttle, 0, req);
3933 if (error || req->newptr == NULL)
3935 if (throttle < 0 || throttle > 1000000000 / 256)
3940 * Set the interrupt throttling rate in 256ns increments,
3941 * recalculate sysctl value assignment to get exact frequency.
3943 throttle = 1000000000 / 256 / throttle;
3945 /* Upper 16bits of ITR is reserved and should be zero */
3946 if (throttle & 0xffff0000)
3950 ifnet_serialize_all(ifp);
3953 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3955 sc->int_throttle_ceil = 0;
3957 if (ifp->if_flags & IFF_RUNNING)
3958 emx_set_itr(sc, throttle);
3960 ifnet_deserialize_all(ifp);
3963 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3964 sc->int_throttle_ceil);
3970 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3972 struct emx_softc *sc = (void *)arg1;
3973 struct ifnet *ifp = &sc->arpcom.ac_if;
3974 struct emx_txdata *tdata = &sc->tx_data[0];
3977 segs = tdata->tx_intr_nsegs;
3978 error = sysctl_handle_int(oidp, &segs, 0, req);
3979 if (error || req->newptr == NULL)
3984 ifnet_serialize_all(ifp);
3987 * Don't allow tx_intr_nsegs to become:
3988 * o Less the oact_tx_desc
3989 * o Too large that no TX desc will cause TX interrupt to
3990 * be generated (OACTIVE will never recover)
3991 * o Too small that will cause tx_dd[] overflow
3993 if (segs < tdata->oact_tx_desc ||
3994 segs >= tdata->num_tx_desc - tdata->oact_tx_desc ||
3995 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) {
4001 for (i = 0; i < sc->tx_ring_cnt; ++i)
4002 sc->tx_data[i].tx_intr_nsegs = segs;
4005 ifnet_deserialize_all(ifp);
4011 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
4013 struct emx_softc *sc = (void *)arg1;
4014 struct ifnet *ifp = &sc->arpcom.ac_if;
4015 int error, nsegs, i;
4017 nsegs = sc->tx_data[0].tx_wreg_nsegs;
4018 error = sysctl_handle_int(oidp, &nsegs, 0, req);
4019 if (error || req->newptr == NULL)
4022 ifnet_serialize_all(ifp);
4023 for (i = 0; i < sc->tx_ring_cnt; ++i)
4024 sc->tx_data[i].tx_wreg_nsegs =nsegs;
4025 ifnet_deserialize_all(ifp);
4031 emx_dma_alloc(struct emx_softc *sc)
4036 * Create top level busdma tag
4038 error = bus_dma_tag_create(NULL, 1, 0,
4039 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4041 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
4042 0, &sc->parent_dtag);
4044 device_printf(sc->dev, "could not create top level DMA tag\n");
4049 * Allocate transmit descriptors ring and buffers
4051 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4052 error = emx_create_tx_ring(&sc->tx_data[i]);
4054 device_printf(sc->dev,
4055 "Could not setup transmit structures\n");
4061 * Allocate receive descriptors ring and buffers
4063 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4064 error = emx_create_rx_ring(&sc->rx_data[i]);
4066 device_printf(sc->dev,
4067 "Could not setup receive structures\n");
4075 emx_dma_free(struct emx_softc *sc)
4079 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4080 emx_destroy_tx_ring(&sc->tx_data[i],
4081 sc->tx_data[i].num_tx_desc);
4084 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4085 emx_destroy_rx_ring(&sc->rx_data[i],
4086 sc->rx_data[i].num_rx_desc);
4089 /* Free top level busdma tag */
4090 if (sc->parent_dtag != NULL)
4091 bus_dma_tag_destroy(sc->parent_dtag);
4095 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
4097 struct emx_softc *sc = ifp->if_softc;
4099 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz);
4103 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4105 struct emx_softc *sc = ifp->if_softc;
4107 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz);
4111 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4113 struct emx_softc *sc = ifp->if_softc;
4115 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz);
4119 emx_serialize_skipmain(struct emx_softc *sc)
4121 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
4125 emx_deserialize_skipmain(struct emx_softc *sc)
4127 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
4133 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
4134 boolean_t serialized)
4136 struct emx_softc *sc = ifp->if_softc;
4138 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
4142 #endif /* INVARIANTS */
4144 #ifdef IFPOLL_ENABLE
4147 emx_npoll_status(struct ifnet *ifp)
4149 struct emx_softc *sc = ifp->if_softc;
4152 ASSERT_SERIALIZED(&sc->main_serialize);
4154 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4155 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4156 callout_stop(&sc->timer);
4157 sc->hw.mac.get_link_status = 1;
4158 emx_update_link_status(sc);
4159 callout_reset(&sc->timer, hz, emx_timer, sc);
4164 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
4166 struct emx_txdata *tdata = arg;
4168 ASSERT_SERIALIZED(&tdata->tx_serialize);
4171 emx_try_txgc(tdata, 1);
4175 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
4177 struct emx_rxdata *rdata = arg;
4179 ASSERT_SERIALIZED(&rdata->rx_serialize);
4181 emx_rxeof(rdata, cycle);
4185 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
4187 struct emx_softc *sc = ifp->if_softc;
4190 ASSERT_IFNET_SERIALIZED_ALL(ifp);
4195 info->ifpi_status.status_func = emx_npoll_status;
4196 info->ifpi_status.serializer = &sc->main_serialize;
4198 txr_cnt = emx_get_txring_inuse(sc, TRUE);
4199 for (i = 0; i < txr_cnt; ++i) {
4200 struct emx_txdata *tdata = &sc->tx_data[i];
4202 cpu = if_ringmap_cpumap(sc->tx_rmap, i);
4203 KKASSERT(cpu < netisr_ncpus);
4204 info->ifpi_tx[cpu].poll_func = emx_npoll_tx;
4205 info->ifpi_tx[cpu].arg = tdata;
4206 info->ifpi_tx[cpu].serializer = &tdata->tx_serialize;
4207 ifsq_set_cpuid(tdata->ifsq, cpu);
4210 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4211 struct emx_rxdata *rdata = &sc->rx_data[i];
4213 cpu = if_ringmap_cpumap(sc->rx_rmap, i);
4214 KKASSERT(cpu < netisr_ncpus);
4215 info->ifpi_rx[cpu].poll_func = emx_npoll_rx;
4216 info->ifpi_rx[cpu].arg = rdata;
4217 info->ifpi_rx[cpu].serializer = &rdata->rx_serialize;
4220 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4221 struct emx_txdata *tdata = &sc->tx_data[i];
4223 ifsq_set_cpuid(tdata->ifsq,
4224 rman_get_cpuid(sc->intr_res));
4227 if (ifp->if_flags & IFF_RUNNING)
4231 #endif /* IFPOLL_ENABLE */
4234 emx_set_itr(struct emx_softc *sc, uint32_t itr)
4236 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
4237 if (sc->hw.mac.type == e1000_82574) {
4241 * When using MSIX interrupts we need to
4242 * throttle using the EITR register
4244 for (i = 0; i < 4; ++i)
4245 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
4250 * Disable the L0s, 82574L Errata #20
4253 emx_disable_aspm(struct emx_softc *sc)
4255 uint16_t link_cap, link_ctrl, disable;
4256 uint8_t pcie_ptr, reg;
4257 device_t dev = sc->dev;
4259 switch (sc->hw.mac.type) {
4264 * 82573 specification update
4265 * errata #8 disable L0s
4266 * errata #41 disable L1
4268 * 82571/82572 specification update
4269 # errata #13 disable L1
4270 * errata #68 disable L0s
4272 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4277 * 82574 specification update errata #20
4279 * There is no need to disable L1
4281 disable = PCIEM_LNKCTL_ASPM_L0S;
4288 pcie_ptr = pci_get_pciecap_ptr(dev);
4292 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4293 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4297 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
4299 reg = pcie_ptr + PCIER_LINKCTRL;
4300 link_ctrl = pci_read_config(dev, reg, 2);
4301 link_ctrl &= ~disable;
4302 pci_write_config(dev, reg, link_ctrl, 2);
4306 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp)
4308 int iphlen, hoff, thoff, ex = 0;
4313 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4315 iphlen = m->m_pkthdr.csum_iphlen;
4316 thoff = m->m_pkthdr.csum_thlen;
4317 hoff = m->m_pkthdr.csum_lhlen;
4319 KASSERT(iphlen > 0, ("invalid ip hlen"));
4320 KASSERT(thoff > 0, ("invalid tcp hlen"));
4321 KASSERT(hoff > 0, ("invalid ether hlen"));
4323 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX)
4326 if (m->m_len < hoff + iphlen + thoff + ex) {
4327 m = m_pullup(m, hoff + iphlen + thoff + ex);
4334 ip = mtodoff(m, struct ip *, hoff);
4341 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp,
4342 uint32_t *txd_upper, uint32_t *txd_lower)
4344 struct e1000_context_desc *TXD;
4345 int hoff, iphlen, thoff, hlen;
4346 int mss, pktlen, curr_txd;
4348 #ifdef EMX_TSO_DEBUG
4349 tdata->tso_segments++;
4352 iphlen = mp->m_pkthdr.csum_iphlen;
4353 thoff = mp->m_pkthdr.csum_thlen;
4354 hoff = mp->m_pkthdr.csum_lhlen;
4355 mss = mp->m_pkthdr.tso_segsz;
4356 pktlen = mp->m_pkthdr.len;
4358 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
4359 tdata->csum_flags == CSUM_TSO &&
4360 tdata->csum_iphlen == iphlen &&
4361 tdata->csum_lhlen == hoff &&
4362 tdata->csum_thlen == thoff &&
4363 tdata->csum_mss == mss &&
4364 tdata->csum_pktlen == pktlen) {
4365 *txd_upper = tdata->csum_txd_upper;
4366 *txd_lower = tdata->csum_txd_lower;
4367 #ifdef EMX_TSO_DEBUG
4368 tdata->tso_ctx_reused++;
4372 hlen = hoff + iphlen + thoff;
4375 * Setup a new TSO context.
4378 curr_txd = tdata->next_avail_tx_desc;
4379 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
4381 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4382 E1000_TXD_DTYP_D | /* Data descr type */
4383 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4385 /* IP and/or TCP header checksum calculation and insertion. */
4386 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4389 * Start offset for header checksum calculation.
4390 * End offset for header checksum calculation.
4391 * Offset of place put the checksum.
4393 TXD->lower_setup.ip_fields.ipcss = hoff;
4394 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4395 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4398 * Start offset for payload checksum calculation.
4399 * End offset for payload checksum calculation.
4400 * Offset of place to put the checksum.
4402 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4403 TXD->upper_setup.tcp_fields.tucse = 0;
4404 TXD->upper_setup.tcp_fields.tucso =
4405 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4408 * Payload size per packet w/o any headers.
4409 * Length of all headers up to payload.
4411 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4412 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4413 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4414 E1000_TXD_CMD_DEXT | /* Extended descr */
4415 E1000_TXD_CMD_TSE | /* TSE context */
4416 E1000_TXD_CMD_IP | /* Do IP csum */
4417 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4418 (pktlen - hlen)); /* Total len */
4420 /* Save the information for this TSO context */
4421 tdata->csum_flags = CSUM_TSO;
4422 tdata->csum_lhlen = hoff;
4423 tdata->csum_iphlen = iphlen;
4424 tdata->csum_thlen = thoff;
4425 tdata->csum_mss = mss;
4426 tdata->csum_pktlen = pktlen;
4427 tdata->csum_txd_upper = *txd_upper;
4428 tdata->csum_txd_lower = *txd_lower;
4430 if (++curr_txd == tdata->num_tx_desc)
4433 KKASSERT(tdata->num_tx_desc_avail > 0);
4434 tdata->num_tx_desc_avail--;
4436 tdata->next_avail_tx_desc = curr_txd;
4441 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling)
4444 return sc->tx_ring_cnt;
4450 * Remove all descriptors from the TX ring.
4452 * We want to clear all pending descriptors from the TX ring. Zeroing
4453 * happens when the HW reads the regs. We assign the ring itself as
4454 * the data of the next descriptor. We don't care about the data we
4455 * are about to reset the HW.
4458 emx_flush_tx_ring(struct emx_softc *sc)
4460 struct e1000_hw *hw = &sc->hw;
4464 tctl = E1000_READ_REG(hw, E1000_TCTL);
4465 E1000_WRITE_REG(hw, E1000_TCTL, tctl | E1000_TCTL_EN);
4467 for (i = 0; i < sc->tx_ring_inuse; ++i) {
4468 struct emx_txdata *tdata = &sc->tx_data[i];
4469 struct e1000_tx_desc *txd;
4471 if (E1000_READ_REG(hw, E1000_TDLEN(i)) == 0)
4474 txd = &tdata->tx_desc_base[tdata->next_avail_tx_desc++];
4475 if (tdata->next_avail_tx_desc == tdata->num_tx_desc)
4476 tdata->next_avail_tx_desc = 0;
4478 /* Just use the ring as a dummy buffer addr */
4479 txd->buffer_addr = tdata->tx_desc_paddr;
4480 txd->lower.data = htole32(E1000_TXD_CMD_IFCS | 512);
4481 txd->upper.data = 0;
4483 E1000_WRITE_REG(hw, E1000_TDT(i), tdata->next_avail_tx_desc);
4489 * Remove all descriptors from the RX rings.
4491 * Mark all descriptors in the RX rings as consumed and disable the RX rings.
4494 emx_flush_rx_ring(struct emx_softc *sc)
4496 struct e1000_hw *hw = &sc->hw;
4500 rctl = E1000_READ_REG(hw, E1000_RCTL);
4501 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
4502 E1000_WRITE_FLUSH(hw);
4505 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4508 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
4509 /* Zero the lower 14 bits (prefetch and host thresholds) */
4510 rxdctl &= 0xffffc000;
4512 * Update thresholds: prefetch threshold to 31, host threshold
4513 * to 1 and make sure the granularity is "descriptors" and not
4516 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
4517 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
4520 /* Momentarily enable the RX rings for the changes to take effect */
4521 E1000_WRITE_REG(hw, E1000_RCTL, rctl | E1000_RCTL_EN);
4522 E1000_WRITE_FLUSH(hw);
4524 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
4528 * Remove all descriptors from the descriptor rings.
4530 * In i219, the descriptor rings must be emptied before resetting the HW
4531 * or before changing the device state to D3 during runtime (runtime PM).
4533 * Failure to do this will cause the HW to enter a unit hang state which
4534 * can only be released by PCI reset on the device.
4537 emx_flush_txrx_ring(struct emx_softc *sc)
4539 struct e1000_hw *hw = &sc->hw;
4540 device_t dev = sc->dev;
4541 uint16_t hang_state;
4542 uint32_t fext_nvm11, tdlen;
4546 * First, disable MULR fix in FEXTNVM11.
4548 fext_nvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
4549 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
4550 E1000_WRITE_REG(hw, E1000_FEXTNVM11, fext_nvm11);
4553 * Do nothing if we're not in faulty state, or if the queue is
4557 for (i = 0; i < sc->tx_ring_inuse; ++i)
4558 tdlen += E1000_READ_REG(hw, E1000_TDLEN(i));
4559 hang_state = pci_read_config(dev, EMX_PCICFG_DESC_RING_STATUS, 2);
4560 if ((hang_state & EMX_FLUSH_DESC_REQUIRED) && tdlen)
4561 emx_flush_tx_ring(sc);
4564 * Recheck, maybe the fault is caused by the RX ring.
4566 hang_state = pci_read_config(dev, EMX_PCICFG_DESC_RING_STATUS, 2);
4567 if (hang_state & EMX_FLUSH_DESC_REQUIRED)
4568 emx_flush_rx_ring(sc);