2 * Copyright (c) 2004, Joerg Sonnenberger <joerg@bec.de>
4 * Copyright (c) 1994,1995 Stefan Esser. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * $DragonFly: src/sys/bus/pci/pci_isab.c,v 1.6 2006/01/22 04:10:32 swildner Exp $
34 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/malloc.h>
38 #include <sys/module.h>
40 #include <sys/systm.h>
42 #include <machine/resource.h>
44 #include <bus/isa/isavar.h>
45 #include <bus/pci/pcivar.h>
46 #include <bus/pci/pcireg.h>
48 #include "pcib_private.h"
50 static void chipset_attach(device_t dev, int unit);
62 #define M_XX 0 /* end of list */
63 #define M_EQ 1 /* mask and return true if equal */
64 #define M_NE 2 /* mask and return true if not equal */
65 #define M_TR 3 /* don't read config, always true */
66 #define M_EN 4 /* mask and print "enabled" if true, "disabled" if false */
67 #define M_NN 5 /* opposite sense of M_EN */
69 static const struct condmsg conf82425ex[] =
71 { 0x00, 0x00, 0x00, M_TR, "\tClock " },
72 { 0x50, 0x06, 0x00, M_EQ, "25" },
73 { 0x50, 0x06, 0x02, M_EQ, "33" },
74 { 0x50, 0x04, 0x04, M_EQ, "??", },
75 { 0x00, 0x00, 0x00, M_TR, "MHz, L1 Cache " },
76 { 0x50, 0x01, 0x00, M_EQ, "Disabled\n" },
77 { 0x50, 0x09, 0x01, M_EQ, "Write-through\n" },
78 { 0x50, 0x09, 0x09, M_EQ, "Write-back\n" },
80 { 0x00, 0x00, 0x00, M_TR, "\tL2 Cache " },
81 { 0x52, 0x07, 0x00, M_EQ, "Disabled" },
82 { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-through" },
83 { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-through" },
84 { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-through" },
85 { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-through" },
86 { 0x52, 0x0f, 0x01, M_EQ, "64KB Write-back" },
87 { 0x52, 0x0f, 0x02, M_EQ, "128KB Write-back" },
88 { 0x52, 0x0f, 0x03, M_EQ, "256KB Write-back" },
89 { 0x52, 0x0f, 0x04, M_EQ, "512KB Write-back" },
90 { 0x53, 0x01, 0x00, M_EQ, ", 3-" },
91 { 0x53, 0x01, 0x01, M_EQ, ", 2-" },
92 { 0x53, 0x06, 0x00, M_EQ, "3-3-3" },
93 { 0x53, 0x06, 0x02, M_EQ, "2-2-2" },
94 { 0x53, 0x06, 0x04, M_EQ, "1-1-1" },
95 { 0x53, 0x06, 0x06, M_EQ, "?-?-?" },
96 { 0x53, 0x18, 0x00, M_EQ, "/4-2-2-2\n" },
97 { 0x53, 0x18, 0x08, M_EQ, "/3-2-2-2\n" },
98 { 0x53, 0x18, 0x10, M_EQ, "/?-?-?-?\n" },
99 { 0x53, 0x18, 0x18, M_EQ, "/2-1-1-1\n" },
101 { 0x56, 0x00, 0x00, M_TR, "\tDRAM: " },
102 { 0x56, 0x02, 0x02, M_EQ, "Fast Code Read, " },
103 { 0x56, 0x04, 0x04, M_EQ, "Fast Data Read, " },
104 { 0x56, 0x08, 0x08, M_EQ, "Fast Write, " },
105 { 0x57, 0x20, 0x20, M_EQ, "Pipelined CAS" },
106 { 0x57, 0x2e, 0x00, M_NE, "\n\t" },
107 { 0x57, 0x00, 0x00, M_TR, "Timing: RAS: " },
108 { 0x57, 0x07, 0x00, M_EQ, "4" },
109 { 0x57, 0x07, 0x01, M_EQ, "3" },
110 { 0x57, 0x07, 0x02, M_EQ, "2" },
111 { 0x57, 0x07, 0x04, M_EQ, "1.5" },
112 { 0x57, 0x07, 0x05, M_EQ, "1" },
113 { 0x57, 0x00, 0x00, M_TR, " Clocks, CAS Read: " },
114 { 0x57, 0x18, 0x00, M_EQ, "3/1", },
115 { 0x57, 0x18, 0x00, M_EQ, "2/1", },
116 { 0x57, 0x18, 0x00, M_EQ, "1.5/0.5", },
117 { 0x57, 0x18, 0x00, M_EQ, "1/1", },
118 { 0x57, 0x00, 0x00, M_TR, ", CAS Write: " },
119 { 0x57, 0x20, 0x00, M_EQ, "2/1", },
120 { 0x57, 0x20, 0x20, M_EQ, "1/1", },
121 { 0x57, 0x00, 0x00, M_TR, "\n" },
123 { 0x40, 0x01, 0x01, M_EQ, "\tCPU-to-PCI Byte Merging\n" },
124 { 0x40, 0x02, 0x02, M_EQ, "\tCPU-to-PCI Bursting\n" },
125 { 0x40, 0x04, 0x04, M_EQ, "\tPCI Posted Writes\n" },
126 { 0x40, 0x20, 0x00, M_EQ, "\tDRAM Parity Disabled\n" },
128 { 0x48, 0x03, 0x01, M_EQ, "\tPCI IDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" },
129 { 0x48, 0x03, 0x02, M_EQ, "\tPCI IDE controller: Secondary (170h-177h,376h,377h)" },
130 { 0x4d, 0x01, 0x01, M_EQ, "\tRTC (70-77h)\n" },
131 { 0x4d, 0x02, 0x02, M_EQ, "\tKeyboard (60,62,64,66h)\n" },
132 { 0x4d, 0x08, 0x08, M_EQ, "\tIRQ12/M Mouse Function\n" },
138 static const struct condmsg conf82424zx[] =
140 { 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
141 { 0x50, 0xe0, 0x00, M_EQ, "486DX" },
142 { 0x50, 0xe0, 0x20, M_EQ, "486SX" },
143 { 0x50, 0xe0, 0x40, M_EQ, "486DX2 or 486DX4" },
144 { 0x50, 0xe0, 0x80, M_EQ, "Overdrive (writeback)" },
146 { 0x00, 0x00, 0x00, M_TR, ", bus=" },
147 { 0x50, 0x03, 0x00, M_EQ, "25MHz" },
148 { 0x50, 0x03, 0x01, M_EQ, "33MHz" },
149 { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
150 { 0x53, 0x01, 0x00, M_EQ, "OFF" },
151 { 0x53, 0x01, 0x01, M_EQ, "ON" },
153 { 0x56, 0x30, 0x00, M_NE, "\n\tWarning:" },
154 { 0x56, 0x20, 0x00, M_NE, " NO cache parity!" },
155 { 0x56, 0x10, 0x00, M_NE, " NO DRAM parity!" },
156 { 0x55, 0x04, 0x04, M_EQ, "\n\tWarning: refresh OFF! " },
158 { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
159 { 0x52, 0x01, 0x00, M_EQ, "None" },
160 { 0x52, 0xc1, 0x01, M_EQ, "64KB" },
161 { 0x52, 0xc1, 0x41, M_EQ, "128KB" },
162 { 0x52, 0xc1, 0x81, M_EQ, "256KB" },
163 { 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
164 { 0x52, 0x03, 0x01, M_EQ, " writethrough" },
165 { 0x52, 0x03, 0x03, M_EQ, " writeback" },
167 { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
168 { 0x52, 0x05, 0x01, M_EQ, "3-1-1-1" },
169 { 0x52, 0x05, 0x05, M_EQ, "2-1-1-1" },
171 { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
172 { 0x55, 0x43, 0x00, M_NE, " page mode" },
173 { 0x55, 0x02, 0x02, M_EQ, " code fetch" },
174 { 0x55, 0x43, 0x43, M_EQ, "," },
175 { 0x55, 0x43, 0x42, M_EQ, " and" },
176 { 0x55, 0x40, 0x40, M_EQ, " read" },
177 { 0x55, 0x03, 0x03, M_EQ, " and" },
178 { 0x55, 0x43, 0x41, M_EQ, " and" },
179 { 0x55, 0x01, 0x01, M_EQ, " write" },
180 { 0x55, 0x43, 0x00, M_NE, "," },
182 { 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
183 { 0x55, 0x20, 0x00, M_EQ, "X-2-2-2" },
184 { 0x55, 0x20, 0x20, M_EQ, "X-1-2-1" },
186 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
187 { 0x53, 0x02, 0x00, M_NE, "ON" },
188 { 0x53, 0x02, 0x00, M_EQ, "OFF" },
189 { 0x00, 0x00, 0x00, M_TR, ", burst mode " },
190 { 0x54, 0x02, 0x00, M_NE, "ON" },
191 { 0x54, 0x02, 0x00, M_EQ, "OFF" },
192 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
193 { 0x54, 0x01, 0x00, M_NE, "ON" },
194 { 0x54, 0x01, 0x00, M_EQ, "OFF" },
196 { 0x00, 0x00, 0x00, M_TR, "\n" },
202 static const struct condmsg conf82434lx[] =
204 { 0x00, 0x00, 0x00, M_TR, "\tCPU: " },
205 { 0x50, 0xe3, 0x82, M_EQ, "Pentium, 60MHz" },
206 { 0x50, 0xe3, 0x83, M_EQ, "Pentium, 66MHz" },
207 { 0x50, 0xe3, 0xa2, M_EQ, "Pentium, 90MHz" },
208 { 0x50, 0xe3, 0xa3, M_EQ, "Pentium, 100MHz" },
209 { 0x50, 0xc2, 0x82, M_NE, "(unknown)" },
210 { 0x50, 0x04, 0x00, M_EQ, " (primary cache OFF)" },
212 { 0x53, 0x01, 0x01, M_TR, ", CPU->Memory posting "},
213 { 0x53, 0x01, 0x01, M_NE, "OFF" },
214 { 0x53, 0x01, 0x01, M_EQ, "ON" },
216 { 0x53, 0x08, 0x00, M_NE, ", read around write"},
218 { 0x70, 0x04, 0x00, M_EQ, "\n\tWarning: Cache parity disabled!" },
219 { 0x57, 0x20, 0x00, M_NE, "\n\tWarning: DRAM parity mask!" },
220 { 0x57, 0x01, 0x00, M_EQ, "\n\tWarning: refresh OFF! " },
222 { 0x00, 0x00, 0x00, M_TR, "\n\tCache: " },
223 { 0x52, 0x01, 0x00, M_EQ, "None" },
224 { 0x52, 0x81, 0x01, M_EQ, "" },
225 { 0x52, 0xc1, 0x81, M_EQ, "256KB" },
226 { 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
227 { 0x52, 0x03, 0x01, M_EQ, " writethrough" },
228 { 0x52, 0x03, 0x03, M_EQ, " writeback" },
230 { 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
231 { 0x52, 0x21, 0x01, M_EQ, "3-2-2-2/4-2-2-2" },
232 { 0x52, 0x21, 0x21, M_EQ, "3-1-1-1" },
234 { 0x52, 0x01, 0x01, M_EQ, "\n\tCache flags: " },
235 { 0x52, 0x11, 0x11, M_EQ, " cache-all" },
236 { 0x52, 0x09, 0x09, M_EQ, " byte-control" },
237 { 0x52, 0x05, 0x05, M_EQ, " powersaver" },
239 { 0x00, 0x00, 0x00, M_TR, "\n\tDRAM:" },
240 { 0x57, 0x10, 0x00, M_EQ, " page mode" },
242 { 0x00, 0x00, 0x00, M_TR, " memory clocks=" },
243 { 0x57, 0xc0, 0x00, M_EQ, "X-4-4-4 (70ns)" },
244 { 0x57, 0xc0, 0x40, M_EQ, "X-4-4-4/X-3-3-3 (60ns)" },
245 { 0x57, 0xc0, 0x80, M_EQ, "???" },
246 { 0x57, 0xc0, 0xc0, M_EQ, "X-3-3-3 (50ns)" },
247 { 0x58, 0x02, 0x02, M_EQ, ", RAS-wait" },
248 { 0x58, 0x01, 0x01, M_EQ, ", CAS-wait" },
250 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU->PCI: posting " },
251 { 0x53, 0x02, 0x02, M_EQ, "ON" },
252 { 0x53, 0x02, 0x00, M_EQ, "OFF" },
253 { 0x00, 0x00, 0x00, M_TR, ", burst mode " },
254 { 0x54, 0x02, 0x00, M_NE, "ON" },
255 { 0x54, 0x02, 0x00, M_EQ, "OFF" },
256 { 0x54, 0x04, 0x00, M_TR, ", PCI clocks=" },
257 { 0x54, 0x04, 0x00, M_EQ, "2-2-2-2" },
258 { 0x54, 0x04, 0x00, M_NE, "2-1-1-1" },
259 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI->Memory: posting " },
260 { 0x54, 0x01, 0x00, M_NE, "ON" },
261 { 0x54, 0x01, 0x00, M_EQ, "OFF" },
263 { 0x57, 0x01, 0x01, M_EQ, "\n\tRefresh:" },
264 { 0x57, 0x03, 0x03, M_EQ, " CAS#/RAS#(Hidden)" },
265 { 0x57, 0x03, 0x01, M_EQ, " RAS#Only" },
266 { 0x57, 0x05, 0x05, M_EQ, " BurstOf4" },
268 { 0x00, 0x00, 0x00, M_TR, "\n" },
274 static const struct condmsg conf82378[] =
276 { 0x00, 0x00, 0x00, M_TR, "\tBus Modes:" },
277 { 0x41, 0x04, 0x04, M_EQ, " Bus Park," },
278 { 0x41, 0x02, 0x02, M_EQ, " Bus Lock," },
279 { 0x41, 0x02, 0x00, M_EQ, " Resource Lock," },
280 { 0x41, 0x01, 0x01, M_EQ, " GAT" },
281 { 0x4d, 0x20, 0x20, M_EQ, "\n\tCoprocessor errors enabled" },
282 { 0x4d, 0x10, 0x10, M_EQ, "\n\tMouse function enabled" },
284 { 0x4e, 0x30, 0x10, M_EQ, "\n\tIDE controller: Primary (1F0h-1F7h,3F6h,3F7h)" },
285 { 0x4e, 0x30, 0x30, M_EQ, "\n\tIDE controller: Secondary (170h-177h,376h,377h)" },
286 { 0x4e, 0x28, 0x08, M_EQ, "\n\tFloppy controller: 3F0h,3F1h " },
287 { 0x4e, 0x24, 0x04, M_EQ, "\n\tFloppy controller: 3F2h-3F7h " },
288 { 0x4e, 0x28, 0x28, M_EQ, "\n\tFloppy controller: 370h,371h " },
289 { 0x4e, 0x24, 0x24, M_EQ, "\n\tFloppy controller: 372h-377h " },
290 { 0x4e, 0x02, 0x02, M_EQ, "\n\tKeyboard controller: 60h,62h,64h,66h" },
291 { 0x4e, 0x01, 0x01, M_EQ, "\n\tRTC: 70h-77h" },
293 { 0x4f, 0x80, 0x80, M_EQ, "\n\tConfiguration RAM: 0C00h,0800h-08FFh" },
294 { 0x4f, 0x40, 0x40, M_EQ, "\n\tPort 92: enabled" },
295 { 0x4f, 0x03, 0x00, M_EQ, "\n\tSerial Port A: COM1 (3F8h-3FFh)" },
296 { 0x4f, 0x03, 0x01, M_EQ, "\n\tSerial Port A: COM2 (2F8h-2FFh)" },
297 { 0x4f, 0x0c, 0x00, M_EQ, "\n\tSerial Port B: COM1 (3F8h-3FFh)" },
298 { 0x4f, 0x0c, 0x04, M_EQ, "\n\tSerial Port B: COM2 (2F8h-2FFh)" },
299 { 0x4f, 0x30, 0x00, M_EQ, "\n\tParallel Port: LPT1 (3BCh-3BFh)" },
300 { 0x4f, 0x30, 0x04, M_EQ, "\n\tParallel Port: LPT2 (378h-37Fh)" },
301 { 0x4f, 0x30, 0x20, M_EQ, "\n\tParallel Port: LPT3 (278h-27Fh)" },
302 { 0x00, 0x00, 0x00, M_TR, "\n" },
308 static const struct condmsg conf82437fx[] =
310 /* PCON -- PCI Control Register */
311 { 0x00, 0x00, 0x00, M_TR, "\tCPU Inactivity timer: " },
312 { 0x50, 0xe0, 0xe0, M_EQ, "8" },
313 { 0x50, 0xe0, 0xd0, M_EQ, "7" },
314 { 0x50, 0xe0, 0xc0, M_EQ, "6" },
315 { 0x50, 0xe0, 0xb0, M_EQ, "5" },
316 { 0x50, 0xe0, 0xa0, M_EQ, "4" },
317 { 0x50, 0xe0, 0x90, M_EQ, "3" },
318 { 0x50, 0xe0, 0x80, M_EQ, "2" },
319 { 0x50, 0xe0, 0x00, M_EQ, "1" },
320 { 0x00, 0x00, 0x00, M_TR, " clocks\n\tPeer Concurrency: " },
321 { 0x50, 0x08, 0x08, M_EN, 0 },
322 { 0x00, 0x00, 0x00, M_TR, "\n\tCPU-to-PCI Write Bursting: " },
323 { 0x50, 0x04, 0x00, M_NN, 0 },
324 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Streaming: " },
325 { 0x50, 0x02, 0x00, M_NN, 0 },
326 { 0x00, 0x00, 0x00, M_TR, "\n\tBus Concurrency: " },
327 { 0x50, 0x01, 0x00, M_NN, 0 },
329 /* CC -- Cache Control Regsiter */
330 { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
331 { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
332 { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
333 { 0x52, 0xc0, 0x00, M_EQ, " NO" },
334 { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
335 { 0x52, 0x30, 0x10, M_EQ, " burst" },
336 { 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
337 { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
338 { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
339 { 0x52, 0x01, 0x00, M_EN, 0 },
340 { 0x00, 0x00, 0x00, M_TR, "\n" },
342 /* DRAMC -- DRAM Control Register */
343 { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" },
344 { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" },
345 { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" },
346 { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" },
347 { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" },
348 { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" },
349 { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" },
350 { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" },
352 /* DRAMT = DRAM Timing Register */
353 { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " },
354 { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
355 { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
356 { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
357 { 0x58, 0x60, 0x60, M_EQ, "???" },
358 { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " },
359 { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
360 { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
361 { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
362 { 0x58, 0x18, 0x18, M_EQ, "???" },
363 { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " },
364 { 0x58, 0x04, 0x00, M_EQ, "3" },
365 { 0x58, 0x04, 0x04, M_EQ, "2" },
366 { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
372 static const struct condmsg conf82437vx[] =
374 /* PCON -- PCI Control Register */
375 { 0x00, 0x00, 0x00, M_TR, "\n\tPCI Concurrency: " },
376 { 0x50, 0x08, 0x08, M_EN, 0 },
378 /* CC -- Cache Control Regsiter */
379 { 0x00, 0x00, 0x00, M_TR, "\n\tCache:" },
380 { 0x52, 0xc0, 0x80, M_EQ, " 512K" },
381 { 0x52, 0xc0, 0x40, M_EQ, " 256K" },
382 { 0x52, 0xc0, 0x00, M_EQ, " NO" },
383 { 0x52, 0x30, 0x00, M_EQ, " pipelined-burst" },
384 { 0x52, 0x30, 0x10, M_EQ, " burst" },
385 { 0x52, 0x30, 0x20, M_EQ, " asynchronous" },
386 { 0x52, 0x30, 0x30, M_EQ, " dual-bank pipelined-burst" },
387 { 0x00, 0x00, 0x00, M_TR, " secondary; L1 " },
388 { 0x52, 0x01, 0x00, M_EN, 0 },
389 { 0x00, 0x00, 0x00, M_TR, "\n" },
391 /* DRAMC -- DRAM Control Register */
392 { 0x57, 0x07, 0x00, M_EQ, "Warning: refresh OFF!\n" },
393 { 0x00, 0x00, 0x00, M_TR, "\tDRAM:" },
394 { 0x57, 0xc0, 0x00, M_EQ, " no memory hole" },
395 { 0x57, 0xc0, 0x40, M_EQ, " 512K-640K memory hole" },
396 { 0x57, 0xc0, 0x80, M_EQ, " 15M-16M memory hole" },
397 { 0x57, 0x07, 0x01, M_EQ, ", 50 MHz refresh" },
398 { 0x57, 0x07, 0x02, M_EQ, ", 60 MHz refresh" },
399 { 0x57, 0x07, 0x03, M_EQ, ", 66 MHz refresh" },
401 /* DRAMT = DRAM Timing Register */
402 { 0x00, 0x00, 0x00, M_TR, "\n\tRead burst timing: " },
403 { 0x58, 0x60, 0x00, M_EQ, "x-4-4-4/x-4-4-4" },
404 { 0x58, 0x60, 0x20, M_EQ, "x-3-3-3/x-4-4-4" },
405 { 0x58, 0x60, 0x40, M_EQ, "x-2-2-2/x-3-3-3" },
406 { 0x58, 0x60, 0x60, M_EQ, "???" },
407 { 0x00, 0x00, 0x00, M_TR, "\n\tWrite burst timing: " },
408 { 0x58, 0x18, 0x00, M_EQ, "x-4-4-4" },
409 { 0x58, 0x18, 0x08, M_EQ, "x-3-3-3" },
410 { 0x58, 0x18, 0x10, M_EQ, "x-2-2-2" },
411 { 0x58, 0x18, 0x18, M_EQ, "???" },
412 { 0x00, 0x00, 0x00, M_TR, "\n\tRAS-CAS delay: " },
413 { 0x58, 0x04, 0x00, M_EQ, "3" },
414 { 0x58, 0x04, 0x04, M_EQ, "2" },
415 { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
421 static const struct condmsg conf82371fb[] =
423 /* IORT -- ISA I/O Recovery Timer Register */
424 { 0x00, 0x00, 0x00, M_TR, "\tI/O Recovery Timing: 8-bit " },
425 { 0x4c, 0x40, 0x00, M_EQ, "3.5" },
426 { 0x4c, 0x78, 0x48, M_EQ, "1" },
427 { 0x4c, 0x78, 0x50, M_EQ, "2" },
428 { 0x4c, 0x78, 0x58, M_EQ, "3" },
429 { 0x4c, 0x78, 0x60, M_EQ, "4" },
430 { 0x4c, 0x78, 0x68, M_EQ, "5" },
431 { 0x4c, 0x78, 0x70, M_EQ, "6" },
432 { 0x4c, 0x78, 0x78, M_EQ, "7" },
433 { 0x4c, 0x78, 0x40, M_EQ, "8" },
434 { 0x00, 0x00, 0x00, M_TR, " clocks, 16-bit " },
435 { 0x4c, 0x04, 0x00, M_EQ, "3.5" },
436 { 0x4c, 0x07, 0x05, M_EQ, "1" },
437 { 0x4c, 0x07, 0x06, M_EQ, "2" },
438 { 0x4c, 0x07, 0x07, M_EQ, "3" },
439 { 0x4c, 0x07, 0x04, M_EQ, "4" },
440 { 0x00, 0x00, 0x00, M_TR, " clocks\n" },
442 /* XBCS -- X-Bus Chip Select Register */
443 { 0x00, 0x00, 0x00, M_TR, "\tExtended BIOS: " },
444 { 0x4e, 0x80, 0x80, M_EN, 0 },
445 { 0x00, 0x00, 0x00, M_TR, "\n\tLower BIOS: " },
446 { 0x4e, 0x40, 0x40, M_EN, 0 },
447 { 0x00, 0x00, 0x00, M_TR, "\n\tCoprocessor IRQ13: " },
448 { 0x4e, 0x20, 0x20, M_EN, 0 },
449 { 0x00, 0x00, 0x00, M_TR, "\n\tMouse IRQ12: " },
450 { 0x4e, 0x10, 0x10, M_EN, 0 },
451 { 0x00, 0x00, 0x00, M_TR, "\n" },
453 { 0x00, 0x00, 0x00, M_TR, "\tInterrupt Routing: " },
455 { 0x00, 0x00, 0x00, M_TR, n ": " }, \
456 { x, 0x80, 0x80, M_EQ, "disabled" }, \
457 { x, 0xc0, 0x40, M_EQ, "[shared] " }, \
458 { x, 0x8f, 0x03, M_EQ, "IRQ3" }, \
459 { x, 0x8f, 0x04, M_EQ, "IRQ4" }, \
460 { x, 0x8f, 0x05, M_EQ, "IRQ5" }, \
461 { x, 0x8f, 0x06, M_EQ, "IRQ6" }, \
462 { x, 0x8f, 0x07, M_EQ, "IRQ7" }, \
463 { x, 0x8f, 0x09, M_EQ, "IRQ9" }, \
464 { x, 0x8f, 0x0a, M_EQ, "IRQ10" }, \
465 { x, 0x8f, 0x0b, M_EQ, "IRQ11" }, \
466 { x, 0x8f, 0x0c, M_EQ, "IRQ12" }, \
467 { x, 0x8f, 0x0e, M_EQ, "IRQ14" }, \
468 { x, 0x8f, 0x0f, M_EQ, "IRQ15" }
470 /* Interrupt routing */
475 PIRQ(0x70, "\n\t\tMB0"),
478 { 0x00, 0x00, 0x00, M_TR, "\n" },
482 /* XXX - do DMA routing, too? */
486 static const struct condmsg conf82371fb2[] =
488 /* IDETM -- IDE Timing Register */
489 { 0x00, 0x00, 0x00, M_TR, "\tPrimary IDE: " },
490 { 0x41, 0x80, 0x80, M_EN, 0 },
491 { 0x00, 0x00, 0x00, M_TR, "\n\tSecondary IDE: " },
492 { 0x43, 0x80, 0x80, M_EN, 0 },
493 { 0x00, 0x00, 0x00, M_TR, "\n" },
500 writeconfig (device_t dev, const struct condmsg *tbl)
502 while (tbl->flags != M_XX) {
503 const char *text = 0;
505 if (tbl->flags == M_TR) {
508 unsigned char v = pci_read_config(dev, tbl->port, 1);
509 switch (tbl->flags) {
511 if ((v & tbl->mask) == tbl->value) text = tbl->text;
514 if ((v & tbl->mask) != tbl->value) text = tbl->text;
517 text = (v & tbl->mask) ? "enabled" : "disabled";
520 text = (v & tbl->mask) ? "disabled" : "enabled";
523 if (text) printf ("%s", text);
528 #endif /* PCI_QUIET */
531 chipset_attach (device_t dev, int unit)
537 switch (pci_get_devid(dev)) {
539 writeconfig (dev, conf82425ex);
542 writeconfig (dev, conf82424zx);
545 writeconfig (dev, conf82434lx);
548 writeconfig (dev, conf82378);
551 writeconfig (dev, conf82437fx);
554 writeconfig (dev, conf82437vx);
558 writeconfig (dev, conf82371fb);
562 writeconfig (dev, conf82371fb2);
565 case 0x00011011: /* DEC 21050 */
566 case 0x00221014: /* IBM xxx */
567 writeconfig (dev, conf_pci2pci);
571 #endif /* PCI_QUIET */
575 eisab_match(device_t dev)
577 switch (pci_get_devid(dev)) {
579 /* Recognize this specifically, it has PCI-HOST class (!) */
580 return ("Intel 82375EB PCI-EISA bridge");
582 if (pci_get_class(dev) == PCIC_BRIDGE
583 && pci_get_subclass(dev) == PCIS_BRIDGE_EISA)
584 return pci_bridge_type(dev);
590 isab_match(device_t dev)
594 switch (pci_get_devid(dev)) {
596 rev = pci_get_revid(dev);
598 return ("Intel 82378ZB PCI to ISA bridge");
599 return ("Intel 82378IB PCI to ISA bridge");
601 return ("Intel 82371FB PCI to ISA bridge");
603 return ("Intel 82371SB PCI to ISA bridge");
605 return ("Intel 82371AB PCI to ISA bridge");
607 return ("Intel 82443MX PCI to ISA bridge");
609 return ("Intel 82801AA (ICH) PCI to LPC bridge");
611 return ("Intel 82801AB (ICH0) PCI to LPC bridge");
613 return ("Intel 82801BA/BAM (ICH2) PCI to LPC bridge");
615 return ("Intel 82801FB/FBW (ICH6) PCI to LPC bridge");
617 return ("Intel 82801FR/FRW (ICH6) PCI to LPC bridge");
619 /* NVIDIA -- vendor 0x10de */
621 return ("NVIDIA nForce2 PCI to ISA bridge");
623 /* VLSI -- vendor 0x1004 */
625 return ("VLSI 82C593 PCI to ISA bridge");
627 /* VIA Technologies -- vendor 0x1106 */
628 case 0x05861106: /* south bridge section */
629 return ("VIA 82C586 PCI-ISA bridge");
631 return ("VIA 82C596B PCI-ISA bridge");
633 return ("VIA 82C686 PCI-ISA bridge");
635 /* AcerLabs -- vendor 0x10b9 */
636 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
637 /* id is '10b9" but the register always shows "10b9". -Foxfair */
639 return ("AcerLabs M1533 portable PCI-ISA bridge");
641 return ("AcerLabs M1543 desktop PCI-ISA bridge");
643 /* SiS -- vendor 0x1039 */
645 return ("SiS 85c503 PCI-ISA bridge");
647 /* Cyrix -- vendor 0x1078 */
649 return ("Cyrix Cx5510 PCI-ISA bridge");
651 return ("Cyrix Cx5530 PCI-ISA bridge");
653 /* UMC United Microelectronics 0x1060 */
655 return ("UMC UM8886 ISA Bridge with EIDE");
657 /* Cypress -- vendor 0x1080 */
659 if (pci_get_class(dev) == PCIC_BRIDGE
660 && pci_get_subclass(dev) == PCIS_BRIDGE_ISA)
661 return ("Cypress 82C693 PCI-ISA bridge");
664 /* ServerWorks -- vendor 0x1166 */
666 return ("ServerWorks IB6566 PCI to ISA bridge");
669 if (pci_get_class(dev) == PCIC_BRIDGE
670 && pci_get_subclass(dev) == PCIS_BRIDGE_ISA)
671 return pci_bridge_type(dev);
677 isab_probe(device_t dev)
683 desc = eisab_match(dev);
687 desc = isab_match(dev);
690 * For a PCI-EISA bridge, add both eisa and isa.
691 * Only add one instance of eisa or isa for now.
693 device_set_desc_copy(dev, desc);
694 if (is_eisa && !devclass_get_device(devclass_find("eisa"), 0))
695 device_add_child(dev, "eisa", -1);
697 if (!devclass_get_device(devclass_find("isa"), 0))
698 device_add_child(dev, "isa", -1);
705 isab_attach(device_t dev)
707 chipset_attach(dev, device_get_unit(dev));
708 return bus_generic_attach(dev);
711 static device_method_t isab_methods[] = {
712 /* Device interface */
713 DEVMETHOD(device_probe, isab_probe),
714 DEVMETHOD(device_attach, isab_attach),
715 DEVMETHOD(device_shutdown, bus_generic_shutdown),
716 DEVMETHOD(device_suspend, bus_generic_suspend),
717 DEVMETHOD(device_resume, bus_generic_resume),
720 DEVMETHOD(bus_print_child, bus_generic_print_child),
721 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
722 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
723 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
724 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
725 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
726 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
731 static driver_t isab_driver = {
737 devclass_t isab_devclass;
739 DRIVER_MODULE(isab, pci, isab_driver, isab_devclass, 0, 0);