2 * Copyright (c) 1998,1999,2000,2001,2002 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * $FreeBSD: src/sys/dev/ata/ata-pci.c,v 1.32.2.15 2003/06/06 13:27:05 fjoe Exp $
29 * $DragonFly: src/sys/dev/disk/ata/ata-pci.c,v 1.6 2003/12/25 07:16:35 dillon Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/malloc.h>
40 #include <sys/devicestat.h>
41 #include <sys/sysctl.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <machine/clock.h>
47 #include <machine/md_var.h>
50 #include <bus/pci/pcivar.h>
51 #include <bus/pci/pcireg.h>
54 /* device structures */
55 struct ata_pci_controller {
56 struct resource *bmio;
63 #define IOMASK 0xfffffffc
64 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev))
65 #define ATA_MASTERDEV(dev) ((pci_get_progif(dev) & 0x80) && \
66 (pci_get_progif(dev) & 0x05) != 0x05)
69 ata_find_dev(device_t dev, u_int32_t devid, u_int32_t revid)
74 if (device_get_children(device_get_parent(dev), &children, &nchildren))
77 for (i = 0; i < nchildren; i++) {
78 if (pci_get_devid(children[i]) == devid &&
79 pci_get_revid(children[i]) >= revid) {
80 free(children, M_TEMP);
84 free(children, M_TEMP);
89 ata_via_southbridge_fixup(device_t dev)
94 if (device_get_children(device_get_parent(dev), &children, &nchildren))
97 for (i = 0; i < nchildren; i++) {
98 if (pci_get_devid(children[i]) == 0x03051106 || /* VIA VT8363 */
99 pci_get_devid(children[i]) == 0x03911106 || /* VIA VT8371 */
100 pci_get_devid(children[i]) == 0x31021106 || /* VIA VT8662 */
101 pci_get_devid(children[i]) == 0x31121106) { /* VIA VT8361 */
102 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
104 if ((reg76 & 0xf0) != 0xd0) {
106 "Correcting VIA config for southbridge data corruption bug\n");
107 pci_write_config(children[i], 0x75, 0x80, 1);
108 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
113 free(children, M_TEMP);
117 ata_pci_match(device_t dev)
119 if (pci_get_class(dev) != PCIC_STORAGE)
122 switch (pci_get_devid(dev)) {
123 /* supported chipsets */
125 return "Intel PIIX ATA controller";
128 return "Intel PIIX3 ATA controller";
133 return "Intel PIIX4 ATA33 controller";
136 return "Intel ICH0 ATA33 controller";
140 return "Intel ICH ATA66 controller";
144 return "Intel ICH2 ATA100 controller";
148 return "Intel ICH3 ATA100 controller";
152 return "Intel ICH4 ATA100 controller";
155 return "Intel ICH5 ATA100 controller";
158 if (pci_get_revid(dev) >= 0xc4)
159 return "AcerLabs Aladdin ATA100 controller";
160 else if (pci_get_revid(dev) >= 0xc2)
161 return "AcerLabs Aladdin ATA66 controller";
162 else if (pci_get_revid(dev) >= 0x20)
163 return "AcerLabs Aladdin ATA33 controller";
165 return "AcerLabs Aladdin ATA controller";
168 if (ata_find_dev(dev, 0x05861106, 0x02))
169 return "VIA 82C586 ATA33 controller";
170 if (ata_find_dev(dev, 0x05861106, 0))
171 return "VIA 82C586 ATA controller";
172 if (ata_find_dev(dev, 0x05961106, 0x12))
173 return "VIA 82C596 ATA66 controller";
174 if (ata_find_dev(dev, 0x05961106, 0))
175 return "VIA 82C596 ATA33 controller";
176 if (ata_find_dev(dev, 0x06861106, 0x40))
177 return "VIA 82C686 ATA100 controller";
178 if (ata_find_dev(dev, 0x06861106, 0x10))
179 return "VIA 82C686 ATA66 controller";
180 if (ata_find_dev(dev, 0x06861106, 0))
181 return "VIA 82C686 ATA33 controller";
182 if (ata_find_dev(dev, 0x82311106, 0))
183 return "VIA 8231 ATA100 controller";
184 if (ata_find_dev(dev, 0x30741106, 0) ||
185 ata_find_dev(dev, 0x31091106, 0))
186 return "VIA 8233 ATA100 controller";
187 if (ata_find_dev(dev, 0x31471106, 0))
188 return "VIA 8233 ATA133 controller";
189 if (ata_find_dev(dev, 0x31771106, 0))
190 return "VIA 8235 ATA133 controller";
191 return "VIA Apollo ATA controller";
194 if (ata_find_dev(dev, 0x06301039, 0x30) ||
195 ata_find_dev(dev, 0x06331039, 0) ||
196 ata_find_dev(dev, 0x06351039, 0) ||
197 ata_find_dev(dev, 0x06401039, 0) ||
198 ata_find_dev(dev, 0x06451039, 0) ||
199 ata_find_dev(dev, 0x06481039, 0) ||
200 ata_find_dev(dev, 0x06501039, 0) ||
201 ata_find_dev(dev, 0x07301039, 0) ||
202 ata_find_dev(dev, 0x07331039, 0) ||
203 ata_find_dev(dev, 0x07351039, 0) ||
204 ata_find_dev(dev, 0x07401039, 0) ||
205 ata_find_dev(dev, 0x07451039, 0) ||
206 ata_find_dev(dev, 0x07501039, 0))
207 return "SiS 5591 ATA100 controller";
208 else if (ata_find_dev(dev, 0x05301039, 0) ||
209 ata_find_dev(dev, 0x05401039, 0) ||
210 ata_find_dev(dev, 0x06201039, 0) ||
211 ata_find_dev(dev, 0x06301039, 0))
212 return "SiS 5591 ATA66 controller";
214 return "SiS 5591 ATA33 controller";
217 return "SiI 0680 ATA133 controller";
220 return "CMD 649 ATA100 controller";
223 return "CMD 648 ATA66 controller";
226 return "CMD 646 ATA controller";
229 if (pci_get_subclass(dev) == PCIS_STORAGE_IDE)
230 return "Cypress 82C693 ATA controller";
234 return "Cyrix 5530 ATA33 controller";
237 return "AMD 756 ATA66 controller";
240 return "AMD 766 ATA100 controller";
243 return "AMD 768 ATA100 controller";
246 return "NVIDIA nForce ATA100 controller";
249 return "NVIDIA nForce ATA133 controller";
252 return "ServerWorks ROSB4 ATA33 controller";
255 if (pci_get_revid(dev) >= 0x92)
256 return "ServerWorks CSB5 ATA100 controller";
258 return "ServerWorks CSB5 ATA66 controller";
261 return "Promise ATA33 controller";
265 return "Promise ATA66 controller";
269 return "Promise ATA100 controller";
273 if (pci_get_devid(GRANDPARENT(dev)) == 0x00221011 &&
274 pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
275 static long start = 0, end = 0;
277 /* we belive we are on a TX4, now do our (simple) magic */
278 if (pci_get_slot(dev) == 1) {
279 bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
280 return "Promise TX4 ATA100 controller (channel 0+1)";
282 else if (pci_get_slot(dev) == 2 && start && end) {
283 bus_set_resource(dev, SYS_RES_IRQ, 0, start, end);
285 return "Promise TX4 ATA100 controller (channel 2+3)";
290 return "Promise TX2 ATA100 controller";
296 return "Promise TX2 ATA133 controller";
299 switch (pci_get_revid(dev)) {
302 return "HighPoint HPT366 ATA66 controller";
304 return "HighPoint HPT368 ATA66 controller";
307 return "HighPoint HPT370 ATA100 controller";
309 return "HighPoint HPT372 ATA133 controller";
314 switch (pci_get_revid(dev)) {
317 return "HighPoint HPT372 ATA133 controller";
322 switch (pci_get_revid(dev)) {
324 return "HighPoint HPT374 ATA133 controller";
329 return "Cenatek Rocket Drive controller";
331 /* unsupported but known chipsets, generic DMA only */
334 return "RZ 100? ATA controller !WARNING! buggy chip data loss possible";
337 return "CMD 640 ATA controller !WARNING! buggy chip data loss possible";
339 /* unknown chipsets, try generic DMA if it seems possible */
341 if (pci_get_class(dev) == PCIC_STORAGE &&
342 (pci_get_subclass(dev) == PCIS_STORAGE_IDE))
343 return "Generic PCI ATA controller";
349 ata_pci_probe(device_t dev)
351 const char *desc = ata_pci_match(dev);
354 device_set_desc(dev, desc);
362 ata_pci_add_child(device_t dev, int unit)
366 /* check if this is located at one of the std addresses */
367 if (ATA_MASTERDEV(dev)) {
368 if (!(child = device_add_child(dev, "ata", unit)))
372 if (!(child = device_add_child(dev, "ata", 2)))
379 ata_pci_attach(device_t dev)
381 struct ata_pci_controller *controller = device_get_softc(dev);
382 u_int8_t class, subclass;
386 /* set up vendor-specific stuff */
387 type = pci_get_devid(dev);
388 class = pci_get_class(dev);
389 subclass = pci_get_subclass(dev);
390 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
392 if (!(cmd & PCIM_CMD_PORTEN)) {
393 device_printf(dev, "ATA channel disabled by BIOS\n");
397 /* is busmastering supported ? */
398 if ((cmd & (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) ==
399 (PCIM_CMD_PORTEN | PCIM_CMD_BUSMASTEREN)) {
401 /* is there a valid port range to connect to ? */
403 controller->bmio = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
404 0, ~0, 1, RF_ACTIVE);
405 if (!controller->bmio)
406 device_printf(dev, "Busmastering DMA not configured\n");
409 device_printf(dev, "Busmastering DMA not supported\n");
411 /* do extra chipset specific setups */
413 case 0x522910b9: /* Aladdin need to activate the ATAPI FIFO */
414 pci_write_config(dev, 0x53,
415 (pci_read_config(dev, 0x53, 1) & ~0x01) | 0x02, 1);
418 case 0x4d38105a: /* Promise 66 & 100 (before TX2) need the clock changed */
421 ATA_OUTB(controller->bmio, 0x11, ATA_INB(controller->bmio, 0x11)|0x0a);
424 case 0x4d33105a: /* Promise (before TX2) need burst mode turned on */
425 ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
428 case 0x00041103: /* HighPoint HPT366/368/370/372 */
429 if (pci_get_revid(dev) < 2) { /* HPT 366 */
430 /* turn off interrupt prediction */
431 pci_write_config(dev, 0x51,
432 (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
435 if (pci_get_revid(dev) < 5) { /* HPT368/370 */
436 /* turn off interrupt prediction */
437 pci_write_config(dev, 0x51,
438 (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
439 pci_write_config(dev, 0x55,
440 (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
442 /* turn on interrupts */
443 pci_write_config(dev, 0x5a,
444 (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
447 pci_write_config(dev, 0x5b, 0x22, 1);
452 case 0x00051103: /* HighPoint HPT372 */
453 case 0x00081103: /* HighPoint HPT374 */
454 /* turn off interrupt prediction */
455 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
456 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
458 /* turn on interrupts */
459 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
462 pci_write_config(dev, 0x5b,
463 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
466 case 0x05711106: /* VIA 82C586, '596, '686 default setup */
467 /* prepare for ATA-66 on the 82C686a and 82C596b */
468 if ((ata_find_dev(dev, 0x06861106, 0x10) &&
469 !ata_find_dev(dev, 0x06861106, 0x40)) ||
470 ata_find_dev(dev, 0x05961106, 0x12))
471 pci_write_config(dev, 0x50, 0x030b030b, 4);
473 /* the southbridge might need the data corruption fix */
474 if (ata_find_dev(dev, 0x06861106, 0x40) ||
475 ata_find_dev(dev, 0x82311106, 0x10))
476 ata_via_southbridge_fixup(dev);
479 case 0x74091022: /* AMD 756 default setup */
480 case 0x74111022: /* AMD 766 default setup */
481 case 0x74411022: /* AMD 768 default setup */
482 case 0x01bc10de: /* NVIDIA nForce default setup */
483 case 0x006510de: /* NVIDIA nForce2 default setup */
484 /* set prefetch, postwrite */
485 pci_write_config(dev, 0x41, pci_read_config(dev, 0x41, 1) | 0xf0, 1);
487 /* set fifo configuration half'n'half */
488 pci_write_config(dev, 0x43,
489 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
491 /* set status register read retry */
492 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
494 /* set DMA read & end-of-sector fifo flush */
495 pci_write_config(dev, 0x46,
496 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
498 /* set sector size */
499 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
500 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
503 case 0x02111166: /* ServerWorks ROSB4 enable UDMA33 */
504 pci_write_config(dev, 0x64,
505 (pci_read_config(dev, 0x64, 4) & ~0x00002000) |
509 case 0x02121166: /* ServerWorks CSB5 enable UDMA66/100 depending on rev */
510 pci_write_config(dev, 0x5a,
511 (pci_read_config(dev, 0x5a, 1) & ~0x40) |
512 (pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
515 case 0x06801095: /* SiI 0680 set ATA reference clock speed */
516 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
517 pci_write_config(dev, 0x8a,
518 (pci_read_config(dev, 0x8a, 1) & 0x0F) | 0x10, 1);
519 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
520 device_printf(dev, "SiI 0680 could not set clock\n");
525 case 0x06461095: /* CMD 646 enable interrupts, set DMA read mode */
526 pci_write_config(dev, 0x71, 0x01, 1);
529 case 0x10001042: /* RZ 100? known bad, no DMA */
531 case 0x06401095: /* CMD 640 known bad, no DMA */
532 controller->bmio = NULL;
533 device_printf(dev, "Busmastering DMA disabled\n");
536 if (controller->bmio) {
537 controller->bmaddr = rman_get_start(controller->bmio);
538 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
539 SYS_RES_IOPORT, rid, controller->bmio);
540 controller->bmio = NULL;
544 * the Cypress chip is a mess, it contains two ATA functions, but
545 * both channels are visible on the first one.
546 * simply ignore the second function for now, as the right
547 * solution (ignoring the second channel on the first function)
548 * doesn't work with the crappy ATA interrupt setup on the alpha.
550 if (pci_get_devid(dev) == 0xc6931080 && pci_get_function(dev) > 1)
553 ata_pci_add_child(dev, 0);
555 if (ATA_MASTERDEV(dev) || pci_read_config(dev, 0x18, 4) & IOMASK)
556 ata_pci_add_child(dev, 1);
558 return bus_generic_attach(dev);
562 ata_pci_intr(struct ata_channel *ch)
567 * since we might share the IRQ with another device, and in some
568 * cases with our twin channel, we only want to process interrupts
569 * that we know this channel generated.
571 switch (ch->chiptype) {
572 case 0x00041103: /* HighPoint HPT366/368/370/372 */
573 case 0x00051103: /* HighPoint HPT372 */
574 case 0x00081103: /* HighPoint HPT374 */
575 if (((dmastat = ata_dmastatus(ch)) &
576 (ATA_BMSTAT_ACTIVE | ATA_BMSTAT_INTERRUPT)) != ATA_BMSTAT_INTERRUPT)
578 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
582 case 0x06481095: /* CMD 648 */
583 case 0x06491095: /* CMD 649 */
584 if (!(pci_read_config(device_get_parent(ch->dev), 0x71, 1) &
585 (ch->unit ? 0x08 : 0x04)))
589 case 0x4d33105a: /* Promise Ultra/Fasttrak 33 */
590 case 0x0d38105a: /* Promise Fasttrak 66 */
591 case 0x4d38105a: /* Promise Ultra/Fasttrak 66 */
592 case 0x0d30105a: /* Promise OEM ATA100 */
593 case 0x4d30105a: /* Promise Ultra/Fasttrak 100 */
594 if (!(ATA_INL(ch->r_bmio, (ch->unit ? 0x14 : 0x1c)) &
595 (ch->unit ? 0x00004000 : 0x00000400)))
599 case 0x4d68105a: /* Promise TX2 ATA100 */
600 case 0x6268105a: /* Promise TX2 ATA100 */
601 case 0x4d69105a: /* Promise TX2 ATA133 */
602 case 0x5275105a: /* Promise TX2 ATA133 */
603 case 0x6269105a: /* Promise TX2 ATA133 */
604 case 0x7275105a: /* Promise TX2 ATA133 */
605 ATA_OUTB(ch->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
606 if (!(ATA_INB(ch->r_bmio, ATA_BMDEVSPEC_1) & 0x20))
611 if (ch->flags & ATA_DMA_ACTIVE) {
612 if (!((dmastat = ata_dmastatus(ch)) & ATA_BMSTAT_INTERRUPT))
614 ATA_OUTB(ch->r_bmio, ATA_BMSTAT_PORT, dmastat | ATA_BMSTAT_INTERRUPT);
621 ata_pci_print_child(device_t dev, device_t child)
623 struct ata_channel *ch = device_get_softc(child);
626 retval += bus_print_child_header(dev, child);
627 retval += printf(": at 0x%lx", rman_get_start(ch->r_io));
629 if (ATA_MASTERDEV(dev))
630 retval += printf(" irq %d", 14 + ch->unit);
632 retval += bus_print_child_footer(dev, child);
637 static struct resource *
638 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
639 u_long start, u_long end, u_long count, u_int flags)
641 struct ata_pci_controller *controller = device_get_softc(dev);
642 struct resource *res = NULL;
643 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
646 if (type == SYS_RES_IOPORT) {
649 if (ATA_MASTERDEV(dev)) {
651 start = (unit ? ATA_SECONDARY : ATA_PRIMARY);
652 end = start + ATA_IOSIZE - 1;
654 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
655 SYS_RES_IOPORT, &myrid,
656 start, end, count, flags);
659 myrid = 0x10 + 8 * unit;
660 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
661 SYS_RES_IOPORT, &myrid,
662 start, end, count, flags);
666 case ATA_ALTADDR_RID:
667 if (ATA_MASTERDEV(dev)) {
669 start = (unit ? ATA_SECONDARY : ATA_PRIMARY) + ATA_ALTOFFSET;
670 end = start + ATA_ALTIOSIZE - 1;
671 count = ATA_ALTIOSIZE;
672 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
673 SYS_RES_IOPORT, &myrid,
674 start, end, count, flags);
677 myrid = 0x14 + 8 * unit;
678 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
679 SYS_RES_IOPORT, &myrid,
680 start, end, count, flags);
682 start = rman_get_start(res) + 2;
683 end = rman_get_start(res) + ATA_ALTIOSIZE - 1;
684 count = ATA_ALTIOSIZE;
685 BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
686 SYS_RES_IOPORT, myrid, res);
687 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
688 SYS_RES_IOPORT, &myrid,
689 start, end, count, flags);
695 if (controller->bmaddr) {
698 controller->bmaddr : controller->bmaddr+ATA_BMIOSIZE);
699 end = start + ATA_BMIOSIZE - 1;
700 count = ATA_BMIOSIZE;
701 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
702 SYS_RES_IOPORT, &myrid,
703 start, end, count, flags);
709 if (type == SYS_RES_IRQ && *rid == ATA_IRQ_RID) {
710 if (ATA_MASTERDEV(dev)) {
712 return alpha_platform_alloc_ide_intr(unit);
714 int irq = (unit == 0 ? 14 : 15);
716 return BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
717 SYS_RES_IRQ, rid, irq, irq, 1, flags);
721 /* primary and secondary channels share interrupt, keep track */
722 if (!controller->irq)
723 controller->irq = BUS_ALLOC_RESOURCE(device_get_parent(dev),
725 rid, 0, ~0, 1, flags);
726 controller->irqcnt++;
727 return controller->irq;
734 ata_pci_release_resource(device_t dev, device_t child, int type, int rid,
737 struct ata_pci_controller *controller = device_get_softc(dev);
738 int unit = ((struct ata_channel *)device_get_softc(child))->unit;
740 if (type == SYS_RES_IOPORT) {
743 if (ATA_MASTERDEV(dev))
744 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
745 SYS_RES_IOPORT, 0x0, r);
747 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
748 SYS_RES_IOPORT, 0x10 + 8 * unit, r);
751 case ATA_ALTADDR_RID:
752 if (ATA_MASTERDEV(dev))
753 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
754 SYS_RES_IOPORT, 0x0, r);
756 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
757 SYS_RES_IOPORT, 0x14 + 8 * unit, r);
761 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
762 SYS_RES_IOPORT, 0x20, r);
767 if (type == SYS_RES_IRQ) {
768 if (rid != ATA_IRQ_RID)
771 if (ATA_MASTERDEV(dev)) {
773 return alpha_platform_release_ide_intr(unit, r);
775 return BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
776 SYS_RES_IRQ, rid, r);
780 /* primary and secondary channels share interrupt, keep track */
781 if (--controller->irqcnt)
783 controller->irq = NULL;
784 return BUS_RELEASE_RESOURCE(device_get_parent(dev), dev,
785 SYS_RES_IRQ, rid, r);
792 ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq,
793 int flags, driver_intr_t *intr, void *arg,
796 if (ATA_MASTERDEV(dev)) {
798 return alpha_platform_setup_ide_intr(irq, intr, arg, cookiep);
800 return BUS_SETUP_INTR(device_get_parent(dev), child, irq,
801 flags, intr, arg, cookiep);
805 return BUS_SETUP_INTR(device_get_parent(dev), dev, irq,
806 flags, intr, arg, cookiep);
810 ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
813 if (ATA_MASTERDEV(dev)) {
815 return alpha_platform_teardown_ide_intr(irq, cookie);
817 return BUS_TEARDOWN_INTR(device_get_parent(dev), child, irq, cookie);
821 return BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie);
824 static device_method_t ata_pci_methods[] = {
825 /* device interface */
826 DEVMETHOD(device_probe, ata_pci_probe),
827 DEVMETHOD(device_attach, ata_pci_attach),
828 DEVMETHOD(device_shutdown, bus_generic_shutdown),
829 DEVMETHOD(device_suspend, bus_generic_suspend),
830 DEVMETHOD(device_resume, bus_generic_resume),
833 DEVMETHOD(bus_print_child, ata_pci_print_child),
834 DEVMETHOD(bus_alloc_resource, ata_pci_alloc_resource),
835 DEVMETHOD(bus_release_resource, ata_pci_release_resource),
836 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
837 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
838 DEVMETHOD(bus_setup_intr, ata_pci_setup_intr),
839 DEVMETHOD(bus_teardown_intr, ata_pci_teardown_intr),
843 static driver_t ata_pci_driver = {
846 sizeof(struct ata_pci_controller),
849 static devclass_t ata_pci_devclass;
851 DRIVER_MODULE(atapci, pci, ata_pci_driver, ata_pci_devclass, 0, 0);
854 ata_pcisub_probe(device_t dev)
856 struct ata_channel *ch = device_get_softc(dev);
860 /* find channel number on this controller */
861 device_get_children(device_get_parent(dev), &children, &count);
862 for (i = 0; i < count; i++) {
863 if (children[i] == dev)
866 free(children, M_TEMP);
867 ch->chiptype = pci_get_devid(device_get_parent(dev));
868 ch->intr_func = ata_pci_intr;
869 return ata_probe(dev);
872 static device_method_t ata_pcisub_methods[] = {
873 /* device interface */
874 DEVMETHOD(device_probe, ata_pcisub_probe),
875 DEVMETHOD(device_attach, ata_attach),
876 DEVMETHOD(device_detach, ata_detach),
877 DEVMETHOD(device_resume, ata_resume),
881 static driver_t ata_pcisub_driver = {
884 sizeof(struct ata_channel),
887 DRIVER_MODULE(ata, atapci, ata_pcisub_driver, ata_devclass, 0, 0);