2 * Copyright (c) 1991 The Regents of the University of California.
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33 * $FreeBSD: src/sys/i386/isa/intr_machdep.h,v 1.19.2.2 2001/10/14 20:05:50 luigi Exp $
34 * $DragonFly: src/sys/platform/pc32/isa/intr_machdep.h,v 1.15 2005/06/16 21:12:47 dillon Exp $
37 #ifndef _I386_ISA_INTR_MACHDEP_H_
38 #define _I386_ISA_INTR_MACHDEP_H_
41 #ifndef _SYS_INTERRUPT_H_
42 #include <sys/interrupt.h>
44 #ifndef _SYS_SERIALIZE_H_
45 #include <sys/serialize.h>
50 * Low level interrupt code.
55 #if defined(SMP) || defined(APIC_IO)
57 * XXX FIXME: rethink location for all IPI vectors.
61 APIC TPR priority vector levels:
63 0xff (255) +-------------+
64 | | 15 (IPIs: Xspuriousint)
65 0xf0 (240) +-------------+
67 0xe0 (224) +-------------+
69 0xd0 (208) +-------------+
71 0xc0 (192) +-------------+
73 0xb0 (176) +-------------+
74 | | 10 (IPIs: Xcpustop)
75 0xa0 (160) +-------------+
76 | | 9 (IPIs: Xinvltlb)
77 0x90 (144) +-------------+
78 | | 8 (linux/BSD syscall, IGNORE FAST HW INTS)
79 0x80 (128) +-------------+
80 | | 7 (FAST_INTR 16-23)
81 0x70 (112) +-------------+
82 | | 6 (FAST_INTR 0-15)
83 0x60 (96) +-------------+
84 | | 5 (IGNORE HW INTS)
85 0x50 (80) +-------------+
87 0x40 (64) +------+------+
88 | | | 3 (upper APIC hardware INTs: PCI)
89 0x30 (48) +------+------+
90 | | 2 (start of hardware INTs: ISA)
91 0x20 (32) +-------------+
92 | | 1 (exceptions, traps, etc.)
93 0x10 (16) +-------------+
94 | | 0 (exceptions, traps, etc.)
95 0x00 (0) +-------------+
98 /* IDT vector base for regular (aka. slow) and fast interrupts */
99 #define TPR_SLOW_INTS 0x20
100 #define TPR_FAST_INTS 0x60
102 /* blocking values for local APIC Task Priority Register */
103 #define TPR_BLOCK_HWI 0x4f /* hardware INTs */
104 #define TPR_IGNORE_HWI 0x5f /* ignore INTs */
105 #define TPR_BLOCK_FHWI 0x7f /* hardware FAST INTs */
106 #define TPR_IGNORE_FHWI 0x8f /* ignore FAST INTs */
107 #define TPR_IPI_ONLY 0x8f /* ignore FAST INTs */
108 #define TPR_BLOCK_XINVLTLB 0x9f /* */
109 #define TPR_BLOCK_XCPUSTOP 0xaf /* */
110 #define TPR_BLOCK_ALL 0xff /* all INTs */
114 /* put a 'fake' HWI in top of APIC prio 0x3x, 32 + 31 = 63 = 0x3f */
115 #define XTEST1_OFFSET (ICU_OFFSET + 31)
116 #endif /** TEST_TEST1 */
119 #define XINVLTLB_OFFSET (ICU_OFFSET + 112)
121 /* unused/open (was inter-cpu clock handling) */
122 #define XUNUSED113_OFFSET (ICU_OFFSET + 113)
124 /* inter-CPU rendezvous */
125 #define XRENDEZVOUS_OFFSET (ICU_OFFSET + 114)
127 /* IPIQ rendezvous */
128 #define XIPIQ_OFFSET (ICU_OFFSET + 115)
130 /* IPI to signal CPUs to stop and wait for another CPU to restart them */
131 #define XCPUSTOP_OFFSET (ICU_OFFSET + 128)
134 * Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
136 #define XSPURIOUSINT_OFFSET (ICU_OFFSET + 223)
138 #endif /* SMP || APIC_IO */
143 * Type of the first (asm) part of an interrupt handler.
145 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
146 typedef void unpendhand_t(void);
148 #define IDTVEC(name) __CONCAT(X,name)
150 extern u_long *intr_countp[]; /* pointers into intrcnt[] */
151 extern inthand2_t *intr_handler[]; /* C entry points for FAST ints */
152 extern void *intr_unit[]; /* cookies to pass to intr handlers */
155 IDTVEC(fastintr0), IDTVEC(fastintr1),
156 IDTVEC(fastintr2), IDTVEC(fastintr3),
157 IDTVEC(fastintr4), IDTVEC(fastintr5),
158 IDTVEC(fastintr6), IDTVEC(fastintr7),
159 IDTVEC(fastintr8), IDTVEC(fastintr9),
160 IDTVEC(fastintr10), IDTVEC(fastintr11),
161 IDTVEC(fastintr12), IDTVEC(fastintr13),
162 IDTVEC(fastintr14), IDTVEC(fastintr15);
164 IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
165 IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
166 IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
167 IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
170 IDTVEC(fastunpend0), IDTVEC(fastunpend1),
171 IDTVEC(fastunpend2), IDTVEC(fastunpend3),
172 IDTVEC(fastunpend4), IDTVEC(fastunpend5),
173 IDTVEC(fastunpend6), IDTVEC(fastunpend7),
174 IDTVEC(fastunpend8), IDTVEC(fastunpend9),
175 IDTVEC(fastunpend10), IDTVEC(fastunpend11),
176 IDTVEC(fastunpend12), IDTVEC(fastunpend13),
177 IDTVEC(fastunpend14), IDTVEC(fastunpend15);
181 IDTVEC(fastintr16), IDTVEC(fastintr17),
182 IDTVEC(fastintr18), IDTVEC(fastintr19),
183 IDTVEC(fastintr20), IDTVEC(fastintr21),
184 IDTVEC(fastintr22), IDTVEC(fastintr23);
186 IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19),
187 IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23);
189 IDTVEC(fastunpend16), IDTVEC(fastunpend17),
190 IDTVEC(fastunpend18), IDTVEC(fastunpend19),
191 IDTVEC(fastunpend20), IDTVEC(fastunpend21),
192 IDTVEC(fastunpend22), IDTVEC(fastunpend23);
197 Xinvltlb, /* TLB shootdowns */
198 Xcpuast, /* Additional software trap on other cpu */
199 Xforward_irq, /* Forward irq to cpu holding ISR lock */
200 Xcpustop, /* CPU stops & waits for another CPU to restart it */
201 Xspuriousint, /* handle APIC "spurious INTs" */
202 Xipiq, /* handle lwkt_send_ipiq() requests */
203 Xrendezvous; /* handle CPU rendezvous */
207 Xtest1; /* 'fake' HWI at top of APIC prio 0x3x, 32+31 = 0x3f */
208 #endif /** TEST_TEST1 */
211 void call_fast_unpend(int irq);
212 void isa_defaultirq (void);
213 int isa_nmi (int cd);
214 int icu_setup (int intr, inthand2_t *func, void *arg, int flags);
215 int icu_unset (int intr, inthand2_t *handler);
216 void icu_reinit (void);
219 * WARNING: These are internal functions and not to be used by device drivers!
220 * They are subject to change without notice.
222 struct intrec *inthand_add(const char *name, int irq, inthand2_t handler,
223 void *arg, int flags, lwkt_serialize_t serializer);
225 int inthand_remove(struct intrec *idesc);
226 void forward_fastint_remote(void *arg);
232 #endif /* !_I386_ISA_INTR_MACHDEP_H_ */