2 * Copyright (c) 1997, 1998
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_rl.c,v 1.38.2.16 2003/03/05 18:42:33 njl Exp $
33 * $DragonFly: src/sys/dev/netif/rl/if_rl.c,v 1.37 2008/05/14 11:59:21 sephe Exp $
37 * RealTek 8129/8139 PCI NIC driver
39 * Supports several extremely cheap PCI 10/100 adapters based on
40 * the RealTek chipset. Datasheets can be obtained from
43 * Written by Bill Paul <wpaul@ctr.columbia.edu>
44 * Electrical Engineering Department
45 * Columbia University, New York City
49 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
50 * probably the worst PCI ethernet controller ever made, with the possible
51 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
52 * DMA, but it has a terrible interface that nullifies any performance
53 * gains that bus-master DMA usually offers.
55 * For transmission, the chip offers a series of four TX descriptor
56 * registers. Each transmit frame must be in a contiguous buffer, aligned
57 * on a longword (32-bit) boundary. This means we almost always have to
58 * do mbuf copies in order to transmit a frame, except in the unlikely
59 * case where a) the packet fits into a single mbuf, and b) the packet
60 * is 32-bit aligned within the mbuf's data area. The presence of only
61 * four descriptor registers means that we can never have more than four
62 * packets queued for transmission at any one time.
64 * Reception is not much better. The driver has to allocate a single large
65 * buffer area (up to 64K in size) into which the chip will DMA received
66 * frames. Because we don't know where within this region received packets
67 * will begin or end, we have no choice but to copy data from the buffer
68 * area into mbufs in order to pass the packets up to the higher protocol
71 * It's impossible given this rotten design to really achieve decent
72 * performance at 100Mbps, unless you happen to have a 400Mhz PII or
73 * some equally overmuscled CPU to drive it.
75 * On the bright side, the 8139 does have a built-in PHY, although
76 * rather than using an MDIO serial interface like most other NICs, the
77 * PHY registers are directly accessible through the 8139's register
78 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
81 * The 8129 chip is an older version of the 8139 that uses an external PHY
82 * chip. The 8129 has a serial MDIO interface for accessing the MII where
83 * the 8139 lets you directly access the on-board PHY registers. We need
84 * to select which interface to use depending on the chip type.
87 #include "opt_polling.h"
89 #include <sys/param.h>
90 #include <sys/endian.h>
91 #include <sys/systm.h>
92 #include <sys/sockio.h>
94 #include <sys/malloc.h>
95 #include <sys/kernel.h>
96 #include <sys/module.h>
97 #include <sys/socket.h>
98 #include <sys/serialize.h>
100 #include <sys/rman.h>
101 #include <sys/thread2.h>
102 #include <sys/interrupt.h>
105 #include <net/ifq_var.h>
106 #include <net/if_arp.h>
107 #include <net/ethernet.h>
108 #include <net/if_dl.h>
109 #include <net/if_media.h>
113 #include <dev/netif/mii_layer/mii.h>
114 #include <dev/netif/mii_layer/miivar.h>
116 #include <bus/pci/pcidevs.h>
117 #include <bus/pci/pcireg.h>
118 #include <bus/pci/pcivar.h>
120 /* "controller miibus0" required. See GENERIC if you get errors here. */
121 #include "miibus_if.h"
124 * Default to using PIO access for this driver. On SMP systems,
125 * there appear to be problems with memory mapped mode: it looks like
126 * doing too many memory mapped access back to back in rapid succession
127 * can hang the bus. I'm inclined to blame this on crummy design/construction
128 * on the part of RealTek. Memory mapped mode does appear to work on
129 * uniprocessor systems though.
131 #define RL_USEIOSPACE
133 #include <dev/netif/rl/if_rlreg.h>
136 * Various supported device vendors/types and their names.
138 static struct rl_type {
143 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8129,
144 "RealTek 8129 10/100BaseTX" },
145 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
146 "RealTek 8139 10/100BaseTX" },
147 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139B,
148 "RealTek 8139 10/100BaseTX CardBus" },
149 { PCI_VENDOR_ACCTON, PCI_PRODUCT_ACCTON_MPX5030,
150 "Accton MPX 5030/5038 10/100BaseTX" },
151 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_8139,
152 "Delta Electronics 8139 10/100BaseTX" },
153 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_8139,
154 "Addtron Technology 8139 10/100BaseTX" },
155 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE530TXPLUS,
156 "D-Link DFE-530TX+ 10/100BaseTX" },
157 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DFE690TXD,
158 "D-Link DFE-690TX 10/100BaseTX" },
159 { PCI_VENDOR_NORTEL, PCI_PRODUCT_NORTEL_BAYSTACK_21,
160 "Nortel Networks 10/100BaseTX" },
161 { PCI_VENDOR_PEPPERCON, PCI_PRODUCT_PEPPERCON_ROLF,
162 "Peppercon AG ROL/F" },
163 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CB_TXD,
164 "Corega FEther CB-TXD" },
165 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_2CB_TXD,
166 "Corega FEtherII CB-TXD" },
167 { PCI_VENDOR_PLANEX, PCI_PRODUCT_PLANEX_FNW_3800_TX,
168 "Planex FNW-3800-TX" },
172 static int rl_probe(device_t);
173 static int rl_attach(device_t);
174 static int rl_detach(device_t);
176 static int rl_encap(struct rl_softc *, struct mbuf * );
178 static void rl_rxeof(struct rl_softc *);
179 static void rl_txeof(struct rl_softc *);
180 static void rl_intr(void *);
181 static void rl_tick(void *);
182 static void rl_start(struct ifnet *);
183 static int rl_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
184 static void rl_init(void *);
185 static void rl_stop (struct rl_softc *);
186 static void rl_watchdog(struct ifnet *);
187 static int rl_suspend(device_t);
188 static int rl_resume(device_t);
189 static void rl_shutdown(device_t);
190 static int rl_ifmedia_upd(struct ifnet *);
191 static void rl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
193 static void rl_eeprom_putbyte(struct rl_softc *, int);
194 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *);
195 static void rl_read_eeprom(struct rl_softc *, caddr_t, int, int, int);
196 static void rl_mii_sync(struct rl_softc *);
197 static void rl_mii_send(struct rl_softc *, uint32_t, int);
198 static int rl_mii_readreg(struct rl_softc *, struct rl_mii_frame *);
199 static int rl_mii_writereg(struct rl_softc *, struct rl_mii_frame *);
201 static int rl_miibus_readreg(device_t, int, int);
202 static int rl_miibus_writereg(device_t, int, int, int);
203 static void rl_miibus_statchg(device_t);
205 static void rl_setmulti(struct rl_softc *);
206 static void rl_reset(struct rl_softc *);
207 static void rl_list_tx_init(struct rl_softc *);
209 static void rl_dma_map_rxbuf(void *, bus_dma_segment_t *, int, int);
210 static void rl_dma_map_txbuf(void *, bus_dma_segment_t *, int, int);
211 #ifdef DEVICE_POLLING
212 static poll_handler_t rl_poll;
216 #define RL_RES SYS_RES_IOPORT
217 #define RL_RID RL_PCI_LOIO
219 #define RL_RES SYS_RES_MEMORY
220 #define RL_RID RL_PCI_LOMEM
223 static device_method_t rl_methods[] = {
224 /* Device interface */
225 DEVMETHOD(device_probe, rl_probe),
226 DEVMETHOD(device_attach, rl_attach),
227 DEVMETHOD(device_detach, rl_detach),
228 DEVMETHOD(device_suspend, rl_suspend),
229 DEVMETHOD(device_resume, rl_resume),
230 DEVMETHOD(device_shutdown, rl_shutdown),
233 DEVMETHOD(bus_print_child, bus_generic_print_child),
234 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
237 DEVMETHOD(miibus_readreg, rl_miibus_readreg),
238 DEVMETHOD(miibus_writereg, rl_miibus_writereg),
239 DEVMETHOD(miibus_statchg, rl_miibus_statchg),
244 static DEFINE_CLASS_0(rl, rl_driver, rl_methods, sizeof(struct rl_softc));
245 static devclass_t rl_devclass;
247 DECLARE_DUMMY_MODULE(if_rl);
248 DRIVER_MODULE(if_rl, pci, rl_driver, rl_devclass, 0, 0);
249 DRIVER_MODULE(if_rl, cardbus, rl_driver, rl_devclass, 0, 0);
250 DRIVER_MODULE(miibus, rl, miibus_driver, miibus_devclass, 0, 0);
251 MODULE_DEPEND(if_rl, miibus, 1, 1, 1);
254 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) | (x))
257 CSR_WRITE_1(sc, RL_EECMD, CSR_READ_1(sc, RL_EECMD) & ~(x))
260 rl_dma_map_rxbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
262 struct rl_softc *sc = arg;
264 CSR_WRITE_4(sc, RL_RXADDR, segs->ds_addr & 0xFFFFFFFF);
268 rl_dma_map_txbuf(void *arg, bus_dma_segment_t *segs, int nseg, int error)
270 struct rl_softc *sc = arg;
272 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), segs->ds_addr & 0xFFFFFFFF);
276 * Send a read command and address to the EEPROM, check for ACK.
279 rl_eeprom_putbyte(struct rl_softc *sc, int addr)
283 d = addr | sc->rl_eecmd_read;
286 * Feed in each bit and strobe the clock.
288 for (i = 0x400; i; i >>= 1) {
290 EE_SET(RL_EE_DATAIN);
292 EE_CLR(RL_EE_DATAIN);
302 * Read a word of data stored in the EEPROM at address 'addr.'
305 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest)
310 /* Enter EEPROM access mode. */
311 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
314 * Send address of word we want to read.
316 rl_eeprom_putbyte(sc, addr);
318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
321 * Start reading bits from EEPROM.
323 for (i = 0x8000; i; i >>= 1) {
326 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
332 /* Turn off EEPROM access mode. */
333 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
339 * Read a sequence of words from the EEPROM.
342 rl_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt, int swap)
345 u_int16_t word = 0, *ptr;
347 for (i = 0; i < cnt; i++) {
348 rl_eeprom_getword(sc, off + i, &word);
349 ptr = (u_int16_t *)(dest + (i * 2));
359 * MII access routines are provided for the 8129, which
360 * doesn't have a built-in PHY. For the 8139, we fake things
361 * up by diverting rl_phy_readreg()/rl_phy_writereg() to the
362 * direct access PHY registers.
365 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) | x)
368 CSR_WRITE_1(sc, RL_MII, CSR_READ_1(sc, RL_MII) & ~x)
371 * Sync the PHYs by setting data bit and strobing the clock 32 times.
374 rl_mii_sync(struct rl_softc *sc)
378 MII_SET(RL_MII_DIR|RL_MII_DATAOUT);
380 for (i = 0; i < 32; i++) {
389 * Clock a series of bits through the MII.
392 rl_mii_send(struct rl_softc *sc, uint32_t bits, int cnt)
398 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
400 MII_SET(RL_MII_DATAOUT);
402 MII_CLR(RL_MII_DATAOUT);
411 * Read an PHY register through the MII.
414 rl_mii_readreg(struct rl_softc *sc, struct rl_mii_frame *frame)
419 * Set up frame for RX.
421 frame->mii_stdelim = RL_MII_STARTDELIM;
422 frame->mii_opcode = RL_MII_READOP;
423 frame->mii_turnaround = 0;
426 CSR_WRITE_2(sc, RL_MII, 0);
436 * Send command/address info.
438 rl_mii_send(sc, frame->mii_stdelim, 2);
439 rl_mii_send(sc, frame->mii_opcode, 2);
440 rl_mii_send(sc, frame->mii_phyaddr, 5);
441 rl_mii_send(sc, frame->mii_regaddr, 5);
444 MII_CLR((RL_MII_CLK|RL_MII_DATAOUT));
455 ack = CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN;
460 * Now try reading data bits. If the ack failed, we still
461 * need to clock through 16 cycles to keep the PHY(s) in sync.
464 for(i = 0; i < 16; i++) {
471 for (i = 0x8000; i; i >>= 1) {
475 if (CSR_READ_2(sc, RL_MII) & RL_MII_DATAIN)
476 frame->mii_data |= i;
493 * Write to a PHY register through the MII.
496 rl_mii_writereg(struct rl_softc *sc, struct rl_mii_frame *frame)
499 * Set up frame for TX.
501 frame->mii_stdelim = RL_MII_STARTDELIM;
502 frame->mii_opcode = RL_MII_WRITEOP;
503 frame->mii_turnaround = RL_MII_TURNAROUND;
506 * Turn on data output.
512 rl_mii_send(sc, frame->mii_stdelim, 2);
513 rl_mii_send(sc, frame->mii_opcode, 2);
514 rl_mii_send(sc, frame->mii_phyaddr, 5);
515 rl_mii_send(sc, frame->mii_regaddr, 5);
516 rl_mii_send(sc, frame->mii_turnaround, 2);
517 rl_mii_send(sc, frame->mii_data, 16);
534 rl_miibus_readreg(device_t dev, int phy, int reg)
537 struct rl_mii_frame frame;
539 uint16_t rl8139_reg = 0;
541 sc = device_get_softc(dev);
543 if (sc->rl_type == RL_8139) {
544 /* Pretend the internal PHY is only at address 0 */
549 rl8139_reg = RL_BMCR;
552 rl8139_reg = RL_BMSR;
555 rl8139_reg = RL_ANAR;
558 rl8139_reg = RL_ANER;
561 rl8139_reg = RL_LPAR;
568 * Allow the rlphy driver to read the media status
569 * register. If we have a link partner which does not
570 * support NWAY, this is the register which will tell
571 * us the results of parallel detection.
574 rval = CSR_READ_1(sc, RL_MEDIASTAT);
577 device_printf(dev, "bad phy register\n");
580 rval = CSR_READ_2(sc, rl8139_reg);
584 bzero(&frame, sizeof(frame));
586 frame.mii_phyaddr = phy;
587 frame.mii_regaddr = reg;
588 rl_mii_readreg(sc, &frame);
590 return(frame.mii_data);
594 rl_miibus_writereg(device_t dev, int phy, int reg, int data)
597 struct rl_mii_frame frame;
598 u_int16_t rl8139_reg = 0;
600 sc = device_get_softc(dev);
602 if (sc->rl_type == RL_8139) {
603 /* Pretend the internal PHY is only at address 0 */
608 rl8139_reg = RL_BMCR;
611 rl8139_reg = RL_BMSR;
614 rl8139_reg = RL_ANAR;
617 rl8139_reg = RL_ANER;
620 rl8139_reg = RL_LPAR;
626 device_printf(dev, "bad phy register\n");
629 CSR_WRITE_2(sc, rl8139_reg, data);
633 bzero(&frame, sizeof(frame));
635 frame.mii_phyaddr = phy;
636 frame.mii_regaddr = reg;
637 frame.mii_data = data;
639 rl_mii_writereg(sc, &frame);
645 rl_miibus_statchg(device_t dev)
650 * Program the 64-bit multicast hash filter.
653 rl_setmulti(struct rl_softc *sc)
657 uint32_t hashes[2] = { 0, 0 };
658 struct ifmultiaddr *ifma;
662 ifp = &sc->arpcom.ac_if;
664 rxfilt = CSR_READ_4(sc, RL_RXCFG);
666 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
667 rxfilt |= RL_RXCFG_RX_MULTI;
668 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
669 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
670 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
674 /* first, zot all the existing hash bits */
675 CSR_WRITE_4(sc, RL_MAR0, 0);
676 CSR_WRITE_4(sc, RL_MAR4, 0);
678 /* now program new ones */
679 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
680 if (ifma->ifma_addr->sa_family != AF_LINK)
683 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
684 ETHER_ADDR_LEN) >> 26;
686 hashes[0] |= (1 << h);
688 hashes[1] |= (1 << (h - 32));
693 rxfilt |= RL_RXCFG_RX_MULTI;
695 rxfilt &= ~RL_RXCFG_RX_MULTI;
697 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
698 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
699 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
703 rl_reset(struct rl_softc *sc)
707 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
709 for (i = 0; i < RL_TIMEOUT; i++) {
711 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
715 device_printf(sc->rl_dev, "reset never completed!\n");
719 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device
720 * IDs against our list and return a device name if we find a match.
722 * Return with a value < 0 to give re(4) a change to attach.
725 rl_probe(device_t dev)
728 uint16_t product = pci_get_device(dev);
729 uint16_t vendor = pci_get_vendor(dev);
731 for (t = rl_devs; t->rl_name != NULL; t++) {
732 if (vendor == t->rl_vid && product == t->rl_did) {
733 device_set_desc(dev, t->rl_name);
742 * Attach the interface. Allocate softc structures, do ifmedia
743 * setup and ethernet/BPF attach.
746 rl_attach(device_t dev)
748 uint8_t eaddr[ETHER_ADDR_LEN];
753 int error = 0, rid, i;
755 sc = device_get_softc(dev);
759 * Handle power management nonsense.
762 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
763 uint32_t iobase, membase, irq;
765 /* Save important PCI config data. */
766 iobase = pci_read_config(dev, RL_PCI_LOIO, 4);
767 membase = pci_read_config(dev, RL_PCI_LOMEM, 4);
768 irq = pci_read_config(dev, RL_PCI_INTLINE, 4);
770 /* Reset the power state. */
771 device_printf(dev, "chip is in D%d power mode "
772 "-- setting to D0\n", pci_get_powerstate(dev));
773 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
775 /* Restore PCI config data. */
776 pci_write_config(dev, RL_PCI_LOIO, iobase, 4);
777 pci_write_config(dev, RL_PCI_LOMEM, membase, 4);
778 pci_write_config(dev, RL_PCI_INTLINE, irq, 4);
781 pci_enable_busmaster(dev);
784 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, RF_ACTIVE);
786 if (sc->rl_res == NULL) {
787 device_printf(dev, "couldn't map ports/memory\n");
792 sc->rl_btag = rman_get_bustag(sc->rl_res);
793 sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
796 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
797 RF_SHAREABLE | RF_ACTIVE);
799 if (sc->rl_irq == NULL) {
800 device_printf(dev, "couldn't map interrupt\n");
805 callout_init(&sc->rl_stat_timer);
807 /* Reset the adapter. */
810 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
811 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0);
812 if (rl_did != 0x8129)
813 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
816 * Get station address from the EEPROM.
818 rl_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
819 for (i = 0; i < 3; i++) {
820 eaddr[(i * 2) + 0] = as[i] & 0xff;
821 eaddr[(i * 2) + 1] = as[i] >> 8;
825 * Now read the exact device type from the EEPROM to find
826 * out if it's an 8129 or 8139.
828 rl_read_eeprom(sc, (caddr_t)&rl_did, RL_EE_PCI_DID, 1, 0);
830 if (rl_did == PCI_PRODUCT_REALTEK_RT8139 ||
831 rl_did == PCI_PRODUCT_ACCTON_MPX5030 ||
832 rl_did == PCI_PRODUCT_DELTA_8139 ||
833 rl_did == PCI_PRODUCT_ADDTRON_8139 ||
834 rl_did == PCI_PRODUCT_DLINK_DFE530TXPLUS ||
835 rl_did == PCI_PRODUCT_REALTEK_RT8139B ||
836 rl_did == PCI_PRODUCT_DLINK_DFE690TXD ||
837 rl_did == PCI_PRODUCT_COREGA_CB_TXD ||
838 rl_did == PCI_PRODUCT_COREGA_2CB_TXD ||
839 rl_did == PCI_PRODUCT_PLANEX_FNW_3800_TX)
840 sc->rl_type = RL_8139;
841 else if (rl_did == PCI_PRODUCT_REALTEK_RT8129)
842 sc->rl_type = RL_8129;
844 device_printf(dev, "unknown device ID: %x\n", rl_did);
849 #define RL_NSEG_NEW 32
850 error = bus_dma_tag_create(NULL, /* parent */
851 1, 0, /* alignment, boundary */
852 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
853 BUS_SPACE_MAXADDR, /* highaddr */
854 NULL, NULL, /* filter, filterarg */
855 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */
856 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
857 BUS_DMA_ALLOCNOW, /* flags */
861 device_printf(dev, "can't create parent tag\n");
866 * Now allocate a tag for the DMA descriptor lists.
867 * All of our lists are allocated as a contiguous block
870 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */
871 1, 0, /* alignment, boundary */
872 BUS_SPACE_MAXADDR, /* lowaddr */
873 BUS_SPACE_MAXADDR, /* highaddr */
874 NULL, NULL, /* filter, filterarg */
875 RL_RXBUFLEN + 1518, 1, /* maxsize, nsegments */
876 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
881 device_printf(dev, "can't create RX tag\n");
886 * Now allocate a chunk of DMA-able memory based on the tag
889 error = bus_dmamem_alloc(sc->rl_tag, (void **)&sc->rl_cdata.rl_rx_buf,
890 BUS_DMA_WAITOK, &sc->rl_cdata.rl_rx_dmamap);
893 device_printf(dev, "can't allocate RX memory!\n");
898 /* Leave a few bytes before the start of the RX ring buffer. */
899 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf;
900 sc->rl_cdata.rl_rx_buf += sizeof(u_int64_t);
903 if (mii_phy_probe(dev, &sc->rl_miibus, rl_ifmedia_upd,
905 device_printf(dev, "MII without any phy!\n");
910 ifp = &sc->arpcom.ac_if;
912 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
913 ifp->if_mtu = ETHERMTU;
914 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
915 ifp->if_ioctl = rl_ioctl;
916 ifp->if_start = rl_start;
917 ifp->if_watchdog = rl_watchdog;
918 ifp->if_init = rl_init;
919 ifp->if_baudrate = 10000000;
920 ifp->if_capabilities = IFCAP_VLAN_MTU;
921 #ifdef DEVICE_POLLING
922 ifp->if_poll = rl_poll;
924 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
925 ifq_set_ready(&ifp->if_snd);
928 * Call MI attach routine.
930 ether_ifattach(ifp, eaddr, NULL);
932 error = bus_setup_intr(dev, sc->rl_irq, INTR_NETSAFE, rl_intr,
933 sc, &sc->rl_intrhand, ifp->if_serializer);
936 device_printf(dev, "couldn't set up irq\n");
941 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->rl_irq));
942 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
952 rl_detach(device_t dev)
957 sc = device_get_softc(dev);
958 ifp = &sc->arpcom.ac_if;
960 if (device_is_attached(dev)) {
961 lwkt_serialize_enter(ifp->if_serializer);
963 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand);
964 lwkt_serialize_exit(ifp->if_serializer);
970 device_delete_child(dev, sc->rl_miibus);
971 bus_generic_detach(dev);
974 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq);
976 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res);
978 if (sc->rl_cdata.rl_rx_buf) {
979 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
980 bus_dmamem_free(sc->rl_tag, sc->rl_cdata.rl_rx_buf,
981 sc->rl_cdata.rl_rx_dmamap);
984 bus_dma_tag_destroy(sc->rl_tag);
985 if (sc->rl_parent_tag)
986 bus_dma_tag_destroy(sc->rl_parent_tag);
992 * Initialize the transmit descriptors.
995 rl_list_tx_init(struct rl_softc *sc)
997 struct rl_chain_data *cd;
1001 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1002 cd->rl_tx_chain[i] = NULL;
1004 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000);
1007 sc->rl_cdata.cur_tx = 0;
1008 sc->rl_cdata.last_tx = 0;
1012 * A frame has been uploaded: pass the resulting mbuf chain up to
1013 * the higher level protocols.
1015 * You know there's something wrong with a PCI bus-master chip design
1016 * when you have to use m_devget().
1018 * The receive operation is badly documented in the datasheet, so I'll
1019 * attempt to document it here. The driver provides a buffer area and
1020 * places its base address in the RX buffer start address register.
1021 * The chip then begins copying frames into the RX buffer. Each frame
1022 * is preceded by a 32-bit RX status word which specifies the length
1023 * of the frame and certain other status bits. Each frame (starting with
1024 * the status word) is also 32-bit aligned. The frame length is in the
1025 * first 16 bits of the status word; the lower 15 bits correspond with
1026 * the 'rx status register' mentioned in the datasheet.
1028 * Note: to make the Alpha happy, the frame payload needs to be aligned
1029 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from
1030 * the ring buffer starting at an address two bytes before the actual
1031 * data location. We can then shave off the first two bytes using m_adj().
1032 * The reason we do this is because m_devget() doesn't let us specify an
1033 * offset into the mbuf storage space, so we have to artificially create
1034 * one. The ring is allocated in such a way that there are a few unused
1035 * bytes of space preceecing it so that it will be safe for us to do the
1036 * 2-byte backstep even if reading from the ring at offset 0.
1039 rl_rxeof(struct rl_softc *sc)
1047 uint16_t cur_rx, limit, max_bytes, rx_bytes = 0;
1049 ifp = &sc->arpcom.ac_if;
1051 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1052 BUS_DMASYNC_POSTREAD);
1054 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN;
1056 /* Do not try to read past this point. */
1057 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN;
1060 max_bytes = (RL_RXBUFLEN - cur_rx) + limit;
1062 max_bytes = limit - cur_rx;
1064 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) {
1065 #ifdef DEVICE_POLLING
1066 if (ifp->if_flags & IFF_POLLING) {
1067 if (sc->rxcycles <= 0)
1071 #endif /* DEVICE_POLLING */
1072 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx;
1073 rxstat = le32toh(*(uint32_t *)rxbufpos);
1076 * Here's a totally undocumented fact for you. When the
1077 * RealTek chip is in the process of copying a packet into
1078 * RAM for you, the length will be 0xfff0. If you spot a
1079 * packet header with this value, you need to stop. The
1080 * datasheet makes absolutely no mention of this and
1081 * RealTek should be shot for this.
1083 if ((uint16_t)(rxstat >> 16) == RL_RXSTAT_UNFINISHED)
1086 if ((rxstat & RL_RXSTAT_RXOK) == 0) {
1092 /* No errors; receive the packet. */
1093 total_len = rxstat >> 16;
1094 rx_bytes += total_len + 4;
1097 * XXX The RealTek chip includes the CRC with every
1098 * received frame, and there's no way to turn this
1099 * behavior off (at least, I can't find anything in
1100 * the manual that explains how to do it) so we have
1101 * to trim off the CRC manually.
1103 total_len -= ETHER_CRC_LEN;
1106 * Avoid trying to read more bytes than we know
1107 * the chip has prepared for us.
1109 if (rx_bytes > max_bytes)
1112 rxbufpos = sc->rl_cdata.rl_rx_buf +
1113 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN);
1115 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN))
1116 rxbufpos = sc->rl_cdata.rl_rx_buf;
1118 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos;
1120 if (total_len > wrap) {
1122 * Fool m_devget() into thinking we want to copy
1123 * the whole buffer so we don't end up fragmenting
1126 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1127 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1131 m_adj(m, RL_ETHER_ALIGN);
1132 m_copyback(m, wrap, total_len - wrap,
1133 sc->rl_cdata.rl_rx_buf);
1135 cur_rx = (total_len - wrap + ETHER_CRC_LEN);
1137 m = m_devget(rxbufpos - RL_ETHER_ALIGN,
1138 total_len + RL_ETHER_ALIGN, 0, ifp, NULL);
1142 m_adj(m, RL_ETHER_ALIGN);
1143 cur_rx += total_len + 4 + ETHER_CRC_LEN;
1147 * Round up to 32-bit boundary.
1149 cur_rx = (cur_rx + 3) & ~3;
1150 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1157 ifp->if_input(ifp, m);
1162 * A frame was downloaded to the chip. It's safe for us to clean up
1166 rl_txeof(struct rl_softc *sc)
1171 ifp = &sc->arpcom.ac_if;
1174 * Go through our tx list and free mbufs for those
1175 * frames that have been uploaded.
1178 if (RL_LAST_TXMBUF(sc) == NULL)
1180 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc));
1181 if ((txstat & (RL_TXSTAT_TX_OK | RL_TXSTAT_TX_UNDERRUN |
1182 RL_TXSTAT_TXABRT)) == 0)
1185 ifp->if_collisions += (txstat & RL_TXSTAT_COLLCNT) >> 24;
1187 bus_dmamap_unload(sc->rl_tag, RL_LAST_DMAMAP(sc));
1188 bus_dmamap_destroy(sc->rl_tag, RL_LAST_DMAMAP(sc));
1189 m_freem(RL_LAST_TXMBUF(sc));
1190 RL_LAST_TXMBUF(sc) = NULL;
1191 RL_INC(sc->rl_cdata.last_tx);
1193 if (txstat & RL_TXSTAT_TX_UNDERRUN) {
1194 sc->rl_txthresh += 32;
1195 if (sc->rl_txthresh > RL_TX_THRESH_MAX)
1196 sc->rl_txthresh = RL_TX_THRESH_MAX;
1199 if (txstat & RL_TXSTAT_TX_OK) {
1203 if (txstat & (RL_TXSTAT_TXABRT | RL_TXSTAT_OUTOFWIN))
1204 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1206 ifp->if_flags &= ~IFF_OACTIVE;
1207 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx);
1209 if (RL_LAST_TXMBUF(sc) == NULL)
1211 else if (ifp->if_timer == 0)
1218 struct rl_softc *sc = xsc;
1219 struct mii_data *mii;
1221 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1223 mii = device_get_softc(sc->rl_miibus);
1226 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1228 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1231 #ifdef DEVICE_POLLING
1234 rl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1236 struct rl_softc *sc = ifp->if_softc;
1240 /* disable interrupts */
1241 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1243 case POLL_DEREGISTER:
1244 /* enable interrupts */
1245 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1248 sc->rxcycles = count;
1251 if (!ifq_is_empty(&ifp->if_snd))
1254 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1257 status = CSR_READ_2(sc, RL_ISR);
1258 if (status == 0xffff)
1261 CSR_WRITE_2(sc, RL_ISR, status);
1264 * XXX check behaviour on receiver stalls.
1267 if (status & RL_ISR_SYSTEM_ERR) {
1275 #endif /* DEVICE_POLLING */
1280 struct rl_softc *sc;
1289 ifp = &sc->arpcom.ac_if;
1292 status = CSR_READ_2(sc, RL_ISR);
1293 /* If the card has gone away, the read returns 0xffff. */
1294 if (status == 0xffff)
1298 CSR_WRITE_2(sc, RL_ISR, status);
1300 if ((status & RL_INTRS) == 0)
1303 if (status & RL_ISR_RX_OK)
1306 if (status & RL_ISR_RX_ERR)
1309 if ((status & RL_ISR_TX_OK) || (status & RL_ISR_TX_ERR))
1312 if (status & RL_ISR_SYSTEM_ERR) {
1319 if (!ifq_is_empty(&ifp->if_snd))
1324 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1325 * pointers to the fragment pointers.
1328 rl_encap(struct rl_softc *sc, struct mbuf *m_head)
1330 struct mbuf *m_new = NULL;
1333 * The RealTek is brain damaged and wants longword-aligned
1334 * TX buffers, plus we can only have one fragment buffer
1335 * per packet. We have to copy pretty much all the time.
1337 m_new = m_defrag(m_head, MB_DONTWAIT);
1339 if (m_new == NULL) {
1345 /* Pad frames to at least 60 bytes. */
1346 if (m_head->m_pkthdr.len < RL_MIN_FRAMELEN) {
1348 * Make security concious people happy: zero out the
1349 * bytes in the pad area, since we don't know what
1350 * this mbuf cluster buffer's previous user might
1353 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
1354 RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1355 m_head->m_pkthdr.len +=
1356 (RL_MIN_FRAMELEN - m_head->m_pkthdr.len);
1357 m_head->m_len = m_head->m_pkthdr.len;
1360 RL_CUR_TXMBUF(sc) = m_head;
1366 * Main transmit routine.
1370 rl_start(struct ifnet *ifp)
1372 struct rl_softc *sc = ifp->if_softc;
1373 struct mbuf *m_head = NULL;
1375 if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
1378 while (RL_CUR_TXMBUF(sc) == NULL) {
1379 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1383 if (rl_encap(sc, m_head))
1387 * If there's a BPF listener, bounce a copy of this frame
1390 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc));
1393 * Transmit the frame.
1395 bus_dmamap_create(sc->rl_tag, 0, &RL_CUR_DMAMAP(sc));
1396 bus_dmamap_load(sc->rl_tag, RL_CUR_DMAMAP(sc),
1397 mtod(RL_CUR_TXMBUF(sc), void *),
1398 RL_CUR_TXMBUF(sc)->m_pkthdr.len,
1399 rl_dma_map_txbuf, sc, 0);
1400 bus_dmamap_sync(sc->rl_tag, RL_CUR_DMAMAP(sc),
1401 BUS_DMASYNC_PREREAD);
1402 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc),
1403 RL_TXTHRESH(sc->rl_txthresh) |
1404 RL_CUR_TXMBUF(sc)->m_pkthdr.len);
1406 RL_INC(sc->rl_cdata.cur_tx);
1409 * Set a timeout in case the chip goes out to lunch.
1415 * We broke out of the loop because all our TX slots are
1416 * full. Mark the NIC as busy until it drains some of the
1417 * packets from the queue.
1419 if (RL_CUR_TXMBUF(sc) != NULL)
1420 ifp->if_flags |= IFF_OACTIVE;
1426 struct rl_softc *sc = xsc;
1427 struct ifnet *ifp = &sc->arpcom.ac_if;
1428 struct mii_data *mii;
1431 mii = device_get_softc(sc->rl_miibus);
1434 * Cancel pending I/O and free all RX/TX buffers.
1439 * Init our MAC address. Even though the chipset documentation
1440 * doesn't mention it, we need to enter "Config register write enable"
1441 * mode to modify the ID registers.
1443 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1444 CSR_WRITE_STREAM_4(sc, RL_IDR0,
1445 *(uint32_t *)(&sc->arpcom.ac_enaddr[0]));
1446 CSR_WRITE_STREAM_4(sc, RL_IDR4,
1447 *(uint32_t *)(&sc->arpcom.ac_enaddr[4]));
1448 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1450 /* Init the RX buffer pointer register. */
1451 bus_dmamap_load(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1452 sc->rl_cdata.rl_rx_buf, RL_RXBUFLEN, rl_dma_map_rxbuf,
1454 bus_dmamap_sync(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap,
1455 BUS_DMASYNC_PREWRITE);
1457 /* Init TX descriptors. */
1458 rl_list_tx_init(sc);
1461 * Enable transmit and receive.
1463 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1466 * Set the initial TX and RX configuration.
1468 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1469 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1471 /* Set the individual bit to receive frames for this host only. */
1472 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1473 rxcfg |= RL_RXCFG_RX_INDIV;
1475 /* If we want promiscuous mode, set the allframes bit. */
1476 if (ifp->if_flags & IFF_PROMISC) {
1477 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1478 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1480 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1481 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1485 * Set capture broadcast bit to capture broadcast frames.
1487 if (ifp->if_flags & IFF_BROADCAST) {
1488 rxcfg |= RL_RXCFG_RX_BROAD;
1489 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1491 rxcfg &= ~RL_RXCFG_RX_BROAD;
1492 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1496 * Program the multicast filter, if necessary.
1500 #ifdef DEVICE_POLLING
1502 * Only enable interrupts if we are polling, keep them off otherwise.
1504 if (ifp->if_flags & IFF_POLLING)
1505 CSR_WRITE_2(sc, RL_IMR, 0);
1507 #endif /* DEVICE_POLLING */
1509 * Enable interrupts.
1511 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1513 /* Set initial TX threshold */
1514 sc->rl_txthresh = RL_TX_THRESH_INIT;
1516 /* Start RX/TX process. */
1517 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1519 /* Enable receiver and transmitter. */
1520 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1524 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1526 ifp->if_flags |= IFF_RUNNING;
1527 ifp->if_flags &= ~IFF_OACTIVE;
1529 callout_reset(&sc->rl_stat_timer, hz, rl_tick, sc);
1533 * Set media options.
1536 rl_ifmedia_upd(struct ifnet *ifp)
1538 struct rl_softc *sc;
1539 struct mii_data *mii;
1542 mii = device_get_softc(sc->rl_miibus);
1549 * Report current media status.
1552 rl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1554 struct rl_softc *sc = ifp->if_softc;
1555 struct mii_data *mii = device_get_softc(sc->rl_miibus);
1558 ifmr->ifm_active = mii->mii_media_active;
1559 ifmr->ifm_status = mii->mii_media_status;
1563 rl_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1565 struct rl_softc *sc = ifp->if_softc;
1566 struct ifreq *ifr = (struct ifreq *) data;
1567 struct mii_data *mii;
1572 if (ifp->if_flags & IFF_UP) {
1575 if (ifp->if_flags & IFF_RUNNING)
1587 mii = device_get_softc(sc->rl_miibus);
1588 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1593 error = ether_ioctl(ifp, command, data);
1601 rl_watchdog(struct ifnet *ifp)
1603 struct rl_softc *sc = ifp->if_softc;
1605 device_printf(sc->rl_dev, "watchdog timeout\n");
1615 * Stop the adapter and free any mbufs allocated to the
1619 rl_stop(struct rl_softc *sc)
1621 struct ifnet *ifp = &sc->arpcom.ac_if;
1626 callout_stop(&sc->rl_stat_timer);
1627 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1629 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1630 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1631 bus_dmamap_unload(sc->rl_tag, sc->rl_cdata.rl_rx_dmamap);
1634 * Free the TX list buffers.
1636 for (i = 0; i < RL_TX_LIST_CNT; i++) {
1637 if (sc->rl_cdata.rl_tx_chain[i] != NULL) {
1638 bus_dmamap_unload(sc->rl_tag,
1639 sc->rl_cdata.rl_tx_dmamap[i]);
1640 bus_dmamap_destroy(sc->rl_tag,
1641 sc->rl_cdata.rl_tx_dmamap[i]);
1642 m_freem(sc->rl_cdata.rl_tx_chain[i]);
1643 sc->rl_cdata.rl_tx_chain[i] = NULL;
1644 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)),
1651 * Stop all chip I/O so that the kernel's probe routines don't
1652 * get confused by errant DMAs when rebooting.
1655 rl_shutdown(device_t dev)
1657 struct rl_softc *sc;
1659 sc = device_get_softc(dev);
1660 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1662 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1666 * Device suspend routine. Stop the interface and save some PCI
1667 * settings in case the BIOS doesn't restore them properly on
1671 rl_suspend(device_t dev)
1673 struct rl_softc *sc = device_get_softc(dev);
1676 lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
1679 for (i = 0; i < 5; i++)
1680 sc->saved_maps[i] = pci_read_config(dev, PCIR_BAR(i), 4);
1681 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
1682 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
1683 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
1684 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
1688 lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
1693 * Device resume routine. Restore some PCI settings in case the BIOS
1694 * doesn't, re-enable busmastering, and restart the interface if
1698 rl_resume(device_t dev)
1700 struct rl_softc *sc = device_get_softc(dev);
1701 struct ifnet *ifp = &sc->arpcom.ac_if;
1704 lwkt_serialize_enter(ifp->if_serializer);
1706 /* better way to do this? */
1707 for (i = 0; i < 5; i++)
1708 pci_write_config(dev, PCIR_BAR(i), sc->saved_maps[i], 4);
1709 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
1710 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
1711 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
1712 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
1714 /* reenable busmastering */
1715 pci_enable_busmaster(dev);
1716 pci_enable_io(dev, RL_RES);
1718 /* reinitialize interface if necessary */
1719 if (ifp->if_flags & IFF_UP)
1723 lwkt_serialize_exit(ifp->if_serializer);