sys/dev/netif/jme/if_jme.c

   1 /*-
   2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
  28  */
  29
  30 #include "opt_polling.h"
  31 #include "opt_rss.h"
  32 #include "opt_jme.h"
  33
  34 #include <sys/param.h>
  35 #include <sys/endian.h>
  36 #include <sys/kernel.h>
  37 #include <sys/bus.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/malloc.h>
  40 #include <sys/proc.h>
  41 #include <sys/rman.h>
  42 #include <sys/serialize.h>
  43 #include <sys/serialize2.h>
  44 #include <sys/socket.h>
  45 #include <sys/sockio.h>
  46 #include <sys/sysctl.h>
  47
  48 #include <net/ethernet.h>
  49 #include <net/if.h>
  50 #include <net/bpf.h>
  51 #include <net/if_arp.h>
  52 #include <net/if_dl.h>
  53 #include <net/if_media.h>
  54 #include <net/ifq_var.h>
  55 #include <net/toeplitz.h>
  56 #include <net/toeplitz2.h>
  57 #include <net/vlan/if_vlan_var.h>
  58 #include <net/vlan/if_vlan_ether.h>
  59
  60 #include <netinet/in.h>
  61
  62 #include <dev/netif/mii_layer/miivar.h>
  63 #include <dev/netif/mii_layer/jmphyreg.h>
  64
  65 #include <bus/pci/pcireg.h>
  66 #include <bus/pci/pcivar.h>
  67 #include <bus/pci/pcidevs.h>
  68
  69 #include <dev/netif/jme/if_jmereg.h>
  70 #include <dev/netif/jme/if_jmevar.h>
  71
  72 #include "miibus_if.h"
  73
  74 /* Define the following to disable printing Rx errors. */
  75 #undef  JME_SHOW_ERRORS
  76
  77 #define JME_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  78
  79 #ifdef JME_RSS_DEBUG
  80 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
  81 do { \
  82         if ((sc)->jme_rss_debug >= (lvl)) \
  83                 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
  84 } while (0)
  85 #else   /* !JME_RSS_DEBUG */
  86 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  87 #endif  /* JME_RSS_DEBUG */
  88
  89 static int      jme_probe(device_t);
  90 static int      jme_attach(device_t);
  91 static int      jme_detach(device_t);
  92 static int      jme_shutdown(device_t);
  93 static int      jme_suspend(device_t);
  94 static int      jme_resume(device_t);
  95
  96 static int      jme_miibus_readreg(device_t, int, int);
  97 static int      jme_miibus_writereg(device_t, int, int, int);
  98 static void     jme_miibus_statchg(device_t);
  99
 100 static void     jme_init(void *);
 101 static int      jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 102 static void     jme_start(struct ifnet *);
 103 static void     jme_watchdog(struct ifnet *);
 104 static void     jme_mediastatus(struct ifnet *, struct ifmediareq *);
 105 static int      jme_mediachange(struct ifnet *);
 106 #ifdef DEVICE_POLLING
 107 static void     jme_poll(struct ifnet *, enum poll_cmd, int);
 108 #endif
 109 static void     jme_serialize(struct ifnet *, enum ifnet_serialize);
 110 static void     jme_deserialize(struct ifnet *, enum ifnet_serialize);
 111 static int      jme_tryserialize(struct ifnet *, enum ifnet_serialize);
 112 #ifdef INVARIANTS
 113 static void     jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
 114                     boolean_t);
 115 #endif
 116
 117 static void     jme_intr(void *);
 118 static void     jme_msix_tx(void *);
 119 static void     jme_msix_rx(void *);
 120 static void     jme_txeof(struct jme_softc *);
 121 static void     jme_rxeof(struct jme_rxdata *, int);
 122 static void     jme_rx_intr(struct jme_softc *, uint32_t);
 123
 124 static int      jme_msix_setup(device_t);
 125 static void     jme_msix_teardown(device_t, int);
 126 static int      jme_intr_setup(device_t);
 127 static void     jme_intr_teardown(device_t);
 128 static void     jme_msix_try_alloc(device_t);
 129 static void     jme_msix_free(device_t);
 130 static int      jme_intr_alloc(device_t);
 131 static void     jme_intr_free(device_t);
 132 static int      jme_dma_alloc(struct jme_softc *);
 133 static void     jme_dma_free(struct jme_softc *);
 134 static int      jme_init_rx_ring(struct jme_rxdata *);
 135 static void     jme_init_tx_ring(struct jme_softc *);
 136 static void     jme_init_ssb(struct jme_softc *);
 137 static int      jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
 138 static int      jme_encap(struct jme_softc *, struct mbuf **);
 139 static void     jme_rxpkt(struct jme_rxdata *);
 140 static int      jme_rxring_dma_alloc(struct jme_rxdata *);
 141 static int      jme_rxbuf_dma_alloc(struct jme_rxdata *);
 142
 143 static void     jme_tick(void *);
 144 static void     jme_stop(struct jme_softc *);
 145 static void     jme_reset(struct jme_softc *);
 146 static void     jme_set_msinum(struct jme_softc *);
 147 static void     jme_set_vlan(struct jme_softc *);
 148 static void     jme_set_filter(struct jme_softc *);
 149 static void     jme_stop_tx(struct jme_softc *);
 150 static void     jme_stop_rx(struct jme_softc *);
 151 static void     jme_mac_config(struct jme_softc *);
 152 static void     jme_reg_macaddr(struct jme_softc *, uint8_t[]);
 153 static int      jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
 154 static int      jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
 155 #ifdef notyet
 156 static void     jme_setwol(struct jme_softc *);
 157 static void     jme_setlinkspeed(struct jme_softc *);
 158 #endif
 159 static void     jme_set_tx_coal(struct jme_softc *);
 160 static void     jme_set_rx_coal(struct jme_softc *);
 161 static void     jme_enable_rss(struct jme_softc *);
 162 static void     jme_disable_rss(struct jme_softc *);
 163
 164 static void     jme_sysctl_node(struct jme_softc *);
 165 static int      jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
 166 static int      jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
 167 static int      jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
 168 static int      jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
 169
 170 /*
 171  * Devices supported by this driver.
 172  */
 173 static const struct jme_dev {
 174         uint16_t        jme_vendorid;
 175         uint16_t        jme_deviceid;
 176         uint32_t        jme_caps;
 177         const char      *jme_name;
 178 } jme_devs[] = {
 179         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
 180             JME_CAP_JUMBO,
 181             "JMicron Inc, JMC250 Gigabit Ethernet" },
 182         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
 183             JME_CAP_FASTETH,
 184             "JMicron Inc, JMC260 Fast Ethernet" },
 185         { 0, 0, 0, NULL }
 186 };
 187
 188 static device_method_t jme_methods[] = {
 189         /* Device interface. */
 190         DEVMETHOD(device_probe,         jme_probe),
 191         DEVMETHOD(device_attach,        jme_attach),
 192         DEVMETHOD(device_detach,        jme_detach),
 193         DEVMETHOD(device_shutdown,      jme_shutdown),
 194         DEVMETHOD(device_suspend,       jme_suspend),
 195         DEVMETHOD(device_resume,        jme_resume),
 196
 197         /* Bus interface. */
 198         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 199         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 200
 201         /* MII interface. */
 202         DEVMETHOD(miibus_readreg,       jme_miibus_readreg),
 203         DEVMETHOD(miibus_writereg,      jme_miibus_writereg),
 204         DEVMETHOD(miibus_statchg,       jme_miibus_statchg),
 205
 206         { NULL, NULL }
 207 };
 208
 209 static driver_t jme_driver = {
 210         "jme",
 211         jme_methods,
 212         sizeof(struct jme_softc)
 213 };
 214
 215 static devclass_t jme_devclass;
 216
 217 DECLARE_DUMMY_MODULE(if_jme);
 218 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
 219 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
 220 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
 221
 222 static const struct {
 223         uint32_t        jme_coal;
 224         uint32_t        jme_comp;
 225         uint32_t        jme_empty;
 226 } jme_rx_status[JME_NRXRING_MAX] = {
 227         { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
 228           INTR_RXQ0_DESC_EMPTY },
 229         { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
 230           INTR_RXQ1_DESC_EMPTY },
 231         { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
 232           INTR_RXQ2_DESC_EMPTY },
 233         { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
 234           INTR_RXQ3_DESC_EMPTY }
 235 };
 236
 237 static int      jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
 238 static int      jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
 239 static int      jme_rx_ring_count = 1;
 240 static int      jme_msi_enable = 1;
 241 static int      jme_msix_enable = 1;
 242
 243 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
 244 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
 245 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
 246 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
 247 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
 248
 249 /*
 250  *      Read a PHY register on the MII of the JMC250.
 251  */
 252 static int
 253 jme_miibus_readreg(device_t dev, int phy, int reg)
 254 {
 255         struct jme_softc *sc = device_get_softc(dev);
 256         uint32_t val;
 257         int i;
 258
 259         /* For FPGA version, PHY address 0 should be ignored. */
 260         if (sc->jme_caps & JME_CAP_FPGA) {
 261                 if (phy == 0)
 262                         return (0);
 263         } else {
 264                 if (sc->jme_phyaddr != phy)
 265                         return (0);
 266         }
 267
 268         CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
 269             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 270
 271         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 272                 DELAY(1);
 273                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 274                         break;
 275         }
 276         if (i == 0) {
 277                 device_printf(sc->jme_dev, "phy read timeout: "
 278                               "phy %d, reg %d\n", phy, reg);
 279                 return (0);
 280         }
 281
 282         return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
 283 }
 284
 285 /*
 286  *      Write a PHY register on the MII of the JMC250.
 287  */
 288 static int
 289 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
 290 {
 291         struct jme_softc *sc = device_get_softc(dev);
 292         int i;
 293
 294         /* For FPGA version, PHY address 0 should be ignored. */
 295         if (sc->jme_caps & JME_CAP_FPGA) {
 296                 if (phy == 0)
 297                         return (0);
 298         } else {
 299                 if (sc->jme_phyaddr != phy)
 300                         return (0);
 301         }
 302
 303         CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
 304             ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
 305             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 306
 307         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 308                 DELAY(1);
 309                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 310                         break;
 311         }
 312         if (i == 0) {
 313                 device_printf(sc->jme_dev, "phy write timeout: "
 314                               "phy %d, reg %d\n", phy, reg);
 315         }
 316
 317         return (0);
 318 }
 319
 320 /*
 321  *      Callback from MII layer when media changes.
 322  */
 323 static void
 324 jme_miibus_statchg(device_t dev)
 325 {
 326         struct jme_softc *sc = device_get_softc(dev);
 327         struct ifnet *ifp = &sc->arpcom.ac_if;
 328         struct mii_data *mii;
 329         struct jme_txdesc *txd;
 330         bus_addr_t paddr;
 331         int i, r;
 332
 333         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 334
 335         if ((ifp->if_flags & IFF_RUNNING) == 0)
 336                 return;
 337
 338         mii = device_get_softc(sc->jme_miibus);
 339
 340         sc->jme_flags &= ~JME_FLAG_LINK;
 341         if ((mii->mii_media_status & IFM_AVALID) != 0) {
 342                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 343                 case IFM_10_T:
 344                 case IFM_100_TX:
 345                         sc->jme_flags |= JME_FLAG_LINK;
 346                         break;
 347                 case IFM_1000_T:
 348                         if (sc->jme_caps & JME_CAP_FASTETH)
 349                                 break;
 350                         sc->jme_flags |= JME_FLAG_LINK;
 351                         break;
 352                 default:
 353                         break;
 354                 }
 355         }
 356
 357         /*
 358          * Disabling Rx/Tx MACs have a side-effect of resetting
 359          * JME_TXNDA/JME_RXNDA register to the first address of
 360          * Tx/Rx descriptor address. So driver should reset its
 361          * internal procucer/consumer pointer and reclaim any
 362          * allocated resources.  Note, just saving the value of
 363          * JME_TXNDA and JME_RXNDA registers before stopping MAC
 364          * and restoring JME_TXNDA/JME_RXNDA register is not
 365          * sufficient to make sure correct MAC state because
 366          * stopping MAC operation can take a while and hardware
 367          * might have updated JME_TXNDA/JME_RXNDA registers
 368          * during the stop operation.
 369          */
 370
 371         /* Disable interrupts */
 372         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
 373
 374         /* Stop driver */
 375         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 376         ifp->if_timer = 0;
 377         callout_stop(&sc->jme_tick_ch);
 378
 379         /* Stop receiver/transmitter. */
 380         jme_stop_rx(sc);
 381         jme_stop_tx(sc);
 382
 383         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
 384                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
 385
 386                 jme_rxeof(rdata, -1);
 387                 if (rdata->jme_rxhead != NULL)
 388                         m_freem(rdata->jme_rxhead);
 389                 JME_RXCHAIN_RESET(rdata);
 390
 391                 /*
 392                  * Reuse configured Rx descriptors and reset
 393                  * procuder/consumer index.
 394                  */
 395                 rdata->jme_rx_cons = 0;
 396         }
 397
 398         jme_txeof(sc);
 399         if (sc->jme_cdata.jme_tx_cnt != 0) {
 400                 /* Remove queued packets for transmit. */
 401                 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
 402                         txd = &sc->jme_cdata.jme_txdesc[i];
 403                         if (txd->tx_m != NULL) {
 404                                 bus_dmamap_unload(
 405                                     sc->jme_cdata.jme_tx_tag,
 406                                     txd->tx_dmamap);
 407                                 m_freem(txd->tx_m);
 408                                 txd->tx_m = NULL;
 409                                 txd->tx_ndesc = 0;
 410                                 ifp->if_oerrors++;
 411                         }
 412                 }
 413         }
 414         jme_init_tx_ring(sc);
 415
 416         /* Initialize shadow status block. */
 417         jme_init_ssb(sc);
 418
 419         /* Program MAC with resolved speed/duplex/flow-control. */
 420         if (sc->jme_flags & JME_FLAG_LINK) {
 421                 jme_mac_config(sc);
 422
 423                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
 424
 425                 /* Set Tx ring address to the hardware. */
 426                 paddr = sc->jme_cdata.jme_tx_ring_paddr;
 427                 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
 428                 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
 429
 430                 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
 431                         CSR_WRITE_4(sc, JME_RXCSR,
 432                             sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
 433
 434                         /* Set Rx ring address to the hardware. */
 435                         paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
 436                         CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
 437                         CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
 438                 }
 439
 440                 /* Restart receiver/transmitter. */
 441                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
 442                     RXCSR_RXQ_START);
 443                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
 444         }
 445
 446         ifp->if_flags |= IFF_RUNNING;
 447         ifp->if_flags &= ~IFF_OACTIVE;
 448         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
 449
 450 #ifdef DEVICE_POLLING
 451         if (!(ifp->if_flags & IFF_POLLING))
 452 #endif
 453         /* Reenable interrupts. */
 454         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
 455 }
 456
 457 /*
 458  *      Get the current interface media status.
 459  */
 460 static void
 461 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 462 {
 463         struct jme_softc *sc = ifp->if_softc;
 464         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 465
 466         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 467
 468         mii_pollstat(mii);
 469         ifmr->ifm_status = mii->mii_media_status;
 470         ifmr->ifm_active = mii->mii_media_active;
 471 }
 472
 473 /*
 474  *      Set hardware to newly-selected media.
 475  */
 476 static int
 477 jme_mediachange(struct ifnet *ifp)
 478 {
 479         struct jme_softc *sc = ifp->if_softc;
 480         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 481         int error;
 482
 483         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 484
 485         if (mii->mii_instance != 0) {
 486                 struct mii_softc *miisc;
 487
 488                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 489                         mii_phy_reset(miisc);
 490         }
 491         error = mii_mediachg(mii);
 492
 493         return (error);
 494 }
 495
 496 static int
 497 jme_probe(device_t dev)
 498 {
 499         const struct jme_dev *sp;
 500         uint16_t vid, did;
 501
 502         vid = pci_get_vendor(dev);
 503         did = pci_get_device(dev);
 504         for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
 505                 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
 506                         struct jme_softc *sc = device_get_softc(dev);
 507
 508                         sc->jme_caps = sp->jme_caps;
 509                         device_set_desc(dev, sp->jme_name);
 510                         return (0);
 511                 }
 512         }
 513         return (ENXIO);
 514 }
 515
 516 static int
 517 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
 518 {
 519         uint32_t reg;
 520         int i;
 521
 522         *val = 0;
 523         for (i = JME_TIMEOUT; i > 0; i--) {
 524                 reg = CSR_READ_4(sc, JME_SMBCSR);
 525                 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
 526                         break;
 527                 DELAY(1);
 528         }
 529
 530         if (i == 0) {
 531                 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
 532                 return (ETIMEDOUT);
 533         }
 534
 535         reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
 536         CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
 537         for (i = JME_TIMEOUT; i > 0; i--) {
 538                 DELAY(1);
 539                 reg = CSR_READ_4(sc, JME_SMBINTF);
 540                 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
 541                         break;
 542         }
 543
 544         if (i == 0) {
 545                 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
 546                 return (ETIMEDOUT);
 547         }
 548
 549         reg = CSR_READ_4(sc, JME_SMBINTF);
 550         *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
 551
 552         return (0);
 553 }
 554
 555 static int
 556 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 557 {
 558         uint8_t fup, reg, val;
 559         uint32_t offset;
 560         int match;
 561
 562         offset = 0;
 563         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 564             fup != JME_EEPROM_SIG0)
 565                 return (ENOENT);
 566         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 567             fup != JME_EEPROM_SIG1)
 568                 return (ENOENT);
 569         match = 0;
 570         do {
 571                 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
 572                         break;
 573                 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
 574                     (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
 575                         if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
 576                                 break;
 577                         if (reg >= JME_PAR0 &&
 578                             reg < JME_PAR0 + ETHER_ADDR_LEN) {
 579                                 if (jme_eeprom_read_byte(sc, offset + 2,
 580                                     &val) != 0)
 581                                         break;
 582                                 eaddr[reg - JME_PAR0] = val;
 583                                 match++;
 584                         }
 585                 }
 586                 /* Check for the end of EEPROM descriptor. */
 587                 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
 588                         break;
 589                 /* Try next eeprom descriptor. */
 590                 offset += JME_EEPROM_DESC_BYTES;
 591         } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
 592
 593         if (match == ETHER_ADDR_LEN)
 594                 return (0);
 595
 596         return (ENOENT);
 597 }
 598
 599 static void
 600 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 601 {
 602         uint32_t par0, par1;
 603
 604         /* Read station address. */
 605         par0 = CSR_READ_4(sc, JME_PAR0);
 606         par1 = CSR_READ_4(sc, JME_PAR1);
 607         par1 &= 0xFFFF;
 608         if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
 609                 device_printf(sc->jme_dev,
 610                     "generating fake ethernet address.\n");
 611                 par0 = karc4random();
 612                 /* Set OUI to JMicron. */
 613                 eaddr[0] = 0x00;
 614                 eaddr[1] = 0x1B;
 615                 eaddr[2] = 0x8C;
 616                 eaddr[3] = (par0 >> 16) & 0xff;
 617                 eaddr[4] = (par0 >> 8) & 0xff;
 618                 eaddr[5] = par0 & 0xff;
 619         } else {
 620                 eaddr[0] = (par0 >> 0) & 0xFF;
 621                 eaddr[1] = (par0 >> 8) & 0xFF;
 622                 eaddr[2] = (par0 >> 16) & 0xFF;
 623                 eaddr[3] = (par0 >> 24) & 0xFF;
 624                 eaddr[4] = (par1 >> 0) & 0xFF;
 625                 eaddr[5] = (par1 >> 8) & 0xFF;
 626         }
 627 }
 628
 629 static int
 630 jme_attach(device_t dev)
 631 {
 632         struct jme_softc *sc = device_get_softc(dev);
 633         struct ifnet *ifp = &sc->arpcom.ac_if;
 634         uint32_t reg;
 635         uint16_t did;
 636         uint8_t pcie_ptr, rev;
 637         int error = 0, i, j;
 638         uint8_t eaddr[ETHER_ADDR_LEN];
 639
 640         lwkt_serialize_init(&sc->jme_serialize);
 641         lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
 642         for (i = 0; i < JME_NRXRING_MAX; ++i) {
 643                 lwkt_serialize_init(
 644                     &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
 645         }
 646
 647         sc->jme_rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
 648             jme_rx_desc_count);
 649         sc->jme_rx_desc_cnt = roundup(sc->jme_rx_desc_cnt, JME_NDESC_ALIGN);
 650         if (sc->jme_rx_desc_cnt > JME_NDESC_MAX)
 651                 sc->jme_rx_desc_cnt = JME_NDESC_MAX;
 652
 653         sc->jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
 654             jme_tx_desc_count);
 655         sc->jme_tx_desc_cnt = roundup(sc->jme_tx_desc_cnt, JME_NDESC_ALIGN);
 656         if (sc->jme_tx_desc_cnt > JME_NDESC_MAX)
 657                 sc->jme_tx_desc_cnt = JME_NDESC_MAX;
 658
 659         /*
 660          * Calculate rx rings
 661          */
 662         sc->jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
 663             jme_rx_ring_count);
 664         sc->jme_rx_ring_cnt = if_ring_count2(sc->jme_rx_ring_cnt,
 665             JME_NRXRING_MAX);
 666
 667         i = 0;
 668         sc->jme_serialize_arr[i++] = &sc->jme_serialize;
 669         sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
 670         for (j = 0; j < sc->jme_rx_ring_cnt; ++j) {
 671                 sc->jme_serialize_arr[i++] =
 672                     &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
 673         }
 674         KKASSERT(i <= JME_NSERIALIZE);
 675         sc->jme_serialize_cnt = i;
 676
 677         sc->jme_cdata.jme_sc = sc;
 678         for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
 679                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
 680
 681                 rdata->jme_sc = sc;
 682                 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
 683                 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
 684                 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
 685                 rdata->jme_rx_idx = i;
 686         }
 687
 688         sc->jme_dev = dev;
 689         sc->jme_lowaddr = BUS_SPACE_MAXADDR;
 690
 691         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 692
 693         callout_init(&sc->jme_tick_ch);
 694
 695 #ifndef BURN_BRIDGES
 696         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 697                 uint32_t irq, mem;
 698
 699                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
 700                 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
 701
 702                 device_printf(dev, "chip is in D%d power mode "
 703                     "-- setting to D0\n", pci_get_powerstate(dev));
 704
 705                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 706
 707                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
 708                 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
 709         }
 710 #endif  /* !BURN_BRIDGE */
 711
 712         /* Enable bus mastering */
 713         pci_enable_busmaster(dev);
 714
 715         /*
 716          * Allocate IO memory
 717          *
 718          * JMC250 supports both memory mapped and I/O register space
 719          * access.  Because I/O register access should use different
 720          * BARs to access registers it's waste of time to use I/O
 721          * register spce access.  JMC250 uses 16K to map entire memory
 722          * space.
 723          */
 724         sc->jme_mem_rid = JME_PCIR_BAR;
 725         sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 726                                                  &sc->jme_mem_rid, RF_ACTIVE);
 727         if (sc->jme_mem_res == NULL) {
 728                 device_printf(dev, "can't allocate IO memory\n");
 729                 return ENXIO;
 730         }
 731         sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
 732         sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
 733
 734         /*
 735          * Allocate IRQ
 736          */
 737         error = jme_intr_alloc(dev);
 738         if (error)
 739                 goto fail;
 740
 741         /*
 742          * Extract revisions
 743          */
 744         reg = CSR_READ_4(sc, JME_CHIPMODE);
 745         if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
 746             CHIPMODE_NOT_FPGA) {
 747                 sc->jme_caps |= JME_CAP_FPGA;
 748                 if (bootverbose) {
 749                         device_printf(dev, "FPGA revision: 0x%04x\n",
 750                                       (reg & CHIPMODE_FPGA_REV_MASK) >>
 751                                       CHIPMODE_FPGA_REV_SHIFT);
 752                 }
 753         }
 754
 755         /* NOTE: FM revision is put in the upper 4 bits */
 756         rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
 757         rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
 758         if (bootverbose)
 759                 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
 760
 761         did = pci_get_device(dev);
 762         switch (did) {
 763         case PCI_PRODUCT_JMICRON_JMC250:
 764                 if (rev == JME_REV1_A2)
 765                         sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
 766                 break;
 767
 768         case PCI_PRODUCT_JMICRON_JMC260:
 769                 if (rev == JME_REV2)
 770                         sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
 771                 break;
 772
 773         default:
 774                 panic("unknown device id 0x%04x\n", did);
 775         }
 776         if (rev >= JME_REV2) {
 777                 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
 778                 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
 779                                       GHC_TXMAC_CLKSRC_1000;
 780         }
 781
 782         /* Reset the ethernet controller. */
 783         jme_reset(sc);
 784
 785         /* Map MSI/MSI-X vectors */
 786         jme_set_msinum(sc);
 787
 788         /* Get station address. */
 789         reg = CSR_READ_4(sc, JME_SMBCSR);
 790         if (reg & SMBCSR_EEPROM_PRESENT)
 791                 error = jme_eeprom_macaddr(sc, eaddr);
 792         if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
 793                 if (error != 0 && (bootverbose)) {
 794                         device_printf(dev, "ethernet hardware address "
 795                                       "not found in EEPROM.\n");
 796                 }
 797                 jme_reg_macaddr(sc, eaddr);
 798         }
 799
 800         /*
 801          * Save PHY address.
 802          * Integrated JR0211 has fixed PHY address whereas FPGA version
 803          * requires PHY probing to get correct PHY address.
 804          */
 805         if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
 806                 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
 807                     GPREG0_PHY_ADDR_MASK;
 808                 if (bootverbose) {
 809                         device_printf(dev, "PHY is at address %d.\n",
 810                             sc->jme_phyaddr);
 811                 }
 812         } else {
 813                 sc->jme_phyaddr = 0;
 814         }
 815
 816         /* Set max allowable DMA size. */
 817         pcie_ptr = pci_get_pciecap_ptr(dev);
 818         if (pcie_ptr != 0) {
 819                 uint16_t ctrl;
 820
 821                 sc->jme_caps |= JME_CAP_PCIE;
 822                 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
 823                 if (bootverbose) {
 824                         device_printf(dev, "Read request size : %d bytes.\n",
 825                             128 << ((ctrl >> 12) & 0x07));
 826                         device_printf(dev, "TLP payload size : %d bytes.\n",
 827                             128 << ((ctrl >> 5) & 0x07));
 828                 }
 829                 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
 830                 case PCIEM_DEVCTL_MAX_READRQ_128:
 831                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
 832                         break;
 833                 case PCIEM_DEVCTL_MAX_READRQ_256:
 834                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
 835                         break;
 836                 default:
 837                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 838                         break;
 839                 }
 840                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 841         } else {
 842                 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 843                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 844         }
 845
 846 #ifdef notyet
 847         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
 848                 sc->jme_caps |= JME_CAP_PMCAP;
 849 #endif
 850
 851         /*
 852          * Create sysctl tree
 853          */
 854         jme_sysctl_node(sc);
 855
 856         /* Allocate DMA stuffs */
 857         error = jme_dma_alloc(sc);
 858         if (error)
 859                 goto fail;
 860
 861         ifp->if_softc = sc;
 862         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 863         ifp->if_init = jme_init;
 864         ifp->if_ioctl = jme_ioctl;
 865         ifp->if_start = jme_start;
 866 #ifdef DEVICE_POLLING
 867         ifp->if_poll = jme_poll;
 868 #endif
 869         ifp->if_watchdog = jme_watchdog;
 870         ifp->if_serialize = jme_serialize;
 871         ifp->if_deserialize = jme_deserialize;
 872         ifp->if_tryserialize = jme_tryserialize;
 873 #ifdef INVARIANTS
 874         ifp->if_serialize_assert = jme_serialize_assert;
 875 #endif
 876         ifq_set_maxlen(&ifp->if_snd, sc->jme_tx_desc_cnt - JME_TXD_RSVD);
 877         ifq_set_ready(&ifp->if_snd);
 878
 879         /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
 880         ifp->if_capabilities = IFCAP_HWCSUM |
 881                                IFCAP_VLAN_MTU |
 882                                IFCAP_VLAN_HWTAGGING;
 883         if (sc->jme_rx_ring_cnt > JME_NRXRING_MIN)
 884                 ifp->if_capabilities |= IFCAP_RSS;
 885         ifp->if_capenable = ifp->if_capabilities;
 886
 887         /*
 888          * Disable TXCSUM by default to improve bulk data
 889          * transmit performance (+20Mbps improvement).
 890          */
 891         ifp->if_capenable &= ~IFCAP_TXCSUM;
 892
 893         if (ifp->if_capenable & IFCAP_TXCSUM)
 894                 ifp->if_hwassist = JME_CSUM_FEATURES;
 895
 896         /* Set up MII bus. */
 897         error = mii_phy_probe(dev, &sc->jme_miibus,
 898                               jme_mediachange, jme_mediastatus);
 899         if (error) {
 900                 device_printf(dev, "no PHY found!\n");
 901                 goto fail;
 902         }
 903
 904         /*
 905          * Save PHYADDR for FPGA mode PHY.
 906          */
 907         if (sc->jme_caps & JME_CAP_FPGA) {
 908                 struct mii_data *mii = device_get_softc(sc->jme_miibus);
 909
 910                 if (mii->mii_instance != 0) {
 911                         struct mii_softc *miisc;
 912
 913                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
 914                                 if (miisc->mii_phy != 0) {
 915                                         sc->jme_phyaddr = miisc->mii_phy;
 916                                         break;
 917                                 }
 918                         }
 919                         if (sc->jme_phyaddr != 0) {
 920                                 device_printf(sc->jme_dev,
 921                                     "FPGA PHY is at %d\n", sc->jme_phyaddr);
 922                                 /* vendor magic. */
 923                                 jme_miibus_writereg(dev, sc->jme_phyaddr,
 924                                     JMPHY_CONF, JMPHY_CONF_DEFFIFO);
 925
 926                                 /* XXX should we clear JME_WA_EXTFIFO */
 927                         }
 928                 }
 929         }
 930
 931         ether_ifattach(ifp, eaddr, NULL);
 932
 933         /* Tell the upper layer(s) we support long frames. */
 934         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 935
 936         error = jme_intr_setup(dev);
 937         if (error) {
 938                 ether_ifdetach(ifp);
 939                 goto fail;
 940         }
 941
 942         return 0;
 943 fail:
 944         jme_detach(dev);
 945         return (error);
 946 }
 947
 948 static int
 949 jme_detach(device_t dev)
 950 {
 951         struct jme_softc *sc = device_get_softc(dev);
 952
 953         if (device_is_attached(dev)) {
 954                 struct ifnet *ifp = &sc->arpcom.ac_if;
 955
 956                 ifnet_serialize_all(ifp);
 957                 jme_stop(sc);
 958                 jme_intr_teardown(dev);
 959                 ifnet_deserialize_all(ifp);
 960
 961                 ether_ifdetach(ifp);
 962         }
 963
 964         if (sc->jme_sysctl_tree != NULL)
 965                 sysctl_ctx_free(&sc->jme_sysctl_ctx);
 966
 967         if (sc->jme_miibus != NULL)
 968                 device_delete_child(dev, sc->jme_miibus);
 969         bus_generic_detach(dev);
 970
 971         jme_intr_free(dev);
 972
 973         if (sc->jme_mem_res != NULL) {
 974                 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
 975                                      sc->jme_mem_res);
 976         }
 977
 978         jme_dma_free(sc);
 979
 980         return (0);
 981 }
 982
 983 static void
 984 jme_sysctl_node(struct jme_softc *sc)
 985 {
 986         int coal_max;
 987 #ifdef JME_RSS_DEBUG
 988         char rx_ring_pkt[32];
 989         int r;
 990 #endif
 991
 992         sysctl_ctx_init(&sc->jme_sysctl_ctx);
 993         sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
 994                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
 995                                 device_get_nameunit(sc->jme_dev),
 996                                 CTLFLAG_RD, 0, "");
 997         if (sc->jme_sysctl_tree == NULL) {
 998                 device_printf(sc->jme_dev, "can't add sysctl node\n");
 999                 return;
1000         }
1001
1002         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1003             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1004             "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1005             sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1006
1007         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1008             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1009             "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1010             sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1011
1012         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1013             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1014             "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1015             sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1016
1017         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1018             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1019             "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1020             sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1021
1022         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1023                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1024                        "rx_desc_count", CTLFLAG_RD, &sc->jme_rx_desc_cnt,
1025                        0, "RX desc count");
1026         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1027                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1028                        "tx_desc_count", CTLFLAG_RD, &sc->jme_tx_desc_cnt,
1029                        0, "TX desc count");
1030         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1031                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1032                        "rx_ring_count", CTLFLAG_RD, &sc->jme_rx_ring_cnt,
1033                        0, "RX ring count");
1034 #ifdef JME_RSS_DEBUG
1035         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1036                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1037                        "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1038                        0, "RSS debug level");
1039         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1040                 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1041                 SYSCTL_ADD_UINT(&sc->jme_sysctl_ctx,
1042                                 SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1043                                 rx_ring_pkt, CTLFLAG_RW,
1044                                 &sc->jme_rx_ring_pkt[r],
1045                                 0, "RXed packets");
1046         }
1047 #endif
1048
1049         /*
1050          * Set default coalesce valves
1051          */
1052         sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1053         sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1054         sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1055         sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1056
1057         /*
1058          * Adjust coalesce valves, in case that the number of TX/RX
1059          * descs are set to small values by users.
1060          *
1061          * NOTE: coal_max will not be zero, since number of descs
1062          * must aligned by JME_NDESC_ALIGN (16 currently)
1063          */
1064         coal_max = sc->jme_tx_desc_cnt / 6;
1065         if (coal_max < sc->jme_tx_coal_pkt)
1066                 sc->jme_tx_coal_pkt = coal_max;
1067
1068         coal_max = sc->jme_rx_desc_cnt / 4;
1069         if (coal_max < sc->jme_rx_coal_pkt)
1070                 sc->jme_rx_coal_pkt = coal_max;
1071 }
1072
1073 static int
1074 jme_dma_alloc(struct jme_softc *sc)
1075 {
1076         struct jme_txdesc *txd;
1077         bus_dmamem_t dmem;
1078         int error, i;
1079
1080         sc->jme_cdata.jme_txdesc =
1081         kmalloc(sc->jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1082                 M_DEVBUF, M_WAITOK | M_ZERO);
1083         for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1084                 sc->jme_cdata.jme_rx_data[i].jme_rxdesc =
1085                 kmalloc(sc->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1086                         M_DEVBUF, M_WAITOK | M_ZERO);
1087         }
1088
1089         /* Create parent ring tag. */
1090         error = bus_dma_tag_create(NULL,/* parent */
1091             1, JME_RING_BOUNDARY,       /* algnmnt, boundary */
1092             sc->jme_lowaddr,            /* lowaddr */
1093             BUS_SPACE_MAXADDR,          /* highaddr */
1094             NULL, NULL,                 /* filter, filterarg */
1095             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1096             0,                          /* nsegments */
1097             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1098             0,                          /* flags */
1099             &sc->jme_cdata.jme_ring_tag);
1100         if (error) {
1101                 device_printf(sc->jme_dev,
1102                     "could not create parent ring DMA tag.\n");
1103                 return error;
1104         }
1105
1106         /*
1107          * Create DMA stuffs for TX ring
1108          */
1109         error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1110                         JME_TX_RING_ALIGN, 0,
1111                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1112                         JME_TX_RING_SIZE(sc),
1113                         BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1114         if (error) {
1115                 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1116                 return error;
1117         }
1118         sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1119         sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1120         sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1121         sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1122
1123         /*
1124          * Create DMA stuffs for RX rings
1125          */
1126         for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1127                 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1128                 if (error)
1129                         return error;
1130         }
1131
1132         /* Create parent buffer tag. */
1133         error = bus_dma_tag_create(NULL,/* parent */
1134             1, 0,                       /* algnmnt, boundary */
1135             sc->jme_lowaddr,            /* lowaddr */
1136             BUS_SPACE_MAXADDR,          /* highaddr */
1137             NULL, NULL,                 /* filter, filterarg */
1138             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1139             0,                          /* nsegments */
1140             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1141             0,                          /* flags */
1142             &sc->jme_cdata.jme_buffer_tag);
1143         if (error) {
1144                 device_printf(sc->jme_dev,
1145                     "could not create parent buffer DMA tag.\n");
1146                 return error;
1147         }
1148
1149         /*
1150          * Create DMA stuffs for shadow status block
1151          */
1152         error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1153                         JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1154                         JME_SSB_SIZE, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1155         if (error) {
1156                 device_printf(sc->jme_dev,
1157                     "could not create shadow status block.\n");
1158                 return error;
1159         }
1160         sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1161         sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1162         sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1163         sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1164
1165         /*
1166          * Create DMA stuffs for TX buffers
1167          */
1168
1169         /* Create tag for Tx buffers. */
1170         error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1171             1, 0,                       /* algnmnt, boundary */
1172             BUS_SPACE_MAXADDR,          /* lowaddr */
1173             BUS_SPACE_MAXADDR,          /* highaddr */
1174             NULL, NULL,                 /* filter, filterarg */
1175             JME_JUMBO_FRAMELEN,         /* maxsize */
1176             JME_MAXTXSEGS,              /* nsegments */
1177             JME_MAXSEGSIZE,             /* maxsegsize */
1178             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1179             &sc->jme_cdata.jme_tx_tag);
1180         if (error != 0) {
1181                 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1182                 return error;
1183         }
1184
1185         /* Create DMA maps for Tx buffers. */
1186         for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1187                 txd = &sc->jme_cdata.jme_txdesc[i];
1188                 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1189                                 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1190                                 &txd->tx_dmamap);
1191                 if (error) {
1192                         int j;
1193
1194                         device_printf(sc->jme_dev,
1195                             "could not create %dth Tx dmamap.\n", i);
1196
1197                         for (j = 0; j < i; ++j) {
1198                                 txd = &sc->jme_cdata.jme_txdesc[j];
1199                                 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1200                                                    txd->tx_dmamap);
1201                         }
1202                         bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1203                         sc->jme_cdata.jme_tx_tag = NULL;
1204                         return error;
1205                 }
1206         }
1207
1208         /*
1209          * Create DMA stuffs for RX buffers
1210          */
1211         for (i = 0; i < sc->jme_rx_ring_cnt; ++i) {
1212                 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1213                 if (error)
1214                         return error;
1215         }
1216         return 0;
1217 }
1218
1219 static void
1220 jme_dma_free(struct jme_softc *sc)
1221 {
1222         struct jme_txdesc *txd;
1223         struct jme_rxdesc *rxd;
1224         struct jme_rxdata *rdata;
1225         int i, r;
1226
1227         /* Tx ring */
1228         if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1229                 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1230                     sc->jme_cdata.jme_tx_ring_map);
1231                 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1232                     sc->jme_cdata.jme_tx_ring,
1233                     sc->jme_cdata.jme_tx_ring_map);
1234                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1235                 sc->jme_cdata.jme_tx_ring_tag = NULL;
1236         }
1237
1238         /* Rx ring */
1239         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1240                 rdata = &sc->jme_cdata.jme_rx_data[r];
1241                 if (rdata->jme_rx_ring_tag != NULL) {
1242                         bus_dmamap_unload(rdata->jme_rx_ring_tag,
1243                                           rdata->jme_rx_ring_map);
1244                         bus_dmamem_free(rdata->jme_rx_ring_tag,
1245                                         rdata->jme_rx_ring,
1246                                         rdata->jme_rx_ring_map);
1247                         bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1248                         rdata->jme_rx_ring_tag = NULL;
1249                 }
1250         }
1251
1252         /* Tx buffers */
1253         if (sc->jme_cdata.jme_tx_tag != NULL) {
1254                 for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
1255                         txd = &sc->jme_cdata.jme_txdesc[i];
1256                         bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1257                             txd->tx_dmamap);
1258                 }
1259                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1260                 sc->jme_cdata.jme_tx_tag = NULL;
1261         }
1262
1263         /* Rx buffers */
1264         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1265                 rdata = &sc->jme_cdata.jme_rx_data[r];
1266                 if (rdata->jme_rx_tag != NULL) {
1267                         for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
1268                                 rxd = &rdata->jme_rxdesc[i];
1269                                 bus_dmamap_destroy(rdata->jme_rx_tag,
1270                                                    rxd->rx_dmamap);
1271                         }
1272                         bus_dmamap_destroy(rdata->jme_rx_tag,
1273                                            rdata->jme_rx_sparemap);
1274                         bus_dma_tag_destroy(rdata->jme_rx_tag);
1275                         rdata->jme_rx_tag = NULL;
1276                 }
1277         }
1278
1279         /* Shadow status block. */
1280         if (sc->jme_cdata.jme_ssb_tag != NULL) {
1281                 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1282                     sc->jme_cdata.jme_ssb_map);
1283                 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1284                     sc->jme_cdata.jme_ssb_block,
1285                     sc->jme_cdata.jme_ssb_map);
1286                 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1287                 sc->jme_cdata.jme_ssb_tag = NULL;
1288         }
1289
1290         if (sc->jme_cdata.jme_buffer_tag != NULL) {
1291                 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1292                 sc->jme_cdata.jme_buffer_tag = NULL;
1293         }
1294         if (sc->jme_cdata.jme_ring_tag != NULL) {
1295                 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1296                 sc->jme_cdata.jme_ring_tag = NULL;
1297         }
1298
1299         if (sc->jme_cdata.jme_txdesc != NULL) {
1300                 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1301                 sc->jme_cdata.jme_txdesc = NULL;
1302         }
1303         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1304                 rdata = &sc->jme_cdata.jme_rx_data[r];
1305                 if (rdata->jme_rxdesc != NULL) {
1306                         kfree(rdata->jme_rxdesc, M_DEVBUF);
1307                         rdata->jme_rxdesc = NULL;
1308                 }
1309         }
1310 }
1311
1312 /*
1313  *      Make sure the interface is stopped at reboot time.
1314  */
1315 static int
1316 jme_shutdown(device_t dev)
1317 {
1318         return jme_suspend(dev);
1319 }
1320
1321 #ifdef notyet
1322 /*
1323  * Unlike other ethernet controllers, JMC250 requires
1324  * explicit resetting link speed to 10/100Mbps as gigabit
1325  * link will cunsume more power than 375mA.
1326  * Note, we reset the link speed to 10/100Mbps with
1327  * auto-negotiation but we don't know whether that operation
1328  * would succeed or not as we have no control after powering
1329  * off. If the renegotiation fail WOL may not work. Running
1330  * at 1Gbps draws more power than 375mA at 3.3V which is
1331  * specified in PCI specification and that would result in
1332  * complete shutdowning power to ethernet controller.
1333  *
1334  * TODO
1335  *  Save current negotiated media speed/duplex/flow-control
1336  *  to softc and restore the same link again after resuming.
1337  *  PHY handling such as power down/resetting to 100Mbps
1338  *  may be better handled in suspend method in phy driver.
1339  */
1340 static void
1341 jme_setlinkspeed(struct jme_softc *sc)
1342 {
1343         struct mii_data *mii;
1344         int aneg, i;
1345
1346         JME_LOCK_ASSERT(sc);
1347
1348         mii = device_get_softc(sc->jme_miibus);
1349         mii_pollstat(mii);
1350         aneg = 0;
1351         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1352                 switch IFM_SUBTYPE(mii->mii_media_active) {
1353                 case IFM_10_T:
1354                 case IFM_100_TX:
1355                         return;
1356                 case IFM_1000_T:
1357                         aneg++;
1358                 default:
1359                         break;
1360                 }
1361         }
1362         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1363         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1364             ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1365         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1366             BMCR_AUTOEN | BMCR_STARTNEG);
1367         DELAY(1000);
1368         if (aneg != 0) {
1369                 /* Poll link state until jme(4) get a 10/100 link. */
1370                 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1371                         mii_pollstat(mii);
1372                         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1373                                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1374                                 case IFM_10_T:
1375                                 case IFM_100_TX:
1376                                         jme_mac_config(sc);
1377                                         return;
1378                                 default:
1379                                         break;
1380                                 }
1381                         }
1382                         JME_UNLOCK(sc);
1383                         pause("jmelnk", hz);
1384                         JME_LOCK(sc);
1385                 }
1386                 if (i == MII_ANEGTICKS_GIGE)
1387                         device_printf(sc->jme_dev, "establishing link failed, "
1388                             "WOL may not work!");
1389         }
1390         /*
1391          * No link, force MAC to have 100Mbps, full-duplex link.
1392          * This is the last resort and may/may not work.
1393          */
1394         mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1395         mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1396         jme_mac_config(sc);
1397 }
1398
1399 static void
1400 jme_setwol(struct jme_softc *sc)
1401 {
1402         struct ifnet *ifp = &sc->arpcom.ac_if;
1403         uint32_t gpr, pmcs;
1404         uint16_t pmstat;
1405         int pmc;
1406
1407         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1408                 /* No PME capability, PHY power down. */
1409                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1410                     MII_BMCR, BMCR_PDOWN);
1411                 return;
1412         }
1413
1414         gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1415         pmcs = CSR_READ_4(sc, JME_PMCS);
1416         pmcs &= ~PMCS_WOL_ENB_MASK;
1417         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1418                 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1419                 /* Enable PME message. */
1420                 gpr |= GPREG0_PME_ENB;
1421                 /* For gigabit controllers, reset link speed to 10/100. */
1422                 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1423                         jme_setlinkspeed(sc);
1424         }
1425
1426         CSR_WRITE_4(sc, JME_PMCS, pmcs);
1427         CSR_WRITE_4(sc, JME_GPREG0, gpr);
1428
1429         /* Request PME. */
1430         pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1431         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1432         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1433                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1434         pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1435         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1436                 /* No WOL, PHY power down. */
1437                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1438                     MII_BMCR, BMCR_PDOWN);
1439         }
1440 }
1441 #endif
1442
1443 static int
1444 jme_suspend(device_t dev)
1445 {
1446         struct jme_softc *sc = device_get_softc(dev);
1447         struct ifnet *ifp = &sc->arpcom.ac_if;
1448
1449         ifnet_serialize_all(ifp);
1450         jme_stop(sc);
1451 #ifdef notyet
1452         jme_setwol(sc);
1453 #endif
1454         ifnet_deserialize_all(ifp);
1455
1456         return (0);
1457 }
1458
1459 static int
1460 jme_resume(device_t dev)
1461 {
1462         struct jme_softc *sc = device_get_softc(dev);
1463         struct ifnet *ifp = &sc->arpcom.ac_if;
1464 #ifdef notyet
1465         int pmc;
1466 #endif
1467
1468         ifnet_serialize_all(ifp);
1469
1470 #ifdef notyet
1471         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1472                 uint16_t pmstat;
1473
1474                 pmstat = pci_read_config(sc->jme_dev,
1475                     pmc + PCIR_POWER_STATUS, 2);
1476                 /* Disable PME clear PME status. */
1477                 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1478                 pci_write_config(sc->jme_dev,
1479                     pmc + PCIR_POWER_STATUS, pmstat, 2);
1480         }
1481 #endif
1482
1483         if (ifp->if_flags & IFF_UP)
1484                 jme_init(sc);
1485
1486         ifnet_deserialize_all(ifp);
1487
1488         return (0);
1489 }
1490
1491 static int
1492 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1493 {
1494         struct jme_txdesc *txd;
1495         struct jme_desc *desc;
1496         struct mbuf *m;
1497         bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1498         int maxsegs, nsegs;
1499         int error, i, prod, symbol_desc;
1500         uint32_t cflags, flag64;
1501
1502         M_ASSERTPKTHDR((*m_head));
1503
1504         prod = sc->jme_cdata.jme_tx_prod;
1505         txd = &sc->jme_cdata.jme_txdesc[prod];
1506
1507         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1508                 symbol_desc = 1;
1509         else
1510                 symbol_desc = 0;
1511
1512         maxsegs = (sc->jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1513                   (JME_TXD_RSVD + symbol_desc);
1514         if (maxsegs > JME_MAXTXSEGS)
1515                 maxsegs = JME_MAXTXSEGS;
1516         KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1517                 ("not enough segments %d\n", maxsegs));
1518
1519         error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1520                         txd->tx_dmamap, m_head,
1521                         txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1522         if (error)
1523                 goto fail;
1524
1525         bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1526                         BUS_DMASYNC_PREWRITE);
1527
1528         m = *m_head;
1529         cflags = 0;
1530
1531         /* Configure checksum offload. */
1532         if (m->m_pkthdr.csum_flags & CSUM_IP)
1533                 cflags |= JME_TD_IPCSUM;
1534         if (m->m_pkthdr.csum_flags & CSUM_TCP)
1535                 cflags |= JME_TD_TCPCSUM;
1536         if (m->m_pkthdr.csum_flags & CSUM_UDP)
1537                 cflags |= JME_TD_UDPCSUM;
1538
1539         /* Configure VLAN. */
1540         if (m->m_flags & M_VLANTAG) {
1541                 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1542                 cflags |= JME_TD_VLAN_TAG;
1543         }
1544
1545         desc = &sc->jme_cdata.jme_tx_ring[prod];
1546         desc->flags = htole32(cflags);
1547         desc->addr_hi = htole32(m->m_pkthdr.len);
1548         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1549                 /*
1550                  * Use 64bits TX desc chain format.
1551                  *
1552                  * The first TX desc of the chain, which is setup here,
1553                  * is just a symbol TX desc carrying no payload.
1554                  */
1555                 flag64 = JME_TD_64BIT;
1556                 desc->buflen = 0;
1557                 desc->addr_lo = 0;
1558
1559                 /* No effective TX desc is consumed */
1560                 i = 0;
1561         } else {
1562                 /*
1563                  * Use 32bits TX desc chain format.
1564                  *
1565                  * The first TX desc of the chain, which is setup here,
1566                  * is an effective TX desc carrying the first segment of
1567                  * the mbuf chain.
1568                  */
1569                 flag64 = 0;
1570                 desc->buflen = htole32(txsegs[0].ds_len);
1571                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1572
1573                 /* One effective TX desc is consumed */
1574                 i = 1;
1575         }
1576         sc->jme_cdata.jme_tx_cnt++;
1577         KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1578                  sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1579         JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1580
1581         txd->tx_ndesc = 1 - i;
1582         for (; i < nsegs; i++) {
1583                 desc = &sc->jme_cdata.jme_tx_ring[prod];
1584                 desc->flags = htole32(JME_TD_OWN | flag64);
1585                 desc->buflen = htole32(txsegs[i].ds_len);
1586                 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1587                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1588
1589                 sc->jme_cdata.jme_tx_cnt++;
1590                 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1591                          sc->jme_tx_desc_cnt - JME_TXD_RSVD);
1592                 JME_DESC_INC(prod, sc->jme_tx_desc_cnt);
1593         }
1594
1595         /* Update producer index. */
1596         sc->jme_cdata.jme_tx_prod = prod;
1597         /*
1598          * Finally request interrupt and give the first descriptor
1599          * owenership to hardware.
1600          */
1601         desc = txd->tx_desc;
1602         desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1603
1604         txd->tx_m = m;
1605         txd->tx_ndesc += nsegs;
1606
1607         return 0;
1608 fail:
1609         m_freem(*m_head);
1610         *m_head = NULL;
1611         return error;
1612 }
1613
1614 static void
1615 jme_start(struct ifnet *ifp)
1616 {
1617         struct jme_softc *sc = ifp->if_softc;
1618         struct mbuf *m_head;
1619         int enq = 0;
1620
1621         ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1622
1623         if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1624                 ifq_purge(&ifp->if_snd);
1625                 return;
1626         }
1627
1628         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1629                 return;
1630
1631         if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1632                 jme_txeof(sc);
1633
1634         while (!ifq_is_empty(&ifp->if_snd)) {
1635                 /*
1636                  * Check number of available TX descs, always
1637                  * leave JME_TXD_RSVD free TX descs.
1638                  */
1639                 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1640                     sc->jme_tx_desc_cnt - JME_TXD_RSVD) {
1641                         ifp->if_flags |= IFF_OACTIVE;
1642                         break;
1643                 }
1644
1645                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1646                 if (m_head == NULL)
1647                         break;
1648
1649                 /*
1650                  * Pack the data into the transmit ring. If we
1651                  * don't have room, set the OACTIVE flag and wait
1652                  * for the NIC to drain the ring.
1653                  */
1654                 if (jme_encap(sc, &m_head)) {
1655                         KKASSERT(m_head == NULL);
1656                         ifp->if_oerrors++;
1657                         ifp->if_flags |= IFF_OACTIVE;
1658                         break;
1659                 }
1660                 enq++;
1661
1662                 /*
1663                  * If there's a BPF listener, bounce a copy of this frame
1664                  * to him.
1665                  */
1666                 ETHER_BPF_MTAP(ifp, m_head);
1667         }
1668
1669         if (enq > 0) {
1670                 /*
1671                  * Reading TXCSR takes very long time under heavy load
1672                  * so cache TXCSR value and writes the ORed value with
1673                  * the kick command to the TXCSR. This saves one register
1674                  * access cycle.
1675                  */
1676                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1677                     TXCSR_TXQ_N_START(TXCSR_TXQ0));
1678                 /* Set a timeout in case the chip goes out to lunch. */
1679                 ifp->if_timer = JME_TX_TIMEOUT;
1680         }
1681 }
1682
1683 static void
1684 jme_watchdog(struct ifnet *ifp)
1685 {
1686         struct jme_softc *sc = ifp->if_softc;
1687
1688         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1689
1690         if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1691                 if_printf(ifp, "watchdog timeout (missed link)\n");
1692                 ifp->if_oerrors++;
1693                 jme_init(sc);
1694                 return;
1695         }
1696
1697         jme_txeof(sc);
1698         if (sc->jme_cdata.jme_tx_cnt == 0) {
1699                 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1700                           "-- recovering\n");
1701                 if (!ifq_is_empty(&ifp->if_snd))
1702                         if_devstart(ifp);
1703                 return;
1704         }
1705
1706         if_printf(ifp, "watchdog timeout\n");
1707         ifp->if_oerrors++;
1708         jme_init(sc);
1709         if (!ifq_is_empty(&ifp->if_snd))
1710                 if_devstart(ifp);
1711 }
1712
1713 static int
1714 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1715 {
1716         struct jme_softc *sc = ifp->if_softc;
1717         struct mii_data *mii = device_get_softc(sc->jme_miibus);
1718         struct ifreq *ifr = (struct ifreq *)data;
1719         int error = 0, mask;
1720
1721         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1722
1723         switch (cmd) {
1724         case SIOCSIFMTU:
1725                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1726                     (!(sc->jme_caps & JME_CAP_JUMBO) &&
1727                      ifr->ifr_mtu > JME_MAX_MTU)) {
1728                         error = EINVAL;
1729                         break;
1730                 }
1731
1732                 if (ifp->if_mtu != ifr->ifr_mtu) {
1733                         /*
1734                          * No special configuration is required when interface
1735                          * MTU is changed but availability of Tx checksum
1736                          * offload should be chcked against new MTU size as
1737                          * FIFO size is just 2K.
1738                          */
1739                         if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1740                                 ifp->if_capenable &= ~IFCAP_TXCSUM;
1741                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1742                         }
1743                         ifp->if_mtu = ifr->ifr_mtu;
1744                         if (ifp->if_flags & IFF_RUNNING)
1745                                 jme_init(sc);
1746                 }
1747                 break;
1748
1749         case SIOCSIFFLAGS:
1750                 if (ifp->if_flags & IFF_UP) {
1751                         if (ifp->if_flags & IFF_RUNNING) {
1752                                 if ((ifp->if_flags ^ sc->jme_if_flags) &
1753                                     (IFF_PROMISC | IFF_ALLMULTI))
1754                                         jme_set_filter(sc);
1755                         } else {
1756                                 jme_init(sc);
1757                         }
1758                 } else {
1759                         if (ifp->if_flags & IFF_RUNNING)
1760                                 jme_stop(sc);
1761                 }
1762                 sc->jme_if_flags = ifp->if_flags;
1763                 break;
1764
1765         case SIOCADDMULTI:
1766         case SIOCDELMULTI:
1767                 if (ifp->if_flags & IFF_RUNNING)
1768                         jme_set_filter(sc);
1769                 break;
1770
1771         case SIOCSIFMEDIA:
1772         case SIOCGIFMEDIA:
1773                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1774                 break;
1775
1776         case SIOCSIFCAP:
1777                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1778
1779                 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1780                         ifp->if_capenable ^= IFCAP_TXCSUM;
1781                         if (IFCAP_TXCSUM & ifp->if_capenable)
1782                                 ifp->if_hwassist |= JME_CSUM_FEATURES;
1783                         else
1784                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1785                 }
1786                 if (mask & IFCAP_RXCSUM) {
1787                         uint32_t reg;
1788
1789                         ifp->if_capenable ^= IFCAP_RXCSUM;
1790                         reg = CSR_READ_4(sc, JME_RXMAC);
1791                         reg &= ~RXMAC_CSUM_ENB;
1792                         if (ifp->if_capenable & IFCAP_RXCSUM)
1793                                 reg |= RXMAC_CSUM_ENB;
1794                         CSR_WRITE_4(sc, JME_RXMAC, reg);
1795                 }
1796
1797                 if (mask & IFCAP_VLAN_HWTAGGING) {
1798                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1799                         jme_set_vlan(sc);
1800                 }
1801
1802                 if (mask & IFCAP_RSS)
1803                         ifp->if_capenable ^= IFCAP_RSS;
1804                 break;
1805
1806         default:
1807                 error = ether_ioctl(ifp, cmd, data);
1808                 break;
1809         }
1810         return (error);
1811 }
1812
1813 static void
1814 jme_mac_config(struct jme_softc *sc)
1815 {
1816         struct mii_data *mii;
1817         uint32_t ghc, rxmac, txmac, txpause, gp1;
1818         int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1819
1820         mii = device_get_softc(sc->jme_miibus);
1821
1822         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1823         DELAY(10);
1824         CSR_WRITE_4(sc, JME_GHC, 0);
1825         ghc = 0;
1826         rxmac = CSR_READ_4(sc, JME_RXMAC);
1827         rxmac &= ~RXMAC_FC_ENB;
1828         txmac = CSR_READ_4(sc, JME_TXMAC);
1829         txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1830         txpause = CSR_READ_4(sc, JME_TXPFC);
1831         txpause &= ~TXPFC_PAUSE_ENB;
1832         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1833                 ghc |= GHC_FULL_DUPLEX;
1834                 rxmac &= ~RXMAC_COLL_DET_ENB;
1835                 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1836                     TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1837                     TXMAC_FRAME_BURST);
1838 #ifdef notyet
1839                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1840                         txpause |= TXPFC_PAUSE_ENB;
1841                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1842                         rxmac |= RXMAC_FC_ENB;
1843 #endif
1844                 /* Disable retry transmit timer/retry limit. */
1845                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1846                     ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1847         } else {
1848                 rxmac |= RXMAC_COLL_DET_ENB;
1849                 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1850                 /* Enable retry transmit timer/retry limit. */
1851                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1852                     TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1853         }
1854
1855         /*
1856          * Reprogram Tx/Rx MACs with resolved speed/duplex.
1857          */
1858         gp1 = CSR_READ_4(sc, JME_GPREG1);
1859         gp1 &= ~GPREG1_WA_HDX;
1860
1861         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1862                 hdx = 1;
1863
1864         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1865         case IFM_10_T:
1866                 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1867                 if (hdx)
1868                         gp1 |= GPREG1_WA_HDX;
1869                 break;
1870
1871         case IFM_100_TX:
1872                 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1873                 if (hdx)
1874                         gp1 |= GPREG1_WA_HDX;
1875
1876                 /*
1877                  * Use extended FIFO depth to workaround CRC errors
1878                  * emitted by chips before JMC250B
1879                  */
1880                 phyconf = JMPHY_CONF_EXTFIFO;
1881                 break;
1882
1883         case IFM_1000_T:
1884                 if (sc->jme_caps & JME_CAP_FASTETH)
1885                         break;
1886
1887                 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1888                 if (hdx)
1889                         txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1890                 break;
1891
1892         default:
1893                 break;
1894         }
1895         CSR_WRITE_4(sc, JME_GHC, ghc);
1896         CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1897         CSR_WRITE_4(sc, JME_TXMAC, txmac);
1898         CSR_WRITE_4(sc, JME_TXPFC, txpause);
1899
1900         if (sc->jme_workaround & JME_WA_EXTFIFO) {
1901                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1902                                     JMPHY_CONF, phyconf);
1903         }
1904         if (sc->jme_workaround & JME_WA_HDX)
1905                 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1906 }
1907
1908 static void
1909 jme_intr(void *xsc)
1910 {
1911         struct jme_softc *sc = xsc;
1912         struct ifnet *ifp = &sc->arpcom.ac_if;
1913         uint32_t status;
1914         int r;
1915
1916         ASSERT_SERIALIZED(&sc->jme_serialize);
1917
1918         status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1919         if (status == 0 || status == 0xFFFFFFFF)
1920                 return;
1921
1922         /* Disable interrupts. */
1923         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1924
1925         status = CSR_READ_4(sc, JME_INTR_STATUS);
1926         if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1927                 goto back;
1928
1929         /* Reset PCC counter/timer and Ack interrupts. */
1930         status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1931
1932         if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1933                 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1934
1935         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
1936                 if (status & jme_rx_status[r].jme_coal) {
1937                         status |= jme_rx_status[r].jme_coal |
1938                                   jme_rx_status[r].jme_comp;
1939                 }
1940         }
1941
1942         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1943
1944         if (ifp->if_flags & IFF_RUNNING) {
1945                 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1946                         jme_rx_intr(sc, status);
1947
1948                 if (status & INTR_RXQ_DESC_EMPTY) {
1949                         /*
1950                          * Notify hardware availability of new Rx buffers.
1951                          * Reading RXCSR takes very long time under heavy
1952                          * load so cache RXCSR value and writes the ORed
1953                          * value with the kick command to the RXCSR. This
1954                          * saves one register access cycle.
1955                          */
1956                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1957                             RXCSR_RX_ENB | RXCSR_RXQ_START);
1958                 }
1959
1960                 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1961                         lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
1962                         jme_txeof(sc);
1963                         if (!ifq_is_empty(&ifp->if_snd))
1964                                 if_devstart(ifp);
1965                         lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
1966                 }
1967         }
1968 back:
1969         /* Reenable interrupts. */
1970         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1971 }
1972
1973 static void
1974 jme_txeof(struct jme_softc *sc)
1975 {
1976         struct ifnet *ifp = &sc->arpcom.ac_if;
1977         struct jme_txdesc *txd;
1978         uint32_t status;
1979         int cons, nsegs;
1980
1981         cons = sc->jme_cdata.jme_tx_cons;
1982         if (cons == sc->jme_cdata.jme_tx_prod)
1983                 return;
1984
1985         /*
1986          * Go through our Tx list and free mbufs for those
1987          * frames which have been transmitted.
1988          */
1989         while (cons != sc->jme_cdata.jme_tx_prod) {
1990                 txd = &sc->jme_cdata.jme_txdesc[cons];
1991                 KASSERT(txd->tx_m != NULL,
1992                         ("%s: freeing NULL mbuf!\n", __func__));
1993
1994                 status = le32toh(txd->tx_desc->flags);
1995                 if ((status & JME_TD_OWN) == JME_TD_OWN)
1996                         break;
1997
1998                 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
1999                         ifp->if_oerrors++;
2000                 } else {
2001                         ifp->if_opackets++;
2002                         if (status & JME_TD_COLLISION) {
2003                                 ifp->if_collisions +=
2004                                     le32toh(txd->tx_desc->buflen) &
2005                                     JME_TD_BUF_LEN_MASK;
2006                         }
2007                 }
2008
2009                 /*
2010                  * Only the first descriptor of multi-descriptor
2011                  * transmission is updated so driver have to skip entire
2012                  * chained buffers for the transmiited frame. In other
2013                  * words, JME_TD_OWN bit is valid only at the first
2014                  * descriptor of a multi-descriptor transmission.
2015                  */
2016                 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2017                         sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2018                         JME_DESC_INC(cons, sc->jme_tx_desc_cnt);
2019                 }
2020
2021                 /* Reclaim transferred mbufs. */
2022                 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2023                 m_freem(txd->tx_m);
2024                 txd->tx_m = NULL;
2025                 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2026                 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2027                         ("%s: Active Tx desc counter was garbled\n", __func__));
2028                 txd->tx_ndesc = 0;
2029         }
2030         sc->jme_cdata.jme_tx_cons = cons;
2031
2032         if (sc->jme_cdata.jme_tx_cnt == 0)
2033                 ifp->if_timer = 0;
2034
2035         if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2036             sc->jme_tx_desc_cnt - JME_TXD_RSVD)
2037                 ifp->if_flags &= ~IFF_OACTIVE;
2038 }
2039
2040 static __inline void
2041 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2042 {
2043         int i;
2044
2045         for (i = 0; i < count; ++i) {
2046                 struct jme_desc *desc = &rdata->jme_rx_ring[cons];
2047
2048                 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2049                 desc->buflen = htole32(MCLBYTES);
2050                 JME_DESC_INC(cons, rdata->jme_sc->jme_rx_desc_cnt);
2051         }
2052 }
2053
2054 static __inline struct pktinfo *
2055 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2056 {
2057         if (flags & JME_RD_IPV4)
2058                 pi->pi_netisr = NETISR_IP;
2059         else if (flags & JME_RD_IPV6)
2060                 pi->pi_netisr = NETISR_IPV6;
2061         else
2062                 return NULL;
2063
2064         pi->pi_flags = 0;
2065         pi->pi_l3proto = IPPROTO_UNKNOWN;
2066
2067         if (flags & JME_RD_MORE_FRAG)
2068                 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2069         else if (flags & JME_RD_TCP)
2070                 pi->pi_l3proto = IPPROTO_TCP;
2071         else if (flags & JME_RD_UDP)
2072                 pi->pi_l3proto = IPPROTO_UDP;
2073         else
2074                 pi = NULL;
2075         return pi;
2076 }
2077
2078 /* Receive a frame. */
2079 static void
2080 jme_rxpkt(struct jme_rxdata *rdata)
2081 {
2082         struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2083         struct jme_desc *desc;
2084         struct jme_rxdesc *rxd;
2085         struct mbuf *mp, *m;
2086         uint32_t flags, status, hash, hashinfo;
2087         int cons, count, nsegs;
2088
2089         cons = rdata->jme_rx_cons;
2090         desc = &rdata->jme_rx_ring[cons];
2091         flags = le32toh(desc->flags);
2092         status = le32toh(desc->buflen);
2093         hash = le32toh(desc->addr_hi);
2094         hashinfo = le32toh(desc->addr_lo);
2095         nsegs = JME_RX_NSEGS(status);
2096
2097         JME_RSS_DPRINTF(sc, 15, "ring%d, flags 0x%08x, "
2098                         "hash 0x%08x, hash info 0x%08x\n",
2099                         ring, flags, hash, hashinfo);
2100
2101         if (status & JME_RX_ERR_STAT) {
2102                 ifp->if_ierrors++;
2103                 jme_discard_rxbufs(rdata, cons, nsegs);
2104 #ifdef JME_SHOW_ERRORS
2105                 device_printf(sc->jme_dev, "%s : receive error = 0x%b\n",
2106                     __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2107 #endif
2108                 rdata->jme_rx_cons += nsegs;
2109                 rdata->jme_rx_cons %= rdata->jme_sc->jme_rx_desc_cnt;
2110                 return;
2111         }
2112
2113         rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2114         for (count = 0; count < nsegs; count++,
2115              JME_DESC_INC(cons, rdata->jme_sc->jme_rx_desc_cnt)) {
2116                 rxd = &rdata->jme_rxdesc[cons];
2117                 mp = rxd->rx_m;
2118
2119                 /* Add a new receive buffer to the ring. */
2120                 if (jme_newbuf(rdata, rxd, 0) != 0) {
2121                         ifp->if_iqdrops++;
2122                         /* Reuse buffer. */
2123                         jme_discard_rxbufs(rdata, cons, nsegs - count);
2124                         if (rdata->jme_rxhead != NULL) {
2125                                 m_freem(rdata->jme_rxhead);
2126                                 JME_RXCHAIN_RESET(rdata);
2127                         }
2128                         break;
2129                 }
2130
2131                 /*
2132                  * Assume we've received a full sized frame.
2133                  * Actual size is fixed when we encounter the end of
2134                  * multi-segmented frame.
2135                  */
2136                 mp->m_len = MCLBYTES;
2137
2138                 /* Chain received mbufs. */
2139                 if (rdata->jme_rxhead == NULL) {
2140                         rdata->jme_rxhead = mp;
2141                         rdata->jme_rxtail = mp;
2142                 } else {
2143                         /*
2144                          * Receive processor can receive a maximum frame
2145                          * size of 65535 bytes.
2146                          */
2147                         rdata->jme_rxtail->m_next = mp;
2148                         rdata->jme_rxtail = mp;
2149                 }
2150
2151                 if (count == nsegs - 1) {
2152                         struct pktinfo pi0, *pi;
2153
2154                         /* Last desc. for this frame. */
2155                         m = rdata->jme_rxhead;
2156                         m->m_pkthdr.len = rdata->jme_rxlen;
2157                         if (nsegs > 1) {
2158                                 /* Set first mbuf size. */
2159                                 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2160                                 /* Set last mbuf size. */
2161                                 mp->m_len = rdata->jme_rxlen -
2162                                     ((MCLBYTES - JME_RX_PAD_BYTES) +
2163                                     (MCLBYTES * (nsegs - 2)));
2164                         } else {
2165                                 m->m_len = rdata->jme_rxlen;
2166                         }
2167                         m->m_pkthdr.rcvif = ifp;
2168
2169                         /*
2170                          * Account for 10bytes auto padding which is used
2171                          * to align IP header on 32bit boundary. Also note,
2172                          * CRC bytes is automatically removed by the
2173                          * hardware.
2174                          */
2175                         m->m_data += JME_RX_PAD_BYTES;
2176
2177                         /* Set checksum information. */
2178                         if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2179                             (flags & JME_RD_IPV4)) {
2180                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2181                                 if (flags & JME_RD_IPCSUM)
2182                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2183                                 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2184                                     ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2185                                      (JME_RD_TCP | JME_RD_TCPCSUM) ||
2186                                      (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2187                                      (JME_RD_UDP | JME_RD_UDPCSUM))) {
2188                                         m->m_pkthdr.csum_flags |=
2189                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2190                                         m->m_pkthdr.csum_data = 0xffff;
2191                                 }
2192                         }
2193
2194                         /* Check for VLAN tagged packets. */
2195                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2196                             (flags & JME_RD_VLAN_TAG)) {
2197                                 m->m_pkthdr.ether_vlantag =
2198                                     flags & JME_RD_VLAN_MASK;
2199                                 m->m_flags |= M_VLANTAG;
2200                         }
2201
2202                         ifp->if_ipackets++;
2203
2204                         if (ifp->if_capenable & IFCAP_RSS)
2205                                 pi = jme_pktinfo(&pi0, flags);
2206                         else
2207                                 pi = NULL;
2208
2209                         if (pi != NULL &&
2210                             (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2211                                 m->m_flags |= M_HASH;
2212                                 m->m_pkthdr.hash = toeplitz_hash(hash);
2213                         }
2214
2215 #ifdef JME_RSS_DEBUG
2216                         if (pi != NULL) {
2217                                 JME_RSS_DPRINTF(sc, 10,
2218                                     "isr %d flags %08x, l3 %d %s\n",
2219                                     pi->pi_netisr, pi->pi_flags,
2220                                     pi->pi_l3proto,
2221                                     (m->m_flags & M_HASH) ? "hash" : "");
2222                         }
2223 #endif
2224
2225                         /* Pass it on. */
2226                         ether_input_pkt(ifp, m, pi);
2227
2228                         /* Reset mbuf chains. */
2229                         JME_RXCHAIN_RESET(rdata);
2230 #ifdef JME_RSS_DEBUG
2231                         sc->jme_rx_ring_pkt[ring]++;
2232 #endif
2233                 }
2234         }
2235
2236         rdata->jme_rx_cons += nsegs;
2237         rdata->jme_rx_cons %= rdata->jme_sc->jme_rx_desc_cnt;
2238 }
2239
2240 static void
2241 jme_rxeof(struct jme_rxdata *rdata, int count)
2242 {
2243         struct jme_desc *desc;
2244         int nsegs, pktlen;
2245
2246         for (;;) {
2247 #ifdef DEVICE_POLLING
2248                 if (count >= 0 && count-- == 0)
2249                         break;
2250 #endif
2251                 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2252                 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2253                         break;
2254                 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2255                         break;
2256
2257                 /*
2258                  * Check number of segments against received bytes.
2259                  * Non-matching value would indicate that hardware
2260                  * is still trying to update Rx descriptors. I'm not
2261                  * sure whether this check is needed.
2262                  */
2263                 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2264                 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2265                 if (nsegs != howmany(pktlen, MCLBYTES)) {
2266                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2267                             "RX fragment count(%d) and "
2268                             "packet size(%d) mismach\n", nsegs, pktlen);
2269                         break;
2270                 }
2271
2272                 /* Received a frame. */
2273                 jme_rxpkt(rdata);
2274         }
2275 }
2276
2277 static void
2278 jme_tick(void *xsc)
2279 {
2280         struct jme_softc *sc = xsc;
2281         struct ifnet *ifp = &sc->arpcom.ac_if;
2282         struct mii_data *mii = device_get_softc(sc->jme_miibus);
2283
2284         ifnet_serialize_all(ifp);
2285
2286         mii_tick(mii);
2287         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2288
2289         ifnet_deserialize_all(ifp);
2290 }
2291
2292 static void
2293 jme_reset(struct jme_softc *sc)
2294 {
2295         uint32_t val;
2296
2297         /* Make sure that TX and RX are stopped */
2298         jme_stop_tx(sc);
2299         jme_stop_rx(sc);
2300
2301         /* Start reset */
2302         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2303         DELAY(20);
2304
2305         /*
2306          * Hold reset bit before stop reset
2307          */
2308
2309         /* Disable TXMAC and TXOFL clock sources */
2310         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2311         /* Disable RXMAC clock source */
2312         val = CSR_READ_4(sc, JME_GPREG1);
2313         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2314         /* Flush */
2315         CSR_READ_4(sc, JME_GHC);
2316
2317         /* Stop reset */
2318         CSR_WRITE_4(sc, JME_GHC, 0);
2319         /* Flush */
2320         CSR_READ_4(sc, JME_GHC);
2321
2322         /*
2323          * Clear reset bit after stop reset
2324          */
2325
2326         /* Enable TXMAC and TXOFL clock sources */
2327         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2328         /* Enable RXMAC clock source */
2329         val = CSR_READ_4(sc, JME_GPREG1);
2330         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2331         /* Flush */
2332         CSR_READ_4(sc, JME_GHC);
2333
2334         /* Disable TXMAC and TXOFL clock sources */
2335         CSR_WRITE_4(sc, JME_GHC, 0);
2336         /* Disable RXMAC clock source */
2337         val = CSR_READ_4(sc, JME_GPREG1);
2338         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2339         /* Flush */
2340         CSR_READ_4(sc, JME_GHC);
2341
2342         /* Enable TX and RX */
2343         val = CSR_READ_4(sc, JME_TXCSR);
2344         CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2345         val = CSR_READ_4(sc, JME_RXCSR);
2346         CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2347         /* Flush */
2348         CSR_READ_4(sc, JME_TXCSR);
2349         CSR_READ_4(sc, JME_RXCSR);
2350
2351         /* Enable TXMAC and TXOFL clock sources */
2352         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2353         /* Eisable RXMAC clock source */
2354         val = CSR_READ_4(sc, JME_GPREG1);
2355         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2356         /* Flush */
2357         CSR_READ_4(sc, JME_GHC);
2358
2359         /* Stop TX and RX */
2360         jme_stop_tx(sc);
2361         jme_stop_rx(sc);
2362 }
2363
2364 static void
2365 jme_init(void *xsc)
2366 {
2367         struct jme_softc *sc = xsc;
2368         struct ifnet *ifp = &sc->arpcom.ac_if;
2369         struct mii_data *mii;
2370         uint8_t eaddr[ETHER_ADDR_LEN];
2371         bus_addr_t paddr;
2372         uint32_t reg;
2373         int error, r;
2374
2375         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2376
2377         /*
2378          * Cancel any pending I/O.
2379          */
2380         jme_stop(sc);
2381
2382         /*
2383          * Reset the chip to a known state.
2384          */
2385         jme_reset(sc);
2386
2387         /*
2388          * Setup MSI/MSI-X vectors to interrupts mapping
2389          */
2390         jme_set_msinum(sc);
2391
2392         sc->jme_txd_spare =
2393         howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2394         KKASSERT(sc->jme_txd_spare >= 1);
2395
2396         /*
2397          * If we use 64bit address mode for transmitting, each Tx request
2398          * needs one more symbol descriptor.
2399          */
2400         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2401                 sc->jme_txd_spare += 1;
2402
2403         if (sc->jme_rx_ring_cnt > JME_NRXRING_MIN)
2404                 jme_enable_rss(sc);
2405         else
2406                 jme_disable_rss(sc);
2407
2408         /* Init RX descriptors */
2409         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
2410                 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2411                 if (error) {
2412                         if_printf(ifp, "initialization failed: "
2413                                   "no memory for %dth RX ring.\n", r);
2414                         jme_stop(sc);
2415                         return;
2416                 }
2417         }
2418
2419         /* Init TX descriptors */
2420         jme_init_tx_ring(sc);
2421
2422         /* Initialize shadow status block. */
2423         jme_init_ssb(sc);
2424
2425         /* Reprogram the station address. */
2426         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2427         CSR_WRITE_4(sc, JME_PAR0,
2428             eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2429         CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2430
2431         /*
2432          * Configure Tx queue.
2433          *  Tx priority queue weight value : 0
2434          *  Tx FIFO threshold for processing next packet : 16QW
2435          *  Maximum Tx DMA length : 512
2436          *  Allow Tx DMA burst.
2437          */
2438         sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2439         sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2440         sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2441         sc->jme_txcsr |= sc->jme_tx_dma_size;
2442         sc->jme_txcsr |= TXCSR_DMA_BURST;
2443         CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2444
2445         /* Set Tx descriptor counter. */
2446         CSR_WRITE_4(sc, JME_TXQDC, sc->jme_tx_desc_cnt);
2447
2448         /* Set Tx ring address to the hardware. */
2449         paddr = sc->jme_cdata.jme_tx_ring_paddr;
2450         CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2451         CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2452
2453         /* Configure TxMAC parameters. */
2454         reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2455         reg |= TXMAC_THRESH_1_PKT;
2456         reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2457         CSR_WRITE_4(sc, JME_TXMAC, reg);
2458
2459         /*
2460          * Configure Rx queue.
2461          *  FIFO full threshold for transmitting Tx pause packet : 128T
2462          *  FIFO threshold for processing next packet : 128QW
2463          *  Rx queue 0 select
2464          *  Max Rx DMA length : 128
2465          *  Rx descriptor retry : 32
2466          *  Rx descriptor retry time gap : 256ns
2467          *  Don't receive runt/bad frame.
2468          */
2469         sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2470 #if 0
2471         /*
2472          * Since Rx FIFO size is 4K bytes, receiving frames larger
2473          * than 4K bytes will suffer from Rx FIFO overruns. So
2474          * decrease FIFO threshold to reduce the FIFO overruns for
2475          * frames larger than 4000 bytes.
2476          * For best performance of standard MTU sized frames use
2477          * maximum allowable FIFO threshold, 128QW.
2478          */
2479         if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2480             JME_RX_FIFO_SIZE)
2481                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2482         else
2483                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2484 #else
2485         /* Improve PCI Express compatibility */
2486         sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2487 #endif
2488         sc->jme_rxcsr |= sc->jme_rx_dma_size;
2489         sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2490         sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2491         /* XXX TODO DROP_BAD */
2492
2493         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
2494                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2495
2496                 /* Set Rx descriptor counter. */
2497                 CSR_WRITE_4(sc, JME_RXQDC, sc->jme_rx_desc_cnt);
2498
2499                 /* Set Rx ring address to the hardware. */
2500                 paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
2501                 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2502                 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2503         }
2504
2505         /* Clear receive filter. */
2506         CSR_WRITE_4(sc, JME_RXMAC, 0);
2507
2508         /* Set up the receive filter. */
2509         jme_set_filter(sc);
2510         jme_set_vlan(sc);
2511
2512         /*
2513          * Disable all WOL bits as WOL can interfere normal Rx
2514          * operation. Also clear WOL detection status bits.
2515          */
2516         reg = CSR_READ_4(sc, JME_PMCS);
2517         reg &= ~PMCS_WOL_ENB_MASK;
2518         CSR_WRITE_4(sc, JME_PMCS, reg);
2519
2520         /*
2521          * Pad 10bytes right before received frame. This will greatly
2522          * help Rx performance on strict-alignment architectures as
2523          * it does not need to copy the frame to align the payload.
2524          */
2525         reg = CSR_READ_4(sc, JME_RXMAC);
2526         reg |= RXMAC_PAD_10BYTES;
2527
2528         if (ifp->if_capenable & IFCAP_RXCSUM)
2529                 reg |= RXMAC_CSUM_ENB;
2530         CSR_WRITE_4(sc, JME_RXMAC, reg);
2531
2532         /* Configure general purpose reg0 */
2533         reg = CSR_READ_4(sc, JME_GPREG0);
2534         reg &= ~GPREG0_PCC_UNIT_MASK;
2535         /* Set PCC timer resolution to micro-seconds unit. */
2536         reg |= GPREG0_PCC_UNIT_US;
2537         /*
2538          * Disable all shadow register posting as we have to read
2539          * JME_INTR_STATUS register in jme_intr. Also it seems
2540          * that it's hard to synchronize interrupt status between
2541          * hardware and software with shadow posting due to
2542          * requirements of bus_dmamap_sync(9).
2543          */
2544         reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2545             GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2546             GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2547             GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2548         /* Disable posting of DW0. */
2549         reg &= ~GPREG0_POST_DW0_ENB;
2550         /* Clear PME message. */
2551         reg &= ~GPREG0_PME_ENB;
2552         /* Set PHY address. */
2553         reg &= ~GPREG0_PHY_ADDR_MASK;
2554         reg |= sc->jme_phyaddr;
2555         CSR_WRITE_4(sc, JME_GPREG0, reg);
2556
2557         /* Configure Tx queue 0 packet completion coalescing. */
2558         jme_set_tx_coal(sc);
2559
2560         /* Configure Rx queues packet completion coalescing. */
2561         jme_set_rx_coal(sc);
2562
2563         /* Configure shadow status block but don't enable posting. */
2564         paddr = sc->jme_cdata.jme_ssb_block_paddr;
2565         CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2566         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2567
2568         /* Disable Timer 1 and Timer 2. */
2569         CSR_WRITE_4(sc, JME_TIMER1, 0);
2570         CSR_WRITE_4(sc, JME_TIMER2, 0);
2571
2572         /* Configure retry transmit period, retry limit value. */
2573         CSR_WRITE_4(sc, JME_TXTRHD,
2574             ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2575             TXTRHD_RT_PERIOD_MASK) |
2576             ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2577             TXTRHD_RT_LIMIT_SHIFT));
2578
2579 #ifdef DEVICE_POLLING
2580         if (!(ifp->if_flags & IFF_POLLING))
2581 #endif
2582         /* Initialize the interrupt mask. */
2583         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2584         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2585
2586         /*
2587          * Enabling Tx/Rx DMA engines and Rx queue processing is
2588          * done after detection of valid link in jme_miibus_statchg.
2589          */
2590         sc->jme_flags &= ~JME_FLAG_LINK;
2591
2592         /* Set the current media. */
2593         mii = device_get_softc(sc->jme_miibus);
2594         mii_mediachg(mii);
2595
2596         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2597
2598         ifp->if_flags |= IFF_RUNNING;
2599         ifp->if_flags &= ~IFF_OACTIVE;
2600 }
2601
2602 static void
2603 jme_stop(struct jme_softc *sc)
2604 {
2605         struct ifnet *ifp = &sc->arpcom.ac_if;
2606         struct jme_txdesc *txd;
2607         struct jme_rxdesc *rxd;
2608         struct jme_rxdata *rdata;
2609         int i, r;
2610
2611         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2612
2613         /*
2614          * Mark the interface down and cancel the watchdog timer.
2615          */
2616         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2617         ifp->if_timer = 0;
2618
2619         callout_stop(&sc->jme_tick_ch);
2620         sc->jme_flags &= ~JME_FLAG_LINK;
2621
2622         /*
2623          * Disable interrupts.
2624          */
2625         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2626         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2627
2628         /* Disable updating shadow status block. */
2629         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2630             CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2631
2632         /* Stop receiver, transmitter. */
2633         jme_stop_rx(sc);
2634         jme_stop_tx(sc);
2635
2636         /*
2637          * Free partial finished RX segments
2638          */
2639         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
2640                 rdata = &sc->jme_cdata.jme_rx_data[r];
2641                 if (rdata->jme_rxhead != NULL)
2642                         m_freem(rdata->jme_rxhead);
2643                 JME_RXCHAIN_RESET(rdata);
2644         }
2645
2646         /*
2647          * Free RX and TX mbufs still in the queues.
2648          */
2649         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
2650                 rdata = &sc->jme_cdata.jme_rx_data[r];
2651                 for (i = 0; i < sc->jme_rx_desc_cnt; i++) {
2652                         rxd = &rdata->jme_rxdesc[i];
2653                         if (rxd->rx_m != NULL) {
2654                                 bus_dmamap_unload(rdata->jme_rx_tag,
2655                                                   rxd->rx_dmamap);
2656                                 m_freem(rxd->rx_m);
2657                                 rxd->rx_m = NULL;
2658                         }
2659                 }
2660         }
2661         for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2662                 txd = &sc->jme_cdata.jme_txdesc[i];
2663                 if (txd->tx_m != NULL) {
2664                         bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2665                             txd->tx_dmamap);
2666                         m_freem(txd->tx_m);
2667                         txd->tx_m = NULL;
2668                         txd->tx_ndesc = 0;
2669                 }
2670         }
2671 }
2672
2673 static void
2674 jme_stop_tx(struct jme_softc *sc)
2675 {
2676         uint32_t reg;
2677         int i;
2678
2679         reg = CSR_READ_4(sc, JME_TXCSR);
2680         if ((reg & TXCSR_TX_ENB) == 0)
2681                 return;
2682         reg &= ~TXCSR_TX_ENB;
2683         CSR_WRITE_4(sc, JME_TXCSR, reg);
2684         for (i = JME_TIMEOUT; i > 0; i--) {
2685                 DELAY(1);
2686                 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2687                         break;
2688         }
2689         if (i == 0)
2690                 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2691 }
2692
2693 static void
2694 jme_stop_rx(struct jme_softc *sc)
2695 {
2696         uint32_t reg;
2697         int i;
2698
2699         reg = CSR_READ_4(sc, JME_RXCSR);
2700         if ((reg & RXCSR_RX_ENB) == 0)
2701                 return;
2702         reg &= ~RXCSR_RX_ENB;
2703         CSR_WRITE_4(sc, JME_RXCSR, reg);
2704         for (i = JME_TIMEOUT; i > 0; i--) {
2705                 DELAY(1);
2706                 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2707                         break;
2708         }
2709         if (i == 0)
2710                 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2711 }
2712
2713 static void
2714 jme_init_tx_ring(struct jme_softc *sc)
2715 {
2716         struct jme_chain_data *cd;
2717         struct jme_txdesc *txd;
2718         int i;
2719
2720         sc->jme_cdata.jme_tx_prod = 0;
2721         sc->jme_cdata.jme_tx_cons = 0;
2722         sc->jme_cdata.jme_tx_cnt = 0;
2723
2724         cd = &sc->jme_cdata;
2725         bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2726         for (i = 0; i < sc->jme_tx_desc_cnt; i++) {
2727                 txd = &sc->jme_cdata.jme_txdesc[i];
2728                 txd->tx_m = NULL;
2729                 txd->tx_desc = &cd->jme_tx_ring[i];
2730                 txd->tx_ndesc = 0;
2731         }
2732 }
2733
2734 static void
2735 jme_init_ssb(struct jme_softc *sc)
2736 {
2737         struct jme_chain_data *cd;
2738
2739         cd = &sc->jme_cdata;
2740         bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2741 }
2742
2743 static int
2744 jme_init_rx_ring(struct jme_rxdata *rdata)
2745 {
2746         struct jme_rxdesc *rxd;
2747         int i;
2748
2749         KKASSERT(rdata->jme_rxhead == NULL &&
2750                  rdata->jme_rxtail == NULL &&
2751                  rdata->jme_rxlen == 0);
2752         rdata->jme_rx_cons = 0;
2753
2754         bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata->jme_sc));
2755         for (i = 0; i < rdata->jme_sc->jme_rx_desc_cnt; i++) {
2756                 int error;
2757
2758                 rxd = &rdata->jme_rxdesc[i];
2759                 rxd->rx_m = NULL;
2760                 rxd->rx_desc = &rdata->jme_rx_ring[i];
2761                 error = jme_newbuf(rdata, rxd, 1);
2762                 if (error)
2763                         return error;
2764         }
2765         return 0;
2766 }
2767
2768 static int
2769 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
2770 {
2771         struct jme_desc *desc;
2772         struct mbuf *m;
2773         bus_dma_segment_t segs;
2774         bus_dmamap_t map;
2775         int error, nsegs;
2776
2777         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2778         if (m == NULL)
2779                 return ENOBUFS;
2780         /*
2781          * JMC250 has 64bit boundary alignment limitation so jme(4)
2782          * takes advantage of 10 bytes padding feature of hardware
2783          * in order not to copy entire frame to align IP header on
2784          * 32bit boundary.
2785          */
2786         m->m_len = m->m_pkthdr.len = MCLBYTES;
2787
2788         error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2789                         rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2790                         BUS_DMA_NOWAIT);
2791         if (error) {
2792                 m_freem(m);
2793                 if (init) {
2794                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2795                             "can't load RX mbuf\n");
2796                 }
2797                 return error;
2798         }
2799
2800         if (rxd->rx_m != NULL) {
2801                 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2802                                 BUS_DMASYNC_POSTREAD);
2803                 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2804         }
2805         map = rxd->rx_dmamap;
2806         rxd->rx_dmamap = rdata->jme_rx_sparemap;
2807         rdata->jme_rx_sparemap = map;
2808         rxd->rx_m = m;
2809
2810         desc = rxd->rx_desc;
2811         desc->buflen = htole32(segs.ds_len);
2812         desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2813         desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2814         desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2815
2816         return 0;
2817 }
2818
2819 static void
2820 jme_set_vlan(struct jme_softc *sc)
2821 {
2822         struct ifnet *ifp = &sc->arpcom.ac_if;
2823         uint32_t reg;
2824
2825         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2826
2827         reg = CSR_READ_4(sc, JME_RXMAC);
2828         reg &= ~RXMAC_VLAN_ENB;
2829         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2830                 reg |= RXMAC_VLAN_ENB;
2831         CSR_WRITE_4(sc, JME_RXMAC, reg);
2832 }
2833
2834 static void
2835 jme_set_filter(struct jme_softc *sc)
2836 {
2837         struct ifnet *ifp = &sc->arpcom.ac_if;
2838         struct ifmultiaddr *ifma;
2839         uint32_t crc;
2840         uint32_t mchash[2];
2841         uint32_t rxcfg;
2842
2843         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2844
2845         rxcfg = CSR_READ_4(sc, JME_RXMAC);
2846         rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2847             RXMAC_ALLMULTI);
2848
2849         /*
2850          * Always accept frames destined to our station address.
2851          * Always accept broadcast frames.
2852          */
2853         rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2854
2855         if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2856                 if (ifp->if_flags & IFF_PROMISC)
2857                         rxcfg |= RXMAC_PROMISC;
2858                 if (ifp->if_flags & IFF_ALLMULTI)
2859                         rxcfg |= RXMAC_ALLMULTI;
2860                 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2861                 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2862                 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2863                 return;
2864         }
2865
2866         /*
2867          * Set up the multicast address filter by passing all multicast
2868          * addresses through a CRC generator, and then using the low-order
2869          * 6 bits as an index into the 64 bit multicast hash table.  The
2870          * high order bits select the register, while the rest of the bits
2871          * select the bit within the register.
2872          */
2873         rxcfg |= RXMAC_MULTICAST;
2874         bzero(mchash, sizeof(mchash));
2875
2876         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2877                 if (ifma->ifma_addr->sa_family != AF_LINK)
2878                         continue;
2879                 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2880                     ifma->ifma_addr), ETHER_ADDR_LEN);
2881
2882                 /* Just want the 6 least significant bits. */
2883                 crc &= 0x3f;
2884
2885                 /* Set the corresponding bit in the hash table. */
2886                 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2887         }
2888
2889         CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2890         CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2891         CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2892 }
2893
2894 static int
2895 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2896 {
2897         struct jme_softc *sc = arg1;
2898         struct ifnet *ifp = &sc->arpcom.ac_if;
2899         int error, v;
2900
2901         ifnet_serialize_all(ifp);
2902
2903         v = sc->jme_tx_coal_to;
2904         error = sysctl_handle_int(oidp, &v, 0, req);
2905         if (error || req->newptr == NULL)
2906                 goto back;
2907
2908         if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2909                 error = EINVAL;
2910                 goto back;
2911         }
2912
2913         if (v != sc->jme_tx_coal_to) {
2914                 sc->jme_tx_coal_to = v;
2915                 if (ifp->if_flags & IFF_RUNNING)
2916                         jme_set_tx_coal(sc);
2917         }
2918 back:
2919         ifnet_deserialize_all(ifp);
2920         return error;
2921 }
2922
2923 static int
2924 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2925 {
2926         struct jme_softc *sc = arg1;
2927         struct ifnet *ifp = &sc->arpcom.ac_if;
2928         int error, v;
2929
2930         ifnet_serialize_all(ifp);
2931
2932         v = sc->jme_tx_coal_pkt;
2933         error = sysctl_handle_int(oidp, &v, 0, req);
2934         if (error || req->newptr == NULL)
2935                 goto back;
2936
2937         if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2938                 error = EINVAL;
2939                 goto back;
2940         }
2941
2942         if (v != sc->jme_tx_coal_pkt) {
2943                 sc->jme_tx_coal_pkt = v;
2944                 if (ifp->if_flags & IFF_RUNNING)
2945                         jme_set_tx_coal(sc);
2946         }
2947 back:
2948         ifnet_deserialize_all(ifp);
2949         return error;
2950 }
2951
2952 static int
2953 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
2954 {
2955         struct jme_softc *sc = arg1;
2956         struct ifnet *ifp = &sc->arpcom.ac_if;
2957         int error, v;
2958
2959         ifnet_serialize_all(ifp);
2960
2961         v = sc->jme_rx_coal_to;
2962         error = sysctl_handle_int(oidp, &v, 0, req);
2963         if (error || req->newptr == NULL)
2964                 goto back;
2965
2966         if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2967                 error = EINVAL;
2968                 goto back;
2969         }
2970
2971         if (v != sc->jme_rx_coal_to) {
2972                 sc->jme_rx_coal_to = v;
2973                 if (ifp->if_flags & IFF_RUNNING)
2974                         jme_set_rx_coal(sc);
2975         }
2976 back:
2977         ifnet_deserialize_all(ifp);
2978         return error;
2979 }
2980
2981 static int
2982 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2983 {
2984         struct jme_softc *sc = arg1;
2985         struct ifnet *ifp = &sc->arpcom.ac_if;
2986         int error, v;
2987
2988         ifnet_serialize_all(ifp);
2989
2990         v = sc->jme_rx_coal_pkt;
2991         error = sysctl_handle_int(oidp, &v, 0, req);
2992         if (error || req->newptr == NULL)
2993                 goto back;
2994
2995         if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
2996                 error = EINVAL;
2997                 goto back;
2998         }
2999
3000         if (v != sc->jme_rx_coal_pkt) {
3001                 sc->jme_rx_coal_pkt = v;
3002                 if (ifp->if_flags & IFF_RUNNING)
3003                         jme_set_rx_coal(sc);
3004         }
3005 back:
3006         ifnet_deserialize_all(ifp);
3007         return error;
3008 }
3009
3010 static void
3011 jme_set_tx_coal(struct jme_softc *sc)
3012 {
3013         uint32_t reg;
3014
3015         reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3016             PCCTX_COAL_TO_MASK;
3017         reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3018             PCCTX_COAL_PKT_MASK;
3019         reg |= PCCTX_COAL_TXQ0;
3020         CSR_WRITE_4(sc, JME_PCCTX, reg);
3021 }
3022
3023 static void
3024 jme_set_rx_coal(struct jme_softc *sc)
3025 {
3026         uint32_t reg;
3027         int r;
3028
3029         reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3030             PCCRX_COAL_TO_MASK;
3031         reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3032             PCCRX_COAL_PKT_MASK;
3033         for (r = 0; r < sc->jme_rx_ring_cnt; ++r)
3034                 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3035 }
3036
3037 #ifdef DEVICE_POLLING
3038
3039 static void
3040 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3041 {
3042         struct jme_softc *sc = ifp->if_softc;
3043         uint32_t status;
3044         int r;
3045
3046         ASSERT_SERIALIZED(&sc->jme_serialize);
3047
3048         switch (cmd) {
3049         case POLL_REGISTER:
3050                 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3051                 break;
3052
3053         case POLL_DEREGISTER:
3054                 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3055                 break;
3056
3057         case POLL_AND_CHECK_STATUS:
3058         case POLL_ONLY:
3059                 status = CSR_READ_4(sc, JME_INTR_STATUS);
3060
3061                 for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
3062                         struct jme_rxdata *rdata =
3063                             &sc->jme_cdata.jme_rx_data[r];
3064
3065                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3066                         jme_rxeof(rdata, count);
3067                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3068                 }
3069
3070                 if (status & INTR_RXQ_DESC_EMPTY) {
3071                         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3072                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3073                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3074                 }
3075
3076                 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3077                 jme_txeof(sc);
3078                 if (!ifq_is_empty(&ifp->if_snd))
3079                         if_devstart(ifp);
3080                 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3081                 break;
3082         }
3083 }
3084
3085 #endif  /* DEVICE_POLLING */
3086
3087 static int
3088 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3089 {
3090         bus_dmamem_t dmem;
3091         int error;
3092
3093         error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3094                         JME_RX_RING_ALIGN, 0,
3095                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3096                         JME_RX_RING_SIZE(rdata->jme_sc),
3097                         BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3098         if (error) {
3099                 device_printf(rdata->jme_sc->jme_dev,
3100                     "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3101                 return error;
3102         }
3103         rdata->jme_rx_ring_tag = dmem.dmem_tag;
3104         rdata->jme_rx_ring_map = dmem.dmem_map;
3105         rdata->jme_rx_ring = dmem.dmem_addr;
3106         rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3107
3108         return 0;
3109 }
3110
3111 static int
3112 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3113 {
3114         int i, error;
3115
3116         /* Create tag for Rx buffers. */
3117         error = bus_dma_tag_create(
3118             rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3119             JME_RX_BUF_ALIGN, 0,        /* algnmnt, boundary */
3120             BUS_SPACE_MAXADDR,          /* lowaddr */
3121             BUS_SPACE_MAXADDR,          /* highaddr */
3122             NULL, NULL,                 /* filter, filterarg */
3123             MCLBYTES,                   /* maxsize */
3124             1,                          /* nsegments */
3125             MCLBYTES,                   /* maxsegsize */
3126             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3127             &rdata->jme_rx_tag);
3128         if (error) {
3129                 device_printf(rdata->jme_sc->jme_dev,
3130                     "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3131                 return error;
3132         }
3133
3134         /* Create DMA maps for Rx buffers. */
3135         error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3136                                   &rdata->jme_rx_sparemap);
3137         if (error) {
3138                 device_printf(rdata->jme_sc->jme_dev,
3139                     "could not create %dth spare Rx dmamap.\n",
3140                     rdata->jme_rx_idx);
3141                 bus_dma_tag_destroy(rdata->jme_rx_tag);
3142                 rdata->jme_rx_tag = NULL;
3143                 return error;
3144         }
3145         for (i = 0; i < rdata->jme_sc->jme_rx_desc_cnt; i++) {
3146                 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3147
3148                 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3149                                           &rxd->rx_dmamap);
3150                 if (error) {
3151                         int j;
3152
3153                         device_printf(rdata->jme_sc->jme_dev,
3154                             "could not create %dth Rx dmamap "
3155                             "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3156
3157                         for (j = 0; j < i; ++j) {
3158                                 rxd = &rdata->jme_rxdesc[j];
3159                                 bus_dmamap_destroy(rdata->jme_rx_tag,
3160                                                    rxd->rx_dmamap);
3161                         }
3162                         bus_dmamap_destroy(rdata->jme_rx_tag,
3163                                            rdata->jme_rx_sparemap);
3164                         bus_dma_tag_destroy(rdata->jme_rx_tag);
3165                         rdata->jme_rx_tag = NULL;
3166                         return error;
3167                 }
3168         }
3169         return 0;
3170 }
3171
3172 static void
3173 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3174 {
3175         int r;
3176
3177         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
3178                 if (status & jme_rx_status[r].jme_coal) {
3179                         struct jme_rxdata *rdata =
3180                             &sc->jme_cdata.jme_rx_data[r];
3181
3182                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3183                         jme_rxeof(rdata, -1);
3184                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3185                 }
3186         }
3187 }
3188
3189 static void
3190 jme_enable_rss(struct jme_softc *sc)
3191 {
3192         uint32_t rssc, ind;
3193         uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3194         int i;
3195
3196         KASSERT(sc->jme_rx_ring_cnt == JME_NRXRING_2 ||
3197                 sc->jme_rx_ring_cnt == JME_NRXRING_4,
3198                 ("%s: invalid # of RX rings (%d)\n",
3199                  sc->arpcom.ac_if.if_xname, sc->jme_rx_ring_cnt));
3200
3201         rssc = RSSC_HASH_64_ENTRY;
3202         rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3203         rssc |= sc->jme_rx_ring_cnt >> 1;
3204         JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3205         CSR_WRITE_4(sc, JME_RSSC, rssc);
3206
3207         toeplitz_get_key(key, sizeof(key));
3208         for (i = 0; i < RSSKEY_NREGS; ++i) {
3209                 uint32_t keyreg;
3210
3211                 keyreg = RSSKEY_REGVAL(key, i);
3212                 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3213
3214                 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3215         }
3216
3217         /*
3218          * Create redirect table in following fashion:
3219          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3220          */
3221         ind = 0;
3222         for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3223                 int q;
3224
3225                 q = i % sc->jme_rx_ring_cnt;
3226                 ind |= q << (i * 8);
3227         }
3228         JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3229
3230         for (i = 0; i < RSSTBL_NREGS; ++i)
3231                 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3232 }
3233
3234 static void
3235 jme_disable_rss(struct jme_softc *sc)
3236 {
3237         CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3238 }
3239
3240 static void
3241 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3242 {
3243         struct jme_softc *sc = ifp->if_softc;
3244
3245         switch (slz) {
3246         case IFNET_SERIALIZE_ALL:
3247                 lwkt_serialize_array_enter(sc->jme_serialize_arr,
3248                     sc->jme_serialize_cnt, 0);
3249                 break;
3250
3251         case IFNET_SERIALIZE_MAIN:
3252                 lwkt_serialize_enter(&sc->jme_serialize);
3253                 break;
3254
3255         case IFNET_SERIALIZE_TX:
3256                 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3257                 break;
3258
3259         case IFNET_SERIALIZE_RX(0):
3260                 lwkt_serialize_enter(
3261                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3262                 break;
3263
3264         case IFNET_SERIALIZE_RX(1):
3265                 lwkt_serialize_enter(
3266                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3267                 break;
3268
3269         case IFNET_SERIALIZE_RX(2):
3270                 lwkt_serialize_enter(
3271                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3272                 break;
3273
3274         case IFNET_SERIALIZE_RX(3):
3275                 lwkt_serialize_enter(
3276                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3277                 break;
3278
3279         default:
3280                 panic("%s unsupported serialize type\n", ifp->if_xname);
3281         }
3282 }
3283
3284 static void
3285 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3286 {
3287         struct jme_softc *sc = ifp->if_softc;
3288
3289         switch (slz) {
3290         case IFNET_SERIALIZE_ALL:
3291                 lwkt_serialize_array_exit(sc->jme_serialize_arr,
3292                     sc->jme_serialize_cnt, 0);
3293                 break;
3294
3295         case IFNET_SERIALIZE_MAIN:
3296                 lwkt_serialize_exit(&sc->jme_serialize);
3297                 break;
3298
3299         case IFNET_SERIALIZE_TX:
3300                 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3301                 break;
3302
3303         case IFNET_SERIALIZE_RX(0):
3304                 lwkt_serialize_exit(
3305                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3306                 break;
3307
3308         case IFNET_SERIALIZE_RX(1):
3309                 lwkt_serialize_exit(
3310                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3311                 break;
3312
3313         case IFNET_SERIALIZE_RX(2):
3314                 lwkt_serialize_exit(
3315                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3316                 break;
3317
3318         case IFNET_SERIALIZE_RX(3):
3319                 lwkt_serialize_exit(
3320                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3321                 break;
3322
3323         default:
3324                 panic("%s unsupported serialize type\n", ifp->if_xname);
3325         }
3326 }
3327
3328 static int
3329 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3330 {
3331         struct jme_softc *sc = ifp->if_softc;
3332
3333         switch (slz) {
3334         case IFNET_SERIALIZE_ALL:
3335                 return lwkt_serialize_array_try(sc->jme_serialize_arr,
3336                     sc->jme_serialize_cnt, 0);
3337
3338         case IFNET_SERIALIZE_MAIN:
3339                 return lwkt_serialize_try(&sc->jme_serialize);
3340
3341         case IFNET_SERIALIZE_TX:
3342                 return lwkt_serialize_try(&sc->jme_cdata.jme_tx_serialize);
3343
3344         case IFNET_SERIALIZE_RX(0):
3345                 return lwkt_serialize_try(
3346                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3347
3348         case IFNET_SERIALIZE_RX(1):
3349                 return lwkt_serialize_try(
3350                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3351
3352         case IFNET_SERIALIZE_RX(2):
3353                 return lwkt_serialize_try(
3354                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3355
3356         case IFNET_SERIALIZE_RX(3):
3357                 return lwkt_serialize_try(
3358                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3359
3360         default:
3361                 panic("%s unsupported serialize type\n", ifp->if_xname);
3362         }
3363 }
3364
3365 #ifdef INVARIANTS
3366
3367 static void
3368 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3369     boolean_t serialized)
3370 {
3371         struct jme_softc *sc = ifp->if_softc;
3372         struct jme_rxdata *rdata;
3373         int i;
3374
3375         switch (slz) {
3376         case IFNET_SERIALIZE_ALL:
3377                 if (serialized) {
3378                         for (i = 0; i < sc->jme_serialize_cnt; ++i)
3379                                 ASSERT_SERIALIZED(sc->jme_serialize_arr[i]);
3380                 } else {
3381                         for (i = 0; i < sc->jme_serialize_cnt; ++i)
3382                                 ASSERT_NOT_SERIALIZED(sc->jme_serialize_arr[i]);
3383                 }
3384                 break;
3385
3386         case IFNET_SERIALIZE_MAIN:
3387                 if (serialized)
3388                         ASSERT_SERIALIZED(&sc->jme_serialize);
3389                 else
3390                         ASSERT_NOT_SERIALIZED(&sc->jme_serialize);
3391                 break;
3392
3393         case IFNET_SERIALIZE_TX:
3394                 if (serialized)
3395                         ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3396                 else
3397                         ASSERT_NOT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3398                 break;
3399
3400         case IFNET_SERIALIZE_RX(0):
3401                 rdata = &sc->jme_cdata.jme_rx_data[0];
3402                 if (serialized)
3403                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3404                 else
3405                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3406                 break;
3407
3408         case IFNET_SERIALIZE_RX(1):
3409                 rdata = &sc->jme_cdata.jme_rx_data[1];
3410                 if (serialized)
3411                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3412                 else
3413                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3414                 break;
3415
3416         case IFNET_SERIALIZE_RX(2):
3417                 rdata = &sc->jme_cdata.jme_rx_data[2];
3418                 if (serialized)
3419                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3420                 else
3421                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3422                 break;
3423
3424         case IFNET_SERIALIZE_RX(3):
3425                 rdata = &sc->jme_cdata.jme_rx_data[3];
3426                 if (serialized)
3427                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3428                 else
3429                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3430                 break;
3431
3432         default:
3433                 panic("%s unsupported serialize type\n", ifp->if_xname);
3434         }
3435 }
3436
3437 #endif  /* INVARIANTS */
3438
3439 static void
3440 jme_msix_try_alloc(device_t dev)
3441 {
3442         struct jme_softc *sc = device_get_softc(dev);
3443         struct jme_msix_data *msix;
3444         int error, i, r, msix_enable, msix_count;
3445
3446         msix_count = 1 + sc->jme_rx_ring_cnt;
3447         KKASSERT(msix_count <= JME_NMSIX);
3448
3449         msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3450
3451         /*
3452          * We leave the 1st MSI-X vector unused, so we
3453          * actually need msix_count + 1 MSI-X vectors.
3454          */
3455         if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3456                 return;
3457
3458         for (i = 0; i < msix_count; ++i)
3459                 sc->jme_msix[i].jme_msix_rid = -1;
3460
3461         i = 0;
3462
3463         msix = &sc->jme_msix[i++];
3464         msix->jme_msix_cpuid = 0;               /* XXX Put TX to cpu0 */
3465         msix->jme_msix_arg = &sc->jme_cdata;
3466         msix->jme_msix_func = jme_msix_tx;
3467         msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3468         msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3469         ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3470             device_get_nameunit(dev));
3471
3472         for (r = 0; r < sc->jme_rx_ring_cnt; ++r) {
3473                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3474
3475                 msix = &sc->jme_msix[i++];
3476                 msix->jme_msix_cpuid = r;       /* XXX Put RX to cpuX */
3477                 msix->jme_msix_arg = rdata;
3478                 msix->jme_msix_func = jme_msix_rx;
3479                 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3480                 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3481                 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3482                     "%s rx%d", device_get_nameunit(dev), r);
3483         }
3484
3485         KKASSERT(i == msix_count);
3486
3487         error = pci_setup_msix(dev);
3488         if (error)
3489                 return;
3490
3491         /* Setup jme_msix_cnt early, so we could cleanup */
3492         sc->jme_msix_cnt = msix_count;
3493
3494         for (i = 0; i < msix_count; ++i) {
3495                 msix = &sc->jme_msix[i];
3496
3497                 msix->jme_msix_vector = i + 1;
3498                 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3499                     &msix->jme_msix_rid, msix->jme_msix_cpuid);
3500                 if (error)
3501                         goto back;
3502
3503                 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3504                     &msix->jme_msix_rid, RF_ACTIVE);
3505                 if (msix->jme_msix_res == NULL) {
3506                         error = ENOMEM;
3507                         goto back;
3508                 }
3509         }
3510
3511         for (i = 0; i < JME_INTR_CNT; ++i) {
3512                 uint32_t intr_mask = (1 << i);
3513                 int x;
3514
3515                 if ((JME_INTRS & intr_mask) == 0)
3516                         continue;
3517
3518                 for (x = 0; x < msix_count; ++x) {
3519                         msix = &sc->jme_msix[x];
3520                         if (msix->jme_msix_intrs & intr_mask) {
3521                                 int reg, shift;
3522
3523                                 reg = i / JME_MSINUM_FACTOR;
3524                                 KKASSERT(reg < JME_MSINUM_CNT);
3525
3526                                 shift = (i % JME_MSINUM_FACTOR) * 4;
3527
3528                                 sc->jme_msinum[reg] |=
3529                                     (msix->jme_msix_vector << shift);
3530
3531                                 break;
3532                         }
3533                 }
3534         }
3535
3536         if (bootverbose) {
3537                 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3538                         device_printf(dev, "MSINUM%d: %#x\n", i,
3539                             sc->jme_msinum[i]);
3540                 }
3541         }
3542
3543         pci_enable_msix(dev);
3544         sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3545
3546 back:
3547         if (error)
3548                 jme_msix_free(dev);
3549 }
3550
3551 static int
3552 jme_intr_alloc(device_t dev)
3553 {
3554         struct jme_softc *sc = device_get_softc(dev);
3555         u_int irq_flags;
3556
3557         jme_msix_try_alloc(dev);
3558
3559         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3560                 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3561                     &sc->jme_irq_rid, &irq_flags);
3562
3563                 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3564                     &sc->jme_irq_rid, irq_flags);
3565                 if (sc->jme_irq_res == NULL) {
3566                         device_printf(dev, "can't allocate irq\n");
3567                         return ENXIO;
3568                 }
3569         }
3570         return 0;
3571 }
3572
3573 static void
3574 jme_msix_free(device_t dev)
3575 {
3576         struct jme_softc *sc = device_get_softc(dev);
3577         int i;
3578
3579         KKASSERT(sc->jme_msix_cnt > 1);
3580
3581         for (i = 0; i < sc->jme_msix_cnt; ++i) {
3582                 struct jme_msix_data *msix = &sc->jme_msix[i];
3583
3584                 if (msix->jme_msix_res != NULL) {
3585                         bus_release_resource(dev, SYS_RES_IRQ,
3586                             msix->jme_msix_rid, msix->jme_msix_res);
3587                         msix->jme_msix_res = NULL;
3588                 }
3589                 if (msix->jme_msix_rid >= 0) {
3590                         pci_release_msix_vector(dev, msix->jme_msix_rid);
3591                         msix->jme_msix_rid = -1;
3592                 }
3593         }
3594         pci_teardown_msix(dev);
3595 }
3596
3597 static void
3598 jme_intr_free(device_t dev)
3599 {
3600         struct jme_softc *sc = device_get_softc(dev);
3601
3602         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3603                 if (sc->jme_irq_res != NULL) {
3604                         bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3605                                              sc->jme_irq_res);
3606                 }
3607                 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3608                         pci_release_msi(dev);
3609         } else {
3610                 jme_msix_free(dev);
3611         }
3612 }
3613
3614 static void
3615 jme_msix_tx(void *xcd)
3616 {
3617         struct jme_chain_data *cd = xcd;
3618         struct jme_softc *sc = cd->jme_sc;
3619         struct ifnet *ifp = &sc->arpcom.ac_if;
3620
3621         ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3622
3623         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3624
3625         CSR_WRITE_4(sc, JME_INTR_STATUS,
3626             INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3627
3628         if (ifp->if_flags & IFF_RUNNING) {
3629                 jme_txeof(sc);
3630                 if (!ifq_is_empty(&ifp->if_snd))
3631                         if_devstart(ifp);
3632         }
3633
3634         CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3635 }
3636
3637 static void
3638 jme_msix_rx(void *xrdata)
3639 {
3640         struct jme_rxdata *rdata = xrdata;
3641         struct jme_softc *sc = rdata->jme_sc;
3642         struct ifnet *ifp = &sc->arpcom.ac_if;
3643         uint32_t status;
3644
3645         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3646
3647         CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3648             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3649
3650         status = CSR_READ_4(sc, JME_INTR_STATUS);
3651         status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3652
3653         if (status & rdata->jme_rx_coal)
3654                 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3655         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3656
3657         if (ifp->if_flags & IFF_RUNNING) {
3658                 if (status & rdata->jme_rx_coal)
3659                         jme_rxeof(rdata, -1);
3660
3661                 if (status & rdata->jme_rx_empty) {
3662                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3663                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3664                 }
3665         }
3666
3667         CSR_WRITE_4(sc, JME_INTR_MASK_SET,
3668             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3669 }
3670
3671 static void
3672 jme_set_msinum(struct jme_softc *sc)
3673 {
3674         int i;
3675
3676         for (i = 0; i < JME_MSINUM_CNT; ++i)
3677                 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3678 }
3679
3680 static int
3681 jme_intr_setup(device_t dev)
3682 {
3683         struct jme_softc *sc = device_get_softc(dev);
3684         struct ifnet *ifp = &sc->arpcom.ac_if;
3685         int error;
3686
3687         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3688                 return jme_msix_setup(dev);
3689
3690         error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3691             jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3692         if (error) {
3693                 device_printf(dev, "could not set up interrupt handler.\n");
3694                 return error;
3695         }
3696
3697         ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3698         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3699         return 0;
3700 }
3701
3702 static void
3703 jme_intr_teardown(device_t dev)
3704 {
3705         struct jme_softc *sc = device_get_softc(dev);
3706
3707         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3708                 jme_msix_teardown(dev, sc->jme_msix_cnt);
3709         else
3710                 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3711 }
3712
3713 static int
3714 jme_msix_setup(device_t dev)
3715 {
3716         struct jme_softc *sc = device_get_softc(dev);
3717         struct ifnet *ifp = &sc->arpcom.ac_if;
3718         int x;
3719
3720         for (x = 0; x < sc->jme_msix_cnt; ++x) {
3721                 struct jme_msix_data *msix = &sc->jme_msix[x];
3722                 int error;
3723
3724                 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3725                     INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3726                     &msix->jme_msix_handle, msix->jme_msix_serialize,
3727                     msix->jme_msix_desc);
3728                 if (error) {
3729                         device_printf(dev, "could not set up %s "
3730                             "interrupt handler.\n", msix->jme_msix_desc);
3731                         jme_msix_teardown(dev, x);
3732                         return error;
3733                 }
3734         }
3735         ifp->if_cpuid = 0; /* XXX */
3736         return 0;
3737 }
3738
3739 static void
3740 jme_msix_teardown(device_t dev, int msix_count)
3741 {
3742         struct jme_softc *sc = device_get_softc(dev);
3743         int x;
3744
3745         for (x = 0; x < msix_count; ++x) {
3746                 struct jme_msix_data *msix = &sc->jme_msix[x];
3747
3748                 bus_teardown_intr(dev, msix->jme_msix_res,
3749                     msix->jme_msix_handle);
3750         }
3751 }