2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2000, 2001
4 * Bill Paul <wpaul@bsdi.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/nge/if_nge.c,v 1.13.2.13 2003/02/05 22:03:57 mbr Exp $
34 * $DragonFly: src/sys/dev/netif/nge/if_nge.c,v 1.29 2005/06/13 20:09:24 joerg Exp $
38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39 * for FreeBSD. Datasheets are available from:
41 * http://www.national.com/ds/DP/DP83820.pdf
42 * http://www.national.com/ds/DP/DP83821.pdf
44 * These chips are used on several low cost gigabit ethernet NICs
45 * sold by D-Link, Addtron, SMC and Asante. Both parts are
46 * virtually the same, except the 83820 is a 64-bit/32-bit part,
47 * while the 83821 is 32-bit only.
49 * Many cards also use National gigE transceivers, such as the
50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51 * contains a full register description that applies to all of these
54 * http://www.national.com/ds/DP/DP83861.pdf
56 * Written by Bill Paul <wpaul@bsdi.com>
57 * BSDi Open Source Solutions
61 * The NatSemi DP83820 and 83821 controllers are enhanced versions
62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67 * matching buffers, one perfect address filter buffer and interrupt
68 * moderation. The 83820 supports both 64-bit and 32-bit addressing
69 * and data transfers: the 64-bit support can be toggled on or off
70 * via software. This affects the size of certain fields in the DMA
73 * There are two bugs/misfeatures in the 83820/83821 that I have
76 * - Receive buffers must be aligned on 64-bit boundaries, which means
77 * you must resort to copying data in order to fix up the payload
80 * - In order to transmit jumbo frames larger than 8170 bytes, you have
81 * to turn off transmit checksum offloading, because the chip can't
82 * compute the checksum on an outgoing frame unless it fits entirely
83 * within the TX FIFO, which is only 8192 bytes in size. If you have
84 * TX checksum offload enabled and you transmit attempt to transmit a
85 * frame larger than 8170 bytes, the transmitter will wedge.
87 * To work around the latter problem, TX checksum offload is disabled
88 * if the user selects an MTU larger than 8152 (8170 - 18).
91 #include <sys/param.h>
92 #include <sys/systm.h>
93 #include <sys/sockio.h>
95 #include <sys/malloc.h>
96 #include <sys/kernel.h>
97 #include <sys/socket.h>
98 #include <sys/thread2.h>
101 #include <net/ifq_var.h>
102 #include <net/if_arp.h>
103 #include <net/ethernet.h>
104 #include <net/if_dl.h>
105 #include <net/if_media.h>
106 #include <net/if_types.h>
107 #include <net/vlan/if_vlan_var.h>
111 #include <vm/vm.h> /* for vtophys */
112 #include <vm/pmap.h> /* for vtophys */
113 #include <machine/bus.h>
114 #include <machine/resource.h>
116 #include <sys/rman.h>
118 #include <dev/netif/mii_layer/mii.h>
119 #include <dev/netif/mii_layer/miivar.h>
121 #include <bus/pci/pcireg.h>
122 #include <bus/pci/pcivar.h>
124 #define NGE_USEIOSPACE
126 #include "if_ngereg.h"
129 /* "controller miibus0" required. See GENERIC if you get errors here. */
130 #include "miibus_if.h"
132 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
135 * Various supported device vendors/types and their names.
137 static struct nge_type nge_devs[] = {
138 { NGE_VENDORID, NGE_DEVICEID,
139 "National Semiconductor Gigabit Ethernet" },
143 static int nge_probe(device_t);
144 static int nge_attach(device_t);
145 static int nge_detach(device_t);
147 static int nge_alloc_jumbo_mem(struct nge_softc *);
148 static struct nge_jslot
149 *nge_jalloc(struct nge_softc *);
150 static void nge_jfree(void *);
151 static void nge_jref(void *);
153 static int nge_newbuf(struct nge_softc *, struct nge_desc *,
155 static int nge_encap(struct nge_softc *, struct mbuf *, uint32_t *);
156 static void nge_rxeof(struct nge_softc *);
157 static void nge_txeof(struct nge_softc *);
158 static void nge_intr(void *);
159 static void nge_tick(void *);
160 static void nge_start(struct ifnet *);
161 static int nge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
162 static void nge_init(void *);
163 static void nge_stop(struct nge_softc *);
164 static void nge_watchdog(struct ifnet *);
165 static void nge_shutdown(device_t);
166 static int nge_ifmedia_upd(struct ifnet *);
167 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
169 static void nge_delay(struct nge_softc *);
170 static void nge_eeprom_idle(struct nge_softc *);
171 static void nge_eeprom_putbyte(struct nge_softc *, int);
172 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *);
173 static void nge_read_eeprom(struct nge_softc *, void *, int, int);
175 static void nge_mii_sync(struct nge_softc *);
176 static void nge_mii_send(struct nge_softc *, uint32_t, int);
177 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
178 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
180 static int nge_miibus_readreg(device_t, int, int);
181 static int nge_miibus_writereg(device_t, int, int, int);
182 static void nge_miibus_statchg(device_t);
184 static void nge_setmulti(struct nge_softc *);
185 static void nge_reset(struct nge_softc *);
186 static int nge_list_rx_init(struct nge_softc *);
187 static int nge_list_tx_init(struct nge_softc *);
188 #ifdef DEVICE_POLLING
189 static void nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
192 #ifdef NGE_USEIOSPACE
193 #define NGE_RES SYS_RES_IOPORT
194 #define NGE_RID NGE_PCI_LOIO
196 #define NGE_RES SYS_RES_MEMORY
197 #define NGE_RID NGE_PCI_LOMEM
200 static device_method_t nge_methods[] = {
201 /* Device interface */
202 DEVMETHOD(device_probe, nge_probe),
203 DEVMETHOD(device_attach, nge_attach),
204 DEVMETHOD(device_detach, nge_detach),
205 DEVMETHOD(device_shutdown, nge_shutdown),
208 DEVMETHOD(bus_print_child, bus_generic_print_child),
209 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
212 DEVMETHOD(miibus_readreg, nge_miibus_readreg),
213 DEVMETHOD(miibus_writereg, nge_miibus_writereg),
214 DEVMETHOD(miibus_statchg, nge_miibus_statchg),
219 static DEFINE_CLASS_0(nge, nge_driver, nge_methods, sizeof(struct nge_softc));
220 static devclass_t nge_devclass;
222 DECLARE_DUMMY_MODULE(if_nge);
223 MODULE_DEPEND(if_nge, miibus, 1, 1, 1);
224 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0);
225 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
227 #define NGE_SETBIT(sc, reg, x) \
228 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
230 #define NGE_CLRBIT(sc, reg, x) \
231 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
234 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
237 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
240 nge_delay(struct nge_softc *sc)
244 for (idx = (300 / 33) + 1; idx > 0; idx--)
245 CSR_READ_4(sc, NGE_CSR);
249 nge_eeprom_idle(struct nge_softc *sc)
253 SIO_SET(NGE_MEAR_EE_CSEL);
255 SIO_SET(NGE_MEAR_EE_CLK);
258 for (i = 0; i < 25; i++) {
259 SIO_CLR(NGE_MEAR_EE_CLK);
261 SIO_SET(NGE_MEAR_EE_CLK);
265 SIO_CLR(NGE_MEAR_EE_CLK);
267 SIO_CLR(NGE_MEAR_EE_CSEL);
269 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
273 * Send a read command and address to the EEPROM, check for ACK.
276 nge_eeprom_putbyte(struct nge_softc *sc, int addr)
280 d = addr | NGE_EECMD_READ;
283 * Feed in each bit and stobe the clock.
285 for (i = 0x400; i; i >>= 1) {
287 SIO_SET(NGE_MEAR_EE_DIN);
289 SIO_CLR(NGE_MEAR_EE_DIN);
291 SIO_SET(NGE_MEAR_EE_CLK);
293 SIO_CLR(NGE_MEAR_EE_CLK);
299 * Read a word of data stored in the EEPROM at address 'addr.'
302 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest)
307 /* Force EEPROM to idle state. */
310 /* Enter EEPROM access mode. */
312 SIO_CLR(NGE_MEAR_EE_CLK);
314 SIO_SET(NGE_MEAR_EE_CSEL);
318 * Send address of word we want to read.
320 nge_eeprom_putbyte(sc, addr);
323 * Start reading bits from EEPROM.
325 for (i = 0x8000; i; i >>= 1) {
326 SIO_SET(NGE_MEAR_EE_CLK);
328 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
331 SIO_CLR(NGE_MEAR_EE_CLK);
335 /* Turn off EEPROM access mode. */
342 * Read a sequence of words from the EEPROM.
345 nge_read_eeprom(struct nge_softc *sc, void *dest, int off, int cnt)
348 uint16_t word = 0, *ptr;
350 for (i = 0; i < cnt; i++) {
351 nge_eeprom_getword(sc, off + i, &word);
352 ptr = (uint16_t *)((uint8_t *)dest + (i * 2));
358 * Sync the PHYs by setting data bit and strobing the clock 32 times.
361 nge_mii_sync(struct nge_softc *sc)
365 SIO_SET(NGE_MEAR_MII_DIR | NGE_MEAR_MII_DATA);
367 for (i = 0; i < 32; i++) {
368 SIO_SET(NGE_MEAR_MII_CLK);
370 SIO_CLR(NGE_MEAR_MII_CLK);
376 * Clock a series of bits through the MII.
379 nge_mii_send(struct nge_softc *sc, uint32_t bits, int cnt)
383 SIO_CLR(NGE_MEAR_MII_CLK);
385 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
387 SIO_SET(NGE_MEAR_MII_DATA);
389 SIO_CLR(NGE_MEAR_MII_DATA);
391 SIO_CLR(NGE_MEAR_MII_CLK);
393 SIO_SET(NGE_MEAR_MII_CLK);
398 * Read an PHY register through the MII.
401 nge_mii_readreg(struct nge_softc *sc, struct nge_mii_frame *frame)
408 * Set up frame for RX.
410 frame->mii_stdelim = NGE_MII_STARTDELIM;
411 frame->mii_opcode = NGE_MII_READOP;
412 frame->mii_turnaround = 0;
415 CSR_WRITE_4(sc, NGE_MEAR, 0);
420 SIO_SET(NGE_MEAR_MII_DIR);
425 * Send command/address info.
427 nge_mii_send(sc, frame->mii_stdelim, 2);
428 nge_mii_send(sc, frame->mii_opcode, 2);
429 nge_mii_send(sc, frame->mii_phyaddr, 5);
430 nge_mii_send(sc, frame->mii_regaddr, 5);
433 SIO_CLR((NGE_MEAR_MII_CLK | NGE_MEAR_MII_DATA));
435 SIO_SET(NGE_MEAR_MII_CLK);
439 SIO_CLR(NGE_MEAR_MII_DIR);
441 SIO_CLR(NGE_MEAR_MII_CLK);
443 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
444 SIO_SET(NGE_MEAR_MII_CLK);
448 * Now try reading data bits. If the ack failed, we still
449 * need to clock through 16 cycles to keep the PHY(s) in sync.
452 for(i = 0; i < 16; i++) {
453 SIO_CLR(NGE_MEAR_MII_CLK);
455 SIO_SET(NGE_MEAR_MII_CLK);
461 for (i = 0x8000; i; i >>= 1) {
462 SIO_CLR(NGE_MEAR_MII_CLK);
465 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
466 frame->mii_data |= i;
469 SIO_SET(NGE_MEAR_MII_CLK);
474 SIO_CLR(NGE_MEAR_MII_CLK);
476 SIO_SET(NGE_MEAR_MII_CLK);
487 * Write to a PHY register through the MII.
490 nge_mii_writereg(struct nge_softc *sc, struct nge_mii_frame *frame)
495 * Set up frame for TX.
498 frame->mii_stdelim = NGE_MII_STARTDELIM;
499 frame->mii_opcode = NGE_MII_WRITEOP;
500 frame->mii_turnaround = NGE_MII_TURNAROUND;
503 * Turn on data output.
505 SIO_SET(NGE_MEAR_MII_DIR);
509 nge_mii_send(sc, frame->mii_stdelim, 2);
510 nge_mii_send(sc, frame->mii_opcode, 2);
511 nge_mii_send(sc, frame->mii_phyaddr, 5);
512 nge_mii_send(sc, frame->mii_regaddr, 5);
513 nge_mii_send(sc, frame->mii_turnaround, 2);
514 nge_mii_send(sc, frame->mii_data, 16);
517 SIO_SET(NGE_MEAR_MII_CLK);
519 SIO_CLR(NGE_MEAR_MII_CLK);
525 SIO_CLR(NGE_MEAR_MII_DIR);
533 nge_miibus_readreg(device_t dev, int phy, int reg)
535 struct nge_softc *sc = device_get_softc(dev);
536 struct nge_mii_frame frame;
538 bzero((char *)&frame, sizeof(frame));
540 frame.mii_phyaddr = phy;
541 frame.mii_regaddr = reg;
542 nge_mii_readreg(sc, &frame);
544 return(frame.mii_data);
548 nge_miibus_writereg(device_t dev, int phy, int reg, int data)
550 struct nge_softc *sc = device_get_softc(dev);
551 struct nge_mii_frame frame;
553 bzero((char *)&frame, sizeof(frame));
555 frame.mii_phyaddr = phy;
556 frame.mii_regaddr = reg;
557 frame.mii_data = data;
558 nge_mii_writereg(sc, &frame);
564 nge_miibus_statchg(device_t dev)
566 struct nge_softc *sc = device_get_softc(dev);
567 struct mii_data *mii;
571 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
573 status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
574 if (status == 0 || status & NGE_TBIANAR_FDX) {
575 NGE_SETBIT(sc, NGE_TX_CFG,
576 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
577 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
579 NGE_CLRBIT(sc, NGE_TX_CFG,
580 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
581 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
583 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
585 NGE_CLRBIT(sc, NGE_TX_CFG,
586 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
587 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
589 NGE_SETBIT(sc, NGE_TX_CFG,
590 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
591 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
594 mii = device_get_softc(sc->nge_miibus);
596 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
597 NGE_SETBIT(sc, NGE_TX_CFG,
598 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
599 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
601 NGE_CLRBIT(sc, NGE_TX_CFG,
602 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
603 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
606 /* If we have a 1000Mbps link, set the mode_1000 bit. */
607 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
608 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
609 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
611 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
617 nge_setmulti(struct nge_softc *sc)
619 struct ifnet *ifp = &sc->arpcom.ac_if;
620 struct ifmultiaddr *ifma;
621 uint32_t filtsave, h = 0, i;
624 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
625 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
626 NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH);
627 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
632 * We have to explicitly enable the multicast hash table
633 * on the NatSemi chip if we want to use it, which we do.
634 * We also have to tell it that we don't want to use the
635 * hash table for matching unicast addresses.
637 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
638 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
639 NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_UCHASH);
641 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
643 /* first, zot all the existing hash bits */
644 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
645 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
646 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
650 * From the 11 bits returned by the crc routine, the top 7
651 * bits represent the 16-bit word in the mcast hash table
652 * that needs to be updated, and the lower 4 bits represent
653 * which bit within that byte needs to be set.
655 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
656 if (ifma->ifma_addr->sa_family != AF_LINK)
658 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
659 ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
660 index = (h >> 4) & 0x7F;
662 CSR_WRITE_4(sc, NGE_RXFILT_CTL,
663 NGE_FILTADDR_MCAST_LO + (index * 2));
664 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
667 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
671 nge_reset(struct nge_softc *sc)
675 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
677 for (i = 0; i < NGE_TIMEOUT; i++) {
678 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET) == 0)
682 if (i == NGE_TIMEOUT)
683 printf("nge%d: reset never completed\n", sc->nge_unit);
685 /* Wait a little while for the chip to get its brains in order. */
689 * If this is a NetSemi chip, make sure to clear
692 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
693 CSR_WRITE_4(sc, NGE_CLKRUN, 0);
697 * Probe for an NatSemi chip. Check the PCI vendor and device
698 * IDs against our list and return a device name if we find a match.
701 nge_probe(device_t dev)
704 uint16_t vendor, product;
706 vendor = pci_get_vendor(dev);
707 product = pci_get_device(dev);
709 for (t = nge_devs; t->nge_name != NULL; t++) {
710 if (vendor == t->nge_vid && product == t->nge_did) {
711 device_set_desc(dev, t->nge_name);
720 * Attach the interface. Allocate softc structures, do ifmedia
721 * setup and ethernet/BPF attach.
724 nge_attach(device_t dev)
726 struct nge_softc *sc;
728 uint8_t eaddr[ETHER_ADDR_LEN];
730 int error = 0, rid, unit;
731 const char *sep = "";
733 sc = device_get_softc(dev);
734 unit = device_get_unit(dev);
735 callout_init(&sc->nge_stat_timer);
738 * Handle power management nonsense.
740 command = pci_read_config(dev, NGE_PCI_CAPID, 4) & 0x000000FF;
741 if (command == 0x01) {
742 command = pci_read_config(dev, NGE_PCI_PWRMGMTCTRL, 4);
743 if (command & NGE_PSTATE_MASK) {
744 uint32_t iobase, membase, irq;
746 /* Save important PCI config data. */
747 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4);
748 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4);
749 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4);
751 /* Reset the power state. */
752 printf("nge%d: chip is in D%d power mode "
753 "-- setting to D0\n", unit, command & NGE_PSTATE_MASK);
754 command &= 0xFFFFFFFC;
755 pci_write_config(dev, NGE_PCI_PWRMGMTCTRL, command, 4);
757 /* Restore PCI config data. */
758 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4);
759 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4);
760 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4);
765 * Map control/status registers.
767 command = pci_read_config(dev, PCIR_COMMAND, 4);
768 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
769 pci_write_config(dev, PCIR_COMMAND, command, 4);
770 command = pci_read_config(dev, PCIR_COMMAND, 4);
772 #ifdef NGE_USEIOSPACE
773 if (!(command & PCIM_CMD_PORTEN)) {
774 printf("nge%d: failed to enable I/O ports!\n", unit);
779 if (!(command & PCIM_CMD_MEMEN)) {
780 printf("nge%d: failed to enable memory mapping!\n", unit);
787 sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
789 if (sc->nge_res == NULL) {
790 printf("nge%d: couldn't map ports/memory\n", unit);
795 sc->nge_btag = rman_get_bustag(sc->nge_res);
796 sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
798 /* Allocate interrupt */
800 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
801 RF_SHAREABLE | RF_ACTIVE);
803 if (sc->nge_irq == NULL) {
804 printf("nge%d: couldn't map interrupt\n", unit);
809 /* Reset the adapter. */
813 * Get station address from the EEPROM.
815 nge_read_eeprom(sc, &eaddr[4], NGE_EE_NODEADDR, 1);
816 nge_read_eeprom(sc, &eaddr[2], NGE_EE_NODEADDR + 1, 1);
817 nge_read_eeprom(sc, &eaddr[0], NGE_EE_NODEADDR + 2, 1);
821 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
822 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
824 if (sc->nge_ldata == NULL) {
825 printf("nge%d: no memory for list buffers!\n", unit);
829 bzero(sc->nge_ldata, sizeof(struct nge_list_data));
831 /* Try to allocate memory for jumbo buffers. */
832 if (nge_alloc_jumbo_mem(sc)) {
833 printf("nge%d: jumbo buffer allocation failed\n",
839 ifp = &sc->arpcom.ac_if;
841 if_initname(ifp, "nge", unit);
842 ifp->if_mtu = ETHERMTU;
843 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
844 ifp->if_ioctl = nge_ioctl;
845 ifp->if_start = nge_start;
846 #ifdef DEVICE_POLLING
847 ifp->if_poll = nge_poll;
849 ifp->if_watchdog = nge_watchdog;
850 ifp->if_init = nge_init;
851 ifp->if_baudrate = 1000000000;
852 ifq_set_maxlen(&ifp->if_snd, NGE_TX_LIST_CNT - 1);
853 ifq_set_ready(&ifp->if_snd);
854 ifp->if_hwassist = NGE_CSUM_FEATURES;
855 ifp->if_capabilities = IFCAP_HWCSUM;
856 ifp->if_capenable = ifp->if_capabilities;
861 if (mii_phy_probe(dev, &sc->nge_miibus,
862 nge_ifmedia_upd, nge_ifmedia_sts)) {
863 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
865 device_printf(dev, "Using TBI\n");
867 sc->nge_miibus = dev;
869 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
871 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
872 #define PRINT(s) printf("%s%s", sep, s); sep = ", "
873 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
874 device_printf(dev, " ");
875 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
877 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
878 PRINT("1000baseSX-FDX");
879 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
885 ifmedia_set(&sc->nge_ifmedia,
886 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
888 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
890 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
891 | NGE_GPIO_GP3_OUTENB
892 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
895 printf("nge%d: MII without any PHY!\n", sc->nge_unit);
902 * Call MI attach routine.
904 ether_ifattach(ifp, eaddr);
906 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET,
907 nge_intr, sc, &sc->nge_intrhand, NULL);
910 device_printf(dev, "couldn't set up irq\n");
921 nge_detach(device_t dev)
923 struct nge_softc *sc = device_get_softc(dev);
924 struct ifnet *ifp = &sc->arpcom.ac_if;
928 if (device_is_attached(dev)) {
935 device_delete_child(dev, sc->nge_miibus);
936 bus_generic_detach(dev);
938 if (sc->nge_intrhand)
939 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
944 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
946 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
948 contigfree(sc->nge_ldata, sizeof(struct nge_list_data),
951 if (sc->nge_cdata.nge_jumbo_buf)
952 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF);
958 * Initialize the transmit descriptors.
961 nge_list_tx_init(struct nge_softc *sc)
963 struct nge_list_data *ld;
964 struct nge_ring_data *cd;
970 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
971 if (i == (NGE_TX_LIST_CNT - 1)) {
972 ld->nge_tx_list[i].nge_nextdesc =
974 ld->nge_tx_list[i].nge_next =
975 vtophys(&ld->nge_tx_list[0]);
977 ld->nge_tx_list[i].nge_nextdesc =
978 &ld->nge_tx_list[i + 1];
979 ld->nge_tx_list[i].nge_next =
980 vtophys(&ld->nge_tx_list[i + 1]);
982 ld->nge_tx_list[i].nge_mbuf = NULL;
983 ld->nge_tx_list[i].nge_ptr = 0;
984 ld->nge_tx_list[i].nge_ctl = 0;
987 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
994 * Initialize the RX descriptors and allocate mbufs for them. Note that
995 * we arrange the descriptors in a closed ring, so that the last descriptor
996 * points back to the first.
999 nge_list_rx_init(struct nge_softc *sc)
1001 struct nge_list_data *ld;
1002 struct nge_ring_data *cd;
1006 cd = &sc->nge_cdata;
1008 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1009 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1011 if (i == (NGE_RX_LIST_CNT - 1)) {
1012 ld->nge_rx_list[i].nge_nextdesc =
1013 &ld->nge_rx_list[0];
1014 ld->nge_rx_list[i].nge_next =
1015 vtophys(&ld->nge_rx_list[0]);
1017 ld->nge_rx_list[i].nge_nextdesc =
1018 &ld->nge_rx_list[i + 1];
1019 ld->nge_rx_list[i].nge_next =
1020 vtophys(&ld->nge_rx_list[i + 1]);
1024 cd->nge_rx_prod = 0;
1030 * Initialize an RX descriptor and attach an MBUF cluster.
1033 nge_newbuf(struct nge_softc *sc, struct nge_desc *c, struct mbuf *m)
1035 struct mbuf *m_new = NULL;
1036 struct nge_jslot *buf;
1039 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1040 if (m_new == NULL) {
1041 printf("nge%d: no memory for rx list "
1042 "-- packet dropped!\n", sc->nge_unit);
1046 /* Allocate the jumbo buffer */
1047 buf = nge_jalloc(sc);
1050 printf("nge%d: jumbo allocation failed "
1051 "-- packet dropped!\n", sc->nge_unit);
1056 /* Attach the buffer to the mbuf */
1057 m_new->m_ext.ext_arg = buf;
1058 m_new->m_ext.ext_buf = buf->nge_buf;
1059 m_new->m_ext.ext_free = nge_jfree;
1060 m_new->m_ext.ext_ref = nge_jref;
1061 m_new->m_ext.ext_size = NGE_JUMBO_FRAMELEN;
1063 m_new->m_data = m_new->m_ext.ext_buf;
1064 m_new->m_flags |= M_EXT;
1065 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1068 m_new->m_len = m_new->m_pkthdr.len = NGE_JLEN;
1069 m_new->m_data = m_new->m_ext.ext_buf;
1072 m_adj(m_new, sizeof(uint64_t));
1074 c->nge_mbuf = m_new;
1075 c->nge_ptr = vtophys(mtod(m_new, caddr_t));
1076 c->nge_ctl = m_new->m_len;
1083 nge_alloc_jumbo_mem(struct nge_softc *sc)
1087 struct nge_jslot *entry;
1089 /* Grab a big chunk o' storage. */
1090 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF,
1091 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1093 if (sc->nge_cdata.nge_jumbo_buf == NULL) {
1094 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit);
1098 SLIST_INIT(&sc->nge_jfree_listhead);
1101 * Now divide it up into 9K pieces and save the addresses
1104 ptr = sc->nge_cdata.nge_jumbo_buf;
1105 for (i = 0; i < NGE_JSLOTS; i++) {
1106 entry = &sc->nge_cdata.nge_jslots[i];
1108 entry->nge_buf = ptr;
1109 entry->nge_inuse = 0;
1110 entry->nge_slot = i;
1111 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
1120 * Allocate a jumbo buffer.
1122 static struct nge_jslot *
1123 nge_jalloc(struct nge_softc *sc)
1125 struct nge_jslot *entry;
1127 entry = SLIST_FIRST(&sc->nge_jfree_listhead);
1129 if (entry == NULL) {
1131 printf("nge%d: no free jumbo buffers\n", sc->nge_unit);
1136 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jslot_link);
1137 entry->nge_inuse = 1;
1143 * Adjust usage count on a jumbo buffer. In general this doesn't
1144 * get used much because our jumbo buffers don't get passed around
1145 * a lot, but it's implemented for correctness.
1150 struct nge_jslot *entry = (struct nge_jslot *)arg;
1151 struct nge_softc *sc = entry->nge_sc;
1154 panic("nge_jref: can't find softc pointer!");
1156 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
1157 panic("nge_jref: asked to reference buffer "
1158 "that we don't manage!");
1159 else if (entry->nge_inuse == 0)
1160 panic("nge_jref: buffer already free!");
1166 * Release a jumbo buffer.
1169 nge_jfree(void *arg)
1171 struct nge_jslot *entry = (struct nge_jslot *)arg;
1172 struct nge_softc *sc = entry->nge_sc;
1175 panic("nge_jref: can't find softc pointer!");
1177 if (&sc->nge_cdata.nge_jslots[entry->nge_slot] != entry)
1178 panic("nge_jref: asked to reference buffer "
1179 "that we don't manage!");
1180 else if (entry->nge_inuse == 0)
1181 panic("nge_jref: buffer already free!");
1182 else if (--entry->nge_inuse == 0)
1183 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jslot_link);
1186 * A frame has been uploaded: pass the resulting mbuf chain up to
1187 * the higher level protocols.
1190 nge_rxeof(struct nge_softc *sc)
1193 struct ifnet *ifp = &sc->arpcom.ac_if;
1194 struct nge_desc *cur_rx;
1195 int i, total_len = 0;
1198 i = sc->nge_cdata.nge_rx_prod;
1200 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1201 struct mbuf *m0 = NULL;
1204 #ifdef DEVICE_POLLING
1205 if (ifp->if_flags & IFF_POLLING) {
1206 if (sc->rxcycles <= 0)
1210 #endif /* DEVICE_POLLING */
1212 cur_rx = &sc->nge_ldata->nge_rx_list[i];
1213 rxstat = cur_rx->nge_rxstat;
1214 extsts = cur_rx->nge_extsts;
1215 m = cur_rx->nge_mbuf;
1216 cur_rx->nge_mbuf = NULL;
1217 total_len = NGE_RXBYTES(cur_rx);
1218 NGE_INC(i, NGE_RX_LIST_CNT);
1220 * If an error occurs, update stats, clear the
1221 * status word and leave the mbuf cluster in place:
1222 * it should simply get re-used next time this descriptor
1223 * comes up in the ring.
1225 if ((rxstat & NGE_CMDSTS_PKT_OK) == 0) {
1227 nge_newbuf(sc, cur_rx, m);
1232 * Ok. NatSemi really screwed up here. This is the
1233 * only gigE chip I know of with alignment constraints
1234 * on receive buffers. RX buffers must be 64-bit aligned.
1238 * By popular demand, ignore the alignment problems
1239 * on the Intel x86 platform. The performance hit
1240 * incurred due to unaligned accesses is much smaller
1241 * than the hit produced by forcing buffer copies all
1242 * the time, especially with jumbo frames. We still
1243 * need to fix up the alignment everywhere else though.
1245 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
1247 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1248 total_len + ETHER_ALIGN, 0, ifp, NULL);
1249 nge_newbuf(sc, cur_rx, m);
1251 printf("nge%d: no receive buffers "
1252 "available -- packet dropped!\n",
1257 m_adj(m0, ETHER_ALIGN);
1261 m->m_pkthdr.rcvif = ifp;
1262 m->m_pkthdr.len = m->m_len = total_len;
1268 /* Do IP checksum checking. */
1269 if (extsts & NGE_RXEXTSTS_IPPKT)
1270 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1271 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1272 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1273 if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1274 (extsts & NGE_RXEXTSTS_TCPCSUMERR) == 0) ||
1275 (extsts & NGE_RXEXTSTS_UDPPKT &&
1276 (extsts & NGE_RXEXTSTS_UDPCSUMERR) == 0)) {
1277 m->m_pkthdr.csum_flags |=
1278 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1279 m->m_pkthdr.csum_data = 0xffff;
1283 * If we received a packet with a vlan tag, pass it
1284 * to vlan_input() instead of ether_input().
1286 if (extsts & NGE_RXEXTSTS_VLANPKT)
1287 VLAN_INPUT_TAG(m, extsts & NGE_RXEXTSTS_VTCI);
1289 (*ifp->if_input)(ifp, m);
1292 sc->nge_cdata.nge_rx_prod = i;
1296 * A frame was downloaded to the chip. It's safe for us to clean up
1300 nge_txeof(struct nge_softc *sc)
1302 struct ifnet *ifp = &sc->arpcom.ac_if;
1303 struct nge_desc *cur_tx = NULL;
1306 /* Clear the timeout timer. */
1310 * Go through our tx list and free mbufs for those
1311 * frames that have been transmitted.
1313 idx = sc->nge_cdata.nge_tx_cons;
1314 while (idx != sc->nge_cdata.nge_tx_prod) {
1315 cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1317 if (NGE_OWNDESC(cur_tx))
1320 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1321 sc->nge_cdata.nge_tx_cnt--;
1322 NGE_INC(idx, NGE_TX_LIST_CNT);
1326 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1328 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1329 ifp->if_collisions++;
1330 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1331 ifp->if_collisions++;
1334 ifp->if_collisions +=
1335 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1338 if (cur_tx->nge_mbuf != NULL) {
1339 m_freem(cur_tx->nge_mbuf);
1340 cur_tx->nge_mbuf = NULL;
1343 sc->nge_cdata.nge_tx_cnt--;
1344 NGE_INC(idx, NGE_TX_LIST_CNT);
1348 sc->nge_cdata.nge_tx_cons = idx;
1351 ifp->if_flags &= ~IFF_OACTIVE;
1357 struct nge_softc *sc = xsc;
1358 struct ifnet *ifp = &sc->arpcom.ac_if;
1359 struct mii_data *mii;
1364 if (sc->nge_link == 0) {
1365 if (CSR_READ_4(sc, NGE_TBI_BMSR)
1366 & NGE_TBIBMSR_ANEG_DONE) {
1367 printf("nge%d: gigabit link up\n",
1369 nge_miibus_statchg(sc->nge_miibus);
1371 if (!ifq_is_empty(&ifp->if_snd))
1376 mii = device_get_softc(sc->nge_miibus);
1379 if (sc->nge_link == 0) {
1380 if (mii->mii_media_status & IFM_ACTIVE &&
1381 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1383 if (IFM_SUBTYPE(mii->mii_media_active)
1385 printf("nge%d: gigabit link up\n",
1387 if (!ifq_is_empty(&ifp->if_snd))
1392 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1397 #ifdef DEVICE_POLLING
1400 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1402 struct nge_softc *sc = ifp->if_softc;
1406 /* disable interrupts */
1407 CSR_WRITE_4(sc, NGE_IER, 0);
1409 case POLL_DEREGISTER:
1410 /* enable interrupts */
1411 CSR_WRITE_4(sc, NGE_IER, 1);
1415 * On the nge, reading the status register also clears it.
1416 * So before returning to intr mode we must make sure that all
1417 * possible pending sources of interrupts have been served.
1418 * In practice this means run to completion the *eof routines,
1419 * and then call the interrupt routine
1421 sc->rxcycles = count;
1424 if (!ifq_is_empty(&ifp->if_snd))
1427 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1430 /* Reading the ISR register clears all interrupts. */
1431 status = CSR_READ_4(sc, NGE_ISR);
1433 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1436 if (status & (NGE_ISR_RX_IDLE))
1437 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1439 if (status & NGE_ISR_SYSERR) {
1448 #endif /* DEVICE_POLLING */
1453 struct nge_softc *sc = arg;
1454 struct ifnet *ifp = &sc->arpcom.ac_if;
1457 /* Supress unwanted interrupts */
1458 if (!(ifp->if_flags & IFF_UP)) {
1463 /* Disable interrupts. */
1464 CSR_WRITE_4(sc, NGE_IER, 0);
1466 /* Data LED on for TBI mode */
1468 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1469 | NGE_GPIO_GP3_OUT);
1472 /* Reading the ISR register clears all interrupts. */
1473 status = CSR_READ_4(sc, NGE_ISR);
1475 if ((status & NGE_INTRS) == 0)
1478 if ((status & NGE_ISR_TX_DESC_OK) ||
1479 (status & NGE_ISR_TX_ERR) ||
1480 (status & NGE_ISR_TX_OK) ||
1481 (status & NGE_ISR_TX_IDLE))
1484 if ((status & NGE_ISR_RX_DESC_OK) ||
1485 (status & NGE_ISR_RX_ERR) ||
1486 (status & NGE_ISR_RX_OFLOW) ||
1487 (status & NGE_ISR_RX_FIFO_OFLOW) ||
1488 (status & NGE_ISR_RX_IDLE) ||
1489 (status & NGE_ISR_RX_OK))
1492 if ((status & NGE_ISR_RX_IDLE))
1493 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1495 if (status & NGE_ISR_SYSERR) {
1497 ifp->if_flags &= ~IFF_RUNNING;
1502 /* mii_tick should only be called once per second */
1503 if (status & NGE_ISR_PHY_INTR) {
1510 /* Re-enable interrupts. */
1511 CSR_WRITE_4(sc, NGE_IER, 1);
1513 if (!ifq_is_empty(&ifp->if_snd))
1516 /* Data LED off for TBI mode */
1519 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1520 & ~NGE_GPIO_GP3_OUT);
1524 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1525 * pointers to the fragment pointers.
1528 nge_encap(struct nge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
1530 struct nge_desc *f = NULL;
1532 int frag, cur, cnt = 0;
1533 struct ifvlan *ifv = NULL;
1535 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1536 m_head->m_pkthdr.rcvif != NULL &&
1537 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1538 ifv = m_head->m_pkthdr.rcvif->if_softc;
1541 * Start packing the mbufs in this chain into
1542 * the fragment pointers. Stop when we run out
1543 * of fragments or hit the end of the mbuf chain.
1546 cur = frag = *txidx;
1548 for (m = m_head; m != NULL; m = m->m_next) {
1549 if (m->m_len != 0) {
1550 if ((NGE_TX_LIST_CNT -
1551 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1553 f = &sc->nge_ldata->nge_tx_list[frag];
1554 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1555 f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1557 f->nge_ctl |= NGE_CMDSTS_OWN;
1559 NGE_INC(frag, NGE_TX_LIST_CNT);
1567 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1568 if (m_head->m_pkthdr.csum_flags) {
1569 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1570 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1571 NGE_TXEXTSTS_IPCSUM;
1572 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1573 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1574 NGE_TXEXTSTS_TCPCSUM;
1575 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1576 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1577 NGE_TXEXTSTS_UDPCSUM;
1581 sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1582 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag);
1585 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1586 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1587 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1588 sc->nge_cdata.nge_tx_cnt += cnt;
1595 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1596 * to the mbuf data regions directly in the transmit lists. We also save a
1597 * copy of the pointers since the transmit list fragment pointers are
1598 * physical addresses.
1602 nge_start(struct ifnet *ifp)
1604 struct nge_softc *sc = ifp->if_softc;
1605 struct mbuf *m_head = NULL;
1611 idx = sc->nge_cdata.nge_tx_prod;
1613 if (ifp->if_flags & IFF_OACTIVE)
1616 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1617 m_head = ifq_poll(&ifp->if_snd);
1621 if (nge_encap(sc, m_head, &idx)) {
1622 ifp->if_flags |= IFF_OACTIVE;
1625 m_head = ifq_dequeue(&ifp->if_snd);
1627 BPF_MTAP(ifp, m_head);
1631 sc->nge_cdata.nge_tx_prod = idx;
1632 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1635 * Set a timeout in case the chip goes out to lunch.
1643 struct nge_softc *sc = xsc;
1644 struct ifnet *ifp = &sc->arpcom.ac_if;
1645 struct mii_data *mii;
1649 if (ifp->if_flags & IFF_RUNNING) {
1655 * Cancel pending I/O and free all RX/TX buffers.
1658 callout_reset(&sc->nge_stat_timer, hz, nge_tick, sc);
1663 mii = device_get_softc(sc->nge_miibus);
1665 /* Set MAC address */
1666 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1667 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1668 ((uint16_t *)sc->arpcom.ac_enaddr)[0]);
1669 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1670 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1671 ((uint16_t *)sc->arpcom.ac_enaddr)[1]);
1672 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1673 CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1674 ((uint16_t *)sc->arpcom.ac_enaddr)[2]);
1676 /* Init circular RX list. */
1677 if (nge_list_rx_init(sc) == ENOBUFS) {
1678 printf("nge%d: initialization failed: no "
1679 "memory for rx buffers\n", sc->nge_unit);
1686 * Init tx descriptors.
1688 nge_list_tx_init(sc);
1691 * For the NatSemi chip, we have to explicitly enable the
1692 * reception of ARP frames, as well as turn on the 'perfect
1693 * match' filter where we store the station address, otherwise
1694 * we won't receive unicasts meant for this host.
1696 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1697 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1699 /* If we want promiscuous mode, set the allframes bit. */
1700 if (ifp->if_flags & IFF_PROMISC)
1701 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1703 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1706 * Set the capture broadcast bit to capture broadcast frames.
1708 if (ifp->if_flags & IFF_BROADCAST)
1709 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1711 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1714 * Load the multicast filter.
1718 /* Turn the receive filter on */
1719 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1722 * Load the address of the RX and TX lists.
1724 CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1725 vtophys(&sc->nge_ldata->nge_rx_list[0]));
1726 CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1727 vtophys(&sc->nge_ldata->nge_tx_list[0]));
1729 /* Set RX configuration */
1730 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1732 * Enable hardware checksum validation for all IPv4
1733 * packets, do not reject packets with bad checksums.
1735 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1738 * Tell the chip to detect and strip VLAN tag info from
1739 * received frames. The tag will be provided in the extsts
1740 * field in the RX descriptors.
1742 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1743 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1745 /* Set TX configuration */
1746 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1749 * Enable TX IPv4 checksumming on a per-packet basis.
1751 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1754 * Tell the chip to insert VLAN tags on a per-packet basis as
1755 * dictated by the code in the frame encapsulation routine.
1757 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1759 /* Set full/half duplex mode. */
1761 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1763 NGE_SETBIT(sc, NGE_TX_CFG,
1764 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1765 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1767 NGE_CLRBIT(sc, NGE_TX_CFG,
1768 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1769 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1772 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1773 NGE_SETBIT(sc, NGE_TX_CFG,
1774 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1775 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1777 NGE_CLRBIT(sc, NGE_TX_CFG,
1778 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR));
1779 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1784 * Enable the delivery of PHY interrupts based on
1785 * link/speed/duplex status changes. Also enable the
1786 * extsts field in the DMA descriptors (needed for
1787 * TCP/IP checksum offload on transmit).
1789 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD |
1790 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB);
1793 * Configure interrupt holdoff (moderation). We can
1794 * have the chip delay interrupt delivery for a certain
1795 * period. Units are in 100us, and the max setting
1796 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1798 CSR_WRITE_4(sc, NGE_IHR, 0x01);
1801 * Enable interrupts.
1803 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1804 #ifdef DEVICE_POLLING
1806 * ... only enable interrupts if we are not polling, make sure
1807 * they are off otherwise.
1809 if (ifp->if_flags & IFF_POLLING)
1810 CSR_WRITE_4(sc, NGE_IER, 0);
1812 #endif /* DEVICE_POLLING */
1813 CSR_WRITE_4(sc, NGE_IER, 1);
1815 /* Enable receiver and transmitter. */
1816 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE);
1817 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1819 nge_ifmedia_upd(ifp);
1821 ifp->if_flags |= IFF_RUNNING;
1822 ifp->if_flags &= ~IFF_OACTIVE;
1828 * Set media options.
1831 nge_ifmedia_upd(struct ifnet *ifp)
1833 struct nge_softc *sc = ifp->if_softc;
1834 struct mii_data *mii;
1837 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1839 CSR_WRITE_4(sc, NGE_TBI_ANAR,
1840 CSR_READ_4(sc, NGE_TBI_ANAR)
1841 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1842 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1843 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1844 | NGE_TBIBMCR_RESTART_ANEG);
1845 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1846 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1847 & IFM_GMASK) == IFM_FDX) {
1848 NGE_SETBIT(sc, NGE_TX_CFG,
1849 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1850 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1852 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1853 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1855 NGE_CLRBIT(sc, NGE_TX_CFG,
1856 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1857 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1859 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1860 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1863 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1864 & ~NGE_GPIO_GP3_OUT);
1866 mii = device_get_softc(sc->nge_miibus);
1868 if (mii->mii_instance) {
1869 struct mii_softc *miisc;
1870 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1871 miisc = LIST_NEXT(miisc, mii_list))
1872 mii_phy_reset(miisc);
1881 * Report current media status.
1884 nge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1886 struct nge_softc *sc = ifp->if_softc;
1887 struct mii_data *mii;
1890 ifmr->ifm_status = IFM_AVALID;
1891 ifmr->ifm_active = IFM_ETHER;
1893 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE)
1894 ifmr->ifm_status |= IFM_ACTIVE;
1895 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1896 ifmr->ifm_active |= IFM_LOOP;
1897 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1898 ifmr->ifm_active |= IFM_NONE;
1899 ifmr->ifm_status = 0;
1902 ifmr->ifm_active |= IFM_1000_SX;
1903 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1905 ifmr->ifm_active |= IFM_AUTO;
1906 if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1907 & NGE_TBIANAR_FDX) {
1908 ifmr->ifm_active |= IFM_FDX;
1909 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1910 & NGE_TBIANAR_HDX) {
1911 ifmr->ifm_active |= IFM_HDX;
1913 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1915 ifmr->ifm_active |= IFM_FDX;
1917 ifmr->ifm_active |= IFM_HDX;
1920 mii = device_get_softc(sc->nge_miibus);
1922 ifmr->ifm_active = mii->mii_media_active;
1923 ifmr->ifm_status = mii->mii_media_status;
1928 nge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1930 struct nge_softc *sc = ifp->if_softc;
1931 struct ifreq *ifr = (struct ifreq *) data;
1932 struct mii_data *mii;
1939 if (ifr->ifr_mtu > NGE_JUMBO_MTU) {
1942 ifp->if_mtu = ifr->ifr_mtu;
1944 * Workaround: if the MTU is larger than
1945 * 8152 (TX FIFO size minus 64 minus 18), turn off
1946 * TX checksum offloading.
1948 if (ifr->ifr_mtu >= 8152)
1949 ifp->if_hwassist = 0;
1951 ifp->if_hwassist = NGE_CSUM_FEATURES;
1955 if (ifp->if_flags & IFF_UP) {
1956 if (ifp->if_flags & IFF_RUNNING &&
1957 ifp->if_flags & IFF_PROMISC &&
1958 !(sc->nge_if_flags & IFF_PROMISC)) {
1959 NGE_SETBIT(sc, NGE_RXFILT_CTL,
1960 NGE_RXFILTCTL_ALLPHYS|
1961 NGE_RXFILTCTL_ALLMULTI);
1962 } else if (ifp->if_flags & IFF_RUNNING &&
1963 !(ifp->if_flags & IFF_PROMISC) &&
1964 sc->nge_if_flags & IFF_PROMISC) {
1965 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1966 NGE_RXFILTCTL_ALLPHYS);
1967 if (!(ifp->if_flags & IFF_ALLMULTI))
1968 NGE_CLRBIT(sc, NGE_RXFILT_CTL,
1969 NGE_RXFILTCTL_ALLMULTI);
1971 ifp->if_flags &= ~IFF_RUNNING;
1975 if (ifp->if_flags & IFF_RUNNING)
1978 sc->nge_if_flags = ifp->if_flags;
1989 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
1992 mii = device_get_softc(sc->nge_miibus);
1993 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1998 error = ether_ioctl(ifp, command, data);
2008 nge_watchdog(struct ifnet *ifp)
2010 struct nge_softc *sc = ifp->if_softc;
2013 printf("nge%d: watchdog timeout\n", sc->nge_unit);
2017 ifp->if_flags &= ~IFF_RUNNING;
2020 if (!ifq_is_empty(&ifp->if_snd))
2025 * Stop the adapter and free any mbufs allocated to the
2029 nge_stop(struct nge_softc *sc)
2031 struct ifnet *ifp = &sc->arpcom.ac_if;
2032 struct ifmedia_entry *ifm;
2033 struct mii_data *mii;
2040 mii = device_get_softc(sc->nge_miibus);
2042 callout_stop(&sc->nge_stat_timer);
2043 CSR_WRITE_4(sc, NGE_IER, 0);
2044 CSR_WRITE_4(sc, NGE_IMR, 0);
2045 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2047 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2048 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2051 * Isolate/power down the PHY, but leave the media selection
2052 * unchanged so that things will be put back to normal when
2053 * we bring the interface back up.
2055 itmp = ifp->if_flags;
2056 ifp->if_flags |= IFF_UP;
2059 ifm = sc->nge_ifmedia.ifm_cur;
2061 ifm = mii->mii_media.ifm_cur;
2063 mtmp = ifm->ifm_media;
2064 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2068 ifm->ifm_media = mtmp;
2069 ifp->if_flags = itmp;
2074 * Free data in the RX lists.
2076 for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2077 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2078 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2079 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2082 bzero(&sc->nge_ldata->nge_rx_list,
2083 sizeof(sc->nge_ldata->nge_rx_list));
2086 * Free the TX list buffers.
2088 for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2089 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2090 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2091 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2095 bzero(&sc->nge_ldata->nge_tx_list,
2096 sizeof(sc->nge_ldata->nge_tx_list));
2098 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2102 * Stop all chip I/O so that the kernel's probe routines don't
2103 * get confused by errant DMAs when rebooting.
2106 nge_shutdown(device_t dev)
2108 struct nge_softc *sc = device_get_softc(dev);